1 //===-- ARMConstantIslandPass.cpp - ARM constant islands ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that splits the constant pool up into 'islands'
11 // which are scattered through-out the function. This is required due to the
12 // limited pc-relative displacements that ARM has.
14 //===----------------------------------------------------------------------===//
17 #include "ARMMachineFunctionInfo.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "Thumb2InstrInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallSet.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineJumpTableInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/Format.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
38 #define DEBUG_TYPE "arm-cp-islands"
40 STATISTIC(NumCPEs, "Number of constpool entries");
41 STATISTIC(NumSplit, "Number of uncond branches inserted");
42 STATISTIC(NumCBrFixed, "Number of cond branches fixed");
43 STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
44 STATISTIC(NumTBs, "Number of table branches generated");
45 STATISTIC(NumT2CPShrunk, "Number of Thumb2 constantpool instructions shrunk");
46 STATISTIC(NumT2BrShrunk, "Number of Thumb2 immediate branches shrunk");
47 STATISTIC(NumCBZ, "Number of CBZ / CBNZ formed");
48 STATISTIC(NumJTMoved, "Number of jump table destination blocks moved");
49 STATISTIC(NumJTInserted, "Number of jump table intermediate blocks inserted");
53 AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(true),
54 cl::desc("Adjust basic block layout to better use TB[BH]"));
56 /// UnknownPadding - Return the worst case padding that could result from
57 /// unknown offset bits. This does not include alignment padding caused by
58 /// known offset bits.
60 /// @param LogAlign log2(alignment)
61 /// @param KnownBits Number of known low offset bits.
62 static inline unsigned UnknownPadding(unsigned LogAlign, unsigned KnownBits) {
63 if (KnownBits < LogAlign)
64 return (1u << LogAlign) - (1u << KnownBits);
69 /// ARMConstantIslands - Due to limited PC-relative displacements, ARM
70 /// requires constant pool entries to be scattered among the instructions
71 /// inside a function. To do this, it completely ignores the normal LLVM
72 /// constant pool; instead, it places constants wherever it feels like with
73 /// special instructions.
75 /// The terminology used in this pass includes:
76 /// Islands - Clumps of constants placed in the function.
77 /// Water - Potential places where an island could be formed.
78 /// CPE - A constant pool entry that has been placed somewhere, which
79 /// tracks a list of users.
80 class ARMConstantIslands : public MachineFunctionPass {
81 /// BasicBlockInfo - Information about the offset and size of a single
83 struct BasicBlockInfo {
84 /// Offset - Distance from the beginning of the function to the beginning
85 /// of this basic block.
87 /// Offsets are computed assuming worst case padding before an aligned
88 /// block. This means that subtracting basic block offsets always gives a
89 /// conservative estimate of the real distance which may be smaller.
91 /// Because worst case padding is used, the computed offset of an aligned
92 /// block may not actually be aligned.
95 /// Size - Size of the basic block in bytes. If the block contains
96 /// inline assembly, this is a worst case estimate.
98 /// The size does not include any alignment padding whether from the
99 /// beginning of the block, or from an aligned jump table at the end.
102 /// KnownBits - The number of low bits in Offset that are known to be
103 /// exact. The remaining bits of Offset are an upper bound.
106 /// Unalign - When non-zero, the block contains instructions (inline asm)
107 /// of unknown size. The real size may be smaller than Size bytes by a
108 /// multiple of 1 << Unalign.
111 /// PostAlign - When non-zero, the block terminator contains a .align
112 /// directive, so the end of the block is aligned to 1 << PostAlign
116 BasicBlockInfo() : Offset(0), Size(0), KnownBits(0), Unalign(0),
119 /// Compute the number of known offset bits internally to this block.
120 /// This number should be used to predict worst case padding when
121 /// splitting the block.
122 unsigned internalKnownBits() const {
123 unsigned Bits = Unalign ? Unalign : KnownBits;
124 // If the block size isn't a multiple of the known bits, assume the
125 // worst case padding.
126 if (Size & ((1u << Bits) - 1))
127 Bits = countTrailingZeros(Size);
131 /// Compute the offset immediately following this block. If LogAlign is
132 /// specified, return the offset the successor block will get if it has
134 unsigned postOffset(unsigned LogAlign = 0) const {
135 unsigned PO = Offset + Size;
136 unsigned LA = std::max(unsigned(PostAlign), LogAlign);
139 // Add alignment padding from the terminator.
140 return PO + UnknownPadding(LA, internalKnownBits());
143 /// Compute the number of known low bits of postOffset. If this block
144 /// contains inline asm, the number of known bits drops to the
145 /// instruction alignment. An aligned terminator may increase the number
147 /// If LogAlign is given, also consider the alignment of the next block.
148 unsigned postKnownBits(unsigned LogAlign = 0) const {
149 return std::max(std::max(unsigned(PostAlign), LogAlign),
150 internalKnownBits());
154 std::vector<BasicBlockInfo> BBInfo;
156 /// WaterList - A sorted list of basic blocks where islands could be placed
157 /// (i.e. blocks that don't fall through to the following block, due
158 /// to a return, unreachable, or unconditional branch).
159 std::vector<MachineBasicBlock*> WaterList;
161 /// NewWaterList - The subset of WaterList that was created since the
162 /// previous iteration by inserting unconditional branches.
163 SmallSet<MachineBasicBlock*, 4> NewWaterList;
165 typedef std::vector<MachineBasicBlock*>::iterator water_iterator;
167 /// CPUser - One user of a constant pool, keeping the machine instruction
168 /// pointer, the constant pool being referenced, and the max displacement
169 /// allowed from the instruction to the CP. The HighWaterMark records the
170 /// highest basic block where a new CPEntry can be placed. To ensure this
171 /// pass terminates, the CP entries are initially placed at the end of the
172 /// function and then move monotonically to lower addresses. The
173 /// exception to this rule is when the current CP entry for a particular
174 /// CPUser is out of range, but there is another CP entry for the same
175 /// constant value in range. We want to use the existing in-range CP
176 /// entry, but if it later moves out of range, the search for new water
177 /// should resume where it left off. The HighWaterMark is used to record
182 MachineBasicBlock *HighWaterMark;
187 CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp,
188 bool neg, bool soimm)
189 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm),
190 KnownAlignment(false) {
191 HighWaterMark = CPEMI->getParent();
193 /// getMaxDisp - Returns the maximum displacement supported by MI.
194 /// Correct for unknown alignment.
195 /// Conservatively subtract 2 bytes to handle weird alignment effects.
196 unsigned getMaxDisp() const {
197 return (KnownAlignment ? MaxDisp : MaxDisp - 2) - 2;
201 /// CPUsers - Keep track of all of the machine instructions that use various
202 /// constant pools and their max displacement.
203 std::vector<CPUser> CPUsers;
205 /// CPEntry - One per constant pool entry, keeping the machine instruction
206 /// pointer, the constpool index, and the number of CPUser's which
207 /// reference this entry.
212 CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
213 : CPEMI(cpemi), CPI(cpi), RefCount(rc) {}
216 /// CPEntries - Keep track of all of the constant pool entry machine
217 /// instructions. For each original constpool index (i.e. those that existed
218 /// upon entry to this pass), it keeps a vector of entries. Original
219 /// elements are cloned as we go along; the clones are put in the vector of
220 /// the original element, but have distinct CPIs.
222 /// The first half of CPEntries contains generic constants, the second half
223 /// contains jump tables. Use getCombinedIndex on a generic CPEMI to look up
224 /// which vector it will be in here.
225 std::vector<std::vector<CPEntry> > CPEntries;
227 /// Maps a JT index to the offset in CPEntries containing copies of that
228 /// table. The equivalent map for a CONSTPOOL_ENTRY is the identity.
229 DenseMap<int, int> JumpTableEntryIndices;
231 /// Maps a JT index to the LEA that actually uses the index to calculate its
233 DenseMap<int, int> JumpTableUserIndices;
235 /// ImmBranch - One per immediate branch, keeping the machine instruction
236 /// pointer, conditional or unconditional, the max displacement,
237 /// and (if isCond is true) the corresponding unconditional branch
241 unsigned MaxDisp : 31;
244 ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, unsigned ubr)
245 : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
248 /// ImmBranches - Keep track of all the immediate branch instructions.
250 std::vector<ImmBranch> ImmBranches;
252 /// PushPopMIs - Keep track of all the Thumb push / pop instructions.
254 SmallVector<MachineInstr*, 4> PushPopMIs;
256 /// T2JumpTables - Keep track of all the Thumb2 jumptable instructions.
257 SmallVector<MachineInstr*, 4> T2JumpTables;
259 /// HasFarJump - True if any far jump instruction has been emitted during
260 /// the branch fix up pass.
264 MachineConstantPool *MCP;
265 const ARMBaseInstrInfo *TII;
266 const ARMSubtarget *STI;
267 ARMFunctionInfo *AFI;
273 ARMConstantIslands() : MachineFunctionPass(ID) {}
275 bool runOnMachineFunction(MachineFunction &MF) override;
277 const char *getPassName() const override {
278 return "ARM constant island placement and branch shortening pass";
282 void doInitialConstPlacement(std::vector<MachineInstr *> &CPEMIs);
283 void doInitialJumpTablePlacement(std::vector<MachineInstr *> &CPEMIs);
284 bool BBHasFallthrough(MachineBasicBlock *MBB);
285 CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
286 unsigned getCPELogAlign(const MachineInstr *CPEMI);
287 void scanFunctionJumpTables();
288 void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs);
289 MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
290 void updateForInsertedWaterBlock(MachineBasicBlock *NewBB);
291 void adjustBBOffsetsAfter(MachineBasicBlock *BB);
292 bool decrementCPEReferenceCount(unsigned CPI, MachineInstr* CPEMI);
293 unsigned getCombinedIndex(const MachineInstr *CPEMI);
294 int findInRangeCPEntry(CPUser& U, unsigned UserOffset);
295 bool findAvailableWater(CPUser&U, unsigned UserOffset,
296 water_iterator &WaterIter);
297 void createNewWater(unsigned CPUserIndex, unsigned UserOffset,
298 MachineBasicBlock *&NewMBB);
299 bool handleConstantPoolUser(unsigned CPUserIndex);
300 void removeDeadCPEMI(MachineInstr *CPEMI);
301 bool removeUnusedCPEntries();
302 bool isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
303 MachineInstr *CPEMI, unsigned Disp, bool NegOk,
304 bool DoDump = false);
305 bool isWaterInRange(unsigned UserOffset, MachineBasicBlock *Water,
306 CPUser &U, unsigned &Growth);
307 bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
308 bool fixupImmediateBr(ImmBranch &Br);
309 bool fixupConditionalBr(ImmBranch &Br);
310 bool fixupUnconditionalBr(ImmBranch &Br);
311 bool undoLRSpillRestore();
312 bool mayOptimizeThumb2Instruction(const MachineInstr *MI) const;
313 bool optimizeThumb2Instructions();
314 bool optimizeThumb2Branches();
315 bool reorderThumb2JumpTables();
316 bool preserveBaseRegister(MachineInstr *JumpMI, MachineInstr *LEAMI,
317 unsigned &DeadSize, bool &CanDeleteLEA,
319 bool optimizeThumb2JumpTables();
320 MachineBasicBlock *adjustJTTargetBlockForward(MachineBasicBlock *BB,
321 MachineBasicBlock *JTBB);
323 void computeBlockSize(MachineBasicBlock *MBB);
324 unsigned getOffsetOf(MachineInstr *MI) const;
325 unsigned getUserOffset(CPUser&) const;
329 bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
330 unsigned Disp, bool NegativeOK, bool IsSoImm = false);
331 bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
333 return isOffsetInRange(UserOffset, TrialOffset,
334 U.getMaxDisp(), U.NegOk, U.IsSoImm);
337 char ARMConstantIslands::ID = 0;
340 /// verify - check BBOffsets, BBSizes, alignment of islands
341 void ARMConstantIslands::verify() {
343 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
345 MachineBasicBlock *MBB = MBBI;
346 unsigned MBBId = MBB->getNumber();
347 assert(!MBBId || BBInfo[MBBId - 1].postOffset() <= BBInfo[MBBId].Offset);
349 DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n");
350 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
351 CPUser &U = CPUsers[i];
352 unsigned UserOffset = getUserOffset(U);
353 // Verify offset using the real max displacement without the safety
355 if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, U.getMaxDisp()+2, U.NegOk,
356 /* DoDump = */ true)) {
357 DEBUG(dbgs() << "OK\n");
360 DEBUG(dbgs() << "Out of range.\n");
363 llvm_unreachable("Constant pool entry out of range!");
368 /// print block size and offset information - debugging
369 void ARMConstantIslands::dumpBBs() {
371 for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
372 const BasicBlockInfo &BBI = BBInfo[J];
373 dbgs() << format("%08x BB#%u\t", BBI.Offset, J)
374 << " kb=" << unsigned(BBI.KnownBits)
375 << " ua=" << unsigned(BBI.Unalign)
376 << " pa=" << unsigned(BBI.PostAlign)
377 << format(" size=%#x\n", BBInfo[J].Size);
382 /// createARMConstantIslandPass - returns an instance of the constpool
384 FunctionPass *llvm::createARMConstantIslandPass() {
385 return new ARMConstantIslands();
388 bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
390 MCP = mf.getConstantPool();
392 DEBUG(dbgs() << "***** ARMConstantIslands: "
393 << MCP->getConstants().size() << " CP entries, aligned to "
394 << MCP->getConstantPoolAlignment() << " bytes *****\n");
396 STI = &static_cast<const ARMSubtarget &>(MF->getSubtarget());
397 TII = STI->getInstrInfo();
398 AFI = MF->getInfo<ARMFunctionInfo>();
400 isThumb = AFI->isThumbFunction();
401 isThumb1 = AFI->isThumb1OnlyFunction();
402 isThumb2 = AFI->isThumb2Function();
406 // This pass invalidates liveness information when it splits basic blocks.
407 MF->getRegInfo().invalidateLiveness();
409 // Renumber all of the machine basic blocks in the function, guaranteeing that
410 // the numbers agree with the position of the block in the function.
411 MF->RenumberBlocks();
413 // Try to reorder and otherwise adjust the block layout to make good use
414 // of the TB[BH] instructions.
415 bool MadeChange = false;
416 if (isThumb2 && AdjustJumpTableBlocks) {
417 scanFunctionJumpTables();
418 MadeChange |= reorderThumb2JumpTables();
419 // Data is out of date, so clear it. It'll be re-computed later.
420 T2JumpTables.clear();
421 // Blocks may have shifted around. Keep the numbering up to date.
422 MF->RenumberBlocks();
425 // Perform the initial placement of the constant pool entries. To start with,
426 // we put them all at the end of the function.
427 std::vector<MachineInstr*> CPEMIs;
429 doInitialConstPlacement(CPEMIs);
431 if (MF->getJumpTableInfo())
432 doInitialJumpTablePlacement(CPEMIs);
434 /// The next UID to take is the first unused one.
435 AFI->initPICLabelUId(CPEMIs.size());
437 // Do the initial scan of the function, building up information about the
438 // sizes of each block, the location of all the water, and finding all of the
439 // constant pool users.
440 initializeFunctionInfo(CPEMIs);
444 // Functions with jump tables need an alignment of 4 because they use the ADR
445 // instruction, which aligns the PC to 4 bytes before adding an offset.
446 if (!T2JumpTables.empty())
447 MF->ensureAlignment(2);
449 /// Remove dead constant pool entries.
450 MadeChange |= removeUnusedCPEntries();
452 // Iteratively place constant pool entries and fix up branches until there
454 unsigned NoCPIters = 0, NoBRIters = 0;
456 DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << '\n');
457 bool CPChange = false;
458 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
459 CPChange |= handleConstantPoolUser(i);
460 if (CPChange && ++NoCPIters > 30)
461 report_fatal_error("Constant Island pass failed to converge!");
464 // Clear NewWaterList now. If we split a block for branches, it should
465 // appear as "new water" for the next iteration of constant pool placement.
466 NewWaterList.clear();
468 DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
469 bool BRChange = false;
470 for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
471 BRChange |= fixupImmediateBr(ImmBranches[i]);
472 if (BRChange && ++NoBRIters > 30)
473 report_fatal_error("Branch Fix Up pass failed to converge!");
476 if (!CPChange && !BRChange)
481 // Shrink 32-bit Thumb2 branch, load, and store instructions.
482 if (isThumb2 && !STI->prefers32BitThumb())
483 MadeChange |= optimizeThumb2Instructions();
485 // After a while, this might be made debug-only, but it is not expensive.
488 // If LR has been forced spilled and no far jump (i.e. BL) has been issued,
489 // undo the spill / restore of LR if possible.
490 if (isThumb && !HasFarJump && AFI->isLRSpilledForFarJump())
491 MadeChange |= undoLRSpillRestore();
493 // Save the mapping between original and cloned constpool entries.
494 for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
495 for (unsigned j = 0, je = CPEntries[i].size(); j != je; ++j) {
496 const CPEntry & CPE = CPEntries[i][j];
497 if (CPE.CPEMI && CPE.CPEMI->getOperand(1).isCPI())
498 AFI->recordCPEClone(i, CPE.CPI);
502 DEBUG(dbgs() << '\n'; dumpBBs());
508 JumpTableEntryIndices.clear();
509 JumpTableUserIndices.clear();
512 T2JumpTables.clear();
517 /// \brief Perform the initial placement of the regular constant pool entries.
518 /// To start with, we put them all at the end of the function.
520 ARMConstantIslands::doInitialConstPlacement(std::vector<MachineInstr*> &CPEMIs) {
521 // Create the basic block to hold the CPE's.
522 MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
525 // MachineConstantPool measures alignment in bytes. We measure in log2(bytes).
526 unsigned MaxAlign = Log2_32(MCP->getConstantPoolAlignment());
528 // Mark the basic block as required by the const-pool.
529 BB->setAlignment(MaxAlign);
531 // The function needs to be as aligned as the basic blocks. The linker may
532 // move functions around based on their alignment.
533 MF->ensureAlignment(BB->getAlignment());
535 // Order the entries in BB by descending alignment. That ensures correct
536 // alignment of all entries as long as BB is sufficiently aligned. Keep
537 // track of the insertion point for each alignment. We are going to bucket
538 // sort the entries as they are created.
539 SmallVector<MachineBasicBlock::iterator, 8> InsPoint(MaxAlign + 1, BB->end());
541 // Add all of the constants from the constant pool to the end block, use an
542 // identity mapping of CPI's to CPE's.
543 const std::vector<MachineConstantPoolEntry> &CPs = MCP->getConstants();
545 const DataLayout &TD = *MF->getTarget().getDataLayout();
546 for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
547 unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
548 assert(Size >= 4 && "Too small constant pool entry");
549 unsigned Align = CPs[i].getAlignment();
550 assert(isPowerOf2_32(Align) && "Invalid alignment");
551 // Verify that all constant pool entries are a multiple of their alignment.
552 // If not, we would have to pad them out so that instructions stay aligned.
553 assert((Size % Align) == 0 && "CP Entry not multiple of 4 bytes!");
555 // Insert CONSTPOOL_ENTRY before entries with a smaller alignment.
556 unsigned LogAlign = Log2_32(Align);
557 MachineBasicBlock::iterator InsAt = InsPoint[LogAlign];
558 MachineInstr *CPEMI =
559 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
560 .addImm(i).addConstantPoolIndex(i).addImm(Size);
561 CPEMIs.push_back(CPEMI);
563 // Ensure that future entries with higher alignment get inserted before
564 // CPEMI. This is bucket sort with iterators.
565 for (unsigned a = LogAlign + 1; a <= MaxAlign; ++a)
566 if (InsPoint[a] == InsAt)
569 // Add a new CPEntry, but no corresponding CPUser yet.
570 CPEntries.emplace_back(1, CPEntry(CPEMI, i));
572 DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = "
573 << Size << ", align = " << Align <<'\n');
578 /// \brief Do initial placement of the jump tables. Because Thumb2's TBB and TBH
579 /// instructions can be made more efficient if the jump table immediately
580 /// follows the instruction, it's best to place them immediately next to their
581 /// jumps to begin with. In almost all cases they'll never be moved from that
583 void ARMConstantIslands::doInitialJumpTablePlacement(
584 std::vector<MachineInstr *> &CPEMIs) {
585 unsigned i = CPEntries.size();
586 auto MJTI = MF->getJumpTableInfo();
587 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
589 MachineBasicBlock *LastCorrectlyNumberedBB = nullptr;
590 for (MachineBasicBlock &MBB : *MF) {
591 auto MI = MBB.getLastNonDebugInstr();
594 switch (MI->getOpcode()) {
601 JTOpcode = ARM::JUMPTABLE_ADDRS;
604 JTOpcode = ARM::JUMPTABLE_INSTS;
607 JTOpcode = ARM::JUMPTABLE_TBB;
610 JTOpcode = ARM::JUMPTABLE_TBH;
614 unsigned NumOps = MI->getDesc().getNumOperands();
615 MachineOperand JTOp =
616 MI->getOperand(NumOps - (MI->isPredicable() ? 2 : 1));
617 unsigned JTI = JTOp.getIndex();
618 unsigned Size = JT[JTI].MBBs.size() * sizeof(uint32_t);
619 MachineBasicBlock *JumpTableBB = MF->CreateMachineBasicBlock();
620 MF->insert(std::next(MachineFunction::iterator(MBB)), JumpTableBB);
621 MachineInstr *CPEMI = BuildMI(*JumpTableBB, JumpTableBB->begin(),
622 DebugLoc(), TII->get(JTOpcode))
624 .addJumpTableIndex(JTI)
626 CPEMIs.push_back(CPEMI);
627 CPEntries.emplace_back(1, CPEntry(CPEMI, JTI));
628 JumpTableEntryIndices.insert(std::make_pair(JTI, CPEntries.size() - 1));
629 if (!LastCorrectlyNumberedBB)
630 LastCorrectlyNumberedBB = &MBB;
633 // If we did anything then we need to renumber the subsequent blocks.
634 if (LastCorrectlyNumberedBB)
635 MF->RenumberBlocks(LastCorrectlyNumberedBB);
638 /// BBHasFallthrough - Return true if the specified basic block can fallthrough
639 /// into the block immediately after it.
640 bool ARMConstantIslands::BBHasFallthrough(MachineBasicBlock *MBB) {
641 // Get the next machine basic block in the function.
642 MachineFunction::iterator MBBI = MBB;
643 // Can't fall off end of function.
644 if (std::next(MBBI) == MBB->getParent()->end())
647 MachineBasicBlock *NextBB = std::next(MBBI);
648 if (std::find(MBB->succ_begin(), MBB->succ_end(), NextBB) == MBB->succ_end())
651 // Try to analyze the end of the block. A potential fallthrough may already
652 // have an unconditional branch for whatever reason.
653 MachineBasicBlock *TBB, *FBB;
654 SmallVector<MachineOperand, 4> Cond;
655 bool TooDifficult = TII->AnalyzeBranch(*MBB, TBB, FBB, Cond);
656 return TooDifficult || FBB == nullptr;
659 /// findConstPoolEntry - Given the constpool index and CONSTPOOL_ENTRY MI,
660 /// look up the corresponding CPEntry.
661 ARMConstantIslands::CPEntry
662 *ARMConstantIslands::findConstPoolEntry(unsigned CPI,
663 const MachineInstr *CPEMI) {
664 std::vector<CPEntry> &CPEs = CPEntries[CPI];
665 // Number of entries per constpool index should be small, just do a
667 for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
668 if (CPEs[i].CPEMI == CPEMI)
674 /// getCPELogAlign - Returns the required alignment of the constant pool entry
675 /// represented by CPEMI. Alignment is measured in log2(bytes) units.
676 unsigned ARMConstantIslands::getCPELogAlign(const MachineInstr *CPEMI) {
677 switch (CPEMI->getOpcode()) {
678 case ARM::CONSTPOOL_ENTRY:
680 case ARM::JUMPTABLE_TBB:
682 case ARM::JUMPTABLE_TBH:
683 case ARM::JUMPTABLE_INSTS:
685 case ARM::JUMPTABLE_ADDRS:
688 llvm_unreachable("unknown constpool entry kind");
691 unsigned CPI = getCombinedIndex(CPEMI);
692 assert(CPI < MCP->getConstants().size() && "Invalid constant pool index.");
693 unsigned Align = MCP->getConstants()[CPI].getAlignment();
694 assert(isPowerOf2_32(Align) && "Invalid CPE alignment");
695 return Log2_32(Align);
698 /// scanFunctionJumpTables - Do a scan of the function, building up
699 /// information about the sizes of each block and the locations of all
701 void ARMConstantIslands::scanFunctionJumpTables() {
702 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
704 MachineBasicBlock &MBB = *MBBI;
706 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
708 if (I->isBranch() && I->getOpcode() == ARM::t2BR_JT)
709 T2JumpTables.push_back(I);
713 /// initializeFunctionInfo - Do the initial scan of the function, building up
714 /// information about the sizes of each block, the location of all the water,
715 /// and finding all of the constant pool users.
716 void ARMConstantIslands::
717 initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
719 BBInfo.resize(MF->getNumBlockIDs());
721 // First thing, compute the size of all basic blocks, and see if the function
722 // has any inline assembly in it. If so, we have to be conservative about
723 // alignment assumptions, as we don't know for sure the size of any
724 // instructions in the inline assembly.
725 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I)
728 // The known bits of the entry block offset are determined by the function
730 BBInfo.front().KnownBits = MF->getAlignment();
732 // Compute block offsets and known bits.
733 adjustBBOffsetsAfter(MF->begin());
735 // Now go back through the instructions and build up our data structures.
736 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
738 MachineBasicBlock &MBB = *MBBI;
740 // If this block doesn't fall through into the next MBB, then this is
741 // 'water' that a constant pool island could be placed.
742 if (!BBHasFallthrough(&MBB))
743 WaterList.push_back(&MBB);
745 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
747 if (I->isDebugValue())
750 unsigned Opc = I->getOpcode();
758 continue; // Ignore other JT branches
760 T2JumpTables.push_back(I);
761 continue; // Does not get an entry in ImmBranches
792 // Record this immediate branch.
793 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
794 ImmBranches.push_back(ImmBranch(I, MaxOffs, isCond, UOpc));
797 if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
798 PushPopMIs.push_back(I);
800 if (Opc == ARM::CONSTPOOL_ENTRY || Opc == ARM::JUMPTABLE_ADDRS ||
801 Opc == ARM::JUMPTABLE_INSTS || Opc == ARM::JUMPTABLE_TBB ||
802 Opc == ARM::JUMPTABLE_TBH)
805 // Scan the instructions for constant pool operands.
806 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
807 if (I->getOperand(op).isCPI() || I->getOperand(op).isJTI()) {
808 // We found one. The addressing mode tells us the max displacement
809 // from the PC that this instruction permits.
811 // Basic size info comes from the TSFlags field.
815 bool IsSoImm = false;
819 llvm_unreachable("Unknown addressing mode for CP reference!");
821 // Taking the address of a CP entry.
823 case ARM::LEApcrelJT:
824 // This takes a SoImm, which is 8 bit immediate rotated. We'll
825 // pretend the maximum offset is 255 * 4. Since each instruction
826 // 4 byte wide, this is always correct. We'll check for other
827 // displacements that fits in a SoImm as well.
833 case ARM::t2LEApcrel:
834 case ARM::t2LEApcrelJT:
839 case ARM::tLEApcrelJT:
848 Bits = 12; // +-offset_12
854 Scale = 4; // +(offset_8*4)
860 Scale = 4; // +-(offset_8*4)
865 // Remember that this is a user of a CP entry.
866 unsigned CPI = I->getOperand(op).getIndex();
867 if (I->getOperand(op).isJTI()) {
868 JumpTableUserIndices.insert(std::make_pair(CPI, CPUsers.size()));
869 CPI = JumpTableEntryIndices[CPI];
872 MachineInstr *CPEMI = CPEMIs[CPI];
873 unsigned MaxOffs = ((1 << Bits)-1) * Scale;
874 CPUsers.push_back(CPUser(I, CPEMI, MaxOffs, NegOk, IsSoImm));
876 // Increment corresponding CPEntry reference count.
877 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
878 assert(CPE && "Cannot find a corresponding CPEntry!");
881 // Instructions can only use one CP entry, don't bother scanning the
882 // rest of the operands.
889 /// computeBlockSize - Compute the size and some alignment information for MBB.
890 /// This function updates BBInfo directly.
891 void ARMConstantIslands::computeBlockSize(MachineBasicBlock *MBB) {
892 BasicBlockInfo &BBI = BBInfo[MBB->getNumber()];
897 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
899 BBI.Size += TII->GetInstSizeInBytes(I);
900 // For inline asm, GetInstSizeInBytes returns a conservative estimate.
901 // The actual size may be smaller, but still a multiple of the instr size.
902 if (I->isInlineAsm())
903 BBI.Unalign = isThumb ? 1 : 2;
904 // Also consider instructions that may be shrunk later.
905 else if (isThumb && mayOptimizeThumb2Instruction(I))
909 // tBR_JTr contains a .align 2 directive.
910 if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) {
912 MBB->getParent()->ensureAlignment(2);
916 /// getOffsetOf - Return the current offset of the specified machine instruction
917 /// from the start of the function. This offset changes as stuff is moved
918 /// around inside the function.
919 unsigned ARMConstantIslands::getOffsetOf(MachineInstr *MI) const {
920 MachineBasicBlock *MBB = MI->getParent();
922 // The offset is composed of two things: the sum of the sizes of all MBB's
923 // before this instruction's block, and the offset from the start of the block
925 unsigned Offset = BBInfo[MBB->getNumber()].Offset;
927 // Sum instructions before MI in MBB.
928 for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
929 assert(I != MBB->end() && "Didn't find MI in its own basic block?");
930 Offset += TII->GetInstSizeInBytes(I);
935 /// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB
937 static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
938 const MachineBasicBlock *RHS) {
939 return LHS->getNumber() < RHS->getNumber();
942 /// updateForInsertedWaterBlock - When a block is newly inserted into the
943 /// machine function, it upsets all of the block numbers. Renumber the blocks
944 /// and update the arrays that parallel this numbering.
945 void ARMConstantIslands::updateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
946 // Renumber the MBB's to keep them consecutive.
947 NewBB->getParent()->RenumberBlocks(NewBB);
949 // Insert an entry into BBInfo to align it properly with the (newly
950 // renumbered) block numbers.
951 BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
953 // Next, update WaterList. Specifically, we need to add NewMBB as having
954 // available water after it.
956 std::lower_bound(WaterList.begin(), WaterList.end(), NewBB,
958 WaterList.insert(IP, NewBB);
962 /// Split the basic block containing MI into two blocks, which are joined by
963 /// an unconditional branch. Update data structures and renumber blocks to
964 /// account for this change and returns the newly created block.
965 MachineBasicBlock *ARMConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
966 MachineBasicBlock *OrigBB = MI->getParent();
968 // Create a new MBB for the code after the OrigBB.
969 MachineBasicBlock *NewBB =
970 MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
971 MachineFunction::iterator MBBI = OrigBB; ++MBBI;
972 MF->insert(MBBI, NewBB);
974 // Splice the instructions starting with MI over to NewBB.
975 NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
977 // Add an unconditional branch from OrigBB to NewBB.
978 // Note the new unconditional branch is not being recorded.
979 // There doesn't seem to be meaningful DebugInfo available; this doesn't
980 // correspond to anything in the source.
981 unsigned Opc = isThumb ? (isThumb2 ? ARM::t2B : ARM::tB) : ARM::B;
983 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
985 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB)
986 .addImm(ARMCC::AL).addReg(0);
989 // Update the CFG. All succs of OrigBB are now succs of NewBB.
990 NewBB->transferSuccessors(OrigBB);
992 // OrigBB branches to NewBB.
993 OrigBB->addSuccessor(NewBB);
995 // Update internal data structures to account for the newly inserted MBB.
996 // This is almost the same as updateForInsertedWaterBlock, except that
997 // the Water goes after OrigBB, not NewBB.
998 MF->RenumberBlocks(NewBB);
1000 // Insert an entry into BBInfo to align it properly with the (newly
1001 // renumbered) block numbers.
1002 BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
1004 // Next, update WaterList. Specifically, we need to add OrigMBB as having
1005 // available water after it (but not if it's already there, which happens
1006 // when splitting before a conditional branch that is followed by an
1007 // unconditional branch - in that case we want to insert NewBB).
1009 std::lower_bound(WaterList.begin(), WaterList.end(), OrigBB,
1011 MachineBasicBlock* WaterBB = *IP;
1012 if (WaterBB == OrigBB)
1013 WaterList.insert(std::next(IP), NewBB);
1015 WaterList.insert(IP, OrigBB);
1016 NewWaterList.insert(OrigBB);
1018 // Figure out how large the OrigBB is. As the first half of the original
1019 // block, it cannot contain a tablejump. The size includes
1020 // the new jump we added. (It should be possible to do this without
1021 // recounting everything, but it's very confusing, and this is rarely
1023 computeBlockSize(OrigBB);
1025 // Figure out how large the NewMBB is. As the second half of the original
1026 // block, it may contain a tablejump.
1027 computeBlockSize(NewBB);
1029 // All BBOffsets following these blocks must be modified.
1030 adjustBBOffsetsAfter(OrigBB);
1035 /// getUserOffset - Compute the offset of U.MI as seen by the hardware
1036 /// displacement computation. Update U.KnownAlignment to match its current
1037 /// basic block location.
1038 unsigned ARMConstantIslands::getUserOffset(CPUser &U) const {
1039 unsigned UserOffset = getOffsetOf(U.MI);
1040 const BasicBlockInfo &BBI = BBInfo[U.MI->getParent()->getNumber()];
1041 unsigned KnownBits = BBI.internalKnownBits();
1043 // The value read from PC is offset from the actual instruction address.
1044 UserOffset += (isThumb ? 4 : 8);
1046 // Because of inline assembly, we may not know the alignment (mod 4) of U.MI.
1047 // Make sure U.getMaxDisp() returns a constrained range.
1048 U.KnownAlignment = (KnownBits >= 2);
1050 // On Thumb, offsets==2 mod 4 are rounded down by the hardware for
1051 // purposes of the displacement computation; compensate for that here.
1052 // For unknown alignments, getMaxDisp() constrains the range instead.
1053 if (isThumb && U.KnownAlignment)
1059 /// isOffsetInRange - Checks whether UserOffset (the location of a constant pool
1060 /// reference) is within MaxDisp of TrialOffset (a proposed location of a
1061 /// constant pool entry).
1062 /// UserOffset is computed by getUserOffset above to include PC adjustments. If
1063 /// the mod 4 alignment of UserOffset is not known, the uncertainty must be
1064 /// subtracted from MaxDisp instead. CPUser::getMaxDisp() does that.
1065 bool ARMConstantIslands::isOffsetInRange(unsigned UserOffset,
1066 unsigned TrialOffset, unsigned MaxDisp,
1067 bool NegativeOK, bool IsSoImm) {
1068 if (UserOffset <= TrialOffset) {
1069 // User before the Trial.
1070 if (TrialOffset - UserOffset <= MaxDisp)
1072 // FIXME: Make use full range of soimm values.
1073 } else if (NegativeOK) {
1074 if (UserOffset - TrialOffset <= MaxDisp)
1076 // FIXME: Make use full range of soimm values.
1081 /// isWaterInRange - Returns true if a CPE placed after the specified
1082 /// Water (a basic block) will be in range for the specific MI.
1084 /// Compute how much the function will grow by inserting a CPE after Water.
1085 bool ARMConstantIslands::isWaterInRange(unsigned UserOffset,
1086 MachineBasicBlock* Water, CPUser &U,
1088 unsigned CPELogAlign = getCPELogAlign(U.CPEMI);
1089 unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(CPELogAlign);
1090 unsigned NextBlockOffset, NextBlockAlignment;
1091 MachineFunction::const_iterator NextBlock = Water;
1092 if (++NextBlock == MF->end()) {
1093 NextBlockOffset = BBInfo[Water->getNumber()].postOffset();
1094 NextBlockAlignment = 0;
1096 NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset;
1097 NextBlockAlignment = NextBlock->getAlignment();
1099 unsigned Size = U.CPEMI->getOperand(2).getImm();
1100 unsigned CPEEnd = CPEOffset + Size;
1102 // The CPE may be able to hide in the alignment padding before the next
1103 // block. It may also cause more padding to be required if it is more aligned
1104 // that the next block.
1105 if (CPEEnd > NextBlockOffset) {
1106 Growth = CPEEnd - NextBlockOffset;
1107 // Compute the padding that would go at the end of the CPE to align the next
1109 Growth += OffsetToAlignment(CPEEnd, 1u << NextBlockAlignment);
1111 // If the CPE is to be inserted before the instruction, that will raise
1112 // the offset of the instruction. Also account for unknown alignment padding
1113 // in blocks between CPE and the user.
1114 if (CPEOffset < UserOffset)
1115 UserOffset += Growth + UnknownPadding(MF->getAlignment(), CPELogAlign);
1117 // CPE fits in existing padding.
1120 return isOffsetInRange(UserOffset, CPEOffset, U);
1123 /// isCPEntryInRange - Returns true if the distance between specific MI and
1124 /// specific ConstPool entry instruction can fit in MI's displacement field.
1125 bool ARMConstantIslands::isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
1126 MachineInstr *CPEMI, unsigned MaxDisp,
1127 bool NegOk, bool DoDump) {
1128 unsigned CPEOffset = getOffsetOf(CPEMI);
1132 unsigned Block = MI->getParent()->getNumber();
1133 const BasicBlockInfo &BBI = BBInfo[Block];
1134 dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
1135 << " max delta=" << MaxDisp
1136 << format(" insn address=%#x", UserOffset)
1137 << " in BB#" << Block << ": "
1138 << format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI
1139 << format("CPE address=%#x offset=%+d: ", CPEOffset,
1140 int(CPEOffset-UserOffset));
1144 return isOffsetInRange(UserOffset, CPEOffset, MaxDisp, NegOk);
1148 /// BBIsJumpedOver - Return true of the specified basic block's only predecessor
1149 /// unconditionally branches to its only successor.
1150 static bool BBIsJumpedOver(MachineBasicBlock *MBB) {
1151 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
1154 MachineBasicBlock *Succ = *MBB->succ_begin();
1155 MachineBasicBlock *Pred = *MBB->pred_begin();
1156 MachineInstr *PredMI = &Pred->back();
1157 if (PredMI->getOpcode() == ARM::B || PredMI->getOpcode() == ARM::tB
1158 || PredMI->getOpcode() == ARM::t2B)
1159 return PredMI->getOperand(0).getMBB() == Succ;
1164 void ARMConstantIslands::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
1165 unsigned BBNum = BB->getNumber();
1166 for(unsigned i = BBNum + 1, e = MF->getNumBlockIDs(); i < e; ++i) {
1167 // Get the offset and known bits at the end of the layout predecessor.
1168 // Include the alignment of the current block.
1169 unsigned LogAlign = MF->getBlockNumbered(i)->getAlignment();
1170 unsigned Offset = BBInfo[i - 1].postOffset(LogAlign);
1171 unsigned KnownBits = BBInfo[i - 1].postKnownBits(LogAlign);
1173 // This is where block i begins. Stop if the offset is already correct,
1174 // and we have updated 2 blocks. This is the maximum number of blocks
1175 // changed before calling this function.
1176 if (i > BBNum + 2 &&
1177 BBInfo[i].Offset == Offset &&
1178 BBInfo[i].KnownBits == KnownBits)
1181 BBInfo[i].Offset = Offset;
1182 BBInfo[i].KnownBits = KnownBits;
1186 /// decrementCPEReferenceCount - find the constant pool entry with index CPI
1187 /// and instruction CPEMI, and decrement its refcount. If the refcount
1188 /// becomes 0 remove the entry and instruction. Returns true if we removed
1189 /// the entry, false if we didn't.
1191 bool ARMConstantIslands::decrementCPEReferenceCount(unsigned CPI,
1192 MachineInstr *CPEMI) {
1193 // Find the old entry. Eliminate it if it is no longer used.
1194 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
1195 assert(CPE && "Unexpected!");
1196 if (--CPE->RefCount == 0) {
1197 removeDeadCPEMI(CPEMI);
1198 CPE->CPEMI = nullptr;
1205 unsigned ARMConstantIslands::getCombinedIndex(const MachineInstr *CPEMI) {
1206 if (CPEMI->getOperand(1).isCPI())
1207 return CPEMI->getOperand(1).getIndex();
1209 return JumpTableEntryIndices[CPEMI->getOperand(1).getIndex()];
1212 /// LookForCPEntryInRange - see if the currently referenced CPE is in range;
1213 /// if not, see if an in-range clone of the CPE is in range, and if so,
1214 /// change the data structures so the user references the clone. Returns:
1215 /// 0 = no existing entry found
1216 /// 1 = entry found, and there were no code insertions or deletions
1217 /// 2 = entry found, and there were code insertions or deletions
1218 int ARMConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset)
1220 MachineInstr *UserMI = U.MI;
1221 MachineInstr *CPEMI = U.CPEMI;
1223 // Check to see if the CPE is already in-range.
1224 if (isCPEntryInRange(UserMI, UserOffset, CPEMI, U.getMaxDisp(), U.NegOk,
1226 DEBUG(dbgs() << "In range\n");
1230 // No. Look for previously created clones of the CPE that are in range.
1231 unsigned CPI = getCombinedIndex(CPEMI);
1232 std::vector<CPEntry> &CPEs = CPEntries[CPI];
1233 for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
1234 // We already tried this one
1235 if (CPEs[i].CPEMI == CPEMI)
1237 // Removing CPEs can leave empty entries, skip
1238 if (CPEs[i].CPEMI == nullptr)
1240 if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.getMaxDisp(),
1242 DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#"
1243 << CPEs[i].CPI << "\n");
1244 // Point the CPUser node to the replacement
1245 U.CPEMI = CPEs[i].CPEMI;
1246 // Change the CPI in the instruction operand to refer to the clone.
1247 for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
1248 if (UserMI->getOperand(j).isCPI()) {
1249 UserMI->getOperand(j).setIndex(CPEs[i].CPI);
1252 // Adjust the refcount of the clone...
1254 // ...and the original. If we didn't remove the old entry, none of the
1255 // addresses changed, so we don't need another pass.
1256 return decrementCPEReferenceCount(CPI, CPEMI) ? 2 : 1;
1262 /// getUnconditionalBrDisp - Returns the maximum displacement that can fit in
1263 /// the specific unconditional branch instruction.
1264 static inline unsigned getUnconditionalBrDisp(int Opc) {
1267 return ((1<<10)-1)*2;
1269 return ((1<<23)-1)*2;
1274 return ((1<<23)-1)*4;
1277 /// findAvailableWater - Look for an existing entry in the WaterList in which
1278 /// we can place the CPE referenced from U so it's within range of U's MI.
1279 /// Returns true if found, false if not. If it returns true, WaterIter
1280 /// is set to the WaterList entry. For Thumb, prefer water that will not
1281 /// introduce padding to water that will. To ensure that this pass
1282 /// terminates, the CPE location for a particular CPUser is only allowed to
1283 /// move to a lower address, so search backward from the end of the list and
1284 /// prefer the first water that is in range.
1285 bool ARMConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
1286 water_iterator &WaterIter) {
1287 if (WaterList.empty())
1290 unsigned BestGrowth = ~0u;
1291 for (water_iterator IP = std::prev(WaterList.end()), B = WaterList.begin();;
1293 MachineBasicBlock* WaterBB = *IP;
1294 // Check if water is in range and is either at a lower address than the
1295 // current "high water mark" or a new water block that was created since
1296 // the previous iteration by inserting an unconditional branch. In the
1297 // latter case, we want to allow resetting the high water mark back to
1298 // this new water since we haven't seen it before. Inserting branches
1299 // should be relatively uncommon and when it does happen, we want to be
1300 // sure to take advantage of it for all the CPEs near that block, so that
1301 // we don't insert more branches than necessary.
1303 if (isWaterInRange(UserOffset, WaterBB, U, Growth) &&
1304 (WaterBB->getNumber() < U.HighWaterMark->getNumber() ||
1305 NewWaterList.count(WaterBB) || WaterBB == U.MI->getParent()) &&
1306 Growth < BestGrowth) {
1307 // This is the least amount of required padding seen so far.
1308 BestGrowth = Growth;
1310 DEBUG(dbgs() << "Found water after BB#" << WaterBB->getNumber()
1311 << " Growth=" << Growth << '\n');
1313 // Keep looking unless it is perfect.
1314 if (BestGrowth == 0)
1320 return BestGrowth != ~0u;
1323 /// createNewWater - No existing WaterList entry will work for
1324 /// CPUsers[CPUserIndex], so create a place to put the CPE. The end of the
1325 /// block is used if in range, and the conditional branch munged so control
1326 /// flow is correct. Otherwise the block is split to create a hole with an
1327 /// unconditional branch around it. In either case NewMBB is set to a
1328 /// block following which the new island can be inserted (the WaterList
1329 /// is not adjusted).
1330 void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
1331 unsigned UserOffset,
1332 MachineBasicBlock *&NewMBB) {
1333 CPUser &U = CPUsers[CPUserIndex];
1334 MachineInstr *UserMI = U.MI;
1335 MachineInstr *CPEMI = U.CPEMI;
1336 unsigned CPELogAlign = getCPELogAlign(CPEMI);
1337 MachineBasicBlock *UserMBB = UserMI->getParent();
1338 const BasicBlockInfo &UserBBI = BBInfo[UserMBB->getNumber()];
1340 // If the block does not end in an unconditional branch already, and if the
1341 // end of the block is within range, make new water there. (The addition
1342 // below is for the unconditional branch we will be adding: 4 bytes on ARM +
1343 // Thumb2, 2 on Thumb1.
1344 if (BBHasFallthrough(UserMBB)) {
1345 // Size of branch to insert.
1346 unsigned Delta = isThumb1 ? 2 : 4;
1347 // Compute the offset where the CPE will begin.
1348 unsigned CPEOffset = UserBBI.postOffset(CPELogAlign) + Delta;
1350 if (isOffsetInRange(UserOffset, CPEOffset, U)) {
1351 DEBUG(dbgs() << "Split at end of BB#" << UserMBB->getNumber()
1352 << format(", expected CPE offset %#x\n", CPEOffset));
1353 NewMBB = std::next(MachineFunction::iterator(UserMBB));
1354 // Add an unconditional branch from UserMBB to fallthrough block. Record
1355 // it for branch lengthening; this new branch will not get out of range,
1356 // but if the preceding conditional branch is out of range, the targets
1357 // will be exchanged, and the altered branch may be out of range, so the
1358 // machinery has to know about it.
1359 int UncondBr = isThumb ? ((isThumb2) ? ARM::t2B : ARM::tB) : ARM::B;
1361 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1363 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB)
1364 .addImm(ARMCC::AL).addReg(0);
1365 unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
1366 ImmBranches.push_back(ImmBranch(&UserMBB->back(),
1367 MaxDisp, false, UncondBr));
1368 computeBlockSize(UserMBB);
1369 adjustBBOffsetsAfter(UserMBB);
1374 // What a big block. Find a place within the block to split it. This is a
1375 // little tricky on Thumb1 since instructions are 2 bytes and constant pool
1376 // entries are 4 bytes: if instruction I references island CPE, and
1377 // instruction I+1 references CPE', it will not work well to put CPE as far
1378 // forward as possible, since then CPE' cannot immediately follow it (that
1379 // location is 2 bytes farther away from I+1 than CPE was from I) and we'd
1380 // need to create a new island. So, we make a first guess, then walk through
1381 // the instructions between the one currently being looked at and the
1382 // possible insertion point, and make sure any other instructions that
1383 // reference CPEs will be able to use the same island area; if not, we back
1384 // up the insertion point.
1386 // Try to split the block so it's fully aligned. Compute the latest split
1387 // point where we can add a 4-byte branch instruction, and then align to
1388 // LogAlign which is the largest possible alignment in the function.
1389 unsigned LogAlign = MF->getAlignment();
1390 assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
1391 unsigned KnownBits = UserBBI.internalKnownBits();
1392 unsigned UPad = UnknownPadding(LogAlign, KnownBits);
1393 unsigned BaseInsertOffset = UserOffset + U.getMaxDisp() - UPad;
1394 DEBUG(dbgs() << format("Split in middle of big block before %#x",
1397 // The 4 in the following is for the unconditional branch we'll be inserting
1398 // (allows for long branch on Thumb1). Alignment of the island is handled
1399 // inside isOffsetInRange.
1400 BaseInsertOffset -= 4;
1402 DEBUG(dbgs() << format(", adjusted to %#x", BaseInsertOffset)
1403 << " la=" << LogAlign
1404 << " kb=" << KnownBits
1405 << " up=" << UPad << '\n');
1407 // This could point off the end of the block if we've already got constant
1408 // pool entries following this block; only the last one is in the water list.
1409 // Back past any possible branches (allow for a conditional and a maximally
1410 // long unconditional).
1411 if (BaseInsertOffset + 8 >= UserBBI.postOffset()) {
1412 // Ensure BaseInsertOffset is larger than the offset of the instruction
1413 // following UserMI so that the loop which searches for the split point
1414 // iterates at least once.
1416 std::max(UserBBI.postOffset() - UPad - 8,
1417 UserOffset + TII->GetInstSizeInBytes(UserMI) + 1);
1418 DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
1420 unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad +
1421 CPEMI->getOperand(2).getImm();
1422 MachineBasicBlock::iterator MI = UserMI;
1424 unsigned CPUIndex = CPUserIndex+1;
1425 unsigned NumCPUsers = CPUsers.size();
1426 MachineInstr *LastIT = nullptr;
1427 for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI);
1428 Offset < BaseInsertOffset;
1429 Offset += TII->GetInstSizeInBytes(MI), MI = std::next(MI)) {
1430 assert(MI != UserMBB->end() && "Fell off end of block");
1431 if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == MI) {
1432 CPUser &U = CPUsers[CPUIndex];
1433 if (!isOffsetInRange(Offset, EndInsertOffset, U)) {
1434 // Shift intertion point by one unit of alignment so it is within reach.
1435 BaseInsertOffset -= 1u << LogAlign;
1436 EndInsertOffset -= 1u << LogAlign;
1438 // This is overly conservative, as we don't account for CPEMIs being
1439 // reused within the block, but it doesn't matter much. Also assume CPEs
1440 // are added in order with alignment padding. We may eventually be able
1441 // to pack the aligned CPEs better.
1442 EndInsertOffset += U.CPEMI->getOperand(2).getImm();
1446 // Remember the last IT instruction.
1447 if (MI->getOpcode() == ARM::t2IT)
1453 // Avoid splitting an IT block.
1455 unsigned PredReg = 0;
1456 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
1457 if (CC != ARMCC::AL)
1461 // We really must not split an IT block.
1462 DEBUG(unsigned PredReg;
1463 assert(!isThumb || getITInstrPredicate(MI, PredReg) == ARMCC::AL));
1465 NewMBB = splitBlockBeforeInstr(MI);
1468 /// handleConstantPoolUser - Analyze the specified user, checking to see if it
1469 /// is out-of-range. If so, pick up the constant pool value and move it some
1470 /// place in-range. Return true if we changed any addresses (thus must run
1471 /// another pass of branch lengthening), false otherwise.
1472 bool ARMConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) {
1473 CPUser &U = CPUsers[CPUserIndex];
1474 MachineInstr *UserMI = U.MI;
1475 MachineInstr *CPEMI = U.CPEMI;
1476 unsigned CPI = getCombinedIndex(CPEMI);
1477 unsigned Size = CPEMI->getOperand(2).getImm();
1478 // Compute this only once, it's expensive.
1479 unsigned UserOffset = getUserOffset(U);
1481 // See if the current entry is within range, or there is a clone of it
1483 int result = findInRangeCPEntry(U, UserOffset);
1484 if (result==1) return false;
1485 else if (result==2) return true;
1487 // No existing clone of this CPE is within range.
1488 // We will be generating a new clone. Get a UID for it.
1489 unsigned ID = AFI->createPICLabelUId();
1491 // Look for water where we can place this CPE.
1492 MachineBasicBlock *NewIsland = MF->CreateMachineBasicBlock();
1493 MachineBasicBlock *NewMBB;
1495 if (findAvailableWater(U, UserOffset, IP)) {
1496 DEBUG(dbgs() << "Found water in range\n");
1497 MachineBasicBlock *WaterBB = *IP;
1499 // If the original WaterList entry was "new water" on this iteration,
1500 // propagate that to the new island. This is just keeping NewWaterList
1501 // updated to match the WaterList, which will be updated below.
1502 if (NewWaterList.erase(WaterBB))
1503 NewWaterList.insert(NewIsland);
1505 // The new CPE goes before the following block (NewMBB).
1506 NewMBB = std::next(MachineFunction::iterator(WaterBB));
1510 DEBUG(dbgs() << "No water found\n");
1511 createNewWater(CPUserIndex, UserOffset, NewMBB);
1513 // splitBlockBeforeInstr adds to WaterList, which is important when it is
1514 // called while handling branches so that the water will be seen on the
1515 // next iteration for constant pools, but in this context, we don't want
1516 // it. Check for this so it will be removed from the WaterList.
1517 // Also remove any entry from NewWaterList.
1518 MachineBasicBlock *WaterBB = std::prev(MachineFunction::iterator(NewMBB));
1519 IP = std::find(WaterList.begin(), WaterList.end(), WaterBB);
1520 if (IP != WaterList.end())
1521 NewWaterList.erase(WaterBB);
1523 // We are adding new water. Update NewWaterList.
1524 NewWaterList.insert(NewIsland);
1527 // Remove the original WaterList entry; we want subsequent insertions in
1528 // this vicinity to go after the one we're about to insert. This
1529 // considerably reduces the number of times we have to move the same CPE
1530 // more than once and is also important to ensure the algorithm terminates.
1531 if (IP != WaterList.end())
1532 WaterList.erase(IP);
1534 // Okay, we know we can put an island before NewMBB now, do it!
1535 MF->insert(NewMBB, NewIsland);
1537 // Update internal data structures to account for the newly inserted MBB.
1538 updateForInsertedWaterBlock(NewIsland);
1540 // Now that we have an island to add the CPE to, clone the original CPE and
1541 // add it to the island.
1542 U.HighWaterMark = NewIsland;
1543 U.CPEMI = BuildMI(NewIsland, DebugLoc(), CPEMI->getDesc())
1544 .addImm(ID).addOperand(CPEMI->getOperand(1)).addImm(Size);
1545 CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
1548 // Decrement the old entry, and remove it if refcount becomes 0.
1549 decrementCPEReferenceCount(CPI, CPEMI);
1551 // Mark the basic block as aligned as required by the const-pool entry.
1552 NewIsland->setAlignment(getCPELogAlign(U.CPEMI));
1554 // Increase the size of the island block to account for the new entry.
1555 BBInfo[NewIsland->getNumber()].Size += Size;
1556 adjustBBOffsetsAfter(std::prev(MachineFunction::iterator(NewIsland)));
1558 // Finally, change the CPI in the instruction operand to be ID.
1559 for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
1560 if (UserMI->getOperand(i).isCPI()) {
1561 UserMI->getOperand(i).setIndex(ID);
1565 DEBUG(dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI
1566 << format(" offset=%#x\n", BBInfo[NewIsland->getNumber()].Offset));
1571 /// removeDeadCPEMI - Remove a dead constant pool entry instruction. Update
1572 /// sizes and offsets of impacted basic blocks.
1573 void ARMConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) {
1574 MachineBasicBlock *CPEBB = CPEMI->getParent();
1575 unsigned Size = CPEMI->getOperand(2).getImm();
1576 CPEMI->eraseFromParent();
1577 BBInfo[CPEBB->getNumber()].Size -= Size;
1578 // All succeeding offsets have the current size value added in, fix this.
1579 if (CPEBB->empty()) {
1580 BBInfo[CPEBB->getNumber()].Size = 0;
1582 // This block no longer needs to be aligned.
1583 CPEBB->setAlignment(0);
1585 // Entries are sorted by descending alignment, so realign from the front.
1586 CPEBB->setAlignment(getCPELogAlign(CPEBB->begin()));
1588 adjustBBOffsetsAfter(CPEBB);
1589 // An island has only one predecessor BB and one successor BB. Check if
1590 // this BB's predecessor jumps directly to this BB's successor. This
1591 // shouldn't happen currently.
1592 assert(!BBIsJumpedOver(CPEBB) && "How did this happen?");
1593 // FIXME: remove the empty blocks after all the work is done?
1596 /// removeUnusedCPEntries - Remove constant pool entries whose refcounts
1598 bool ARMConstantIslands::removeUnusedCPEntries() {
1599 unsigned MadeChange = false;
1600 for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
1601 std::vector<CPEntry> &CPEs = CPEntries[i];
1602 for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
1603 if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
1604 removeDeadCPEMI(CPEs[j].CPEMI);
1605 CPEs[j].CPEMI = nullptr;
1613 /// isBBInRange - Returns true if the distance between specific MI and
1614 /// specific BB can fit in MI's displacement field.
1615 bool ARMConstantIslands::isBBInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
1617 unsigned PCAdj = isThumb ? 4 : 8;
1618 unsigned BrOffset = getOffsetOf(MI) + PCAdj;
1619 unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
1621 DEBUG(dbgs() << "Branch of destination BB#" << DestBB->getNumber()
1622 << " from BB#" << MI->getParent()->getNumber()
1623 << " max delta=" << MaxDisp
1624 << " from " << getOffsetOf(MI) << " to " << DestOffset
1625 << " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
1627 if (BrOffset <= DestOffset) {
1628 // Branch before the Dest.
1629 if (DestOffset-BrOffset <= MaxDisp)
1632 if (BrOffset-DestOffset <= MaxDisp)
1638 /// fixupImmediateBr - Fix up an immediate branch whose destination is too far
1639 /// away to fit in its displacement field.
1640 bool ARMConstantIslands::fixupImmediateBr(ImmBranch &Br) {
1641 MachineInstr *MI = Br.MI;
1642 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1644 // Check to see if the DestBB is already in-range.
1645 if (isBBInRange(MI, DestBB, Br.MaxDisp))
1649 return fixupUnconditionalBr(Br);
1650 return fixupConditionalBr(Br);
1653 /// fixupUnconditionalBr - Fix up an unconditional branch whose destination is
1654 /// too far away to fit in its displacement field. If the LR register has been
1655 /// spilled in the epilogue, then we can use BL to implement a far jump.
1656 /// Otherwise, add an intermediate branch instruction to a branch.
1658 ARMConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
1659 MachineInstr *MI = Br.MI;
1660 MachineBasicBlock *MBB = MI->getParent();
1662 llvm_unreachable("fixupUnconditionalBr is Thumb1 only!");
1664 // Use BL to implement far jump.
1665 Br.MaxDisp = (1 << 21) * 2;
1666 MI->setDesc(TII->get(ARM::tBfar));
1667 BBInfo[MBB->getNumber()].Size += 2;
1668 adjustBBOffsetsAfter(MBB);
1672 DEBUG(dbgs() << " Changed B to long jump " << *MI);
1677 /// fixupConditionalBr - Fix up a conditional branch whose destination is too
1678 /// far away to fit in its displacement field. It is converted to an inverse
1679 /// conditional branch + an unconditional branch to the destination.
1681 ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {
1682 MachineInstr *MI = Br.MI;
1683 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1685 // Add an unconditional branch to the destination and invert the branch
1686 // condition to jump over it:
1692 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm();
1693 CC = ARMCC::getOppositeCondition(CC);
1694 unsigned CCReg = MI->getOperand(2).getReg();
1696 // If the branch is at the end of its MBB and that has a fall-through block,
1697 // direct the updated conditional branch to the fall-through block. Otherwise,
1698 // split the MBB before the next instruction.
1699 MachineBasicBlock *MBB = MI->getParent();
1700 MachineInstr *BMI = &MBB->back();
1701 bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
1705 if (std::next(MachineBasicBlock::iterator(MI)) == std::prev(MBB->end()) &&
1706 BMI->getOpcode() == Br.UncondBr) {
1707 // Last MI in the BB is an unconditional branch. Can we simply invert the
1708 // condition and swap destinations:
1714 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
1715 if (isBBInRange(MI, NewDest, Br.MaxDisp)) {
1716 DEBUG(dbgs() << " Invert Bcc condition and swap its destination with "
1718 BMI->getOperand(0).setMBB(DestBB);
1719 MI->getOperand(0).setMBB(NewDest);
1720 MI->getOperand(1).setImm(CC);
1727 splitBlockBeforeInstr(MI);
1728 // No need for the branch to the next block. We're adding an unconditional
1729 // branch to the destination.
1730 int delta = TII->GetInstSizeInBytes(&MBB->back());
1731 BBInfo[MBB->getNumber()].Size -= delta;
1732 MBB->back().eraseFromParent();
1733 // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
1735 MachineBasicBlock *NextBB = std::next(MachineFunction::iterator(MBB));
1737 DEBUG(dbgs() << " Insert B to BB#" << DestBB->getNumber()
1738 << " also invert condition and change dest. to BB#"
1739 << NextBB->getNumber() << "\n");
1741 // Insert a new conditional branch and a new unconditional branch.
1742 // Also update the ImmBranch as well as adding a new entry for the new branch.
1743 BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
1744 .addMBB(NextBB).addImm(CC).addReg(CCReg);
1745 Br.MI = &MBB->back();
1746 BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
1748 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)
1749 .addImm(ARMCC::AL).addReg(0);
1751 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1752 BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
1753 unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
1754 ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
1756 // Remove the old conditional branch. It may or may not still be in MBB.
1757 BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(MI);
1758 MI->eraseFromParent();
1759 adjustBBOffsetsAfter(MBB);
1763 /// undoLRSpillRestore - Remove Thumb push / pop instructions that only spills
1764 /// LR / restores LR to pc. FIXME: This is done here because it's only possible
1765 /// to do this if tBfar is not used.
1766 bool ARMConstantIslands::undoLRSpillRestore() {
1767 bool MadeChange = false;
1768 for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
1769 MachineInstr *MI = PushPopMIs[i];
1770 // First two operands are predicates.
1771 if (MI->getOpcode() == ARM::tPOP_RET &&
1772 MI->getOperand(2).getReg() == ARM::PC &&
1773 MI->getNumExplicitOperands() == 3) {
1774 // Create the new insn and copy the predicate from the old.
1775 BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET))
1776 .addOperand(MI->getOperand(0))
1777 .addOperand(MI->getOperand(1));
1778 MI->eraseFromParent();
1785 // mayOptimizeThumb2Instruction - Returns true if optimizeThumb2Instructions
1786 // below may shrink MI.
1788 ARMConstantIslands::mayOptimizeThumb2Instruction(const MachineInstr *MI) const {
1789 switch(MI->getOpcode()) {
1790 // optimizeThumb2Instructions.
1791 case ARM::t2LEApcrel:
1793 // optimizeThumb2Branches.
1797 // optimizeThumb2JumpTables.
1804 bool ARMConstantIslands::optimizeThumb2Instructions() {
1805 bool MadeChange = false;
1807 // Shrink ADR and LDR from constantpool.
1808 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
1809 CPUser &U = CPUsers[i];
1810 unsigned Opcode = U.MI->getOpcode();
1811 unsigned NewOpc = 0;
1816 case ARM::t2LEApcrel:
1817 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1818 NewOpc = ARM::tLEApcrel;
1824 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1825 NewOpc = ARM::tLDRpci;
1835 unsigned UserOffset = getUserOffset(U);
1836 unsigned MaxOffs = ((1 << Bits) - 1) * Scale;
1838 // Be conservative with inline asm.
1839 if (!U.KnownAlignment)
1842 // FIXME: Check if offset is multiple of scale if scale is not 4.
1843 if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) {
1844 DEBUG(dbgs() << "Shrink: " << *U.MI);
1845 U.MI->setDesc(TII->get(NewOpc));
1846 MachineBasicBlock *MBB = U.MI->getParent();
1847 BBInfo[MBB->getNumber()].Size -= 2;
1848 adjustBBOffsetsAfter(MBB);
1854 MadeChange |= optimizeThumb2Branches();
1855 MadeChange |= optimizeThumb2JumpTables();
1859 bool ARMConstantIslands::optimizeThumb2Branches() {
1860 bool MadeChange = false;
1862 // The order in which branches appear in ImmBranches is approximately their
1863 // order within the function body. By visiting later branches first, we reduce
1864 // the distance between earlier forward branches and their targets, making it
1865 // more likely that the cbn?z optimization, which can only apply to forward
1866 // branches, will succeed.
1867 for (unsigned i = ImmBranches.size(); i != 0; --i) {
1868 ImmBranch &Br = ImmBranches[i-1];
1869 unsigned Opcode = Br.MI->getOpcode();
1870 unsigned NewOpc = 0;
1888 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
1889 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1890 if (isBBInRange(Br.MI, DestBB, MaxOffs)) {
1891 DEBUG(dbgs() << "Shrink branch: " << *Br.MI);
1892 Br.MI->setDesc(TII->get(NewOpc));
1893 MachineBasicBlock *MBB = Br.MI->getParent();
1894 BBInfo[MBB->getNumber()].Size -= 2;
1895 adjustBBOffsetsAfter(MBB);
1901 Opcode = Br.MI->getOpcode();
1902 if (Opcode != ARM::tBcc)
1905 // If the conditional branch doesn't kill CPSR, then CPSR can be liveout
1906 // so this transformation is not safe.
1907 if (!Br.MI->killsRegister(ARM::CPSR))
1911 unsigned PredReg = 0;
1912 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg);
1913 if (Pred == ARMCC::EQ)
1915 else if (Pred == ARMCC::NE)
1916 NewOpc = ARM::tCBNZ;
1919 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1920 // Check if the distance is within 126. Subtract starting offset by 2
1921 // because the cmp will be eliminated.
1922 unsigned BrOffset = getOffsetOf(Br.MI) + 4 - 2;
1923 unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
1924 if (BrOffset < DestOffset && (DestOffset - BrOffset) <= 126) {
1925 MachineBasicBlock::iterator CmpMI = Br.MI;
1926 if (CmpMI != Br.MI->getParent()->begin()) {
1928 if (CmpMI->getOpcode() == ARM::tCMPi8) {
1929 unsigned Reg = CmpMI->getOperand(0).getReg();
1930 Pred = getInstrPredicate(CmpMI, PredReg);
1931 if (Pred == ARMCC::AL &&
1932 CmpMI->getOperand(1).getImm() == 0 &&
1933 isARMLowRegister(Reg)) {
1934 MachineBasicBlock *MBB = Br.MI->getParent();
1935 DEBUG(dbgs() << "Fold: " << *CmpMI << " and: " << *Br.MI);
1936 MachineInstr *NewBR =
1937 BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc))
1938 .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags());
1939 CmpMI->eraseFromParent();
1940 Br.MI->eraseFromParent();
1942 BBInfo[MBB->getNumber()].Size -= 2;
1943 adjustBBOffsetsAfter(MBB);
1955 static bool isSimpleIndexCalc(MachineInstr &I, unsigned EntryReg,
1957 if (I.getOpcode() != ARM::t2ADDrs)
1960 if (I.getOperand(0).getReg() != EntryReg)
1963 if (I.getOperand(1).getReg() != BaseReg)
1966 // FIXME: what about CC and IdxReg?
1970 /// \brief While trying to form a TBB/TBH instruction, we may (if the table
1971 /// doesn't immediately follow the BR_JT) need access to the start of the
1972 /// jump-table. We know one instruction that produces such a register; this
1973 /// function works out whether that definition can be preserved to the BR_JT,
1974 /// possibly by removing an intervening addition (which is usually needed to
1975 /// calculate the actual entry to jump to).
1976 bool ARMConstantIslands::preserveBaseRegister(MachineInstr *JumpMI,
1977 MachineInstr *LEAMI,
1980 bool &BaseRegKill) {
1981 if (JumpMI->getParent() != LEAMI->getParent())
1984 // Now we hope that we have at least these instructions in the basic block:
1985 // BaseReg = t2LEA ...
1987 // EntryReg = t2ADDrs BaseReg, ...
1991 // We have to be very conservative about what we recognise here though. The
1992 // main perturbing factors to watch out for are:
1993 // + Spills at any point in the chain: not direct problems but we would
1994 // expect a blocking Def of the spilled register so in practice what we
1995 // can do is limited.
1996 // + EntryReg == BaseReg: this is the one situation we should allow a Def
1997 // of BaseReg, but only if the t2ADDrs can be removed.
1998 // + Some instruction other than t2ADDrs computing the entry. Not seen in
1999 // the wild, but we should be careful.
2000 unsigned EntryReg = JumpMI->getOperand(0).getReg();
2001 unsigned BaseReg = LEAMI->getOperand(0).getReg();
2003 CanDeleteLEA = true;
2004 BaseRegKill = false;
2005 MachineInstr *RemovableAdd = nullptr;
2006 MachineBasicBlock::iterator I(LEAMI);
2007 for (++I; &*I != JumpMI; ++I) {
2008 if (isSimpleIndexCalc(*I, EntryReg, BaseReg)) {
2013 for (unsigned K = 0, E = I->getNumOperands(); K != E; ++K) {
2014 const MachineOperand &MO = I->getOperand(K);
2015 if (!MO.isReg() || !MO.getReg())
2017 if (MO.isDef() && MO.getReg() == BaseReg)
2019 if (MO.isUse() && MO.getReg() == BaseReg) {
2020 BaseRegKill = BaseRegKill || MO.isKill();
2021 CanDeleteLEA = false;
2029 // Check the add really is removable, and that nothing else in the block
2030 // clobbers BaseReg.
2031 for (++I; &*I != JumpMI; ++I) {
2032 for (unsigned K = 0, E = I->getNumOperands(); K != E; ++K) {
2033 const MachineOperand &MO = I->getOperand(K);
2034 if (!MO.isReg() || !MO.getReg())
2036 if (MO.isDef() && MO.getReg() == BaseReg)
2038 if (MO.isUse() && MO.getReg() == EntryReg)
2039 RemovableAdd = nullptr;
2044 RemovableAdd->eraseFromParent();
2046 } else if (BaseReg == EntryReg) {
2047 // The add wasn't removable, but clobbered the base for the TBB. So we can't
2052 // We reached the end of the block without seeing another definition of
2053 // BaseReg (except, possibly the t2ADDrs, which was removed). BaseReg can be
2054 // used in the TBB/TBH if necessary.
2058 /// \brief Returns whether CPEMI is the first instruction in the block
2059 /// immediately following JTMI (assumed to be a TBB or TBH terminator). If so,
2060 /// we can switch the first register to PC and usually remove the address
2061 /// calculation that preceeded it.
2062 static bool jumpTableFollowsTB(MachineInstr *JTMI, MachineInstr *CPEMI) {
2063 MachineFunction::iterator MBB = JTMI->getParent();
2064 MachineFunction *MF = MBB->getParent();
2067 return MBB != MF->end() && MBB->begin() != MBB->end() &&
2068 &*MBB->begin() == CPEMI;
2071 /// optimizeThumb2JumpTables - Use tbb / tbh instructions to generate smaller
2072 /// jumptables when it's possible.
2073 bool ARMConstantIslands::optimizeThumb2JumpTables() {
2074 bool MadeChange = false;
2076 // FIXME: After the tables are shrunk, can we get rid some of the
2077 // constantpool tables?
2078 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
2079 if (!MJTI) return false;
2081 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
2082 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
2083 MachineInstr *MI = T2JumpTables[i];
2084 const MCInstrDesc &MCID = MI->getDesc();
2085 unsigned NumOps = MCID.getNumOperands();
2086 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 2 : 1);
2087 MachineOperand JTOP = MI->getOperand(JTOpIdx);
2088 unsigned JTI = JTOP.getIndex();
2089 assert(JTI < JT.size());
2092 bool HalfWordOk = true;
2093 unsigned JTOffset = getOffsetOf(MI) + 4;
2094 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
2095 for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
2096 MachineBasicBlock *MBB = JTBBs[j];
2097 unsigned DstOffset = BBInfo[MBB->getNumber()].Offset;
2098 // Negative offset is not ok. FIXME: We should change BB layout to make
2099 // sure all the branches are forward.
2100 if (ByteOk && (DstOffset - JTOffset) > ((1<<8)-1)*2)
2102 unsigned TBHLimit = ((1<<16)-1)*2;
2103 if (HalfWordOk && (DstOffset - JTOffset) > TBHLimit)
2105 if (!ByteOk && !HalfWordOk)
2109 if (!ByteOk && !HalfWordOk)
2112 MachineBasicBlock *MBB = MI->getParent();
2113 if (!MI->getOperand(0).isKill()) // FIXME: needed now?
2115 unsigned IdxReg = MI->getOperand(1).getReg();
2116 bool IdxRegKill = MI->getOperand(1).isKill();
2118 CPUser &User = CPUsers[JumpTableUserIndices[JTI]];
2119 unsigned DeadSize = 0;
2120 bool CanDeleteLEA = false;
2121 bool BaseRegKill = false;
2122 bool PreservedBaseReg =
2123 preserveBaseRegister(MI, User.MI, DeadSize, CanDeleteLEA, BaseRegKill);
2125 if (!jumpTableFollowsTB(MI, User.CPEMI) && !PreservedBaseReg)
2128 DEBUG(dbgs() << "Shrink JT: " << *MI);
2129 MachineInstr *CPEMI = User.CPEMI;
2130 unsigned Opc = ByteOk ? ARM::t2TBB_JT : ARM::t2TBH_JT;
2131 MachineBasicBlock::iterator MI_JT = MI;
2132 MachineInstr *NewJTMI =
2133 BuildMI(*MBB, MI_JT, MI->getDebugLoc(), TII->get(Opc))
2134 .addReg(User.MI->getOperand(0).getReg(),
2135 getKillRegState(BaseRegKill))
2136 .addReg(IdxReg, getKillRegState(IdxRegKill))
2137 .addJumpTableIndex(JTI, JTOP.getTargetFlags())
2138 .addImm(CPEMI->getOperand(0).getImm());
2139 DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": " << *NewJTMI);
2141 unsigned JTOpc = ByteOk ? ARM::JUMPTABLE_TBB : ARM::JUMPTABLE_TBH;
2142 CPEMI->setDesc(TII->get(JTOpc));
2144 if (jumpTableFollowsTB(MI, User.CPEMI)) {
2145 NewJTMI->getOperand(0).setReg(ARM::PC);
2146 NewJTMI->getOperand(0).setIsKill(false);
2149 User.MI->eraseFromParent();
2152 // The LEA was eliminated, the TBB instruction becomes the only new user
2153 // of the jump table.
2157 User.IsSoImm = false;
2158 User.KnownAlignment = false;
2160 // The LEA couldn't be eliminated, so we must add another CPUser to
2161 // record the TBB or TBH use.
2162 int CPEntryIdx = JumpTableEntryIndices[JTI];
2163 auto &CPEs = CPEntries[CPEntryIdx];
2164 auto Entry = std::find_if(CPEs.begin(), CPEs.end(), [&](CPEntry &E) {
2165 return E.CPEMI == User.CPEMI;
2168 CPUsers.emplace_back(CPUser(NewJTMI, User.CPEMI, 4, false, false));
2172 unsigned NewSize = TII->GetInstSizeInBytes(NewJTMI);
2173 unsigned OrigSize = TII->GetInstSizeInBytes(MI);
2174 MI->eraseFromParent();
2176 int Delta = OrigSize - NewSize + DeadSize;
2177 BBInfo[MBB->getNumber()].Size -= Delta;
2178 adjustBBOffsetsAfter(MBB);
2187 /// reorderThumb2JumpTables - Adjust the function's block layout to ensure that
2188 /// jump tables always branch forwards, since that's what tbb and tbh need.
2189 bool ARMConstantIslands::reorderThumb2JumpTables() {
2190 bool MadeChange = false;
2192 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
2193 if (!MJTI) return false;
2195 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
2196 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
2197 MachineInstr *MI = T2JumpTables[i];
2198 const MCInstrDesc &MCID = MI->getDesc();
2199 unsigned NumOps = MCID.getNumOperands();
2200 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 2 : 1);
2201 MachineOperand JTOP = MI->getOperand(JTOpIdx);
2202 unsigned JTI = JTOP.getIndex();
2203 assert(JTI < JT.size());
2205 // We prefer if target blocks for the jump table come after the jump
2206 // instruction so we can use TB[BH]. Loop through the target blocks
2207 // and try to adjust them such that that's true.
2208 int JTNumber = MI->getParent()->getNumber();
2209 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
2210 for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
2211 MachineBasicBlock *MBB = JTBBs[j];
2212 int DTNumber = MBB->getNumber();
2214 if (DTNumber < JTNumber) {
2215 // The destination precedes the switch. Try to move the block forward
2216 // so we have a positive offset.
2217 MachineBasicBlock *NewBB =
2218 adjustJTTargetBlockForward(MBB, MI->getParent());
2220 MJTI->ReplaceMBBInJumpTable(JTI, JTBBs[j], NewBB);
2229 MachineBasicBlock *ARMConstantIslands::
2230 adjustJTTargetBlockForward(MachineBasicBlock *BB, MachineBasicBlock *JTBB) {
2231 // If the destination block is terminated by an unconditional branch,
2232 // try to move it; otherwise, create a new block following the jump
2233 // table that branches back to the actual target. This is a very simple
2234 // heuristic. FIXME: We can definitely improve it.
2235 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
2236 SmallVector<MachineOperand, 4> Cond;
2237 SmallVector<MachineOperand, 4> CondPrior;
2238 MachineFunction::iterator BBi = BB;
2239 MachineFunction::iterator OldPrior = std::prev(BBi);
2241 // If the block terminator isn't analyzable, don't try to move the block
2242 bool B = TII->AnalyzeBranch(*BB, TBB, FBB, Cond);
2244 // If the block ends in an unconditional branch, move it. The prior block
2245 // has to have an analyzable terminator for us to move this one. Be paranoid
2246 // and make sure we're not trying to move the entry block of the function.
2247 if (!B && Cond.empty() && BB != MF->begin() &&
2248 !TII->AnalyzeBranch(*OldPrior, TBB, FBB, CondPrior)) {
2249 BB->moveAfter(JTBB);
2250 OldPrior->updateTerminator();
2251 BB->updateTerminator();
2252 // Update numbering to account for the block being moved.
2253 MF->RenumberBlocks();
2258 // Create a new MBB for the code after the jump BB.
2259 MachineBasicBlock *NewBB =
2260 MF->CreateMachineBasicBlock(JTBB->getBasicBlock());
2261 MachineFunction::iterator MBBI = JTBB; ++MBBI;
2262 MF->insert(MBBI, NewBB);
2264 // Add an unconditional branch from NewBB to BB.
2265 // There doesn't seem to be meaningful DebugInfo available; this doesn't
2266 // correspond directly to anything in the source.
2267 assert (isThumb2 && "Adjusting for TB[BH] but not in Thumb2?");
2268 BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B)).addMBB(BB)
2269 .addImm(ARMCC::AL).addReg(0);
2271 // Update internal data structures to account for the newly inserted MBB.
2272 MF->RenumberBlocks(NewBB);
2275 NewBB->addSuccessor(BB);
2276 JTBB->removeSuccessor(BB);
2277 JTBB->addSuccessor(NewBB);