1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-pseudo"
19 #include "ARMAddressingModes.h"
20 #include "ARMBaseInstrInfo.h"
21 #include "ARMBaseRegisterInfo.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMRegisterInfo.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
32 class ARMExpandPseudo : public MachineFunctionPass {
35 ARMExpandPseudo() : MachineFunctionPass(ID) {}
37 const ARMBaseInstrInfo *TII;
38 const TargetRegisterInfo *TRI;
40 virtual bool runOnMachineFunction(MachineFunction &Fn);
42 virtual const char *getPassName() const {
43 return "ARM pseudo instruction expansion pass";
47 void TransferImpOps(MachineInstr &OldMI,
48 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
49 bool ExpandMBB(MachineBasicBlock &MBB);
50 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
51 void ExpandVST(MachineBasicBlock::iterator &MBBI);
52 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
53 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
54 unsigned Opc, bool IsExt, unsigned NumRegs);
56 char ARMExpandPseudo::ID = 0;
59 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
60 /// the instructions created from the expansion.
61 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
62 MachineInstrBuilder &UseMI,
63 MachineInstrBuilder &DefMI) {
64 const TargetInstrDesc &Desc = OldMI.getDesc();
65 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
67 const MachineOperand &MO = OldMI.getOperand(i);
68 assert(MO.isReg() && MO.getReg());
77 // Constants for register spacing in NEON load/store instructions.
78 // For quad-register load-lane and store-lane pseudo instructors, the
79 // spacing is initially assumed to be EvenDblSpc, and that is changed to
80 // OddDblSpc depending on the lane number operand.
87 // Entries for NEON load/store information table. The table is sorted by
88 // PseudoOpc for fast binary-search lookups.
89 struct NEONLdStTableEntry {
94 NEONRegSpacing RegSpacing;
95 unsigned char NumRegs; // D registers loaded or stored
96 unsigned char RegElts; // elements per D register; used for lane ops
98 // Comparison methods for binary search of the table.
99 bool operator<(const NEONLdStTableEntry &TE) const {
100 return PseudoOpc < TE.PseudoOpc;
102 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
103 return TE.PseudoOpc < PseudoOpc;
105 friend bool ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
106 const NEONLdStTableEntry &TE) {
107 return PseudoOpc < TE.PseudoOpc;
112 static const NEONLdStTableEntry NEONLdStTable[] = {
113 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 },
114 { ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 },
115 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 },
116 { ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 },
118 { ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 },
119 { ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 },
120 { ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 },
121 { ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 },
122 { ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 },
123 { ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 },
124 { ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 },
125 { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 },
127 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 },
128 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 },
129 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 },
130 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 },
131 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 },
132 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 },
133 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 },
134 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 },
135 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 },
136 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 },
138 { ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 },
139 { ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 },
140 { ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 },
141 { ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 },
142 { ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 },
143 { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 },
145 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 },
146 { ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 },
147 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 },
148 { ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 },
149 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 },
150 { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 },
152 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 },
153 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 },
154 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 },
155 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 },
156 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 },
157 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 },
158 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 },
159 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 },
160 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 },
161 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 },
163 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 },
164 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 },
165 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 },
166 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 },
167 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 },
168 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 },
170 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 },
171 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 },
172 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 },
173 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 },
174 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 },
175 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 },
177 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 },
178 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 },
179 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 },
180 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 },
181 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 },
182 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 },
183 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 },
184 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 },
185 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 },
186 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 },
188 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 },
189 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 },
190 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 },
191 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 },
192 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 },
193 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 },
195 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 },
196 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 },
197 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 },
198 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 },
199 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 },
200 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 },
202 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 },
203 { ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 },
204 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 },
205 { ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 },
207 { ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 },
208 { ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 },
209 { ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 },
210 { ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 },
211 { ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 },
212 { ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 },
213 { ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 },
214 { ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 },
216 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 },
217 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 },
218 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 },
219 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 },
220 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 },
221 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 },
222 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4},
223 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4},
224 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2},
225 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2},
227 { ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 },
228 { ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 },
229 { ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 },
230 { ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 },
231 { ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 },
232 { ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 },
234 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 },
235 { ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 },
236 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 },
237 { ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 },
238 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 },
239 { ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 },
241 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 },
242 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 },
243 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 },
244 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 },
245 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 },
246 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 },
247 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4},
248 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4},
249 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2},
250 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2},
252 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 },
253 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 },
254 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 },
255 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 },
256 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 },
257 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 },
259 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 },
260 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 },
261 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 },
262 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 },
263 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 },
264 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 },
266 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 },
267 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 },
268 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 },
269 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 },
270 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 },
271 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 },
272 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4},
273 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4},
274 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2},
275 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2},
277 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 },
278 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 },
279 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 },
280 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 },
281 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 },
282 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 },
284 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 },
285 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 },
286 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 },
287 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 },
288 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 },
289 { ARM::VST4q8oddPseudo_UPD , ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 }
292 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
293 /// load or store pseudo instruction.
294 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
295 unsigned NumEntries = array_lengthof(NEONLdStTable);
298 // Make sure the table is sorted.
299 static bool TableChecked = false;
301 for (unsigned i = 0; i != NumEntries-1; ++i)
302 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
303 "NEONLdStTable is not sorted!");
308 const NEONLdStTableEntry *I =
309 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
310 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
315 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
316 /// corresponding to the specified register spacing. Not all of the results
317 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
318 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
319 const TargetRegisterInfo *TRI, unsigned &D0,
320 unsigned &D1, unsigned &D2, unsigned &D3) {
321 if (RegSpc == SingleSpc) {
322 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
323 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
324 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
325 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
326 } else if (RegSpc == EvenDblSpc) {
327 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
328 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
329 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
330 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
332 assert(RegSpc == OddDblSpc && "unknown register spacing");
333 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
334 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
335 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
336 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
340 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
341 /// operands to real VLD instructions with D register operands.
342 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
343 MachineInstr &MI = *MBBI;
344 MachineBasicBlock &MBB = *MI.getParent();
346 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
347 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
348 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
349 unsigned NumRegs = TableEntry->NumRegs;
351 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
352 TII->get(TableEntry->RealOpc));
355 bool DstIsDead = MI.getOperand(OpIdx).isDead();
356 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
357 unsigned D0, D1, D2, D3;
358 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
359 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
360 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
362 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
364 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
366 if (TableEntry->HasWriteBack)
367 MIB.addOperand(MI.getOperand(OpIdx++));
369 // Copy the addrmode6 operands.
370 MIB.addOperand(MI.getOperand(OpIdx++));
371 MIB.addOperand(MI.getOperand(OpIdx++));
372 // Copy the am6offset operand.
373 if (TableEntry->HasWriteBack)
374 MIB.addOperand(MI.getOperand(OpIdx++));
376 // For an instruction writing double-spaced subregs, the pseudo instruction
377 // has an extra operand that is a use of the super-register. Record the
378 // operand index and skip over it.
379 unsigned SrcOpIdx = 0;
380 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
383 // Copy the predicate operands.
384 MIB.addOperand(MI.getOperand(OpIdx++));
385 MIB.addOperand(MI.getOperand(OpIdx++));
387 // Copy the super-register source operand used for double-spaced subregs over
388 // to the new instruction as an implicit operand.
390 MachineOperand MO = MI.getOperand(SrcOpIdx);
391 MO.setImplicit(true);
394 // Add an implicit def for the super-register.
395 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
396 TransferImpOps(MI, MIB, MIB);
397 MI.eraseFromParent();
400 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
401 /// operands to real VST instructions with D register operands.
402 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
403 MachineInstr &MI = *MBBI;
404 MachineBasicBlock &MBB = *MI.getParent();
406 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
407 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
408 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
409 unsigned NumRegs = TableEntry->NumRegs;
411 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
412 TII->get(TableEntry->RealOpc));
414 if (TableEntry->HasWriteBack)
415 MIB.addOperand(MI.getOperand(OpIdx++));
417 // Copy the addrmode6 operands.
418 MIB.addOperand(MI.getOperand(OpIdx++));
419 MIB.addOperand(MI.getOperand(OpIdx++));
420 // Copy the am6offset operand.
421 if (TableEntry->HasWriteBack)
422 MIB.addOperand(MI.getOperand(OpIdx++));
424 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
425 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
426 unsigned D0, D1, D2, D3;
427 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
428 MIB.addReg(D0).addReg(D1);
434 // Copy the predicate operands.
435 MIB.addOperand(MI.getOperand(OpIdx++));
436 MIB.addOperand(MI.getOperand(OpIdx++));
439 // Add an implicit kill for the super-reg.
440 (*MIB).addRegisterKilled(SrcReg, TRI, true);
441 TransferImpOps(MI, MIB, MIB);
442 MI.eraseFromParent();
445 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
446 /// register operands to real instructions with D register operands.
447 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
448 MachineInstr &MI = *MBBI;
449 MachineBasicBlock &MBB = *MI.getParent();
451 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
452 assert(TableEntry && "NEONLdStTable lookup failed");
453 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
454 unsigned NumRegs = TableEntry->NumRegs;
455 unsigned RegElts = TableEntry->RegElts;
457 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
458 TII->get(TableEntry->RealOpc));
460 // The lane operand is always the 3rd from last operand, before the 2
461 // predicate operands.
462 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
464 // Adjust the lane and spacing as needed for Q registers.
465 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
466 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
470 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
472 unsigned D0, D1, D2, D3;
474 bool DstIsDead = false;
475 if (TableEntry->IsLoad) {
476 DstIsDead = MI.getOperand(OpIdx).isDead();
477 DstReg = MI.getOperand(OpIdx++).getReg();
478 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
479 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
480 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
482 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
484 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
487 if (TableEntry->HasWriteBack)
488 MIB.addOperand(MI.getOperand(OpIdx++));
490 // Copy the addrmode6 operands.
491 MIB.addOperand(MI.getOperand(OpIdx++));
492 MIB.addOperand(MI.getOperand(OpIdx++));
493 // Copy the am6offset operand.
494 if (TableEntry->HasWriteBack)
495 MIB.addOperand(MI.getOperand(OpIdx++));
497 // Grab the super-register source.
498 MachineOperand MO = MI.getOperand(OpIdx++);
499 if (!TableEntry->IsLoad)
500 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
502 // Add the subregs as sources of the new instruction.
503 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
504 getKillRegState(MO.isKill()));
505 MIB.addReg(D0, SrcFlags).addReg(D1, SrcFlags);
507 MIB.addReg(D2, SrcFlags);
509 MIB.addReg(D3, SrcFlags);
511 // Add the lane number operand.
515 // Copy the predicate operands.
516 MIB.addOperand(MI.getOperand(OpIdx++));
517 MIB.addOperand(MI.getOperand(OpIdx++));
519 // Copy the super-register source to be an implicit source.
520 MO.setImplicit(true);
522 if (TableEntry->IsLoad)
523 // Add an implicit def for the super-register.
524 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
525 TransferImpOps(MI, MIB, MIB);
526 MI.eraseFromParent();
529 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
530 /// register operands to real instructions with D register operands.
531 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
532 unsigned Opc, bool IsExt, unsigned NumRegs) {
533 MachineInstr &MI = *MBBI;
534 MachineBasicBlock &MBB = *MI.getParent();
536 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
539 // Transfer the destination register operand.
540 MIB.addOperand(MI.getOperand(OpIdx++));
542 MIB.addOperand(MI.getOperand(OpIdx++));
544 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
545 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
546 unsigned D0, D1, D2, D3;
547 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
548 MIB.addReg(D0).addReg(D1);
554 // Copy the other source register operand.
555 MIB.addOperand(MI.getOperand(OpIdx++));
557 // Copy the predicate operands.
558 MIB.addOperand(MI.getOperand(OpIdx++));
559 MIB.addOperand(MI.getOperand(OpIdx++));
562 // Add an implicit kill for the super-reg.
563 (*MIB).addRegisterKilled(SrcReg, TRI, true);
564 TransferImpOps(MI, MIB, MIB);
565 MI.eraseFromParent();
568 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
569 bool Modified = false;
571 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
573 MachineInstr &MI = *MBBI;
574 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
576 bool ModifiedOp = true;
577 unsigned Opcode = MI.getOpcode();
583 case ARM::Int_eh_sjlj_dispatchsetup: {
584 MachineFunction &MF = *MI.getParent()->getParent();
585 const ARMBaseInstrInfo *AII =
586 static_cast<const ARMBaseInstrInfo*>(TII);
587 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
588 // For functions using a base pointer, we rematerialize it (via the frame
589 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
590 // for us. Otherwise, expand to nothing.
591 if (RI.hasBasePointer(MF)) {
592 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
593 int32_t NumBytes = AFI->getFramePtrSpillOffset();
594 unsigned FramePtr = RI.getFrameRegister(MF);
595 assert (RI.hasFP(MF) && "base pointer without frame pointer?");
597 if (AFI->isThumb2Function()) {
598 llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
599 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
600 } else if (AFI->isThumbFunction()) {
601 llvm::emitThumbRegPlusImmediate(MBB, MBBI, ARM::R6,
603 *TII, RI, MI.getDebugLoc());
605 llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
606 FramePtr, -NumBytes, ARMCC::AL, 0,
609 // If there's dynamic realignment, adjust for it.
610 if (RI.needsStackRealignment(MF)) {
611 MachineFrameInfo *MFI = MF.getFrameInfo();
612 unsigned MaxAlign = MFI->getMaxAlignment();
613 assert (!AFI->isThumb1OnlyFunction());
614 // Emit bic r6, r6, MaxAlign
615 unsigned bicOpc = AFI->isThumbFunction() ?
616 ARM::t2BICri : ARM::BICri;
617 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
618 TII->get(bicOpc), ARM::R6)
619 .addReg(ARM::R6, RegState::Kill)
620 .addImm(MaxAlign-1)));
624 MI.eraseFromParent();
628 case ARM::MOVsrl_flag:
629 case ARM::MOVsra_flag: {
630 // These are just fancy MOVs insructions.
631 MachineInstrBuilder MIB =
632 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
633 MI.getOperand(0).getReg())
634 .addOperand(MI.getOperand(1))
636 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr
638 .addReg(ARM::CPSR, RegState::Define);
639 MI.eraseFromParent();
643 // This encodes as "MOVs Rd, Rm, rrx
644 MachineInstrBuilder MIB =
645 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
646 MI.getOperand(0).getReg())
647 .addOperand(MI.getOperand(1))
648 .addOperand(MI.getOperand(1))
649 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
651 TransferImpOps(MI, MIB, MIB);
652 MI.eraseFromParent();
655 case ARM::tLDRpci_pic:
656 case ARM::t2LDRpci_pic: {
657 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
658 ? ARM::tLDRpci : ARM::t2LDRpci;
659 unsigned DstReg = MI.getOperand(0).getReg();
660 bool DstIsDead = MI.getOperand(0).isDead();
661 MachineInstrBuilder MIB1 =
662 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
663 TII->get(NewLdOpc), DstReg)
664 .addOperand(MI.getOperand(1)));
665 (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
666 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
667 TII->get(ARM::tPICADD))
668 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
670 .addOperand(MI.getOperand(2));
671 TransferImpOps(MI, MIB1, MIB2);
672 MI.eraseFromParent();
677 case ARM::t2MOVi32imm: {
678 unsigned PredReg = 0;
679 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
680 unsigned DstReg = MI.getOperand(0).getReg();
681 bool DstIsDead = MI.getOperand(0).isDead();
682 const MachineOperand &MO = MI.getOperand(1);
683 MachineInstrBuilder LO16, HI16;
685 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
686 TII->get(Opcode == ARM::MOVi32imm ?
687 ARM::MOVi16 : ARM::t2MOVi16),
689 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
690 TII->get(Opcode == ARM::MOVi32imm ?
691 ARM::MOVTi16 : ARM::t2MOVTi16))
692 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
696 unsigned Imm = MO.getImm();
697 unsigned Lo16 = Imm & 0xffff;
698 unsigned Hi16 = (Imm >> 16) & 0xffff;
699 LO16 = LO16.addImm(Lo16);
700 HI16 = HI16.addImm(Hi16);
702 const GlobalValue *GV = MO.getGlobal();
703 unsigned TF = MO.getTargetFlags();
704 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
705 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
707 (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
708 (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
709 LO16.addImm(Pred).addReg(PredReg);
710 HI16.addImm(Pred).addReg(PredReg);
711 TransferImpOps(MI, LO16, HI16);
712 MI.eraseFromParent();
717 unsigned DstReg = MI.getOperand(0).getReg();
718 bool DstIsDead = MI.getOperand(0).isDead();
719 unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0);
720 unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1);
721 unsigned SrcReg = MI.getOperand(1).getReg();
722 bool SrcIsKill = MI.getOperand(1).isKill();
723 unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0);
724 unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1);
725 MachineInstrBuilder Even =
726 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
727 TII->get(ARM::VMOVQ))
729 RegState::Define | getDeadRegState(DstIsDead))
730 .addReg(EvenSrc, getKillRegState(SrcIsKill)));
731 MachineInstrBuilder Odd =
732 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
733 TII->get(ARM::VMOVQ))
735 RegState::Define | getDeadRegState(DstIsDead))
736 .addReg(OddSrc, getKillRegState(SrcIsKill)));
737 TransferImpOps(MI, Even, Odd);
738 MI.eraseFromParent();
743 MachineInstrBuilder MIB =
744 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VLDMD));
746 // Grab the Q register destination.
747 bool DstIsDead = MI.getOperand(OpIdx).isDead();
748 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
749 // Copy the addrmode4 operands.
750 MIB.addOperand(MI.getOperand(OpIdx++));
751 MIB.addOperand(MI.getOperand(OpIdx++));
752 // Copy the predicate operands.
753 MIB.addOperand(MI.getOperand(OpIdx++));
754 MIB.addOperand(MI.getOperand(OpIdx++));
755 // Add the destination operands (D subregs).
756 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
757 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
758 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
759 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
760 // Add an implicit def for the super-register.
761 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
762 TransferImpOps(MI, MIB, MIB);
763 MI.eraseFromParent();
768 MachineInstrBuilder MIB =
769 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VSTMD));
771 // Grab the Q register source.
772 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
773 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
774 // Copy the addrmode4 operands.
775 MIB.addOperand(MI.getOperand(OpIdx++));
776 MIB.addOperand(MI.getOperand(OpIdx++));
777 // Copy the predicate operands.
778 MIB.addOperand(MI.getOperand(OpIdx++));
779 MIB.addOperand(MI.getOperand(OpIdx++));
780 // Add the source operands (D subregs).
781 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
782 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
783 MIB.addReg(D0).addReg(D1);
785 // Add an implicit kill for the Q register.
786 (*MIB).addRegisterKilled(SrcReg, TRI, true);
787 TransferImpOps(MI, MIB, MIB);
788 MI.eraseFromParent();
793 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLNfq : ARM::VDUPLNfd;
794 MachineInstrBuilder MIB =
795 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
797 unsigned SrcReg = MI.getOperand(1).getReg();
798 unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
799 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
800 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
801 // The lane is [0,1] for the containing DReg superregister.
802 // Copy the dst/src register operands.
803 MIB.addOperand(MI.getOperand(OpIdx++));
806 // Add the lane select operand.
808 // Add the predicate operands.
809 MIB.addOperand(MI.getOperand(OpIdx++));
810 MIB.addOperand(MI.getOperand(OpIdx++));
812 TransferImpOps(MI, MIB, MIB);
813 MI.eraseFromParent();
817 case ARM::VLD1q8Pseudo:
818 case ARM::VLD1q16Pseudo:
819 case ARM::VLD1q32Pseudo:
820 case ARM::VLD1q64Pseudo:
821 case ARM::VLD1q8Pseudo_UPD:
822 case ARM::VLD1q16Pseudo_UPD:
823 case ARM::VLD1q32Pseudo_UPD:
824 case ARM::VLD1q64Pseudo_UPD:
825 case ARM::VLD2d8Pseudo:
826 case ARM::VLD2d16Pseudo:
827 case ARM::VLD2d32Pseudo:
828 case ARM::VLD2q8Pseudo:
829 case ARM::VLD2q16Pseudo:
830 case ARM::VLD2q32Pseudo:
831 case ARM::VLD2d8Pseudo_UPD:
832 case ARM::VLD2d16Pseudo_UPD:
833 case ARM::VLD2d32Pseudo_UPD:
834 case ARM::VLD2q8Pseudo_UPD:
835 case ARM::VLD2q16Pseudo_UPD:
836 case ARM::VLD2q32Pseudo_UPD:
837 case ARM::VLD3d8Pseudo:
838 case ARM::VLD3d16Pseudo:
839 case ARM::VLD3d32Pseudo:
840 case ARM::VLD1d64TPseudo:
841 case ARM::VLD3d8Pseudo_UPD:
842 case ARM::VLD3d16Pseudo_UPD:
843 case ARM::VLD3d32Pseudo_UPD:
844 case ARM::VLD1d64TPseudo_UPD:
845 case ARM::VLD3q8Pseudo_UPD:
846 case ARM::VLD3q16Pseudo_UPD:
847 case ARM::VLD3q32Pseudo_UPD:
848 case ARM::VLD3q8oddPseudo_UPD:
849 case ARM::VLD3q16oddPseudo_UPD:
850 case ARM::VLD3q32oddPseudo_UPD:
851 case ARM::VLD4d8Pseudo:
852 case ARM::VLD4d16Pseudo:
853 case ARM::VLD4d32Pseudo:
854 case ARM::VLD1d64QPseudo:
855 case ARM::VLD4d8Pseudo_UPD:
856 case ARM::VLD4d16Pseudo_UPD:
857 case ARM::VLD4d32Pseudo_UPD:
858 case ARM::VLD1d64QPseudo_UPD:
859 case ARM::VLD4q8Pseudo_UPD:
860 case ARM::VLD4q16Pseudo_UPD:
861 case ARM::VLD4q32Pseudo_UPD:
862 case ARM::VLD4q8oddPseudo_UPD:
863 case ARM::VLD4q16oddPseudo_UPD:
864 case ARM::VLD4q32oddPseudo_UPD:
868 case ARM::VST1q8Pseudo:
869 case ARM::VST1q16Pseudo:
870 case ARM::VST1q32Pseudo:
871 case ARM::VST1q64Pseudo:
872 case ARM::VST1q8Pseudo_UPD:
873 case ARM::VST1q16Pseudo_UPD:
874 case ARM::VST1q32Pseudo_UPD:
875 case ARM::VST1q64Pseudo_UPD:
876 case ARM::VST2d8Pseudo:
877 case ARM::VST2d16Pseudo:
878 case ARM::VST2d32Pseudo:
879 case ARM::VST2q8Pseudo:
880 case ARM::VST2q16Pseudo:
881 case ARM::VST2q32Pseudo:
882 case ARM::VST2d8Pseudo_UPD:
883 case ARM::VST2d16Pseudo_UPD:
884 case ARM::VST2d32Pseudo_UPD:
885 case ARM::VST2q8Pseudo_UPD:
886 case ARM::VST2q16Pseudo_UPD:
887 case ARM::VST2q32Pseudo_UPD:
888 case ARM::VST3d8Pseudo:
889 case ARM::VST3d16Pseudo:
890 case ARM::VST3d32Pseudo:
891 case ARM::VST1d64TPseudo:
892 case ARM::VST3d8Pseudo_UPD:
893 case ARM::VST3d16Pseudo_UPD:
894 case ARM::VST3d32Pseudo_UPD:
895 case ARM::VST1d64TPseudo_UPD:
896 case ARM::VST3q8Pseudo_UPD:
897 case ARM::VST3q16Pseudo_UPD:
898 case ARM::VST3q32Pseudo_UPD:
899 case ARM::VST3q8oddPseudo_UPD:
900 case ARM::VST3q16oddPseudo_UPD:
901 case ARM::VST3q32oddPseudo_UPD:
902 case ARM::VST4d8Pseudo:
903 case ARM::VST4d16Pseudo:
904 case ARM::VST4d32Pseudo:
905 case ARM::VST1d64QPseudo:
906 case ARM::VST4d8Pseudo_UPD:
907 case ARM::VST4d16Pseudo_UPD:
908 case ARM::VST4d32Pseudo_UPD:
909 case ARM::VST1d64QPseudo_UPD:
910 case ARM::VST4q8Pseudo_UPD:
911 case ARM::VST4q16Pseudo_UPD:
912 case ARM::VST4q32Pseudo_UPD:
913 case ARM::VST4q8oddPseudo_UPD:
914 case ARM::VST4q16oddPseudo_UPD:
915 case ARM::VST4q32oddPseudo_UPD:
919 case ARM::VLD2LNd8Pseudo:
920 case ARM::VLD2LNd16Pseudo:
921 case ARM::VLD2LNd32Pseudo:
922 case ARM::VLD2LNq16Pseudo:
923 case ARM::VLD2LNq32Pseudo:
924 case ARM::VLD2LNd8Pseudo_UPD:
925 case ARM::VLD2LNd16Pseudo_UPD:
926 case ARM::VLD2LNd32Pseudo_UPD:
927 case ARM::VLD2LNq16Pseudo_UPD:
928 case ARM::VLD2LNq32Pseudo_UPD:
929 case ARM::VLD3LNd8Pseudo:
930 case ARM::VLD3LNd16Pseudo:
931 case ARM::VLD3LNd32Pseudo:
932 case ARM::VLD3LNq16Pseudo:
933 case ARM::VLD3LNq32Pseudo:
934 case ARM::VLD3LNd8Pseudo_UPD:
935 case ARM::VLD3LNd16Pseudo_UPD:
936 case ARM::VLD3LNd32Pseudo_UPD:
937 case ARM::VLD3LNq16Pseudo_UPD:
938 case ARM::VLD3LNq32Pseudo_UPD:
939 case ARM::VLD4LNd8Pseudo:
940 case ARM::VLD4LNd16Pseudo:
941 case ARM::VLD4LNd32Pseudo:
942 case ARM::VLD4LNq16Pseudo:
943 case ARM::VLD4LNq32Pseudo:
944 case ARM::VLD4LNd8Pseudo_UPD:
945 case ARM::VLD4LNd16Pseudo_UPD:
946 case ARM::VLD4LNd32Pseudo_UPD:
947 case ARM::VLD4LNq16Pseudo_UPD:
948 case ARM::VLD4LNq32Pseudo_UPD:
949 case ARM::VST2LNd8Pseudo:
950 case ARM::VST2LNd16Pseudo:
951 case ARM::VST2LNd32Pseudo:
952 case ARM::VST2LNq16Pseudo:
953 case ARM::VST2LNq32Pseudo:
954 case ARM::VST2LNd8Pseudo_UPD:
955 case ARM::VST2LNd16Pseudo_UPD:
956 case ARM::VST2LNd32Pseudo_UPD:
957 case ARM::VST2LNq16Pseudo_UPD:
958 case ARM::VST2LNq32Pseudo_UPD:
959 case ARM::VST3LNd8Pseudo:
960 case ARM::VST3LNd16Pseudo:
961 case ARM::VST3LNd32Pseudo:
962 case ARM::VST3LNq16Pseudo:
963 case ARM::VST3LNq32Pseudo:
964 case ARM::VST3LNd8Pseudo_UPD:
965 case ARM::VST3LNd16Pseudo_UPD:
966 case ARM::VST3LNd32Pseudo_UPD:
967 case ARM::VST3LNq16Pseudo_UPD:
968 case ARM::VST3LNq32Pseudo_UPD:
969 case ARM::VST4LNd8Pseudo:
970 case ARM::VST4LNd16Pseudo:
971 case ARM::VST4LNd32Pseudo:
972 case ARM::VST4LNq16Pseudo:
973 case ARM::VST4LNq32Pseudo:
974 case ARM::VST4LNd8Pseudo_UPD:
975 case ARM::VST4LNd16Pseudo_UPD:
976 case ARM::VST4LNd32Pseudo_UPD:
977 case ARM::VST4LNq16Pseudo_UPD:
978 case ARM::VST4LNq32Pseudo_UPD:
982 case ARM::VTBL2Pseudo:
983 ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break;
984 case ARM::VTBL3Pseudo:
985 ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break;
986 case ARM::VTBL4Pseudo:
987 ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break;
988 case ARM::VTBX2Pseudo:
989 ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break;
990 case ARM::VTBX3Pseudo:
991 ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break;
992 case ARM::VTBX4Pseudo:
993 ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break;
1004 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1005 TII = static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
1006 TRI = MF.getTarget().getRegisterInfo();
1008 bool Modified = false;
1009 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1011 Modified |= ExpandMBB(*MFI);
1015 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1017 FunctionPass *llvm::createARMExpandPseudoPass() {
1018 return new ARMExpandPseudo();