1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expand pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // post- regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-pseudo"
19 #include "ARMBaseInstrInfo.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 class ARMExpandPseudo : public MachineFunctionPass {
29 ARMExpandPseudo() : MachineFunctionPass(&ID) {}
31 const TargetInstrInfo *TII;
33 virtual bool runOnMachineFunction(MachineFunction &Fn);
35 virtual const char *getPassName() const {
36 return "ARM pseudo instruction expansion pass";
40 bool ExpandMBB(MachineBasicBlock &MBB);
42 char ARMExpandPseudo::ID = 0;
45 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
46 bool Modified = false;
48 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
50 MachineInstr &MI = *MBBI;
51 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
53 unsigned Opcode = MI.getOpcode();
56 case ARM::tLDRpci_pic:
57 case ARM::t2LDRpci_pic: {
58 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
59 ? ARM::tLDRpci : ARM::t2LDRpci;
60 unsigned DstReg = MI.getOperand(0).getReg();
61 if (!MI.getOperand(0).isDead()) {
63 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
64 TII->get(NewLdOpc), DstReg)
65 .addOperand(MI.getOperand(1)));
66 NewMI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
67 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
68 .addReg(DstReg, getDefRegState(true))
70 .addOperand(MI.getOperand(2));
76 case ARM::t2MOVi32imm: {
77 unsigned DstReg = MI.getOperand(0).getReg();
78 if (!MI.getOperand(0).isDead()) {
79 const MachineOperand &MO = MI.getOperand(1);
80 MachineInstrBuilder LO16, HI16;
82 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::t2MOVi16),
84 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::t2MOVTi16))
85 .addReg(DstReg, getDefRegState(true)).addReg(DstReg);
88 unsigned Imm = MO.getImm();
89 unsigned Lo16 = Imm & 0xffff;
90 unsigned Hi16 = (Imm >> 16) & 0xffff;
91 LO16 = LO16.addImm(Lo16);
92 HI16 = HI16.addImm(Hi16);
94 GlobalValue *GV = MO.getGlobal();
95 unsigned TF = MO.getTargetFlags();
96 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
97 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
98 // FIXME: What's about memoperands?
100 AddDefaultPred(LO16);
101 AddDefaultPred(HI16);
103 MI.eraseFromParent();
106 // FIXME: expand t2MOVi32imm
114 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
115 TII = MF.getTarget().getInstrInfo();
117 bool Modified = false;
118 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
120 Modified |= ExpandMBB(*MFI);
124 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
126 FunctionPass *llvm::createARMExpandPseudoPass() {
127 return new ARMExpandPseudo();