1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-pseudo"
19 #include "ARMBaseInstrInfo.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMRegisterInfo.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/Target/TargetFrameLowering.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
34 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
35 cl::desc("Verify machine code after expanding ARM pseudos"));
38 class ARMExpandPseudo : public MachineFunctionPass {
41 ARMExpandPseudo() : MachineFunctionPass(ID) {}
43 const ARMBaseInstrInfo *TII;
44 const TargetRegisterInfo *TRI;
45 const ARMSubtarget *STI;
48 virtual bool runOnMachineFunction(MachineFunction &Fn);
50 virtual const char *getPassName() const {
51 return "ARM pseudo instruction expansion pass";
55 void TransferImpOps(MachineInstr &OldMI,
56 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
57 bool ExpandMI(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI);
59 bool ExpandMBB(MachineBasicBlock &MBB);
60 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
61 void ExpandVST(MachineBasicBlock::iterator &MBBI);
62 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
63 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
64 unsigned Opc, bool IsExt);
65 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
66 MachineBasicBlock::iterator &MBBI);
68 char ARMExpandPseudo::ID = 0;
71 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
72 /// the instructions created from the expansion.
73 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
74 MachineInstrBuilder &UseMI,
75 MachineInstrBuilder &DefMI) {
76 const MCInstrDesc &Desc = OldMI.getDesc();
77 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
79 const MachineOperand &MO = OldMI.getOperand(i);
80 assert(MO.isReg() && MO.getReg());
89 // Constants for register spacing in NEON load/store instructions.
90 // For quad-register load-lane and store-lane pseudo instructors, the
91 // spacing is initially assumed to be EvenDblSpc, and that is changed to
92 // OddDblSpc depending on the lane number operand.
99 // Entries for NEON load/store information table. The table is sorted by
100 // PseudoOpc for fast binary-search lookups.
101 struct NEONLdStTableEntry {
106 bool hasWritebackOperand;
107 NEONRegSpacing RegSpacing;
108 unsigned char NumRegs; // D registers loaded or stored
109 unsigned char RegElts; // elements per D register; used for lane ops
110 // FIXME: Temporary flag to denote whether the real instruction takes
111 // a single register (like the encoding) or all of the registers in
112 // the list (like the asm syntax and the isel DAG). When all definitions
113 // are converted to take only the single encoded register, this will
115 bool copyAllListRegs;
117 // Comparison methods for binary search of the table.
118 bool operator<(const NEONLdStTableEntry &TE) const {
119 return PseudoOpc < TE.PseudoOpc;
121 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
122 return TE.PseudoOpc < PseudoOpc;
124 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
125 const NEONLdStTableEntry &TE) {
126 return PseudoOpc < TE.PseudoOpc;
131 static const NEONLdStTableEntry NEONLdStTable[] = {
132 { ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, false, SingleSpc, 2, 4,false},
133 { ARM::VLD1DUPq16PseudoWB_fixed, ARM::VLD1DUPq16wb_fixed, true, true, true, SingleSpc, 2, 4,false},
134 { ARM::VLD1DUPq16PseudoWB_register, ARM::VLD1DUPq16wb_register, true, true, true, SingleSpc, 2, 4,false},
135 { ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, false, SingleSpc, 2, 2,false},
136 { ARM::VLD1DUPq32PseudoWB_fixed, ARM::VLD1DUPq32wb_fixed, true, true, false, SingleSpc, 2, 2,false},
137 { ARM::VLD1DUPq32PseudoWB_register, ARM::VLD1DUPq32wb_register, true, true, true, SingleSpc, 2, 2,false},
138 { ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, false, SingleSpc, 2, 8,false},
139 { ARM::VLD1DUPq8PseudoWB_fixed, ARM::VLD1DUPq8wb_fixed, true, true, false, SingleSpc, 2, 8,false},
140 { ARM::VLD1DUPq8PseudoWB_register, ARM::VLD1DUPq8wb_register, true, true, true, SingleSpc, 2, 8,false},
142 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
143 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
144 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
145 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
146 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
147 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
149 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
150 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
151 { ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, false, SingleSpc, 2, 4 ,false},
152 { ARM::VLD1q16PseudoWB_fixed, ARM::VLD1q16wb_fixed,true,false,false,SingleSpc, 2, 4 ,false},
153 { ARM::VLD1q16PseudoWB_register, ARM::VLD1q16wb_register, true, true, true, SingleSpc, 2, 4 ,false},
154 { ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, false, SingleSpc, 2, 2 ,false},
155 { ARM::VLD1q32PseudoWB_fixed, ARM::VLD1q32wb_fixed,true,false, false,SingleSpc, 2, 2 ,false},
156 { ARM::VLD1q32PseudoWB_register, ARM::VLD1q32wb_register, true, true, true, SingleSpc, 2, 2 ,false},
157 { ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, false, SingleSpc, 2, 1 ,false},
158 { ARM::VLD1q64PseudoWB_fixed, ARM::VLD1q64wb_fixed,true,false, false,SingleSpc, 2, 2 ,false},
159 { ARM::VLD1q64PseudoWB_register, ARM::VLD1q64wb_register, true, true, true, SingleSpc, 2, 1 ,false},
160 { ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, false, SingleSpc, 2, 8 ,false},
161 { ARM::VLD1q8PseudoWB_fixed, ARM::VLD1q8wb_fixed,true,false, false, SingleSpc, 2, 8 ,false},
162 { ARM::VLD1q8PseudoWB_register, ARM::VLD1q8wb_register,true,true, true,SingleSpc,2,8,false},
164 { ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, false, SingleSpc, 2, 4,false},
165 { ARM::VLD2DUPd16PseudoWB_fixed, ARM::VLD2DUPd16wb_fixed, true, true, false, SingleSpc, 2, 4,false},
166 { ARM::VLD2DUPd16PseudoWB_register, ARM::VLD2DUPd16wb_register, true, true, true, SingleSpc, 2, 4,false},
167 { ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, false, SingleSpc, 2, 2,false},
168 { ARM::VLD2DUPd32PseudoWB_fixed, ARM::VLD2DUPd32wb_fixed, true, true, false, SingleSpc, 2, 2,false},
169 { ARM::VLD2DUPd32PseudoWB_register, ARM::VLD2DUPd32wb_register, true, true, true, SingleSpc, 2, 2,false},
170 { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, false, SingleSpc, 2, 8,false},
171 { ARM::VLD2DUPd8PseudoWB_fixed, ARM::VLD2DUPd8wb_fixed, true, true, false, SingleSpc, 2, 8,false},
172 { ARM::VLD2DUPd8PseudoWB_register, ARM::VLD2DUPd8wb_register, true, true, true, SingleSpc, 2, 8,false},
174 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
175 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
176 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
177 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
178 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
179 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
180 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
181 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
182 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
183 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
185 { ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, false, SingleSpc, 2, 4 ,false},
186 { ARM::VLD2d16PseudoWB_fixed, ARM::VLD2d16wb_fixed, true, true, false, SingleSpc, 2, 4 ,false},
187 { ARM::VLD2d16PseudoWB_register, ARM::VLD2d16wb_register, true, true, true, SingleSpc, 2, 4 ,false},
188 { ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, false, SingleSpc, 2, 2 ,false},
189 { ARM::VLD2d32PseudoWB_fixed, ARM::VLD2d32wb_fixed, true, true, false, SingleSpc, 2, 2 ,false},
190 { ARM::VLD2d32PseudoWB_register, ARM::VLD2d32wb_register, true, true, true, SingleSpc, 2, 2 ,false},
191 { ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, false, SingleSpc, 2, 8 ,false},
192 { ARM::VLD2d8PseudoWB_fixed, ARM::VLD2d8wb_fixed, true, true, false, SingleSpc, 2, 8 ,false},
193 { ARM::VLD2d8PseudoWB_register, ARM::VLD2d8wb_register, true, true, true, SingleSpc, 2, 8 ,false},
195 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
196 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
197 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
198 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
199 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
200 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
201 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
202 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
203 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
205 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
206 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
207 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
208 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
209 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
210 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
212 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
213 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
214 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
215 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
216 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
217 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
218 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
219 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
220 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
221 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
223 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
224 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
225 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
226 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
227 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
228 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
230 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
231 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
232 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
233 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
234 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
235 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
236 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
237 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
238 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
240 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
241 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
242 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
243 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
244 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
245 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
247 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
248 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
249 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
250 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
251 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
252 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
253 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
254 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
255 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
256 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
258 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
259 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
260 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
261 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
262 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
263 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
265 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
266 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
267 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
268 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
269 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
270 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
271 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
272 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
273 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
275 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
276 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
277 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
278 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
279 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
280 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
282 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
283 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
284 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
285 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
286 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
287 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
289 { ARM::VST1q16Pseudo, ARM::VST1q16, false, false, false, SingleSpc, 2, 4 ,false},
290 { ARM::VST1q16PseudoWB_fixed, ARM::VST1q16wb_fixed, false, true, false, SingleSpc, 2, 4 ,false},
291 { ARM::VST1q16PseudoWB_register, ARM::VST1q16wb_register, false, true, true, SingleSpc, 2, 4 ,false},
292 { ARM::VST1q32Pseudo, ARM::VST1q32, false, false, false, SingleSpc, 2, 2 ,false},
293 { ARM::VST1q32PseudoWB_fixed, ARM::VST1q32wb_fixed, false, true, false, SingleSpc, 2, 2 ,false},
294 { ARM::VST1q32PseudoWB_register, ARM::VST1q32wb_register, false, true, true, SingleSpc, 2, 2 ,false},
295 { ARM::VST1q64Pseudo, ARM::VST1q64, false, false, false, SingleSpc, 2, 1 ,false},
296 { ARM::VST1q64PseudoWB_fixed, ARM::VST1q64wb_fixed, false, true, false, SingleSpc, 2, 1 ,false},
297 { ARM::VST1q64PseudoWB_register, ARM::VST1q64wb_register, false, true, true, SingleSpc, 2, 1 ,false},
298 { ARM::VST1q8Pseudo, ARM::VST1q8, false, false, false, SingleSpc, 2, 8 ,false},
299 { ARM::VST1q8PseudoWB_fixed, ARM::VST1q8wb_fixed, false, true, false, SingleSpc, 2, 8 ,false},
300 { ARM::VST1q8PseudoWB_register, ARM::VST1q8wb_register, false, true, true, SingleSpc, 2, 8 ,false},
302 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
303 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
304 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
305 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
306 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
307 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
308 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
309 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
310 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
311 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
313 { ARM::VST2d16Pseudo, ARM::VST2d16, false, false, false, SingleSpc, 2, 4 ,false},
314 { ARM::VST2d16PseudoWB_fixed, ARM::VST2d16wb_fixed, false, true, false, SingleSpc, 2, 4 ,false},
315 { ARM::VST2d16PseudoWB_register, ARM::VST2d16wb_register, false, true, true, SingleSpc, 2, 4 ,false},
316 { ARM::VST2d32Pseudo, ARM::VST2d32, false, false, false, SingleSpc, 2, 2 ,false},
317 { ARM::VST2d32PseudoWB_fixed, ARM::VST2d32wb_fixed, false, true, true, SingleSpc, 2, 2 ,false},
318 { ARM::VST2d32PseudoWB_register, ARM::VST2d32wb_register, false, true, true, SingleSpc, 2, 2 ,false},
319 { ARM::VST2d8Pseudo, ARM::VST2d8, false, false, false, SingleSpc, 2, 8 ,false},
320 { ARM::VST2d8PseudoWB_fixed, ARM::VST2d8wb_fixed, false, true, false, SingleSpc, 2, 8 ,false},
321 { ARM::VST2d8PseudoWB_register, ARM::VST2d8wb_register, false, true, true, SingleSpc, 2, 8 ,false},
323 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
324 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
325 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
326 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
327 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
328 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
329 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
330 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
331 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
333 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
334 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
335 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
336 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
337 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
338 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
339 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
340 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
341 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
342 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
344 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
345 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
346 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
347 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
348 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
349 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
351 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
352 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
353 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
354 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
355 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
356 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
357 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
358 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
359 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
361 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
362 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
363 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
364 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
365 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
366 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
367 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
368 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
369 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
370 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
372 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
373 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
374 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
375 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
376 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
377 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
379 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
380 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
381 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
382 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
383 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
384 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
385 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
386 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
387 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
390 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
391 /// load or store pseudo instruction.
392 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
393 unsigned NumEntries = array_lengthof(NEONLdStTable);
396 // Make sure the table is sorted.
397 static bool TableChecked = false;
399 for (unsigned i = 0; i != NumEntries-1; ++i)
400 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
401 "NEONLdStTable is not sorted!");
406 const NEONLdStTableEntry *I =
407 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
408 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
413 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
414 /// corresponding to the specified register spacing. Not all of the results
415 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
416 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
417 const TargetRegisterInfo *TRI, unsigned &D0,
418 unsigned &D1, unsigned &D2, unsigned &D3) {
419 if (RegSpc == SingleSpc) {
420 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
421 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
422 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
423 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
424 } else if (RegSpc == EvenDblSpc) {
425 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
426 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
427 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
428 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
430 assert(RegSpc == OddDblSpc && "unknown register spacing");
431 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
432 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
433 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
434 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
438 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
439 /// operands to real VLD instructions with D register operands.
440 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
441 MachineInstr &MI = *MBBI;
442 MachineBasicBlock &MBB = *MI.getParent();
444 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
445 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
446 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
447 unsigned NumRegs = TableEntry->NumRegs;
449 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
450 TII->get(TableEntry->RealOpc));
453 bool DstIsDead = MI.getOperand(OpIdx).isDead();
454 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
455 unsigned D0, D1, D2, D3;
456 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
457 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
458 if (NumRegs > 1 && TableEntry->copyAllListRegs)
459 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
460 if (NumRegs > 2 && TableEntry->copyAllListRegs)
461 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
462 if (NumRegs > 3 && TableEntry->copyAllListRegs)
463 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
465 if (TableEntry->isUpdating)
466 MIB.addOperand(MI.getOperand(OpIdx++));
468 // Copy the addrmode6 operands.
469 MIB.addOperand(MI.getOperand(OpIdx++));
470 MIB.addOperand(MI.getOperand(OpIdx++));
471 // Copy the am6offset operand.
472 if (TableEntry->hasWritebackOperand)
473 MIB.addOperand(MI.getOperand(OpIdx++));
475 // For an instruction writing double-spaced subregs, the pseudo instruction
476 // has an extra operand that is a use of the super-register. Record the
477 // operand index and skip over it.
478 unsigned SrcOpIdx = 0;
479 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
482 // Copy the predicate operands.
483 MIB.addOperand(MI.getOperand(OpIdx++));
484 MIB.addOperand(MI.getOperand(OpIdx++));
486 // Copy the super-register source operand used for double-spaced subregs over
487 // to the new instruction as an implicit operand.
489 MachineOperand MO = MI.getOperand(SrcOpIdx);
490 MO.setImplicit(true);
493 // Add an implicit def for the super-register.
494 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
495 TransferImpOps(MI, MIB, MIB);
497 // Transfer memoperands.
498 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
500 MI.eraseFromParent();
503 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
504 /// operands to real VST instructions with D register operands.
505 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
506 MachineInstr &MI = *MBBI;
507 MachineBasicBlock &MBB = *MI.getParent();
509 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
510 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
511 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
512 unsigned NumRegs = TableEntry->NumRegs;
514 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
515 TII->get(TableEntry->RealOpc));
517 if (TableEntry->isUpdating)
518 MIB.addOperand(MI.getOperand(OpIdx++));
520 // Copy the addrmode6 operands.
521 MIB.addOperand(MI.getOperand(OpIdx++));
522 MIB.addOperand(MI.getOperand(OpIdx++));
523 // Copy the am6offset operand.
524 if (TableEntry->hasWritebackOperand)
525 MIB.addOperand(MI.getOperand(OpIdx++));
527 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
528 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
529 unsigned D0, D1, D2, D3;
530 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
532 if (NumRegs > 1 && TableEntry->copyAllListRegs)
534 if (NumRegs > 2 && TableEntry->copyAllListRegs)
536 if (NumRegs > 3 && TableEntry->copyAllListRegs)
539 // Copy the predicate operands.
540 MIB.addOperand(MI.getOperand(OpIdx++));
541 MIB.addOperand(MI.getOperand(OpIdx++));
543 if (SrcIsKill) // Add an implicit kill for the super-reg.
544 MIB->addRegisterKilled(SrcReg, TRI, true);
545 TransferImpOps(MI, MIB, MIB);
547 // Transfer memoperands.
548 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
550 MI.eraseFromParent();
553 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
554 /// register operands to real instructions with D register operands.
555 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
556 MachineInstr &MI = *MBBI;
557 MachineBasicBlock &MBB = *MI.getParent();
559 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
560 assert(TableEntry && "NEONLdStTable lookup failed");
561 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
562 unsigned NumRegs = TableEntry->NumRegs;
563 unsigned RegElts = TableEntry->RegElts;
565 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
566 TII->get(TableEntry->RealOpc));
568 // The lane operand is always the 3rd from last operand, before the 2
569 // predicate operands.
570 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
572 // Adjust the lane and spacing as needed for Q registers.
573 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
574 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
578 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
580 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
582 bool DstIsDead = false;
583 if (TableEntry->IsLoad) {
584 DstIsDead = MI.getOperand(OpIdx).isDead();
585 DstReg = MI.getOperand(OpIdx++).getReg();
586 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
587 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
589 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
591 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
593 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
596 if (TableEntry->isUpdating)
597 MIB.addOperand(MI.getOperand(OpIdx++));
599 // Copy the addrmode6 operands.
600 MIB.addOperand(MI.getOperand(OpIdx++));
601 MIB.addOperand(MI.getOperand(OpIdx++));
602 // Copy the am6offset operand.
603 if (TableEntry->hasWritebackOperand)
604 MIB.addOperand(MI.getOperand(OpIdx++));
606 // Grab the super-register source.
607 MachineOperand MO = MI.getOperand(OpIdx++);
608 if (!TableEntry->IsLoad)
609 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
611 // Add the subregs as sources of the new instruction.
612 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
613 getKillRegState(MO.isKill()));
614 MIB.addReg(D0, SrcFlags);
616 MIB.addReg(D1, SrcFlags);
618 MIB.addReg(D2, SrcFlags);
620 MIB.addReg(D3, SrcFlags);
622 // Add the lane number operand.
626 // Copy the predicate operands.
627 MIB.addOperand(MI.getOperand(OpIdx++));
628 MIB.addOperand(MI.getOperand(OpIdx++));
630 // Copy the super-register source to be an implicit source.
631 MO.setImplicit(true);
633 if (TableEntry->IsLoad)
634 // Add an implicit def for the super-register.
635 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
636 TransferImpOps(MI, MIB, MIB);
637 // Transfer memoperands.
638 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
639 MI.eraseFromParent();
642 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
643 /// register operands to real instructions with D register operands.
644 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
645 unsigned Opc, bool IsExt) {
646 MachineInstr &MI = *MBBI;
647 MachineBasicBlock &MBB = *MI.getParent();
649 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
652 // Transfer the destination register operand.
653 MIB.addOperand(MI.getOperand(OpIdx++));
655 MIB.addOperand(MI.getOperand(OpIdx++));
657 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
658 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
659 unsigned D0, D1, D2, D3;
660 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
663 // Copy the other source register operand.
664 MIB.addOperand(MI.getOperand(OpIdx++));
666 // Copy the predicate operands.
667 MIB.addOperand(MI.getOperand(OpIdx++));
668 MIB.addOperand(MI.getOperand(OpIdx++));
670 if (SrcIsKill) // Add an implicit kill for the super-reg.
671 MIB->addRegisterKilled(SrcReg, TRI, true);
672 TransferImpOps(MI, MIB, MIB);
673 MI.eraseFromParent();
676 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
677 MachineBasicBlock::iterator &MBBI) {
678 MachineInstr &MI = *MBBI;
679 unsigned Opcode = MI.getOpcode();
680 unsigned PredReg = 0;
681 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
682 unsigned DstReg = MI.getOperand(0).getReg();
683 bool DstIsDead = MI.getOperand(0).isDead();
684 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
685 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
686 MachineInstrBuilder LO16, HI16;
688 if (!STI->hasV6T2Ops() &&
689 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
690 // Expand into a movi + orr.
691 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
692 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
693 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
696 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
697 unsigned ImmVal = (unsigned)MO.getImm();
698 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
699 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
700 LO16 = LO16.addImm(SOImmValV1);
701 HI16 = HI16.addImm(SOImmValV2);
702 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
703 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
704 LO16.addImm(Pred).addReg(PredReg).addReg(0);
705 HI16.addImm(Pred).addReg(PredReg).addReg(0);
706 TransferImpOps(MI, LO16, HI16);
707 MI.eraseFromParent();
711 unsigned LO16Opc = 0;
712 unsigned HI16Opc = 0;
713 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
714 LO16Opc = ARM::t2MOVi16;
715 HI16Opc = ARM::t2MOVTi16;
717 LO16Opc = ARM::MOVi16;
718 HI16Opc = ARM::MOVTi16;
721 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
722 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
723 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
727 unsigned Imm = MO.getImm();
728 unsigned Lo16 = Imm & 0xffff;
729 unsigned Hi16 = (Imm >> 16) & 0xffff;
730 LO16 = LO16.addImm(Lo16);
731 HI16 = HI16.addImm(Hi16);
733 const GlobalValue *GV = MO.getGlobal();
734 unsigned TF = MO.getTargetFlags();
735 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
736 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
739 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
740 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
741 LO16.addImm(Pred).addReg(PredReg);
742 HI16.addImm(Pred).addReg(PredReg);
744 TransferImpOps(MI, LO16, HI16);
745 MI.eraseFromParent();
748 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
749 MachineBasicBlock::iterator MBBI) {
750 MachineInstr &MI = *MBBI;
751 unsigned Opcode = MI.getOpcode();
757 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
758 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
759 MI.getOperand(1).getReg())
760 .addReg(MI.getOperand(2).getReg(),
761 getKillRegState(MI.getOperand(2).isKill()))
762 .addImm(MI.getOperand(3).getImm()) // 'pred'
763 .addReg(MI.getOperand(4).getReg());
765 MI.eraseFromParent();
770 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
771 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
772 MI.getOperand(1).getReg())
773 .addReg(MI.getOperand(2).getReg(),
774 getKillRegState(MI.getOperand(2).isKill()))
775 .addImm(MI.getOperand(3).getImm()) // 'pred'
776 .addReg(MI.getOperand(4).getReg())
777 .addReg(0); // 's' bit
779 MI.eraseFromParent();
783 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
784 (MI.getOperand(1).getReg()))
785 .addReg(MI.getOperand(2).getReg(),
786 getKillRegState(MI.getOperand(2).isKill()))
787 .addImm(MI.getOperand(3).getImm())
788 .addImm(MI.getOperand(4).getImm()) // 'pred'
789 .addReg(MI.getOperand(5).getReg())
790 .addReg(0); // 's' bit
792 MI.eraseFromParent();
797 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
798 (MI.getOperand(1).getReg()))
799 .addReg(MI.getOperand(2).getReg(),
800 getKillRegState(MI.getOperand(2).isKill()))
801 .addReg(MI.getOperand(3).getReg(),
802 getKillRegState(MI.getOperand(3).isKill()))
803 .addImm(MI.getOperand(4).getImm())
804 .addImm(MI.getOperand(5).getImm()) // 'pred'
805 .addReg(MI.getOperand(6).getReg())
806 .addReg(0); // 's' bit
808 MI.eraseFromParent();
811 case ARM::MOVCCi16: {
812 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi16),
813 MI.getOperand(1).getReg())
814 .addImm(MI.getOperand(2).getImm())
815 .addImm(MI.getOperand(3).getImm()) // 'pred'
816 .addReg(MI.getOperand(4).getReg());
818 MI.eraseFromParent();
823 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
824 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
825 MI.getOperand(1).getReg())
826 .addImm(MI.getOperand(2).getImm())
827 .addImm(MI.getOperand(3).getImm()) // 'pred'
828 .addReg(MI.getOperand(4).getReg())
829 .addReg(0); // 's' bit
831 MI.eraseFromParent();
835 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi),
836 MI.getOperand(1).getReg())
837 .addImm(MI.getOperand(2).getImm())
838 .addImm(MI.getOperand(3).getImm()) // 'pred'
839 .addReg(MI.getOperand(4).getReg())
840 .addReg(0); // 's' bit
842 MI.eraseFromParent();
845 case ARM::Int_eh_sjlj_dispatchsetup:
846 case ARM::Int_eh_sjlj_dispatchsetup_nofp:
847 case ARM::tInt_eh_sjlj_dispatchsetup: {
848 MachineFunction &MF = *MI.getParent()->getParent();
849 const ARMBaseInstrInfo *AII =
850 static_cast<const ARMBaseInstrInfo*>(TII);
851 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
852 // For functions using a base pointer, we rematerialize it (via the frame
853 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
854 // for us. Otherwise, expand to nothing.
855 if (RI.hasBasePointer(MF)) {
856 int32_t NumBytes = AFI->getFramePtrSpillOffset();
857 unsigned FramePtr = RI.getFrameRegister(MF);
858 assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
859 "base pointer without frame pointer?");
861 if (AFI->isThumb2Function()) {
862 llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
863 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
864 } else if (AFI->isThumbFunction()) {
865 llvm::emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
866 FramePtr, -NumBytes, *TII, RI);
868 llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
869 FramePtr, -NumBytes, ARMCC::AL, 0,
872 // If there's dynamic realignment, adjust for it.
873 if (RI.needsStackRealignment(MF)) {
874 MachineFrameInfo *MFI = MF.getFrameInfo();
875 unsigned MaxAlign = MFI->getMaxAlignment();
876 assert (!AFI->isThumb1OnlyFunction());
877 // Emit bic r6, r6, MaxAlign
878 unsigned bicOpc = AFI->isThumbFunction() ?
879 ARM::t2BICri : ARM::BICri;
880 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
881 TII->get(bicOpc), ARM::R6)
882 .addReg(ARM::R6, RegState::Kill)
883 .addImm(MaxAlign-1)));
887 MI.eraseFromParent();
891 case ARM::MOVsrl_flag:
892 case ARM::MOVsra_flag: {
893 // These are just fancy MOVs insructions.
894 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
895 MI.getOperand(0).getReg())
896 .addOperand(MI.getOperand(1))
897 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ?
898 ARM_AM::lsr : ARM_AM::asr),
900 .addReg(ARM::CPSR, RegState::Define);
901 MI.eraseFromParent();
905 // This encodes as "MOVs Rd, Rm, rrx
906 MachineInstrBuilder MIB =
907 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
908 MI.getOperand(0).getReg())
909 .addOperand(MI.getOperand(1))
910 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
912 TransferImpOps(MI, MIB, MIB);
913 MI.eraseFromParent();
918 MachineInstrBuilder MIB =
919 BuildMI(MBB, MBBI, MI.getDebugLoc(),
920 TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
921 .addExternalSymbol("__aeabi_read_tp", 0);
923 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
924 TransferImpOps(MI, MIB, MIB);
925 MI.eraseFromParent();
928 case ARM::tLDRpci_pic:
929 case ARM::t2LDRpci_pic: {
930 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
931 ? ARM::tLDRpci : ARM::t2LDRpci;
932 unsigned DstReg = MI.getOperand(0).getReg();
933 bool DstIsDead = MI.getOperand(0).isDead();
934 MachineInstrBuilder MIB1 =
935 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
936 TII->get(NewLdOpc), DstReg)
937 .addOperand(MI.getOperand(1)));
938 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
939 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
940 TII->get(ARM::tPICADD))
941 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
943 .addOperand(MI.getOperand(2));
944 TransferImpOps(MI, MIB1, MIB2);
945 MI.eraseFromParent();
949 case ARM::MOV_ga_dyn:
950 case ARM::MOV_ga_pcrel:
951 case ARM::MOV_ga_pcrel_ldr:
952 case ARM::t2MOV_ga_dyn:
953 case ARM::t2MOV_ga_pcrel: {
954 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
955 unsigned LabelId = AFI->createPICLabelUId();
956 unsigned DstReg = MI.getOperand(0).getReg();
957 bool DstIsDead = MI.getOperand(0).isDead();
958 const MachineOperand &MO1 = MI.getOperand(1);
959 const GlobalValue *GV = MO1.getGlobal();
960 unsigned TF = MO1.getTargetFlags();
961 bool isARM = (Opcode != ARM::t2MOV_ga_pcrel && Opcode!=ARM::t2MOV_ga_dyn);
962 bool isPIC = (Opcode != ARM::MOV_ga_dyn && Opcode != ARM::t2MOV_ga_dyn);
963 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
964 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
965 unsigned LO16TF = isPIC
966 ? ARMII::MO_LO16_NONLAZY_PIC : ARMII::MO_LO16_NONLAZY;
967 unsigned HI16TF = isPIC
968 ? ARMII::MO_HI16_NONLAZY_PIC : ARMII::MO_HI16_NONLAZY;
969 unsigned PICAddOpc = isARM
970 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
972 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
973 TII->get(LO16Opc), DstReg)
974 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
976 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
977 TII->get(HI16Opc), DstReg)
979 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
982 TransferImpOps(MI, MIB1, MIB2);
983 MI.eraseFromParent();
987 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
989 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
990 .addReg(DstReg).addImm(LabelId);
992 AddDefaultPred(MIB3);
993 if (Opcode == ARM::MOV_ga_pcrel_ldr)
994 MIB2->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
996 TransferImpOps(MI, MIB1, MIB3);
997 MI.eraseFromParent();
1001 case ARM::MOVi32imm:
1002 case ARM::MOVCCi32imm:
1003 case ARM::t2MOVi32imm:
1004 case ARM::t2MOVCCi32imm:
1005 ExpandMOV32BitImm(MBB, MBBI);
1008 case ARM::VLDMQIA: {
1009 unsigned NewOpc = ARM::VLDMDIA;
1010 MachineInstrBuilder MIB =
1011 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1014 // Grab the Q register destination.
1015 bool DstIsDead = MI.getOperand(OpIdx).isDead();
1016 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1018 // Copy the source register.
1019 MIB.addOperand(MI.getOperand(OpIdx++));
1021 // Copy the predicate operands.
1022 MIB.addOperand(MI.getOperand(OpIdx++));
1023 MIB.addOperand(MI.getOperand(OpIdx++));
1025 // Add the destination operands (D subregs).
1026 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1027 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1028 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1029 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1031 // Add an implicit def for the super-register.
1032 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1033 TransferImpOps(MI, MIB, MIB);
1034 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1035 MI.eraseFromParent();
1039 case ARM::VSTMQIA: {
1040 unsigned NewOpc = ARM::VSTMDIA;
1041 MachineInstrBuilder MIB =
1042 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1045 // Grab the Q register source.
1046 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1047 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1049 // Copy the destination register.
1050 MIB.addOperand(MI.getOperand(OpIdx++));
1052 // Copy the predicate operands.
1053 MIB.addOperand(MI.getOperand(OpIdx++));
1054 MIB.addOperand(MI.getOperand(OpIdx++));
1056 // Add the source operands (D subregs).
1057 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1058 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1059 MIB.addReg(D0).addReg(D1);
1061 if (SrcIsKill) // Add an implicit kill for the Q register.
1062 MIB->addRegisterKilled(SrcReg, TRI, true);
1064 TransferImpOps(MI, MIB, MIB);
1065 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1066 MI.eraseFromParent();
1071 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q :
1073 MachineInstrBuilder MIB =
1074 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1076 unsigned SrcReg = MI.getOperand(1).getReg();
1077 unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
1078 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
1079 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
1080 &ARM::DPR_VFP2RegClass);
1081 // The lane is [0,1] for the containing DReg superregister.
1082 // Copy the dst/src register operands.
1083 MIB.addOperand(MI.getOperand(OpIdx++));
1086 // Add the lane select operand.
1088 // Add the predicate operands.
1089 MIB.addOperand(MI.getOperand(OpIdx++));
1090 MIB.addOperand(MI.getOperand(OpIdx++));
1092 TransferImpOps(MI, MIB, MIB);
1093 MI.eraseFromParent();
1097 case ARM::VLD1q8Pseudo:
1098 case ARM::VLD1q16Pseudo:
1099 case ARM::VLD1q32Pseudo:
1100 case ARM::VLD1q64Pseudo:
1101 case ARM::VLD1q8PseudoWB_register:
1102 case ARM::VLD1q16PseudoWB_register:
1103 case ARM::VLD1q32PseudoWB_register:
1104 case ARM::VLD1q64PseudoWB_register:
1105 case ARM::VLD1q8PseudoWB_fixed:
1106 case ARM::VLD1q16PseudoWB_fixed:
1107 case ARM::VLD1q32PseudoWB_fixed:
1108 case ARM::VLD1q64PseudoWB_fixed:
1109 case ARM::VLD2d8Pseudo:
1110 case ARM::VLD2d16Pseudo:
1111 case ARM::VLD2d32Pseudo:
1112 case ARM::VLD2q8Pseudo:
1113 case ARM::VLD2q16Pseudo:
1114 case ARM::VLD2q32Pseudo:
1115 case ARM::VLD2d8PseudoWB_fixed:
1116 case ARM::VLD2d16PseudoWB_fixed:
1117 case ARM::VLD2d32PseudoWB_fixed:
1118 case ARM::VLD2q8PseudoWB_fixed:
1119 case ARM::VLD2q16PseudoWB_fixed:
1120 case ARM::VLD2q32PseudoWB_fixed:
1121 case ARM::VLD2d8PseudoWB_register:
1122 case ARM::VLD2d16PseudoWB_register:
1123 case ARM::VLD2d32PseudoWB_register:
1124 case ARM::VLD2q8PseudoWB_register:
1125 case ARM::VLD2q16PseudoWB_register:
1126 case ARM::VLD2q32PseudoWB_register:
1127 case ARM::VLD3d8Pseudo:
1128 case ARM::VLD3d16Pseudo:
1129 case ARM::VLD3d32Pseudo:
1130 case ARM::VLD1d64TPseudo:
1131 case ARM::VLD3d8Pseudo_UPD:
1132 case ARM::VLD3d16Pseudo_UPD:
1133 case ARM::VLD3d32Pseudo_UPD:
1134 case ARM::VLD3q8Pseudo_UPD:
1135 case ARM::VLD3q16Pseudo_UPD:
1136 case ARM::VLD3q32Pseudo_UPD:
1137 case ARM::VLD3q8oddPseudo:
1138 case ARM::VLD3q16oddPseudo:
1139 case ARM::VLD3q32oddPseudo:
1140 case ARM::VLD3q8oddPseudo_UPD:
1141 case ARM::VLD3q16oddPseudo_UPD:
1142 case ARM::VLD3q32oddPseudo_UPD:
1143 case ARM::VLD4d8Pseudo:
1144 case ARM::VLD4d16Pseudo:
1145 case ARM::VLD4d32Pseudo:
1146 case ARM::VLD1d64QPseudo:
1147 case ARM::VLD4d8Pseudo_UPD:
1148 case ARM::VLD4d16Pseudo_UPD:
1149 case ARM::VLD4d32Pseudo_UPD:
1150 case ARM::VLD4q8Pseudo_UPD:
1151 case ARM::VLD4q16Pseudo_UPD:
1152 case ARM::VLD4q32Pseudo_UPD:
1153 case ARM::VLD4q8oddPseudo:
1154 case ARM::VLD4q16oddPseudo:
1155 case ARM::VLD4q32oddPseudo:
1156 case ARM::VLD4q8oddPseudo_UPD:
1157 case ARM::VLD4q16oddPseudo_UPD:
1158 case ARM::VLD4q32oddPseudo_UPD:
1159 case ARM::VLD1DUPq8Pseudo:
1160 case ARM::VLD1DUPq16Pseudo:
1161 case ARM::VLD1DUPq32Pseudo:
1162 case ARM::VLD1DUPq8PseudoWB_fixed:
1163 case ARM::VLD1DUPq16PseudoWB_fixed:
1164 case ARM::VLD1DUPq32PseudoWB_fixed:
1165 case ARM::VLD1DUPq8PseudoWB_register:
1166 case ARM::VLD1DUPq16PseudoWB_register:
1167 case ARM::VLD1DUPq32PseudoWB_register:
1168 case ARM::VLD2DUPd8Pseudo:
1169 case ARM::VLD2DUPd16Pseudo:
1170 case ARM::VLD2DUPd32Pseudo:
1171 case ARM::VLD2DUPd8PseudoWB_fixed:
1172 case ARM::VLD2DUPd16PseudoWB_fixed:
1173 case ARM::VLD2DUPd32PseudoWB_fixed:
1174 case ARM::VLD2DUPd8PseudoWB_register:
1175 case ARM::VLD2DUPd16PseudoWB_register:
1176 case ARM::VLD2DUPd32PseudoWB_register:
1177 case ARM::VLD3DUPd8Pseudo:
1178 case ARM::VLD3DUPd16Pseudo:
1179 case ARM::VLD3DUPd32Pseudo:
1180 case ARM::VLD3DUPd8Pseudo_UPD:
1181 case ARM::VLD3DUPd16Pseudo_UPD:
1182 case ARM::VLD3DUPd32Pseudo_UPD:
1183 case ARM::VLD4DUPd8Pseudo:
1184 case ARM::VLD4DUPd16Pseudo:
1185 case ARM::VLD4DUPd32Pseudo:
1186 case ARM::VLD4DUPd8Pseudo_UPD:
1187 case ARM::VLD4DUPd16Pseudo_UPD:
1188 case ARM::VLD4DUPd32Pseudo_UPD:
1192 case ARM::VST1q8Pseudo:
1193 case ARM::VST1q16Pseudo:
1194 case ARM::VST1q32Pseudo:
1195 case ARM::VST1q64Pseudo:
1196 case ARM::VST1q8PseudoWB_fixed:
1197 case ARM::VST1q16PseudoWB_fixed:
1198 case ARM::VST1q32PseudoWB_fixed:
1199 case ARM::VST1q64PseudoWB_fixed:
1200 case ARM::VST1q8PseudoWB_register:
1201 case ARM::VST1q16PseudoWB_register:
1202 case ARM::VST1q32PseudoWB_register:
1203 case ARM::VST1q64PseudoWB_register:
1204 case ARM::VST2d8Pseudo:
1205 case ARM::VST2d16Pseudo:
1206 case ARM::VST2d32Pseudo:
1207 case ARM::VST2q8Pseudo:
1208 case ARM::VST2q16Pseudo:
1209 case ARM::VST2q32Pseudo:
1210 case ARM::VST2d8PseudoWB_fixed:
1211 case ARM::VST2d16PseudoWB_fixed:
1212 case ARM::VST2d32PseudoWB_fixed:
1213 case ARM::VST2q8PseudoWB_fixed:
1214 case ARM::VST2q16PseudoWB_fixed:
1215 case ARM::VST2q32PseudoWB_fixed:
1216 case ARM::VST2d8PseudoWB_register:
1217 case ARM::VST2d16PseudoWB_register:
1218 case ARM::VST2d32PseudoWB_register:
1219 case ARM::VST2q8PseudoWB_register:
1220 case ARM::VST2q16PseudoWB_register:
1221 case ARM::VST2q32PseudoWB_register:
1222 case ARM::VST3d8Pseudo:
1223 case ARM::VST3d16Pseudo:
1224 case ARM::VST3d32Pseudo:
1225 case ARM::VST1d64TPseudo:
1226 case ARM::VST3d8Pseudo_UPD:
1227 case ARM::VST3d16Pseudo_UPD:
1228 case ARM::VST3d32Pseudo_UPD:
1229 case ARM::VST1d64TPseudoWB_fixed:
1230 case ARM::VST1d64TPseudoWB_register:
1231 case ARM::VST3q8Pseudo_UPD:
1232 case ARM::VST3q16Pseudo_UPD:
1233 case ARM::VST3q32Pseudo_UPD:
1234 case ARM::VST3q8oddPseudo:
1235 case ARM::VST3q16oddPseudo:
1236 case ARM::VST3q32oddPseudo:
1237 case ARM::VST3q8oddPseudo_UPD:
1238 case ARM::VST3q16oddPseudo_UPD:
1239 case ARM::VST3q32oddPseudo_UPD:
1240 case ARM::VST4d8Pseudo:
1241 case ARM::VST4d16Pseudo:
1242 case ARM::VST4d32Pseudo:
1243 case ARM::VST1d64QPseudo:
1244 case ARM::VST4d8Pseudo_UPD:
1245 case ARM::VST4d16Pseudo_UPD:
1246 case ARM::VST4d32Pseudo_UPD:
1247 case ARM::VST1d64QPseudoWB_fixed:
1248 case ARM::VST1d64QPseudoWB_register:
1249 case ARM::VST4q8Pseudo_UPD:
1250 case ARM::VST4q16Pseudo_UPD:
1251 case ARM::VST4q32Pseudo_UPD:
1252 case ARM::VST4q8oddPseudo:
1253 case ARM::VST4q16oddPseudo:
1254 case ARM::VST4q32oddPseudo:
1255 case ARM::VST4q8oddPseudo_UPD:
1256 case ARM::VST4q16oddPseudo_UPD:
1257 case ARM::VST4q32oddPseudo_UPD:
1261 case ARM::VLD1LNq8Pseudo:
1262 case ARM::VLD1LNq16Pseudo:
1263 case ARM::VLD1LNq32Pseudo:
1264 case ARM::VLD1LNq8Pseudo_UPD:
1265 case ARM::VLD1LNq16Pseudo_UPD:
1266 case ARM::VLD1LNq32Pseudo_UPD:
1267 case ARM::VLD2LNd8Pseudo:
1268 case ARM::VLD2LNd16Pseudo:
1269 case ARM::VLD2LNd32Pseudo:
1270 case ARM::VLD2LNq16Pseudo:
1271 case ARM::VLD2LNq32Pseudo:
1272 case ARM::VLD2LNd8Pseudo_UPD:
1273 case ARM::VLD2LNd16Pseudo_UPD:
1274 case ARM::VLD2LNd32Pseudo_UPD:
1275 case ARM::VLD2LNq16Pseudo_UPD:
1276 case ARM::VLD2LNq32Pseudo_UPD:
1277 case ARM::VLD3LNd8Pseudo:
1278 case ARM::VLD3LNd16Pseudo:
1279 case ARM::VLD3LNd32Pseudo:
1280 case ARM::VLD3LNq16Pseudo:
1281 case ARM::VLD3LNq32Pseudo:
1282 case ARM::VLD3LNd8Pseudo_UPD:
1283 case ARM::VLD3LNd16Pseudo_UPD:
1284 case ARM::VLD3LNd32Pseudo_UPD:
1285 case ARM::VLD3LNq16Pseudo_UPD:
1286 case ARM::VLD3LNq32Pseudo_UPD:
1287 case ARM::VLD4LNd8Pseudo:
1288 case ARM::VLD4LNd16Pseudo:
1289 case ARM::VLD4LNd32Pseudo:
1290 case ARM::VLD4LNq16Pseudo:
1291 case ARM::VLD4LNq32Pseudo:
1292 case ARM::VLD4LNd8Pseudo_UPD:
1293 case ARM::VLD4LNd16Pseudo_UPD:
1294 case ARM::VLD4LNd32Pseudo_UPD:
1295 case ARM::VLD4LNq16Pseudo_UPD:
1296 case ARM::VLD4LNq32Pseudo_UPD:
1297 case ARM::VST1LNq8Pseudo:
1298 case ARM::VST1LNq16Pseudo:
1299 case ARM::VST1LNq32Pseudo:
1300 case ARM::VST1LNq8Pseudo_UPD:
1301 case ARM::VST1LNq16Pseudo_UPD:
1302 case ARM::VST1LNq32Pseudo_UPD:
1303 case ARM::VST2LNd8Pseudo:
1304 case ARM::VST2LNd16Pseudo:
1305 case ARM::VST2LNd32Pseudo:
1306 case ARM::VST2LNq16Pseudo:
1307 case ARM::VST2LNq32Pseudo:
1308 case ARM::VST2LNd8Pseudo_UPD:
1309 case ARM::VST2LNd16Pseudo_UPD:
1310 case ARM::VST2LNd32Pseudo_UPD:
1311 case ARM::VST2LNq16Pseudo_UPD:
1312 case ARM::VST2LNq32Pseudo_UPD:
1313 case ARM::VST3LNd8Pseudo:
1314 case ARM::VST3LNd16Pseudo:
1315 case ARM::VST3LNd32Pseudo:
1316 case ARM::VST3LNq16Pseudo:
1317 case ARM::VST3LNq32Pseudo:
1318 case ARM::VST3LNd8Pseudo_UPD:
1319 case ARM::VST3LNd16Pseudo_UPD:
1320 case ARM::VST3LNd32Pseudo_UPD:
1321 case ARM::VST3LNq16Pseudo_UPD:
1322 case ARM::VST3LNq32Pseudo_UPD:
1323 case ARM::VST4LNd8Pseudo:
1324 case ARM::VST4LNd16Pseudo:
1325 case ARM::VST4LNd32Pseudo:
1326 case ARM::VST4LNq16Pseudo:
1327 case ARM::VST4LNq32Pseudo:
1328 case ARM::VST4LNd8Pseudo_UPD:
1329 case ARM::VST4LNd16Pseudo_UPD:
1330 case ARM::VST4LNd32Pseudo_UPD:
1331 case ARM::VST4LNq16Pseudo_UPD:
1332 case ARM::VST4LNq32Pseudo_UPD:
1336 case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false); return true;
1337 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1338 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1339 case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true); return true;
1340 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1341 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1347 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1348 bool Modified = false;
1350 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1352 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
1353 Modified |= ExpandMI(MBB, MBBI);
1360 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1361 const TargetMachine &TM = MF.getTarget();
1362 TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
1363 TRI = TM.getRegisterInfo();
1364 STI = &TM.getSubtarget<ARMSubtarget>();
1365 AFI = MF.getInfo<ARMFunctionInfo>();
1367 bool Modified = false;
1368 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1370 Modified |= ExpandMBB(*MFI);
1371 if (VerifyARMPseudo)
1372 MF.verify(this, "After expanding ARM pseudo instructions.");
1376 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1378 FunctionPass *llvm::createARMExpandPseudoPass() {
1379 return new ARMExpandPseudo();