1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-pseudo"
19 #include "ARMBaseInstrInfo.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
28 #include "llvm/Target/TargetFrameLowering.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
33 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
34 cl::desc("Verify machine code after expanding ARM pseudos"));
37 class ARMExpandPseudo : public MachineFunctionPass {
40 ARMExpandPseudo() : MachineFunctionPass(ID) {}
42 const ARMBaseInstrInfo *TII;
43 const TargetRegisterInfo *TRI;
44 const ARMSubtarget *STI;
47 virtual bool runOnMachineFunction(MachineFunction &Fn);
49 virtual const char *getPassName() const {
50 return "ARM pseudo instruction expansion pass";
54 void TransferImpOps(MachineInstr &OldMI,
55 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
56 bool ExpandMI(MachineBasicBlock &MBB,
57 MachineBasicBlock::iterator MBBI);
58 bool ExpandMBB(MachineBasicBlock &MBB);
59 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
60 void ExpandVST(MachineBasicBlock::iterator &MBBI);
61 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
62 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
63 unsigned Opc, bool IsExt);
64 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator &MBBI);
67 char ARMExpandPseudo::ID = 0;
70 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
71 /// the instructions created from the expansion.
72 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
73 MachineInstrBuilder &UseMI,
74 MachineInstrBuilder &DefMI) {
75 const MCInstrDesc &Desc = OldMI.getDesc();
76 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
78 const MachineOperand &MO = OldMI.getOperand(i);
79 assert(MO.isReg() && MO.getReg());
88 // Constants for register spacing in NEON load/store instructions.
89 // For quad-register load-lane and store-lane pseudo instructors, the
90 // spacing is initially assumed to be EvenDblSpc, and that is changed to
91 // OddDblSpc depending on the lane number operand.
98 // Entries for NEON load/store information table. The table is sorted by
99 // PseudoOpc for fast binary-search lookups.
100 struct NEONLdStTableEntry {
105 bool hasWritebackOperand;
106 uint8_t RegSpacing; // One of type NEONRegSpacing
107 uint8_t NumRegs; // D registers loaded or stored
108 uint8_t RegElts; // elements per D register; used for lane ops
109 // FIXME: Temporary flag to denote whether the real instruction takes
110 // a single register (like the encoding) or all of the registers in
111 // the list (like the asm syntax and the isel DAG). When all definitions
112 // are converted to take only the single encoded register, this will
114 bool copyAllListRegs;
116 // Comparison methods for binary search of the table.
117 bool operator<(const NEONLdStTableEntry &TE) const {
118 return PseudoOpc < TE.PseudoOpc;
120 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
121 return TE.PseudoOpc < PseudoOpc;
123 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
124 const NEONLdStTableEntry &TE) {
125 return PseudoOpc < TE.PseudoOpc;
130 static const NEONLdStTableEntry NEONLdStTable[] = {
131 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
132 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
133 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
134 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
135 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
136 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
138 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
139 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
141 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
142 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
143 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
144 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
145 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
146 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
147 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
148 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
149 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
150 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
152 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
153 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
154 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
155 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
156 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
157 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
158 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
159 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
160 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
162 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
163 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
164 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
165 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
166 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
167 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
169 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
170 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
171 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
172 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
173 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
174 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
175 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
176 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
177 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
178 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
180 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
181 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
182 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
183 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
184 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
185 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
187 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
188 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
189 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
190 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
191 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
192 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
193 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
194 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
195 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
197 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
198 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
199 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
200 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
201 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
202 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
204 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
205 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
206 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
207 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
208 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
209 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
210 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
211 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
212 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
213 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
215 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
216 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
217 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
218 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
219 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
220 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
222 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
223 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
224 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
225 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
226 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
227 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
228 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
229 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
230 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
232 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
233 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
234 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
235 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
236 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
237 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
239 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
240 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
241 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
242 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
243 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
244 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
246 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
247 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
248 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
249 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
250 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
251 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
252 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
253 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
254 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
255 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
257 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
258 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
259 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
260 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
261 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
262 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
263 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
264 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
265 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
267 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
268 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
269 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
270 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
271 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
272 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
273 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
274 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
275 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
276 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
278 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
279 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
280 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
281 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
282 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
283 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
285 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
286 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
287 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
288 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
289 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
290 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
291 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
292 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
293 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
295 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
296 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
297 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
298 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
299 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
300 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
301 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
302 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
303 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
304 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
306 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
307 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
308 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
309 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
310 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
311 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
313 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
314 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
315 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
316 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
317 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
318 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
319 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
320 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
321 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
324 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
325 /// load or store pseudo instruction.
326 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
327 const unsigned NumEntries = array_lengthof(NEONLdStTable);
330 // Make sure the table is sorted.
331 static bool TableChecked = false;
333 for (unsigned i = 0; i != NumEntries-1; ++i)
334 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
335 "NEONLdStTable is not sorted!");
340 const NEONLdStTableEntry *I =
341 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
342 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
347 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
348 /// corresponding to the specified register spacing. Not all of the results
349 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
350 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
351 const TargetRegisterInfo *TRI, unsigned &D0,
352 unsigned &D1, unsigned &D2, unsigned &D3) {
353 if (RegSpc == SingleSpc) {
354 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
355 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
356 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
357 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
358 } else if (RegSpc == EvenDblSpc) {
359 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
360 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
361 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
362 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
364 assert(RegSpc == OddDblSpc && "unknown register spacing");
365 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
366 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
367 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
368 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
372 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
373 /// operands to real VLD instructions with D register operands.
374 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
375 MachineInstr &MI = *MBBI;
376 MachineBasicBlock &MBB = *MI.getParent();
378 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
379 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
380 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
381 unsigned NumRegs = TableEntry->NumRegs;
383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
384 TII->get(TableEntry->RealOpc));
387 bool DstIsDead = MI.getOperand(OpIdx).isDead();
388 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
389 unsigned D0, D1, D2, D3;
390 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
392 if (NumRegs > 1 && TableEntry->copyAllListRegs)
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
394 if (NumRegs > 2 && TableEntry->copyAllListRegs)
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
396 if (NumRegs > 3 && TableEntry->copyAllListRegs)
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
399 if (TableEntry->isUpdating)
400 MIB.addOperand(MI.getOperand(OpIdx++));
402 // Copy the addrmode6 operands.
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
405 // Copy the am6offset operand.
406 if (TableEntry->hasWritebackOperand)
407 MIB.addOperand(MI.getOperand(OpIdx++));
409 // For an instruction writing double-spaced subregs, the pseudo instruction
410 // has an extra operand that is a use of the super-register. Record the
411 // operand index and skip over it.
412 unsigned SrcOpIdx = 0;
413 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
416 // Copy the predicate operands.
417 MIB.addOperand(MI.getOperand(OpIdx++));
418 MIB.addOperand(MI.getOperand(OpIdx++));
420 // Copy the super-register source operand used for double-spaced subregs over
421 // to the new instruction as an implicit operand.
423 MachineOperand MO = MI.getOperand(SrcOpIdx);
424 MO.setImplicit(true);
427 // Add an implicit def for the super-register.
428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
429 TransferImpOps(MI, MIB, MIB);
431 // Transfer memoperands.
432 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
434 MI.eraseFromParent();
437 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
438 /// operands to real VST instructions with D register operands.
439 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
440 MachineInstr &MI = *MBBI;
441 MachineBasicBlock &MBB = *MI.getParent();
443 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
444 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
445 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
446 unsigned NumRegs = TableEntry->NumRegs;
448 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
449 TII->get(TableEntry->RealOpc));
451 if (TableEntry->isUpdating)
452 MIB.addOperand(MI.getOperand(OpIdx++));
454 // Copy the addrmode6 operands.
455 MIB.addOperand(MI.getOperand(OpIdx++));
456 MIB.addOperand(MI.getOperand(OpIdx++));
457 // Copy the am6offset operand.
458 if (TableEntry->hasWritebackOperand)
459 MIB.addOperand(MI.getOperand(OpIdx++));
461 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
462 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
463 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
464 unsigned D0, D1, D2, D3;
465 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
466 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
467 if (NumRegs > 1 && TableEntry->copyAllListRegs)
468 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
469 if (NumRegs > 2 && TableEntry->copyAllListRegs)
470 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
471 if (NumRegs > 3 && TableEntry->copyAllListRegs)
472 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
474 // Copy the predicate operands.
475 MIB.addOperand(MI.getOperand(OpIdx++));
476 MIB.addOperand(MI.getOperand(OpIdx++));
478 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
479 MIB->addRegisterKilled(SrcReg, TRI, true);
480 TransferImpOps(MI, MIB, MIB);
482 // Transfer memoperands.
483 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
485 MI.eraseFromParent();
488 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
489 /// register operands to real instructions with D register operands.
490 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
491 MachineInstr &MI = *MBBI;
492 MachineBasicBlock &MBB = *MI.getParent();
494 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
495 assert(TableEntry && "NEONLdStTable lookup failed");
496 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
497 unsigned NumRegs = TableEntry->NumRegs;
498 unsigned RegElts = TableEntry->RegElts;
500 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
501 TII->get(TableEntry->RealOpc));
503 // The lane operand is always the 3rd from last operand, before the 2
504 // predicate operands.
505 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
507 // Adjust the lane and spacing as needed for Q registers.
508 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
509 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
513 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
515 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
517 bool DstIsDead = false;
518 if (TableEntry->IsLoad) {
519 DstIsDead = MI.getOperand(OpIdx).isDead();
520 DstReg = MI.getOperand(OpIdx++).getReg();
521 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
522 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
524 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
526 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
528 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
531 if (TableEntry->isUpdating)
532 MIB.addOperand(MI.getOperand(OpIdx++));
534 // Copy the addrmode6 operands.
535 MIB.addOperand(MI.getOperand(OpIdx++));
536 MIB.addOperand(MI.getOperand(OpIdx++));
537 // Copy the am6offset operand.
538 if (TableEntry->hasWritebackOperand)
539 MIB.addOperand(MI.getOperand(OpIdx++));
541 // Grab the super-register source.
542 MachineOperand MO = MI.getOperand(OpIdx++);
543 if (!TableEntry->IsLoad)
544 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
546 // Add the subregs as sources of the new instruction.
547 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
548 getKillRegState(MO.isKill()));
549 MIB.addReg(D0, SrcFlags);
551 MIB.addReg(D1, SrcFlags);
553 MIB.addReg(D2, SrcFlags);
555 MIB.addReg(D3, SrcFlags);
557 // Add the lane number operand.
561 // Copy the predicate operands.
562 MIB.addOperand(MI.getOperand(OpIdx++));
563 MIB.addOperand(MI.getOperand(OpIdx++));
565 // Copy the super-register source to be an implicit source.
566 MO.setImplicit(true);
568 if (TableEntry->IsLoad)
569 // Add an implicit def for the super-register.
570 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
571 TransferImpOps(MI, MIB, MIB);
572 // Transfer memoperands.
573 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
574 MI.eraseFromParent();
577 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
578 /// register operands to real instructions with D register operands.
579 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
580 unsigned Opc, bool IsExt) {
581 MachineInstr &MI = *MBBI;
582 MachineBasicBlock &MBB = *MI.getParent();
584 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
587 // Transfer the destination register operand.
588 MIB.addOperand(MI.getOperand(OpIdx++));
590 MIB.addOperand(MI.getOperand(OpIdx++));
592 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
593 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
594 unsigned D0, D1, D2, D3;
595 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
598 // Copy the other source register operand.
599 MIB.addOperand(MI.getOperand(OpIdx++));
601 // Copy the predicate operands.
602 MIB.addOperand(MI.getOperand(OpIdx++));
603 MIB.addOperand(MI.getOperand(OpIdx++));
605 if (SrcIsKill) // Add an implicit kill for the super-reg.
606 MIB->addRegisterKilled(SrcReg, TRI, true);
607 TransferImpOps(MI, MIB, MIB);
608 MI.eraseFromParent();
611 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
612 MachineBasicBlock::iterator &MBBI) {
613 MachineInstr &MI = *MBBI;
614 unsigned Opcode = MI.getOpcode();
615 unsigned PredReg = 0;
616 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
617 unsigned DstReg = MI.getOperand(0).getReg();
618 bool DstIsDead = MI.getOperand(0).isDead();
619 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
620 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
621 MachineInstrBuilder LO16, HI16;
623 if (!STI->hasV6T2Ops() &&
624 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
625 // Expand into a movi + orr.
626 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
627 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
628 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
631 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
632 unsigned ImmVal = (unsigned)MO.getImm();
633 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
634 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
635 LO16 = LO16.addImm(SOImmValV1);
636 HI16 = HI16.addImm(SOImmValV2);
637 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
638 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
639 LO16.addImm(Pred).addReg(PredReg).addReg(0);
640 HI16.addImm(Pred).addReg(PredReg).addReg(0);
641 TransferImpOps(MI, LO16, HI16);
642 MI.eraseFromParent();
646 unsigned LO16Opc = 0;
647 unsigned HI16Opc = 0;
648 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
649 LO16Opc = ARM::t2MOVi16;
650 HI16Opc = ARM::t2MOVTi16;
652 LO16Opc = ARM::MOVi16;
653 HI16Opc = ARM::MOVTi16;
656 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
657 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
658 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
662 unsigned Imm = MO.getImm();
663 unsigned Lo16 = Imm & 0xffff;
664 unsigned Hi16 = (Imm >> 16) & 0xffff;
665 LO16 = LO16.addImm(Lo16);
666 HI16 = HI16.addImm(Hi16);
668 const GlobalValue *GV = MO.getGlobal();
669 unsigned TF = MO.getTargetFlags();
670 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
671 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
674 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
675 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
676 LO16.addImm(Pred).addReg(PredReg);
677 HI16.addImm(Pred).addReg(PredReg);
679 TransferImpOps(MI, LO16, HI16);
680 MI.eraseFromParent();
683 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
684 MachineBasicBlock::iterator MBBI) {
685 MachineInstr &MI = *MBBI;
686 unsigned Opcode = MI.getOpcode();
692 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
693 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
694 MI.getOperand(1).getReg())
695 .addReg(MI.getOperand(2).getReg(),
696 getKillRegState(MI.getOperand(2).isKill()))
697 .addImm(MI.getOperand(3).getImm()) // 'pred'
698 .addReg(MI.getOperand(4).getReg());
700 MI.eraseFromParent();
705 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
706 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
707 MI.getOperand(1).getReg())
708 .addReg(MI.getOperand(2).getReg(),
709 getKillRegState(MI.getOperand(2).isKill()))
710 .addImm(MI.getOperand(3).getImm()) // 'pred'
711 .addReg(MI.getOperand(4).getReg())
712 .addReg(0); // 's' bit
714 MI.eraseFromParent();
718 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
719 (MI.getOperand(1).getReg()))
720 .addReg(MI.getOperand(2).getReg(),
721 getKillRegState(MI.getOperand(2).isKill()))
722 .addImm(MI.getOperand(3).getImm())
723 .addImm(MI.getOperand(4).getImm()) // 'pred'
724 .addReg(MI.getOperand(5).getReg())
725 .addReg(0); // 's' bit
727 MI.eraseFromParent();
731 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
732 (MI.getOperand(1).getReg()))
733 .addReg(MI.getOperand(2).getReg(),
734 getKillRegState(MI.getOperand(2).isKill()))
735 .addReg(MI.getOperand(3).getReg(),
736 getKillRegState(MI.getOperand(3).isKill()))
737 .addImm(MI.getOperand(4).getImm())
738 .addImm(MI.getOperand(5).getImm()) // 'pred'
739 .addReg(MI.getOperand(6).getReg())
740 .addReg(0); // 's' bit
742 MI.eraseFromParent();
745 case ARM::t2MOVCCi16:
746 case ARM::MOVCCi16: {
747 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
748 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
749 MI.getOperand(1).getReg())
750 .addImm(MI.getOperand(2).getImm())
751 .addImm(MI.getOperand(3).getImm()) // 'pred'
752 .addReg(MI.getOperand(4).getReg());
753 MI.eraseFromParent();
758 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
759 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
760 MI.getOperand(1).getReg())
761 .addImm(MI.getOperand(2).getImm())
762 .addImm(MI.getOperand(3).getImm()) // 'pred'
763 .addReg(MI.getOperand(4).getReg())
764 .addReg(0); // 's' bit
766 MI.eraseFromParent();
771 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
772 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
773 MI.getOperand(1).getReg())
774 .addImm(MI.getOperand(2).getImm())
775 .addImm(MI.getOperand(3).getImm()) // 'pred'
776 .addReg(MI.getOperand(4).getReg())
777 .addReg(0); // 's' bit
779 MI.eraseFromParent();
782 case ARM::t2MOVCClsl:
783 case ARM::t2MOVCClsr:
784 case ARM::t2MOVCCasr:
785 case ARM::t2MOVCCror: {
788 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
789 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
790 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
791 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
792 default: llvm_unreachable("unexpeced conditional move");
794 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
795 MI.getOperand(1).getReg())
796 .addReg(MI.getOperand(2).getReg())
797 .addImm(MI.getOperand(3).getImm())
798 .addImm(MI.getOperand(4).getImm()) // 'pred'
799 .addReg(MI.getOperand(5).getReg())
800 .addReg(0); // 's' bit
801 MI.eraseFromParent();
804 case ARM::Int_eh_sjlj_dispatchsetup: {
805 MachineFunction &MF = *MI.getParent()->getParent();
806 const ARMBaseInstrInfo *AII =
807 static_cast<const ARMBaseInstrInfo*>(TII);
808 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
809 // For functions using a base pointer, we rematerialize it (via the frame
810 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
811 // for us. Otherwise, expand to nothing.
812 if (RI.hasBasePointer(MF)) {
813 int32_t NumBytes = AFI->getFramePtrSpillOffset();
814 unsigned FramePtr = RI.getFrameRegister(MF);
815 assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
816 "base pointer without frame pointer?");
818 if (AFI->isThumb2Function()) {
819 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
820 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
821 } else if (AFI->isThumbFunction()) {
822 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
823 FramePtr, -NumBytes, *TII, RI);
825 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
826 FramePtr, -NumBytes, ARMCC::AL, 0,
829 // If there's dynamic realignment, adjust for it.
830 if (RI.needsStackRealignment(MF)) {
831 MachineFrameInfo *MFI = MF.getFrameInfo();
832 unsigned MaxAlign = MFI->getMaxAlignment();
833 assert (!AFI->isThumb1OnlyFunction());
834 // Emit bic r6, r6, MaxAlign
835 unsigned bicOpc = AFI->isThumbFunction() ?
836 ARM::t2BICri : ARM::BICri;
837 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
838 TII->get(bicOpc), ARM::R6)
839 .addReg(ARM::R6, RegState::Kill)
840 .addImm(MaxAlign-1)));
844 MI.eraseFromParent();
848 case ARM::MOVsrl_flag:
849 case ARM::MOVsra_flag: {
850 // These are just fancy MOVs insructions.
851 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
852 MI.getOperand(0).getReg())
853 .addOperand(MI.getOperand(1))
854 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ?
855 ARM_AM::lsr : ARM_AM::asr),
857 .addReg(ARM::CPSR, RegState::Define);
858 MI.eraseFromParent();
862 // This encodes as "MOVs Rd, Rm, rrx
863 MachineInstrBuilder MIB =
864 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
865 MI.getOperand(0).getReg())
866 .addOperand(MI.getOperand(1))
867 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
869 TransferImpOps(MI, MIB, MIB);
870 MI.eraseFromParent();
875 MachineInstrBuilder MIB =
876 BuildMI(MBB, MBBI, MI.getDebugLoc(),
877 TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
878 .addExternalSymbol("__aeabi_read_tp", 0);
880 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
881 TransferImpOps(MI, MIB, MIB);
882 MI.eraseFromParent();
885 case ARM::tLDRpci_pic:
886 case ARM::t2LDRpci_pic: {
887 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
888 ? ARM::tLDRpci : ARM::t2LDRpci;
889 unsigned DstReg = MI.getOperand(0).getReg();
890 bool DstIsDead = MI.getOperand(0).isDead();
891 MachineInstrBuilder MIB1 =
892 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
893 TII->get(NewLdOpc), DstReg)
894 .addOperand(MI.getOperand(1)));
895 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
896 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
897 TII->get(ARM::tPICADD))
898 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
900 .addOperand(MI.getOperand(2));
901 TransferImpOps(MI, MIB1, MIB2);
902 MI.eraseFromParent();
906 case ARM::MOV_ga_dyn:
907 case ARM::MOV_ga_pcrel:
908 case ARM::MOV_ga_pcrel_ldr:
909 case ARM::t2MOV_ga_dyn:
910 case ARM::t2MOV_ga_pcrel: {
911 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
912 unsigned LabelId = AFI->createPICLabelUId();
913 unsigned DstReg = MI.getOperand(0).getReg();
914 bool DstIsDead = MI.getOperand(0).isDead();
915 const MachineOperand &MO1 = MI.getOperand(1);
916 const GlobalValue *GV = MO1.getGlobal();
917 unsigned TF = MO1.getTargetFlags();
918 bool isARM = (Opcode != ARM::t2MOV_ga_pcrel && Opcode!=ARM::t2MOV_ga_dyn);
919 bool isPIC = (Opcode != ARM::MOV_ga_dyn && Opcode != ARM::t2MOV_ga_dyn);
920 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
921 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
922 unsigned LO16TF = isPIC
923 ? ARMII::MO_LO16_NONLAZY_PIC : ARMII::MO_LO16_NONLAZY;
924 unsigned HI16TF = isPIC
925 ? ARMII::MO_HI16_NONLAZY_PIC : ARMII::MO_HI16_NONLAZY;
926 unsigned PICAddOpc = isARM
927 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
929 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
930 TII->get(LO16Opc), DstReg)
931 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
933 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
934 TII->get(HI16Opc), DstReg)
936 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
939 TransferImpOps(MI, MIB1, MIB2);
940 MI.eraseFromParent();
944 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
946 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
947 .addReg(DstReg).addImm(LabelId);
949 AddDefaultPred(MIB3);
950 if (Opcode == ARM::MOV_ga_pcrel_ldr)
951 MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
953 TransferImpOps(MI, MIB1, MIB3);
954 MI.eraseFromParent();
959 case ARM::MOVCCi32imm:
960 case ARM::t2MOVi32imm:
961 case ARM::t2MOVCCi32imm:
962 ExpandMOV32BitImm(MBB, MBBI);
966 unsigned NewOpc = ARM::VLDMDIA;
967 MachineInstrBuilder MIB =
968 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
971 // Grab the Q register destination.
972 bool DstIsDead = MI.getOperand(OpIdx).isDead();
973 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
975 // Copy the source register.
976 MIB.addOperand(MI.getOperand(OpIdx++));
978 // Copy the predicate operands.
979 MIB.addOperand(MI.getOperand(OpIdx++));
980 MIB.addOperand(MI.getOperand(OpIdx++));
982 // Add the destination operands (D subregs).
983 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
984 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
985 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
986 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
988 // Add an implicit def for the super-register.
989 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
990 TransferImpOps(MI, MIB, MIB);
991 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
992 MI.eraseFromParent();
997 unsigned NewOpc = ARM::VSTMDIA;
998 MachineInstrBuilder MIB =
999 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1002 // Grab the Q register source.
1003 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1004 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1006 // Copy the destination register.
1007 MIB.addOperand(MI.getOperand(OpIdx++));
1009 // Copy the predicate operands.
1010 MIB.addOperand(MI.getOperand(OpIdx++));
1011 MIB.addOperand(MI.getOperand(OpIdx++));
1013 // Add the source operands (D subregs).
1014 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1015 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1016 MIB.addReg(D0).addReg(D1);
1018 if (SrcIsKill) // Add an implicit kill for the Q register.
1019 MIB->addRegisterKilled(SrcReg, TRI, true);
1021 TransferImpOps(MI, MIB, MIB);
1022 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1023 MI.eraseFromParent();
1028 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q :
1030 MachineInstrBuilder MIB =
1031 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1033 unsigned SrcReg = MI.getOperand(1).getReg();
1034 unsigned Lane = TRI->getEncodingValue(SrcReg) & 1;
1035 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
1036 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
1037 &ARM::DPR_VFP2RegClass);
1038 // The lane is [0,1] for the containing DReg superregister.
1039 // Copy the dst/src register operands.
1040 MIB.addOperand(MI.getOperand(OpIdx++));
1043 // Add the lane select operand.
1045 // Add the predicate operands.
1046 MIB.addOperand(MI.getOperand(OpIdx++));
1047 MIB.addOperand(MI.getOperand(OpIdx++));
1049 TransferImpOps(MI, MIB, MIB);
1050 MI.eraseFromParent();
1054 case ARM::VLD2q8Pseudo:
1055 case ARM::VLD2q16Pseudo:
1056 case ARM::VLD2q32Pseudo:
1057 case ARM::VLD2q8PseudoWB_fixed:
1058 case ARM::VLD2q16PseudoWB_fixed:
1059 case ARM::VLD2q32PseudoWB_fixed:
1060 case ARM::VLD2q8PseudoWB_register:
1061 case ARM::VLD2q16PseudoWB_register:
1062 case ARM::VLD2q32PseudoWB_register:
1063 case ARM::VLD3d8Pseudo:
1064 case ARM::VLD3d16Pseudo:
1065 case ARM::VLD3d32Pseudo:
1066 case ARM::VLD1d64TPseudo:
1067 case ARM::VLD3d8Pseudo_UPD:
1068 case ARM::VLD3d16Pseudo_UPD:
1069 case ARM::VLD3d32Pseudo_UPD:
1070 case ARM::VLD3q8Pseudo_UPD:
1071 case ARM::VLD3q16Pseudo_UPD:
1072 case ARM::VLD3q32Pseudo_UPD:
1073 case ARM::VLD3q8oddPseudo:
1074 case ARM::VLD3q16oddPseudo:
1075 case ARM::VLD3q32oddPseudo:
1076 case ARM::VLD3q8oddPseudo_UPD:
1077 case ARM::VLD3q16oddPseudo_UPD:
1078 case ARM::VLD3q32oddPseudo_UPD:
1079 case ARM::VLD4d8Pseudo:
1080 case ARM::VLD4d16Pseudo:
1081 case ARM::VLD4d32Pseudo:
1082 case ARM::VLD1d64QPseudo:
1083 case ARM::VLD4d8Pseudo_UPD:
1084 case ARM::VLD4d16Pseudo_UPD:
1085 case ARM::VLD4d32Pseudo_UPD:
1086 case ARM::VLD4q8Pseudo_UPD:
1087 case ARM::VLD4q16Pseudo_UPD:
1088 case ARM::VLD4q32Pseudo_UPD:
1089 case ARM::VLD4q8oddPseudo:
1090 case ARM::VLD4q16oddPseudo:
1091 case ARM::VLD4q32oddPseudo:
1092 case ARM::VLD4q8oddPseudo_UPD:
1093 case ARM::VLD4q16oddPseudo_UPD:
1094 case ARM::VLD4q32oddPseudo_UPD:
1095 case ARM::VLD3DUPd8Pseudo:
1096 case ARM::VLD3DUPd16Pseudo:
1097 case ARM::VLD3DUPd32Pseudo:
1098 case ARM::VLD3DUPd8Pseudo_UPD:
1099 case ARM::VLD3DUPd16Pseudo_UPD:
1100 case ARM::VLD3DUPd32Pseudo_UPD:
1101 case ARM::VLD4DUPd8Pseudo:
1102 case ARM::VLD4DUPd16Pseudo:
1103 case ARM::VLD4DUPd32Pseudo:
1104 case ARM::VLD4DUPd8Pseudo_UPD:
1105 case ARM::VLD4DUPd16Pseudo_UPD:
1106 case ARM::VLD4DUPd32Pseudo_UPD:
1110 case ARM::VST2q8Pseudo:
1111 case ARM::VST2q16Pseudo:
1112 case ARM::VST2q32Pseudo:
1113 case ARM::VST2q8PseudoWB_fixed:
1114 case ARM::VST2q16PseudoWB_fixed:
1115 case ARM::VST2q32PseudoWB_fixed:
1116 case ARM::VST2q8PseudoWB_register:
1117 case ARM::VST2q16PseudoWB_register:
1118 case ARM::VST2q32PseudoWB_register:
1119 case ARM::VST3d8Pseudo:
1120 case ARM::VST3d16Pseudo:
1121 case ARM::VST3d32Pseudo:
1122 case ARM::VST1d64TPseudo:
1123 case ARM::VST3d8Pseudo_UPD:
1124 case ARM::VST3d16Pseudo_UPD:
1125 case ARM::VST3d32Pseudo_UPD:
1126 case ARM::VST1d64TPseudoWB_fixed:
1127 case ARM::VST1d64TPseudoWB_register:
1128 case ARM::VST3q8Pseudo_UPD:
1129 case ARM::VST3q16Pseudo_UPD:
1130 case ARM::VST3q32Pseudo_UPD:
1131 case ARM::VST3q8oddPseudo:
1132 case ARM::VST3q16oddPseudo:
1133 case ARM::VST3q32oddPseudo:
1134 case ARM::VST3q8oddPseudo_UPD:
1135 case ARM::VST3q16oddPseudo_UPD:
1136 case ARM::VST3q32oddPseudo_UPD:
1137 case ARM::VST4d8Pseudo:
1138 case ARM::VST4d16Pseudo:
1139 case ARM::VST4d32Pseudo:
1140 case ARM::VST1d64QPseudo:
1141 case ARM::VST4d8Pseudo_UPD:
1142 case ARM::VST4d16Pseudo_UPD:
1143 case ARM::VST4d32Pseudo_UPD:
1144 case ARM::VST1d64QPseudoWB_fixed:
1145 case ARM::VST1d64QPseudoWB_register:
1146 case ARM::VST4q8Pseudo_UPD:
1147 case ARM::VST4q16Pseudo_UPD:
1148 case ARM::VST4q32Pseudo_UPD:
1149 case ARM::VST4q8oddPseudo:
1150 case ARM::VST4q16oddPseudo:
1151 case ARM::VST4q32oddPseudo:
1152 case ARM::VST4q8oddPseudo_UPD:
1153 case ARM::VST4q16oddPseudo_UPD:
1154 case ARM::VST4q32oddPseudo_UPD:
1158 case ARM::VLD1LNq8Pseudo:
1159 case ARM::VLD1LNq16Pseudo:
1160 case ARM::VLD1LNq32Pseudo:
1161 case ARM::VLD1LNq8Pseudo_UPD:
1162 case ARM::VLD1LNq16Pseudo_UPD:
1163 case ARM::VLD1LNq32Pseudo_UPD:
1164 case ARM::VLD2LNd8Pseudo:
1165 case ARM::VLD2LNd16Pseudo:
1166 case ARM::VLD2LNd32Pseudo:
1167 case ARM::VLD2LNq16Pseudo:
1168 case ARM::VLD2LNq32Pseudo:
1169 case ARM::VLD2LNd8Pseudo_UPD:
1170 case ARM::VLD2LNd16Pseudo_UPD:
1171 case ARM::VLD2LNd32Pseudo_UPD:
1172 case ARM::VLD2LNq16Pseudo_UPD:
1173 case ARM::VLD2LNq32Pseudo_UPD:
1174 case ARM::VLD3LNd8Pseudo:
1175 case ARM::VLD3LNd16Pseudo:
1176 case ARM::VLD3LNd32Pseudo:
1177 case ARM::VLD3LNq16Pseudo:
1178 case ARM::VLD3LNq32Pseudo:
1179 case ARM::VLD3LNd8Pseudo_UPD:
1180 case ARM::VLD3LNd16Pseudo_UPD:
1181 case ARM::VLD3LNd32Pseudo_UPD:
1182 case ARM::VLD3LNq16Pseudo_UPD:
1183 case ARM::VLD3LNq32Pseudo_UPD:
1184 case ARM::VLD4LNd8Pseudo:
1185 case ARM::VLD4LNd16Pseudo:
1186 case ARM::VLD4LNd32Pseudo:
1187 case ARM::VLD4LNq16Pseudo:
1188 case ARM::VLD4LNq32Pseudo:
1189 case ARM::VLD4LNd8Pseudo_UPD:
1190 case ARM::VLD4LNd16Pseudo_UPD:
1191 case ARM::VLD4LNd32Pseudo_UPD:
1192 case ARM::VLD4LNq16Pseudo_UPD:
1193 case ARM::VLD4LNq32Pseudo_UPD:
1194 case ARM::VST1LNq8Pseudo:
1195 case ARM::VST1LNq16Pseudo:
1196 case ARM::VST1LNq32Pseudo:
1197 case ARM::VST1LNq8Pseudo_UPD:
1198 case ARM::VST1LNq16Pseudo_UPD:
1199 case ARM::VST1LNq32Pseudo_UPD:
1200 case ARM::VST2LNd8Pseudo:
1201 case ARM::VST2LNd16Pseudo:
1202 case ARM::VST2LNd32Pseudo:
1203 case ARM::VST2LNq16Pseudo:
1204 case ARM::VST2LNq32Pseudo:
1205 case ARM::VST2LNd8Pseudo_UPD:
1206 case ARM::VST2LNd16Pseudo_UPD:
1207 case ARM::VST2LNd32Pseudo_UPD:
1208 case ARM::VST2LNq16Pseudo_UPD:
1209 case ARM::VST2LNq32Pseudo_UPD:
1210 case ARM::VST3LNd8Pseudo:
1211 case ARM::VST3LNd16Pseudo:
1212 case ARM::VST3LNd32Pseudo:
1213 case ARM::VST3LNq16Pseudo:
1214 case ARM::VST3LNq32Pseudo:
1215 case ARM::VST3LNd8Pseudo_UPD:
1216 case ARM::VST3LNd16Pseudo_UPD:
1217 case ARM::VST3LNd32Pseudo_UPD:
1218 case ARM::VST3LNq16Pseudo_UPD:
1219 case ARM::VST3LNq32Pseudo_UPD:
1220 case ARM::VST4LNd8Pseudo:
1221 case ARM::VST4LNd16Pseudo:
1222 case ARM::VST4LNd32Pseudo:
1223 case ARM::VST4LNq16Pseudo:
1224 case ARM::VST4LNq32Pseudo:
1225 case ARM::VST4LNd8Pseudo_UPD:
1226 case ARM::VST4LNd16Pseudo_UPD:
1227 case ARM::VST4LNd32Pseudo_UPD:
1228 case ARM::VST4LNq16Pseudo_UPD:
1229 case ARM::VST4LNq32Pseudo_UPD:
1233 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1234 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1235 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1236 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1240 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1241 bool Modified = false;
1243 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1245 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
1246 Modified |= ExpandMI(MBB, MBBI);
1253 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1254 const TargetMachine &TM = MF.getTarget();
1255 TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
1256 TRI = TM.getRegisterInfo();
1257 STI = &TM.getSubtarget<ARMSubtarget>();
1258 AFI = MF.getInfo<ARMFunctionInfo>();
1260 bool Modified = false;
1261 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1263 Modified |= ExpandMBB(*MFI);
1264 if (VerifyARMPseudo)
1265 MF.verify(this, "After expanding ARM pseudo instructions.");
1269 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1271 FunctionPass *llvm::createARMExpandPseudoPass() {
1272 return new ARMExpandPseudo();