1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
18 #include "ARMBaseInstrInfo.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineInstrBundle.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
30 #include "llvm/Target/TargetFrameLowering.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
34 #define DEBUG_TYPE "arm-pseudo"
37 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
38 cl::desc("Verify machine code after expanding ARM pseudos"));
41 class ARMExpandPseudo : public MachineFunctionPass {
44 ARMExpandPseudo() : MachineFunctionPass(ID) {}
46 const ARMBaseInstrInfo *TII;
47 const TargetRegisterInfo *TRI;
48 const ARMSubtarget *STI;
51 bool runOnMachineFunction(MachineFunction &Fn) override;
53 const char *getPassName() const override {
54 return "ARM pseudo instruction expansion pass";
58 void TransferImpOps(MachineInstr &OldMI,
59 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
60 bool ExpandMI(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MBBI);
62 bool ExpandMBB(MachineBasicBlock &MBB);
63 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
64 void ExpandVST(MachineBasicBlock::iterator &MBBI);
65 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
66 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
67 unsigned Opc, bool IsExt);
68 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator &MBBI);
71 char ARMExpandPseudo::ID = 0;
74 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
75 /// the instructions created from the expansion.
76 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
77 MachineInstrBuilder &UseMI,
78 MachineInstrBuilder &DefMI) {
79 const MCInstrDesc &Desc = OldMI.getDesc();
80 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
82 const MachineOperand &MO = OldMI.getOperand(i);
83 assert(MO.isReg() && MO.getReg());
92 // Constants for register spacing in NEON load/store instructions.
93 // For quad-register load-lane and store-lane pseudo instructors, the
94 // spacing is initially assumed to be EvenDblSpc, and that is changed to
95 // OddDblSpc depending on the lane number operand.
102 // Entries for NEON load/store information table. The table is sorted by
103 // PseudoOpc for fast binary-search lookups.
104 struct NEONLdStTableEntry {
109 bool hasWritebackOperand;
110 uint8_t RegSpacing; // One of type NEONRegSpacing
111 uint8_t NumRegs; // D registers loaded or stored
112 uint8_t RegElts; // elements per D register; used for lane ops
113 // FIXME: Temporary flag to denote whether the real instruction takes
114 // a single register (like the encoding) or all of the registers in
115 // the list (like the asm syntax and the isel DAG). When all definitions
116 // are converted to take only the single encoded register, this will
118 bool copyAllListRegs;
120 // Comparison methods for binary search of the table.
121 bool operator<(const NEONLdStTableEntry &TE) const {
122 return PseudoOpc < TE.PseudoOpc;
124 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
125 return TE.PseudoOpc < PseudoOpc;
127 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
128 const NEONLdStTableEntry &TE) {
129 return PseudoOpc < TE.PseudoOpc;
134 static const NEONLdStTableEntry NEONLdStTable[] = {
135 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
136 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
137 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
138 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
139 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
140 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
142 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
143 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
144 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
145 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
147 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
148 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
149 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
150 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
151 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
152 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
153 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
154 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
155 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
156 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
158 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
159 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
160 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
161 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
162 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
163 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
164 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
165 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
166 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
168 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
169 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
170 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
171 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
172 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
173 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
175 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
176 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
177 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
178 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
179 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
180 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
181 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
182 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
183 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
184 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
186 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
187 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
188 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
189 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
190 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
191 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
193 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
194 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
195 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
196 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
197 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
198 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
199 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
200 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
201 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
203 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
204 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
205 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
206 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
207 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
208 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
210 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
211 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
212 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
213 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
214 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
215 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
216 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
217 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
218 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
219 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
221 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
222 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
223 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
224 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
225 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
226 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
228 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
229 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
230 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
231 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
232 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
233 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
234 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
235 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
236 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
238 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
239 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
240 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
241 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
242 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
243 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
245 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
246 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
247 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
248 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
249 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
250 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
252 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
253 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
254 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
255 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
256 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
257 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
258 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
259 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
260 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
261 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
263 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
264 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
265 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
266 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
267 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
268 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
269 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
270 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
271 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
273 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
274 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
275 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
276 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
277 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
278 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
279 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
280 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
281 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
282 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
284 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
285 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
286 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
287 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
288 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
289 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
291 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
292 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
293 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
294 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
295 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
296 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
297 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
298 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
299 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
301 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
302 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
303 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
304 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
305 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
306 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
307 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
308 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
309 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
310 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
312 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
313 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
314 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
315 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
316 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
317 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
319 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
320 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
321 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
322 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
323 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
324 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
325 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
326 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
327 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
330 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
331 /// load or store pseudo instruction.
332 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
333 const unsigned NumEntries = array_lengthof(NEONLdStTable);
336 // Make sure the table is sorted.
337 static bool TableChecked = false;
339 for (unsigned i = 0; i != NumEntries-1; ++i)
340 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
341 "NEONLdStTable is not sorted!");
346 const NEONLdStTableEntry *I =
347 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
348 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
353 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
354 /// corresponding to the specified register spacing. Not all of the results
355 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
356 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
357 const TargetRegisterInfo *TRI, unsigned &D0,
358 unsigned &D1, unsigned &D2, unsigned &D3) {
359 if (RegSpc == SingleSpc) {
360 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
361 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
362 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
363 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
364 } else if (RegSpc == EvenDblSpc) {
365 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
366 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
367 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
368 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
370 assert(RegSpc == OddDblSpc && "unknown register spacing");
371 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
372 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
373 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
374 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
378 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
379 /// operands to real VLD instructions with D register operands.
380 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
381 MachineInstr &MI = *MBBI;
382 MachineBasicBlock &MBB = *MI.getParent();
384 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
385 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
386 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
387 unsigned NumRegs = TableEntry->NumRegs;
389 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
390 TII->get(TableEntry->RealOpc));
393 bool DstIsDead = MI.getOperand(OpIdx).isDead();
394 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
395 unsigned D0, D1, D2, D3;
396 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
397 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
398 if (NumRegs > 1 && TableEntry->copyAllListRegs)
399 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
400 if (NumRegs > 2 && TableEntry->copyAllListRegs)
401 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
402 if (NumRegs > 3 && TableEntry->copyAllListRegs)
403 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
405 if (TableEntry->isUpdating)
406 MIB.addOperand(MI.getOperand(OpIdx++));
408 // Copy the addrmode6 operands.
409 MIB.addOperand(MI.getOperand(OpIdx++));
410 MIB.addOperand(MI.getOperand(OpIdx++));
411 // Copy the am6offset operand.
412 if (TableEntry->hasWritebackOperand)
413 MIB.addOperand(MI.getOperand(OpIdx++));
415 // For an instruction writing double-spaced subregs, the pseudo instruction
416 // has an extra operand that is a use of the super-register. Record the
417 // operand index and skip over it.
418 unsigned SrcOpIdx = 0;
419 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
422 // Copy the predicate operands.
423 MIB.addOperand(MI.getOperand(OpIdx++));
424 MIB.addOperand(MI.getOperand(OpIdx++));
426 // Copy the super-register source operand used for double-spaced subregs over
427 // to the new instruction as an implicit operand.
429 MachineOperand MO = MI.getOperand(SrcOpIdx);
430 MO.setImplicit(true);
433 // Add an implicit def for the super-register.
434 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
435 TransferImpOps(MI, MIB, MIB);
437 // Transfer memoperands.
438 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
440 MI.eraseFromParent();
443 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
444 /// operands to real VST instructions with D register operands.
445 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
446 MachineInstr &MI = *MBBI;
447 MachineBasicBlock &MBB = *MI.getParent();
449 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
450 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
451 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
452 unsigned NumRegs = TableEntry->NumRegs;
454 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
455 TII->get(TableEntry->RealOpc));
457 if (TableEntry->isUpdating)
458 MIB.addOperand(MI.getOperand(OpIdx++));
460 // Copy the addrmode6 operands.
461 MIB.addOperand(MI.getOperand(OpIdx++));
462 MIB.addOperand(MI.getOperand(OpIdx++));
463 // Copy the am6offset operand.
464 if (TableEntry->hasWritebackOperand)
465 MIB.addOperand(MI.getOperand(OpIdx++));
467 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
468 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
469 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
470 unsigned D0, D1, D2, D3;
471 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
472 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
473 if (NumRegs > 1 && TableEntry->copyAllListRegs)
474 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
475 if (NumRegs > 2 && TableEntry->copyAllListRegs)
476 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
477 if (NumRegs > 3 && TableEntry->copyAllListRegs)
478 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
480 // Copy the predicate operands.
481 MIB.addOperand(MI.getOperand(OpIdx++));
482 MIB.addOperand(MI.getOperand(OpIdx++));
484 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
485 MIB->addRegisterKilled(SrcReg, TRI, true);
486 else if (!SrcIsUndef)
487 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
488 TransferImpOps(MI, MIB, MIB);
490 // Transfer memoperands.
491 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
493 MI.eraseFromParent();
496 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
497 /// register operands to real instructions with D register operands.
498 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
499 MachineInstr &MI = *MBBI;
500 MachineBasicBlock &MBB = *MI.getParent();
502 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
503 assert(TableEntry && "NEONLdStTable lookup failed");
504 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
505 unsigned NumRegs = TableEntry->NumRegs;
506 unsigned RegElts = TableEntry->RegElts;
508 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
509 TII->get(TableEntry->RealOpc));
511 // The lane operand is always the 3rd from last operand, before the 2
512 // predicate operands.
513 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
515 // Adjust the lane and spacing as needed for Q registers.
516 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
517 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
521 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
523 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
525 bool DstIsDead = false;
526 if (TableEntry->IsLoad) {
527 DstIsDead = MI.getOperand(OpIdx).isDead();
528 DstReg = MI.getOperand(OpIdx++).getReg();
529 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
530 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
532 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
534 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
536 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
539 if (TableEntry->isUpdating)
540 MIB.addOperand(MI.getOperand(OpIdx++));
542 // Copy the addrmode6 operands.
543 MIB.addOperand(MI.getOperand(OpIdx++));
544 MIB.addOperand(MI.getOperand(OpIdx++));
545 // Copy the am6offset operand.
546 if (TableEntry->hasWritebackOperand)
547 MIB.addOperand(MI.getOperand(OpIdx++));
549 // Grab the super-register source.
550 MachineOperand MO = MI.getOperand(OpIdx++);
551 if (!TableEntry->IsLoad)
552 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
554 // Add the subregs as sources of the new instruction.
555 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
556 getKillRegState(MO.isKill()));
557 MIB.addReg(D0, SrcFlags);
559 MIB.addReg(D1, SrcFlags);
561 MIB.addReg(D2, SrcFlags);
563 MIB.addReg(D3, SrcFlags);
565 // Add the lane number operand.
569 // Copy the predicate operands.
570 MIB.addOperand(MI.getOperand(OpIdx++));
571 MIB.addOperand(MI.getOperand(OpIdx++));
573 // Copy the super-register source to be an implicit source.
574 MO.setImplicit(true);
576 if (TableEntry->IsLoad)
577 // Add an implicit def for the super-register.
578 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
579 TransferImpOps(MI, MIB, MIB);
580 // Transfer memoperands.
581 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
582 MI.eraseFromParent();
585 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
586 /// register operands to real instructions with D register operands.
587 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
588 unsigned Opc, bool IsExt) {
589 MachineInstr &MI = *MBBI;
590 MachineBasicBlock &MBB = *MI.getParent();
592 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
595 // Transfer the destination register operand.
596 MIB.addOperand(MI.getOperand(OpIdx++));
598 MIB.addOperand(MI.getOperand(OpIdx++));
600 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
601 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
602 unsigned D0, D1, D2, D3;
603 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
606 // Copy the other source register operand.
607 MIB.addOperand(MI.getOperand(OpIdx++));
609 // Copy the predicate operands.
610 MIB.addOperand(MI.getOperand(OpIdx++));
611 MIB.addOperand(MI.getOperand(OpIdx++));
613 // Add an implicit kill and use for the super-reg.
614 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
615 TransferImpOps(MI, MIB, MIB);
616 MI.eraseFromParent();
619 static bool IsAnAddressOperand(const MachineOperand &MO) {
620 // This check is overly conservative. Unless we are certain that the machine
621 // operand is not a symbol reference, we return that it is a symbol reference.
622 // This is important as the load pair may not be split up Windows.
623 switch (MO.getType()) {
624 case MachineOperand::MO_Register:
625 case MachineOperand::MO_Immediate:
626 case MachineOperand::MO_CImmediate:
627 case MachineOperand::MO_FPImmediate:
629 case MachineOperand::MO_MachineBasicBlock:
631 case MachineOperand::MO_FrameIndex:
633 case MachineOperand::MO_ConstantPoolIndex:
634 case MachineOperand::MO_TargetIndex:
635 case MachineOperand::MO_JumpTableIndex:
636 case MachineOperand::MO_ExternalSymbol:
637 case MachineOperand::MO_GlobalAddress:
638 case MachineOperand::MO_BlockAddress:
640 case MachineOperand::MO_RegisterMask:
641 case MachineOperand::MO_RegisterLiveOut:
643 case MachineOperand::MO_Metadata:
644 case MachineOperand::MO_MCSymbol:
646 case MachineOperand::MO_CFIIndex:
649 llvm_unreachable("unhandled machine operand type");
652 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
653 MachineBasicBlock::iterator &MBBI) {
654 MachineInstr &MI = *MBBI;
655 unsigned Opcode = MI.getOpcode();
656 unsigned PredReg = 0;
657 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
658 unsigned DstReg = MI.getOperand(0).getReg();
659 bool DstIsDead = MI.getOperand(0).isDead();
660 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
661 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
662 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
663 MachineInstrBuilder LO16, HI16;
665 if (!STI->hasV6T2Ops() &&
666 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
667 // FIXME Windows CE supports older ARM CPUs
668 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
670 // Expand into a movi + orr.
671 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
672 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
673 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
676 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
677 unsigned ImmVal = (unsigned)MO.getImm();
678 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
679 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
680 LO16 = LO16.addImm(SOImmValV1);
681 HI16 = HI16.addImm(SOImmValV2);
682 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
683 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
684 LO16.addImm(Pred).addReg(PredReg).addReg(0);
685 HI16.addImm(Pred).addReg(PredReg).addReg(0);
686 TransferImpOps(MI, LO16, HI16);
687 MI.eraseFromParent();
691 unsigned LO16Opc = 0;
692 unsigned HI16Opc = 0;
693 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
694 LO16Opc = ARM::t2MOVi16;
695 HI16Opc = ARM::t2MOVTi16;
697 LO16Opc = ARM::MOVi16;
698 HI16Opc = ARM::MOVTi16;
701 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
702 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
703 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
706 switch (MO.getType()) {
707 case MachineOperand::MO_Immediate: {
708 unsigned Imm = MO.getImm();
709 unsigned Lo16 = Imm & 0xffff;
710 unsigned Hi16 = (Imm >> 16) & 0xffff;
711 LO16 = LO16.addImm(Lo16);
712 HI16 = HI16.addImm(Hi16);
715 case MachineOperand::MO_ExternalSymbol: {
716 const char *ES = MO.getSymbolName();
717 unsigned TF = MO.getTargetFlags();
718 LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16);
719 HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16);
723 const GlobalValue *GV = MO.getGlobal();
724 unsigned TF = MO.getTargetFlags();
725 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
726 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
731 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
732 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
733 LO16.addImm(Pred).addReg(PredReg);
734 HI16.addImm(Pred).addReg(PredReg);
736 if (RequiresBundling)
737 finalizeBundle(MBB, &*LO16, &*MBBI);
739 TransferImpOps(MI, LO16, HI16);
740 MI.eraseFromParent();
743 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
744 MachineBasicBlock::iterator MBBI) {
745 MachineInstr &MI = *MBBI;
746 unsigned Opcode = MI.getOpcode();
751 case ARM::TCRETURNdi:
752 case ARM::TCRETURNri: {
753 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
754 assert(MBBI->isReturn() &&
755 "Can only insert epilog into returning blocks");
756 unsigned RetOpcode = MBBI->getOpcode();
757 DebugLoc dl = MBBI->getDebugLoc();
758 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
759 MBB.getParent()->getSubtarget().getInstrInfo());
761 // Tail call return: adjust the stack pointer and jump to callee.
762 MBBI = MBB.getLastNonDebugInstr();
763 MachineOperand &JumpTarget = MBBI->getOperand(0);
765 // Jump to label or value in register.
766 if (RetOpcode == ARM::TCRETURNdi) {
769 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND)
771 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
772 if (JumpTarget.isGlobal())
773 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
774 JumpTarget.getTargetFlags());
776 assert(JumpTarget.isSymbol());
777 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
778 JumpTarget.getTargetFlags());
781 // Add the default predicate in Thumb mode.
783 MIB.addImm(ARMCC::AL).addReg(0);
784 } else if (RetOpcode == ARM::TCRETURNri) {
785 BuildMI(MBB, MBBI, dl,
786 TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr))
787 .addReg(JumpTarget.getReg(), RegState::Kill);
790 MachineInstr *NewMI = std::prev(MBBI);
791 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
792 NewMI->addOperand(MBBI->getOperand(i));
794 // Delete the pseudo instruction TCRETURN.
801 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
802 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
803 MI.getOperand(1).getReg())
804 .addOperand(MI.getOperand(2))
805 .addImm(MI.getOperand(3).getImm()) // 'pred'
806 .addOperand(MI.getOperand(4));
808 MI.eraseFromParent();
813 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
814 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
815 MI.getOperand(1).getReg())
816 .addOperand(MI.getOperand(2))
817 .addImm(MI.getOperand(3).getImm()) // 'pred'
818 .addOperand(MI.getOperand(4))
819 .addReg(0); // 's' bit
821 MI.eraseFromParent();
825 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
826 (MI.getOperand(1).getReg()))
827 .addOperand(MI.getOperand(2))
828 .addImm(MI.getOperand(3).getImm())
829 .addImm(MI.getOperand(4).getImm()) // 'pred'
830 .addOperand(MI.getOperand(5))
831 .addReg(0); // 's' bit
833 MI.eraseFromParent();
837 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
838 (MI.getOperand(1).getReg()))
839 .addOperand(MI.getOperand(2))
840 .addOperand(MI.getOperand(3))
841 .addImm(MI.getOperand(4).getImm())
842 .addImm(MI.getOperand(5).getImm()) // 'pred'
843 .addOperand(MI.getOperand(6))
844 .addReg(0); // 's' bit
846 MI.eraseFromParent();
849 case ARM::t2MOVCCi16:
850 case ARM::MOVCCi16: {
851 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
852 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
853 MI.getOperand(1).getReg())
854 .addImm(MI.getOperand(2).getImm())
855 .addImm(MI.getOperand(3).getImm()) // 'pred'
856 .addOperand(MI.getOperand(4));
857 MI.eraseFromParent();
862 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
863 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
864 MI.getOperand(1).getReg())
865 .addImm(MI.getOperand(2).getImm())
866 .addImm(MI.getOperand(3).getImm()) // 'pred'
867 .addOperand(MI.getOperand(4))
868 .addReg(0); // 's' bit
870 MI.eraseFromParent();
875 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
876 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
877 MI.getOperand(1).getReg())
878 .addImm(MI.getOperand(2).getImm())
879 .addImm(MI.getOperand(3).getImm()) // 'pred'
880 .addOperand(MI.getOperand(4))
881 .addReg(0); // 's' bit
883 MI.eraseFromParent();
886 case ARM::t2MOVCClsl:
887 case ARM::t2MOVCClsr:
888 case ARM::t2MOVCCasr:
889 case ARM::t2MOVCCror: {
892 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
893 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
894 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
895 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
896 default: llvm_unreachable("unexpeced conditional move");
898 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
899 MI.getOperand(1).getReg())
900 .addOperand(MI.getOperand(2))
901 .addImm(MI.getOperand(3).getImm())
902 .addImm(MI.getOperand(4).getImm()) // 'pred'
903 .addOperand(MI.getOperand(5))
904 .addReg(0); // 's' bit
905 MI.eraseFromParent();
908 case ARM::Int_eh_sjlj_dispatchsetup: {
909 MachineFunction &MF = *MI.getParent()->getParent();
910 const ARMBaseInstrInfo *AII =
911 static_cast<const ARMBaseInstrInfo*>(TII);
912 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
913 // For functions using a base pointer, we rematerialize it (via the frame
914 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
915 // for us. Otherwise, expand to nothing.
916 if (RI.hasBasePointer(MF)) {
917 int32_t NumBytes = AFI->getFramePtrSpillOffset();
918 unsigned FramePtr = RI.getFrameRegister(MF);
919 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
920 "base pointer without frame pointer?");
922 if (AFI->isThumb2Function()) {
923 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
924 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
925 } else if (AFI->isThumbFunction()) {
926 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
927 FramePtr, -NumBytes, *TII, RI);
929 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
930 FramePtr, -NumBytes, ARMCC::AL, 0,
933 // If there's dynamic realignment, adjust for it.
934 if (RI.needsStackRealignment(MF)) {
935 MachineFrameInfo *MFI = MF.getFrameInfo();
936 unsigned MaxAlign = MFI->getMaxAlignment();
937 assert (!AFI->isThumb1OnlyFunction());
938 // Emit bic r6, r6, MaxAlign
939 assert(MaxAlign <= 256 && "The BIC instruction cannot encode "
940 "immediates larger than 256 with all lower "
942 unsigned bicOpc = AFI->isThumbFunction() ?
943 ARM::t2BICri : ARM::BICri;
944 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
945 TII->get(bicOpc), ARM::R6)
946 .addReg(ARM::R6, RegState::Kill)
947 .addImm(MaxAlign-1)));
951 MI.eraseFromParent();
955 case ARM::MOVsrl_flag:
956 case ARM::MOVsra_flag: {
957 // These are just fancy MOVs instructions.
958 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
959 MI.getOperand(0).getReg())
960 .addOperand(MI.getOperand(1))
961 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ?
962 ARM_AM::lsr : ARM_AM::asr),
964 .addReg(ARM::CPSR, RegState::Define);
965 MI.eraseFromParent();
969 // This encodes as "MOVs Rd, Rm, rrx
970 MachineInstrBuilder MIB =
971 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
972 MI.getOperand(0).getReg())
973 .addOperand(MI.getOperand(1))
974 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
976 TransferImpOps(MI, MIB, MIB);
977 MI.eraseFromParent();
982 MachineInstrBuilder MIB;
983 if (Opcode == ARM::tTPsoft)
984 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
986 .addImm((unsigned)ARMCC::AL).addReg(0)
987 .addExternalSymbol("__aeabi_read_tp", 0);
989 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
991 .addExternalSymbol("__aeabi_read_tp", 0);
993 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
994 TransferImpOps(MI, MIB, MIB);
995 MI.eraseFromParent();
998 case ARM::tLDRpci_pic:
999 case ARM::t2LDRpci_pic: {
1000 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
1001 ? ARM::tLDRpci : ARM::t2LDRpci;
1002 unsigned DstReg = MI.getOperand(0).getReg();
1003 bool DstIsDead = MI.getOperand(0).isDead();
1004 MachineInstrBuilder MIB1 =
1005 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
1006 TII->get(NewLdOpc), DstReg)
1007 .addOperand(MI.getOperand(1)));
1008 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1009 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1010 TII->get(ARM::tPICADD))
1011 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1013 .addOperand(MI.getOperand(2));
1014 TransferImpOps(MI, MIB1, MIB2);
1015 MI.eraseFromParent();
1019 case ARM::LDRLIT_ga_abs:
1020 case ARM::LDRLIT_ga_pcrel:
1021 case ARM::LDRLIT_ga_pcrel_ldr:
1022 case ARM::tLDRLIT_ga_abs:
1023 case ARM::tLDRLIT_ga_pcrel: {
1024 unsigned DstReg = MI.getOperand(0).getReg();
1025 bool DstIsDead = MI.getOperand(0).isDead();
1026 const MachineOperand &MO1 = MI.getOperand(1);
1027 const GlobalValue *GV = MO1.getGlobal();
1029 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
1031 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
1032 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
1033 unsigned PICAddOpc =
1035 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1038 // We need a new const-pool entry to load from.
1039 MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
1040 unsigned ARMPCLabelIndex = 0;
1041 MachineConstantPoolValue *CPV;
1044 unsigned PCAdj = IsARM ? 8 : 4;
1045 ARMPCLabelIndex = AFI->createPICLabelUId();
1046 CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex,
1047 ARMCP::CPValue, PCAdj);
1049 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
1051 MachineInstrBuilder MIB =
1052 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
1053 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1056 AddDefaultPred(MIB);
1059 MachineInstrBuilder MIB =
1060 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
1061 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1063 .addImm(ARMPCLabelIndex);
1066 AddDefaultPred(MIB);
1069 MI.eraseFromParent();
1072 case ARM::MOV_ga_pcrel:
1073 case ARM::MOV_ga_pcrel_ldr:
1074 case ARM::t2MOV_ga_pcrel: {
1075 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
1076 unsigned LabelId = AFI->createPICLabelUId();
1077 unsigned DstReg = MI.getOperand(0).getReg();
1078 bool DstIsDead = MI.getOperand(0).isDead();
1079 const MachineOperand &MO1 = MI.getOperand(1);
1080 const GlobalValue *GV = MO1.getGlobal();
1081 unsigned TF = MO1.getTargetFlags();
1082 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
1083 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
1084 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
1085 unsigned LO16TF = TF | ARMII::MO_LO16;
1086 unsigned HI16TF = TF | ARMII::MO_HI16;
1087 unsigned PICAddOpc = isARM
1088 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1090 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1091 TII->get(LO16Opc), DstReg)
1092 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
1095 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
1097 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
1100 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1101 TII->get(PICAddOpc))
1102 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1103 .addReg(DstReg).addImm(LabelId);
1105 AddDefaultPred(MIB3);
1106 if (Opcode == ARM::MOV_ga_pcrel_ldr)
1107 MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1109 TransferImpOps(MI, MIB1, MIB3);
1110 MI.eraseFromParent();
1114 case ARM::MOVi32imm:
1115 case ARM::MOVCCi32imm:
1116 case ARM::t2MOVi32imm:
1117 case ARM::t2MOVCCi32imm:
1118 ExpandMOV32BitImm(MBB, MBBI);
1121 case ARM::SUBS_PC_LR: {
1122 MachineInstrBuilder MIB =
1123 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1125 .addOperand(MI.getOperand(0))
1126 .addOperand(MI.getOperand(1))
1127 .addOperand(MI.getOperand(2))
1128 .addReg(ARM::CPSR, RegState::Undef);
1129 TransferImpOps(MI, MIB, MIB);
1130 MI.eraseFromParent();
1133 case ARM::VLDMQIA: {
1134 unsigned NewOpc = ARM::VLDMDIA;
1135 MachineInstrBuilder MIB =
1136 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1139 // Grab the Q register destination.
1140 bool DstIsDead = MI.getOperand(OpIdx).isDead();
1141 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1143 // Copy the source register.
1144 MIB.addOperand(MI.getOperand(OpIdx++));
1146 // Copy the predicate operands.
1147 MIB.addOperand(MI.getOperand(OpIdx++));
1148 MIB.addOperand(MI.getOperand(OpIdx++));
1150 // Add the destination operands (D subregs).
1151 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1152 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1153 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1154 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1156 // Add an implicit def for the super-register.
1157 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1158 TransferImpOps(MI, MIB, MIB);
1159 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1160 MI.eraseFromParent();
1164 case ARM::VSTMQIA: {
1165 unsigned NewOpc = ARM::VSTMDIA;
1166 MachineInstrBuilder MIB =
1167 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1170 // Grab the Q register source.
1171 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1172 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1174 // Copy the destination register.
1175 MIB.addOperand(MI.getOperand(OpIdx++));
1177 // Copy the predicate operands.
1178 MIB.addOperand(MI.getOperand(OpIdx++));
1179 MIB.addOperand(MI.getOperand(OpIdx++));
1181 // Add the source operands (D subregs).
1182 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1183 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1184 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
1185 .addReg(D1, SrcIsKill ? RegState::Kill : 0);
1187 if (SrcIsKill) // Add an implicit kill for the Q register.
1188 MIB->addRegisterKilled(SrcReg, TRI, true);
1190 TransferImpOps(MI, MIB, MIB);
1191 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1192 MI.eraseFromParent();
1196 case ARM::VLD2q8Pseudo:
1197 case ARM::VLD2q16Pseudo:
1198 case ARM::VLD2q32Pseudo:
1199 case ARM::VLD2q8PseudoWB_fixed:
1200 case ARM::VLD2q16PseudoWB_fixed:
1201 case ARM::VLD2q32PseudoWB_fixed:
1202 case ARM::VLD2q8PseudoWB_register:
1203 case ARM::VLD2q16PseudoWB_register:
1204 case ARM::VLD2q32PseudoWB_register:
1205 case ARM::VLD3d8Pseudo:
1206 case ARM::VLD3d16Pseudo:
1207 case ARM::VLD3d32Pseudo:
1208 case ARM::VLD1d64TPseudo:
1209 case ARM::VLD1d64TPseudoWB_fixed:
1210 case ARM::VLD3d8Pseudo_UPD:
1211 case ARM::VLD3d16Pseudo_UPD:
1212 case ARM::VLD3d32Pseudo_UPD:
1213 case ARM::VLD3q8Pseudo_UPD:
1214 case ARM::VLD3q16Pseudo_UPD:
1215 case ARM::VLD3q32Pseudo_UPD:
1216 case ARM::VLD3q8oddPseudo:
1217 case ARM::VLD3q16oddPseudo:
1218 case ARM::VLD3q32oddPseudo:
1219 case ARM::VLD3q8oddPseudo_UPD:
1220 case ARM::VLD3q16oddPseudo_UPD:
1221 case ARM::VLD3q32oddPseudo_UPD:
1222 case ARM::VLD4d8Pseudo:
1223 case ARM::VLD4d16Pseudo:
1224 case ARM::VLD4d32Pseudo:
1225 case ARM::VLD1d64QPseudo:
1226 case ARM::VLD1d64QPseudoWB_fixed:
1227 case ARM::VLD4d8Pseudo_UPD:
1228 case ARM::VLD4d16Pseudo_UPD:
1229 case ARM::VLD4d32Pseudo_UPD:
1230 case ARM::VLD4q8Pseudo_UPD:
1231 case ARM::VLD4q16Pseudo_UPD:
1232 case ARM::VLD4q32Pseudo_UPD:
1233 case ARM::VLD4q8oddPseudo:
1234 case ARM::VLD4q16oddPseudo:
1235 case ARM::VLD4q32oddPseudo:
1236 case ARM::VLD4q8oddPseudo_UPD:
1237 case ARM::VLD4q16oddPseudo_UPD:
1238 case ARM::VLD4q32oddPseudo_UPD:
1239 case ARM::VLD3DUPd8Pseudo:
1240 case ARM::VLD3DUPd16Pseudo:
1241 case ARM::VLD3DUPd32Pseudo:
1242 case ARM::VLD3DUPd8Pseudo_UPD:
1243 case ARM::VLD3DUPd16Pseudo_UPD:
1244 case ARM::VLD3DUPd32Pseudo_UPD:
1245 case ARM::VLD4DUPd8Pseudo:
1246 case ARM::VLD4DUPd16Pseudo:
1247 case ARM::VLD4DUPd32Pseudo:
1248 case ARM::VLD4DUPd8Pseudo_UPD:
1249 case ARM::VLD4DUPd16Pseudo_UPD:
1250 case ARM::VLD4DUPd32Pseudo_UPD:
1254 case ARM::VST2q8Pseudo:
1255 case ARM::VST2q16Pseudo:
1256 case ARM::VST2q32Pseudo:
1257 case ARM::VST2q8PseudoWB_fixed:
1258 case ARM::VST2q16PseudoWB_fixed:
1259 case ARM::VST2q32PseudoWB_fixed:
1260 case ARM::VST2q8PseudoWB_register:
1261 case ARM::VST2q16PseudoWB_register:
1262 case ARM::VST2q32PseudoWB_register:
1263 case ARM::VST3d8Pseudo:
1264 case ARM::VST3d16Pseudo:
1265 case ARM::VST3d32Pseudo:
1266 case ARM::VST1d64TPseudo:
1267 case ARM::VST3d8Pseudo_UPD:
1268 case ARM::VST3d16Pseudo_UPD:
1269 case ARM::VST3d32Pseudo_UPD:
1270 case ARM::VST1d64TPseudoWB_fixed:
1271 case ARM::VST1d64TPseudoWB_register:
1272 case ARM::VST3q8Pseudo_UPD:
1273 case ARM::VST3q16Pseudo_UPD:
1274 case ARM::VST3q32Pseudo_UPD:
1275 case ARM::VST3q8oddPseudo:
1276 case ARM::VST3q16oddPseudo:
1277 case ARM::VST3q32oddPseudo:
1278 case ARM::VST3q8oddPseudo_UPD:
1279 case ARM::VST3q16oddPseudo_UPD:
1280 case ARM::VST3q32oddPseudo_UPD:
1281 case ARM::VST4d8Pseudo:
1282 case ARM::VST4d16Pseudo:
1283 case ARM::VST4d32Pseudo:
1284 case ARM::VST1d64QPseudo:
1285 case ARM::VST4d8Pseudo_UPD:
1286 case ARM::VST4d16Pseudo_UPD:
1287 case ARM::VST4d32Pseudo_UPD:
1288 case ARM::VST1d64QPseudoWB_fixed:
1289 case ARM::VST1d64QPseudoWB_register:
1290 case ARM::VST4q8Pseudo_UPD:
1291 case ARM::VST4q16Pseudo_UPD:
1292 case ARM::VST4q32Pseudo_UPD:
1293 case ARM::VST4q8oddPseudo:
1294 case ARM::VST4q16oddPseudo:
1295 case ARM::VST4q32oddPseudo:
1296 case ARM::VST4q8oddPseudo_UPD:
1297 case ARM::VST4q16oddPseudo_UPD:
1298 case ARM::VST4q32oddPseudo_UPD:
1302 case ARM::VLD1LNq8Pseudo:
1303 case ARM::VLD1LNq16Pseudo:
1304 case ARM::VLD1LNq32Pseudo:
1305 case ARM::VLD1LNq8Pseudo_UPD:
1306 case ARM::VLD1LNq16Pseudo_UPD:
1307 case ARM::VLD1LNq32Pseudo_UPD:
1308 case ARM::VLD2LNd8Pseudo:
1309 case ARM::VLD2LNd16Pseudo:
1310 case ARM::VLD2LNd32Pseudo:
1311 case ARM::VLD2LNq16Pseudo:
1312 case ARM::VLD2LNq32Pseudo:
1313 case ARM::VLD2LNd8Pseudo_UPD:
1314 case ARM::VLD2LNd16Pseudo_UPD:
1315 case ARM::VLD2LNd32Pseudo_UPD:
1316 case ARM::VLD2LNq16Pseudo_UPD:
1317 case ARM::VLD2LNq32Pseudo_UPD:
1318 case ARM::VLD3LNd8Pseudo:
1319 case ARM::VLD3LNd16Pseudo:
1320 case ARM::VLD3LNd32Pseudo:
1321 case ARM::VLD3LNq16Pseudo:
1322 case ARM::VLD3LNq32Pseudo:
1323 case ARM::VLD3LNd8Pseudo_UPD:
1324 case ARM::VLD3LNd16Pseudo_UPD:
1325 case ARM::VLD3LNd32Pseudo_UPD:
1326 case ARM::VLD3LNq16Pseudo_UPD:
1327 case ARM::VLD3LNq32Pseudo_UPD:
1328 case ARM::VLD4LNd8Pseudo:
1329 case ARM::VLD4LNd16Pseudo:
1330 case ARM::VLD4LNd32Pseudo:
1331 case ARM::VLD4LNq16Pseudo:
1332 case ARM::VLD4LNq32Pseudo:
1333 case ARM::VLD4LNd8Pseudo_UPD:
1334 case ARM::VLD4LNd16Pseudo_UPD:
1335 case ARM::VLD4LNd32Pseudo_UPD:
1336 case ARM::VLD4LNq16Pseudo_UPD:
1337 case ARM::VLD4LNq32Pseudo_UPD:
1338 case ARM::VST1LNq8Pseudo:
1339 case ARM::VST1LNq16Pseudo:
1340 case ARM::VST1LNq32Pseudo:
1341 case ARM::VST1LNq8Pseudo_UPD:
1342 case ARM::VST1LNq16Pseudo_UPD:
1343 case ARM::VST1LNq32Pseudo_UPD:
1344 case ARM::VST2LNd8Pseudo:
1345 case ARM::VST2LNd16Pseudo:
1346 case ARM::VST2LNd32Pseudo:
1347 case ARM::VST2LNq16Pseudo:
1348 case ARM::VST2LNq32Pseudo:
1349 case ARM::VST2LNd8Pseudo_UPD:
1350 case ARM::VST2LNd16Pseudo_UPD:
1351 case ARM::VST2LNd32Pseudo_UPD:
1352 case ARM::VST2LNq16Pseudo_UPD:
1353 case ARM::VST2LNq32Pseudo_UPD:
1354 case ARM::VST3LNd8Pseudo:
1355 case ARM::VST3LNd16Pseudo:
1356 case ARM::VST3LNd32Pseudo:
1357 case ARM::VST3LNq16Pseudo:
1358 case ARM::VST3LNq32Pseudo:
1359 case ARM::VST3LNd8Pseudo_UPD:
1360 case ARM::VST3LNd16Pseudo_UPD:
1361 case ARM::VST3LNd32Pseudo_UPD:
1362 case ARM::VST3LNq16Pseudo_UPD:
1363 case ARM::VST3LNq32Pseudo_UPD:
1364 case ARM::VST4LNd8Pseudo:
1365 case ARM::VST4LNd16Pseudo:
1366 case ARM::VST4LNd32Pseudo:
1367 case ARM::VST4LNq16Pseudo:
1368 case ARM::VST4LNq32Pseudo:
1369 case ARM::VST4LNd8Pseudo_UPD:
1370 case ARM::VST4LNd16Pseudo_UPD:
1371 case ARM::VST4LNd32Pseudo_UPD:
1372 case ARM::VST4LNq16Pseudo_UPD:
1373 case ARM::VST4LNq32Pseudo_UPD:
1377 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1378 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1379 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1380 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1384 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1385 bool Modified = false;
1387 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1389 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
1390 Modified |= ExpandMI(MBB, MBBI);
1397 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1398 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1399 TII = STI->getInstrInfo();
1400 TRI = STI->getRegisterInfo();
1401 AFI = MF.getInfo<ARMFunctionInfo>();
1403 bool Modified = false;
1404 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1406 Modified |= ExpandMBB(*MFI);
1407 if (VerifyARMPseudo)
1408 MF.verify(this, "After expanding ARM pseudo instructions.");
1412 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1414 FunctionPass *llvm::createARMExpandPseudoPass() {
1415 return new ARMExpandPseudo();