1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-pseudo"
19 #include "ARMBaseInstrInfo.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
26 class ARMExpandPseudo : public MachineFunctionPass {
27 // Constants for register spacing in NEON load/store instructions.
36 ARMExpandPseudo() : MachineFunctionPass(ID) {}
38 const TargetInstrInfo *TII;
39 const TargetRegisterInfo *TRI;
41 virtual bool runOnMachineFunction(MachineFunction &Fn);
43 virtual const char *getPassName() const {
44 return "ARM pseudo instruction expansion pass";
48 void TransferImpOps(MachineInstr &OldMI,
49 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
50 bool ExpandMBB(MachineBasicBlock &MBB);
51 void ExpandVLD(MachineBasicBlock::iterator &MBBI, unsigned Opc,
52 bool hasWriteBack, NEONRegSpacing RegSpc, unsigned NumRegs);
53 void ExpandVST(MachineBasicBlock::iterator &MBBI, unsigned Opc,
54 bool hasWriteBack, NEONRegSpacing RegSpc, unsigned NumRegs);
56 char ARMExpandPseudo::ID = 0;
59 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
60 /// the instructions created from the expansion.
61 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
62 MachineInstrBuilder &UseMI,
63 MachineInstrBuilder &DefMI) {
64 const TargetInstrDesc &Desc = OldMI.getDesc();
65 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
67 const MachineOperand &MO = OldMI.getOperand(i);
68 assert(MO.isReg() && MO.getReg());
76 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
77 /// operands to real VLD instructions with D register operands.
78 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI,
79 unsigned Opc, bool hasWriteBack,
80 NEONRegSpacing RegSpc, unsigned NumRegs) {
81 MachineInstr &MI = *MBBI;
82 MachineBasicBlock &MBB = *MI.getParent();
84 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
87 bool DstIsDead = MI.getOperand(OpIdx).isDead();
88 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
89 unsigned D0, D1, D2, D3;
90 if (RegSpc == SingleSpc) {
91 D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
92 D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
93 D2 = TRI->getSubReg(DstReg, ARM::dsub_2);
94 D3 = TRI->getSubReg(DstReg, ARM::dsub_3);
95 } else if (RegSpc == EvenDblSpc) {
96 D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
97 D1 = TRI->getSubReg(DstReg, ARM::dsub_2);
98 D2 = TRI->getSubReg(DstReg, ARM::dsub_4);
99 D3 = TRI->getSubReg(DstReg, ARM::dsub_6);
101 assert(RegSpc == OddDblSpc && "unknown register spacing for VLD");
102 D0 = TRI->getSubReg(DstReg, ARM::dsub_1);
103 D1 = TRI->getSubReg(DstReg, ARM::dsub_3);
104 D2 = TRI->getSubReg(DstReg, ARM::dsub_5);
105 D3 = TRI->getSubReg(DstReg, ARM::dsub_7);
107 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
108 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
110 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
112 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
115 MIB.addOperand(MI.getOperand(OpIdx++));
117 // Copy the addrmode6 operands.
118 MIB.addOperand(MI.getOperand(OpIdx++));
119 MIB.addOperand(MI.getOperand(OpIdx++));
120 // Copy the am6offset operand.
122 MIB.addOperand(MI.getOperand(OpIdx++));
124 MIB = AddDefaultPred(MIB);
125 // For an instruction writing double-spaced subregs, the pseudo instruction
126 // has an extra operand that is a use of the super-register. Copy that over
127 // to the new instruction as an implicit operand.
128 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) {
129 MachineOperand MO = MI.getOperand(OpIdx);
130 MO.setImplicit(true);
133 // Add an implicit def for the super-register.
134 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
135 TransferImpOps(MI, MIB, MIB);
136 MI.eraseFromParent();
139 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
140 /// operands to real VST instructions with D register operands.
141 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI,
142 unsigned Opc, bool hasWriteBack,
143 NEONRegSpacing RegSpc, unsigned NumRegs) {
144 MachineInstr &MI = *MBBI;
145 MachineBasicBlock &MBB = *MI.getParent();
147 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
150 MIB.addOperand(MI.getOperand(OpIdx++));
152 // Copy the addrmode6 operands.
153 MIB.addOperand(MI.getOperand(OpIdx++));
154 MIB.addOperand(MI.getOperand(OpIdx++));
155 // Copy the am6offset operand.
157 MIB.addOperand(MI.getOperand(OpIdx++));
159 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
160 unsigned SrcReg = MI.getOperand(OpIdx).getReg();
161 unsigned D0, D1, D2, D3;
162 if (RegSpc == SingleSpc) {
163 D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
164 D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
165 D2 = TRI->getSubReg(SrcReg, ARM::dsub_2);
166 D3 = TRI->getSubReg(SrcReg, ARM::dsub_3);
167 } else if (RegSpc == EvenDblSpc) {
168 D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
169 D1 = TRI->getSubReg(SrcReg, ARM::dsub_2);
170 D2 = TRI->getSubReg(SrcReg, ARM::dsub_4);
171 D3 = TRI->getSubReg(SrcReg, ARM::dsub_6);
173 assert(RegSpc == OddDblSpc && "unknown register spacing for VST");
174 D0 = TRI->getSubReg(SrcReg, ARM::dsub_1);
175 D1 = TRI->getSubReg(SrcReg, ARM::dsub_3);
176 D2 = TRI->getSubReg(SrcReg, ARM::dsub_5);
177 D3 = TRI->getSubReg(SrcReg, ARM::dsub_7);
180 MIB.addReg(D0).addReg(D1);
185 MIB = AddDefaultPred(MIB);
186 TransferImpOps(MI, MIB, MIB);
188 // Add an implicit kill for the super-reg.
189 (*MIB).addRegisterKilled(SrcReg, TRI, true);
190 MI.eraseFromParent();
193 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
194 bool Modified = false;
196 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
198 MachineInstr &MI = *MBBI;
199 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
201 bool ModifiedOp = true;
202 unsigned Opcode = MI.getOpcode();
208 case ARM::tLDRpci_pic:
209 case ARM::t2LDRpci_pic: {
210 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
211 ? ARM::tLDRpci : ARM::t2LDRpci;
212 unsigned DstReg = MI.getOperand(0).getReg();
213 bool DstIsDead = MI.getOperand(0).isDead();
214 MachineInstrBuilder MIB1 =
215 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
216 TII->get(NewLdOpc), DstReg)
217 .addOperand(MI.getOperand(1)));
218 (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
219 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
220 TII->get(ARM::tPICADD))
221 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
223 .addOperand(MI.getOperand(2));
224 TransferImpOps(MI, MIB1, MIB2);
225 MI.eraseFromParent();
230 case ARM::t2MOVi32imm: {
231 unsigned PredReg = 0;
232 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
233 unsigned DstReg = MI.getOperand(0).getReg();
234 bool DstIsDead = MI.getOperand(0).isDead();
235 const MachineOperand &MO = MI.getOperand(1);
236 MachineInstrBuilder LO16, HI16;
238 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
239 TII->get(Opcode == ARM::MOVi32imm ?
240 ARM::MOVi16 : ARM::t2MOVi16),
242 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
243 TII->get(Opcode == ARM::MOVi32imm ?
244 ARM::MOVTi16 : ARM::t2MOVTi16))
245 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
249 unsigned Imm = MO.getImm();
250 unsigned Lo16 = Imm & 0xffff;
251 unsigned Hi16 = (Imm >> 16) & 0xffff;
252 LO16 = LO16.addImm(Lo16);
253 HI16 = HI16.addImm(Hi16);
255 const GlobalValue *GV = MO.getGlobal();
256 unsigned TF = MO.getTargetFlags();
257 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
258 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
260 (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
261 (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
262 LO16.addImm(Pred).addReg(PredReg);
263 HI16.addImm(Pred).addReg(PredReg);
264 TransferImpOps(MI, LO16, HI16);
265 MI.eraseFromParent();
270 unsigned DstReg = MI.getOperand(0).getReg();
271 bool DstIsDead = MI.getOperand(0).isDead();
272 unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0);
273 unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1);
274 unsigned SrcReg = MI.getOperand(1).getReg();
275 bool SrcIsKill = MI.getOperand(1).isKill();
276 unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0);
277 unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1);
278 MachineInstrBuilder Even =
279 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
280 TII->get(ARM::VMOVQ))
282 getDefRegState(true) | getDeadRegState(DstIsDead))
283 .addReg(EvenSrc, getKillRegState(SrcIsKill)));
284 MachineInstrBuilder Odd =
285 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
286 TII->get(ARM::VMOVQ))
288 getDefRegState(true) | getDeadRegState(DstIsDead))
289 .addReg(OddSrc, getKillRegState(SrcIsKill)));
290 TransferImpOps(MI, Even, Odd);
291 MI.eraseFromParent();
294 case ARM::VLD1q8Pseudo:
295 ExpandVLD(MBBI, ARM::VLD1q8, false, SingleSpc, 2); break;
296 case ARM::VLD1q16Pseudo:
297 ExpandVLD(MBBI, ARM::VLD1q16, false, SingleSpc, 2); break;
298 case ARM::VLD1q32Pseudo:
299 ExpandVLD(MBBI, ARM::VLD1q32, false, SingleSpc, 2); break;
300 case ARM::VLD1q64Pseudo:
301 ExpandVLD(MBBI, ARM::VLD1q64, false, SingleSpc, 2); break;
302 case ARM::VLD1q8Pseudo_UPD:
303 ExpandVLD(MBBI, ARM::VLD1q8, true, SingleSpc, 2); break;
304 case ARM::VLD1q16Pseudo_UPD:
305 ExpandVLD(MBBI, ARM::VLD1q16, true, SingleSpc, 2); break;
306 case ARM::VLD1q32Pseudo_UPD:
307 ExpandVLD(MBBI, ARM::VLD1q32, true, SingleSpc, 2); break;
308 case ARM::VLD1q64Pseudo_UPD:
309 ExpandVLD(MBBI, ARM::VLD1q64, true, SingleSpc, 2); break;
311 case ARM::VLD2d8Pseudo:
312 ExpandVLD(MBBI, ARM::VLD2d8, false, SingleSpc, 2); break;
313 case ARM::VLD2d16Pseudo:
314 ExpandVLD(MBBI, ARM::VLD2d16, false, SingleSpc, 2); break;
315 case ARM::VLD2d32Pseudo:
316 ExpandVLD(MBBI, ARM::VLD2d32, false, SingleSpc, 2); break;
317 case ARM::VLD2q8Pseudo:
318 ExpandVLD(MBBI, ARM::VLD2q8, false, SingleSpc, 4); break;
319 case ARM::VLD2q16Pseudo:
320 ExpandVLD(MBBI, ARM::VLD2q16, false, SingleSpc, 4); break;
321 case ARM::VLD2q32Pseudo:
322 ExpandVLD(MBBI, ARM::VLD2q32, false, SingleSpc, 4); break;
323 case ARM::VLD2d8Pseudo_UPD:
324 ExpandVLD(MBBI, ARM::VLD2d8, true, SingleSpc, 2); break;
325 case ARM::VLD2d16Pseudo_UPD:
326 ExpandVLD(MBBI, ARM::VLD2d16, true, SingleSpc, 2); break;
327 case ARM::VLD2d32Pseudo_UPD:
328 ExpandVLD(MBBI, ARM::VLD2d32, true, SingleSpc, 2); break;
329 case ARM::VLD2q8Pseudo_UPD:
330 ExpandVLD(MBBI, ARM::VLD2q8, true, SingleSpc, 4); break;
331 case ARM::VLD2q16Pseudo_UPD:
332 ExpandVLD(MBBI, ARM::VLD2q16, true, SingleSpc, 4); break;
333 case ARM::VLD2q32Pseudo_UPD:
334 ExpandVLD(MBBI, ARM::VLD2q32, true, SingleSpc, 4); break;
336 case ARM::VLD3d8Pseudo:
337 ExpandVLD(MBBI, ARM::VLD3d8, false, SingleSpc, 3); break;
338 case ARM::VLD3d16Pseudo:
339 ExpandVLD(MBBI, ARM::VLD3d16, false, SingleSpc, 3); break;
340 case ARM::VLD3d32Pseudo:
341 ExpandVLD(MBBI, ARM::VLD3d32, false, SingleSpc, 3); break;
342 case ARM::VLD1d64TPseudo:
343 ExpandVLD(MBBI, ARM::VLD1d64T, false, SingleSpc, 3); break;
344 case ARM::VLD3d8Pseudo_UPD:
345 ExpandVLD(MBBI, ARM::VLD3d8_UPD, true, SingleSpc, 3); break;
346 case ARM::VLD3d16Pseudo_UPD:
347 ExpandVLD(MBBI, ARM::VLD3d16_UPD, true, SingleSpc, 3); break;
348 case ARM::VLD3d32Pseudo_UPD:
349 ExpandVLD(MBBI, ARM::VLD3d32_UPD, true, SingleSpc, 3); break;
350 case ARM::VLD1d64TPseudo_UPD:
351 ExpandVLD(MBBI, ARM::VLD1d64T_UPD, true, SingleSpc, 3); break;
352 case ARM::VLD3q8Pseudo_UPD:
353 ExpandVLD(MBBI, ARM::VLD3q8_UPD, true, EvenDblSpc, 3); break;
354 case ARM::VLD3q16Pseudo_UPD:
355 ExpandVLD(MBBI, ARM::VLD3q16_UPD, true, EvenDblSpc, 3); break;
356 case ARM::VLD3q32Pseudo_UPD:
357 ExpandVLD(MBBI, ARM::VLD3q32_UPD, true, EvenDblSpc, 3); break;
358 case ARM::VLD3q8oddPseudo_UPD:
359 ExpandVLD(MBBI, ARM::VLD3q8_UPD, true, OddDblSpc, 3); break;
360 case ARM::VLD3q16oddPseudo_UPD:
361 ExpandVLD(MBBI, ARM::VLD3q16_UPD, true, OddDblSpc, 3); break;
362 case ARM::VLD3q32oddPseudo_UPD:
363 ExpandVLD(MBBI, ARM::VLD3q32_UPD, true, OddDblSpc, 3); break;
365 case ARM::VLD4d8Pseudo:
366 ExpandVLD(MBBI, ARM::VLD4d8, false, SingleSpc, 4); break;
367 case ARM::VLD4d16Pseudo:
368 ExpandVLD(MBBI, ARM::VLD4d16, false, SingleSpc, 4); break;
369 case ARM::VLD4d32Pseudo:
370 ExpandVLD(MBBI, ARM::VLD4d32, false, SingleSpc, 4); break;
371 case ARM::VLD1d64QPseudo:
372 ExpandVLD(MBBI, ARM::VLD1d64Q, false, SingleSpc, 4); break;
373 case ARM::VLD4d8Pseudo_UPD:
374 ExpandVLD(MBBI, ARM::VLD4d8_UPD, true, SingleSpc, 4); break;
375 case ARM::VLD4d16Pseudo_UPD:
376 ExpandVLD(MBBI, ARM::VLD4d16_UPD, true, SingleSpc, 4); break;
377 case ARM::VLD4d32Pseudo_UPD:
378 ExpandVLD(MBBI, ARM::VLD4d32_UPD, true, SingleSpc, 4); break;
379 case ARM::VLD1d64QPseudo_UPD:
380 ExpandVLD(MBBI, ARM::VLD1d64Q_UPD, true, SingleSpc, 4); break;
381 case ARM::VLD4q8Pseudo_UPD:
382 ExpandVLD(MBBI, ARM::VLD4q8_UPD, true, EvenDblSpc, 4); break;
383 case ARM::VLD4q16Pseudo_UPD:
384 ExpandVLD(MBBI, ARM::VLD4q16_UPD, true, EvenDblSpc, 4); break;
385 case ARM::VLD4q32Pseudo_UPD:
386 ExpandVLD(MBBI, ARM::VLD4q32_UPD, true, EvenDblSpc, 4); break;
387 case ARM::VLD4q8oddPseudo_UPD:
388 ExpandVLD(MBBI, ARM::VLD4q8_UPD, true, OddDblSpc, 4); break;
389 case ARM::VLD4q16oddPseudo_UPD:
390 ExpandVLD(MBBI, ARM::VLD4q16_UPD, true, OddDblSpc, 4); break;
391 case ARM::VLD4q32oddPseudo_UPD:
392 ExpandVLD(MBBI, ARM::VLD4q32_UPD, true, OddDblSpc, 4); break;
394 case ARM::VST1q8Pseudo:
395 ExpandVST(MBBI, ARM::VST1q8, false, SingleSpc, 2); break;
396 case ARM::VST1q16Pseudo:
397 ExpandVST(MBBI, ARM::VST1q16, false, SingleSpc, 2); break;
398 case ARM::VST1q32Pseudo:
399 ExpandVST(MBBI, ARM::VST1q32, false, SingleSpc, 2); break;
400 case ARM::VST1q64Pseudo:
401 ExpandVST(MBBI, ARM::VST1q64, false, SingleSpc, 2); break;
402 case ARM::VST1q8Pseudo_UPD:
403 ExpandVST(MBBI, ARM::VST1q8_UPD, true, SingleSpc, 2); break;
404 case ARM::VST1q16Pseudo_UPD:
405 ExpandVST(MBBI, ARM::VST1q16_UPD, true, SingleSpc, 2); break;
406 case ARM::VST1q32Pseudo_UPD:
407 ExpandVST(MBBI, ARM::VST1q32_UPD, true, SingleSpc, 2); break;
408 case ARM::VST1q64Pseudo_UPD:
409 ExpandVST(MBBI, ARM::VST1q64_UPD, true, SingleSpc, 2); break;
411 case ARM::VST2d8Pseudo:
412 ExpandVST(MBBI, ARM::VST2d8, false, SingleSpc, 2); break;
413 case ARM::VST2d16Pseudo:
414 ExpandVST(MBBI, ARM::VST2d16, false, SingleSpc, 2); break;
415 case ARM::VST2d32Pseudo:
416 ExpandVST(MBBI, ARM::VST2d32, false, SingleSpc, 2); break;
417 case ARM::VST2q8Pseudo:
418 ExpandVST(MBBI, ARM::VST2q8, false, SingleSpc, 4); break;
419 case ARM::VST2q16Pseudo:
420 ExpandVST(MBBI, ARM::VST2q16, false, SingleSpc, 4); break;
421 case ARM::VST2q32Pseudo:
422 ExpandVST(MBBI, ARM::VST2q32, false, SingleSpc, 4); break;
423 case ARM::VST2d8Pseudo_UPD:
424 ExpandVST(MBBI, ARM::VST2d8_UPD, true, SingleSpc, 2); break;
425 case ARM::VST2d16Pseudo_UPD:
426 ExpandVST(MBBI, ARM::VST2d16_UPD, true, SingleSpc, 2); break;
427 case ARM::VST2d32Pseudo_UPD:
428 ExpandVST(MBBI, ARM::VST2d32_UPD, true, SingleSpc, 2); break;
429 case ARM::VST2q8Pseudo_UPD:
430 ExpandVST(MBBI, ARM::VST2q8_UPD, true, SingleSpc, 4); break;
431 case ARM::VST2q16Pseudo_UPD:
432 ExpandVST(MBBI, ARM::VST2q16_UPD, true, SingleSpc, 4); break;
433 case ARM::VST2q32Pseudo_UPD:
434 ExpandVST(MBBI, ARM::VST2q32_UPD, true, SingleSpc, 4); break;
436 case ARM::VST3d8Pseudo:
437 ExpandVST(MBBI, ARM::VST3d8, false, SingleSpc, 3); break;
438 case ARM::VST3d16Pseudo:
439 ExpandVST(MBBI, ARM::VST3d16, false, SingleSpc, 3); break;
440 case ARM::VST3d32Pseudo:
441 ExpandVST(MBBI, ARM::VST3d32, false, SingleSpc, 3); break;
442 case ARM::VST1d64TPseudo:
443 ExpandVST(MBBI, ARM::VST1d64T, false, SingleSpc, 3); break;
444 case ARM::VST3d8Pseudo_UPD:
445 ExpandVST(MBBI, ARM::VST3d8_UPD, true, SingleSpc, 3); break;
446 case ARM::VST3d16Pseudo_UPD:
447 ExpandVST(MBBI, ARM::VST3d16_UPD, true, SingleSpc, 3); break;
448 case ARM::VST3d32Pseudo_UPD:
449 ExpandVST(MBBI, ARM::VST3d32_UPD, true, SingleSpc, 3); break;
450 case ARM::VST1d64TPseudo_UPD:
451 ExpandVST(MBBI, ARM::VST1d64T_UPD, true, SingleSpc, 3); break;
452 case ARM::VST3q8Pseudo_UPD:
453 ExpandVST(MBBI, ARM::VST3q8_UPD, true, EvenDblSpc, 3); break;
454 case ARM::VST3q16Pseudo_UPD:
455 ExpandVST(MBBI, ARM::VST3q16_UPD, true, EvenDblSpc, 3); break;
456 case ARM::VST3q32Pseudo_UPD:
457 ExpandVST(MBBI, ARM::VST3q32_UPD, true, EvenDblSpc, 3); break;
458 case ARM::VST3q8oddPseudo_UPD:
459 ExpandVST(MBBI, ARM::VST3q8_UPD, true, OddDblSpc, 3); break;
460 case ARM::VST3q16oddPseudo_UPD:
461 ExpandVST(MBBI, ARM::VST3q16_UPD, true, OddDblSpc, 3); break;
462 case ARM::VST3q32oddPseudo_UPD:
463 ExpandVST(MBBI, ARM::VST3q32_UPD, true, OddDblSpc, 3); break;
465 case ARM::VST4d8Pseudo:
466 ExpandVST(MBBI, ARM::VST4d8, false, SingleSpc, 4); break;
467 case ARM::VST4d16Pseudo:
468 ExpandVST(MBBI, ARM::VST4d16, false, SingleSpc, 4); break;
469 case ARM::VST4d32Pseudo:
470 ExpandVST(MBBI, ARM::VST4d32, false, SingleSpc, 4); break;
471 case ARM::VST1d64QPseudo:
472 ExpandVST(MBBI, ARM::VST1d64Q, false, SingleSpc, 4); break;
473 case ARM::VST4d8Pseudo_UPD:
474 ExpandVST(MBBI, ARM::VST4d8_UPD, true, SingleSpc, 4); break;
475 case ARM::VST4d16Pseudo_UPD:
476 ExpandVST(MBBI, ARM::VST4d16_UPD, true, SingleSpc, 4); break;
477 case ARM::VST4d32Pseudo_UPD:
478 ExpandVST(MBBI, ARM::VST4d32_UPD, true, SingleSpc, 4); break;
479 case ARM::VST1d64QPseudo_UPD:
480 ExpandVST(MBBI, ARM::VST1d64Q_UPD, true, SingleSpc, 4); break;
481 case ARM::VST4q8Pseudo_UPD:
482 ExpandVST(MBBI, ARM::VST4q8_UPD, true, EvenDblSpc, 4); break;
483 case ARM::VST4q16Pseudo_UPD:
484 ExpandVST(MBBI, ARM::VST4q16_UPD, true, EvenDblSpc, 4); break;
485 case ARM::VST4q32Pseudo_UPD:
486 ExpandVST(MBBI, ARM::VST4q32_UPD, true, EvenDblSpc, 4); break;
487 case ARM::VST4q8oddPseudo_UPD:
488 ExpandVST(MBBI, ARM::VST4q8_UPD, true, OddDblSpc, 4); break;
489 case ARM::VST4q16oddPseudo_UPD:
490 ExpandVST(MBBI, ARM::VST4q16_UPD, true, OddDblSpc, 4); break;
491 case ARM::VST4q32oddPseudo_UPD:
492 ExpandVST(MBBI, ARM::VST4q32_UPD, true, OddDblSpc, 4); break;
503 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
504 TII = MF.getTarget().getInstrInfo();
505 TRI = MF.getTarget().getRegisterInfo();
507 bool Modified = false;
508 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
510 Modified |= ExpandMBB(*MFI);
514 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
516 FunctionPass *llvm::createARMExpandPseudoPass() {
517 return new ARMExpandPseudo();