1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
18 #include "ARMBaseInstrInfo.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/IR/GlobalValue.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
29 #include "llvm/Target/TargetFrameLowering.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
33 #define DEBUG_TYPE "arm-pseudo"
36 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
37 cl::desc("Verify machine code after expanding ARM pseudos"));
40 class ARMExpandPseudo : public MachineFunctionPass {
43 ARMExpandPseudo() : MachineFunctionPass(ID) {}
45 const ARMBaseInstrInfo *TII;
46 const TargetRegisterInfo *TRI;
47 const ARMSubtarget *STI;
50 bool runOnMachineFunction(MachineFunction &Fn) override;
52 const char *getPassName() const override {
53 return "ARM pseudo instruction expansion pass";
57 void TransferImpOps(MachineInstr &OldMI,
58 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
59 bool ExpandMI(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MBBI);
61 bool ExpandMBB(MachineBasicBlock &MBB);
62 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
63 void ExpandVST(MachineBasicBlock::iterator &MBBI);
64 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
65 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
66 unsigned Opc, bool IsExt);
67 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator &MBBI);
70 char ARMExpandPseudo::ID = 0;
73 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
74 /// the instructions created from the expansion.
75 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
76 MachineInstrBuilder &UseMI,
77 MachineInstrBuilder &DefMI) {
78 const MCInstrDesc &Desc = OldMI.getDesc();
79 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
81 const MachineOperand &MO = OldMI.getOperand(i);
82 assert(MO.isReg() && MO.getReg());
91 // Constants for register spacing in NEON load/store instructions.
92 // For quad-register load-lane and store-lane pseudo instructors, the
93 // spacing is initially assumed to be EvenDblSpc, and that is changed to
94 // OddDblSpc depending on the lane number operand.
101 // Entries for NEON load/store information table. The table is sorted by
102 // PseudoOpc for fast binary-search lookups.
103 struct NEONLdStTableEntry {
108 bool hasWritebackOperand;
109 uint8_t RegSpacing; // One of type NEONRegSpacing
110 uint8_t NumRegs; // D registers loaded or stored
111 uint8_t RegElts; // elements per D register; used for lane ops
112 // FIXME: Temporary flag to denote whether the real instruction takes
113 // a single register (like the encoding) or all of the registers in
114 // the list (like the asm syntax and the isel DAG). When all definitions
115 // are converted to take only the single encoded register, this will
117 bool copyAllListRegs;
119 // Comparison methods for binary search of the table.
120 bool operator<(const NEONLdStTableEntry &TE) const {
121 return PseudoOpc < TE.PseudoOpc;
123 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
124 return TE.PseudoOpc < PseudoOpc;
126 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
127 const NEONLdStTableEntry &TE) {
128 return PseudoOpc < TE.PseudoOpc;
133 static const NEONLdStTableEntry NEONLdStTable[] = {
134 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
135 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
136 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
137 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
138 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
139 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
141 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
142 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
143 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
144 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
146 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
147 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
148 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
149 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
150 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
151 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
152 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
153 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
154 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
155 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
157 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
158 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
159 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
160 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
161 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
162 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
163 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
164 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
165 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
167 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
168 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
169 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
170 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
171 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
172 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
174 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
175 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
176 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
177 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
178 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
179 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
180 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
181 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
182 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
183 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
185 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
186 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
187 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
188 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
189 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
190 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
192 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
193 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
194 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
195 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
196 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
197 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
198 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
199 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
200 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
202 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
203 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
204 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
205 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
206 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
207 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
209 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
210 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
211 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
212 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
213 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
214 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
215 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
216 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
217 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
218 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
220 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
221 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
222 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
223 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
224 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
225 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
227 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
228 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
229 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
230 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
231 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
232 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
233 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
234 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
235 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
237 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
238 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
239 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
240 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
241 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
242 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
244 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
245 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
246 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
247 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
248 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
249 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
251 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
252 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
253 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
254 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
255 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
256 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
257 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
258 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
259 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
260 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
262 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
263 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
264 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
265 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
266 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
267 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
268 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
269 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
270 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
272 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
273 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
274 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
275 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
276 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
277 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
278 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
279 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
280 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
281 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
283 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
284 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
285 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
286 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
287 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
288 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
290 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
291 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
292 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
293 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
294 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
295 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
296 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
297 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
298 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
300 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
301 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
302 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
303 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
304 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
305 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
306 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
307 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
308 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
309 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
311 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
312 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
313 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
314 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
315 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
316 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
318 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
319 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
320 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
321 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
322 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
323 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
324 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
325 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
326 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
329 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
330 /// load or store pseudo instruction.
331 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
332 const unsigned NumEntries = array_lengthof(NEONLdStTable);
335 // Make sure the table is sorted.
336 static bool TableChecked = false;
338 for (unsigned i = 0; i != NumEntries-1; ++i)
339 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
340 "NEONLdStTable is not sorted!");
345 const NEONLdStTableEntry *I =
346 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
347 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
352 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
353 /// corresponding to the specified register spacing. Not all of the results
354 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
355 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
356 const TargetRegisterInfo *TRI, unsigned &D0,
357 unsigned &D1, unsigned &D2, unsigned &D3) {
358 if (RegSpc == SingleSpc) {
359 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
360 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
361 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
362 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
363 } else if (RegSpc == EvenDblSpc) {
364 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
365 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
366 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
367 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
369 assert(RegSpc == OddDblSpc && "unknown register spacing");
370 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
371 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
372 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
373 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
377 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
378 /// operands to real VLD instructions with D register operands.
379 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
380 MachineInstr &MI = *MBBI;
381 MachineBasicBlock &MBB = *MI.getParent();
383 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
384 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
385 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
386 unsigned NumRegs = TableEntry->NumRegs;
388 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
389 TII->get(TableEntry->RealOpc));
392 bool DstIsDead = MI.getOperand(OpIdx).isDead();
393 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
394 unsigned D0, D1, D2, D3;
395 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
396 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
397 if (NumRegs > 1 && TableEntry->copyAllListRegs)
398 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
399 if (NumRegs > 2 && TableEntry->copyAllListRegs)
400 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
401 if (NumRegs > 3 && TableEntry->copyAllListRegs)
402 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
404 if (TableEntry->isUpdating)
405 MIB.addOperand(MI.getOperand(OpIdx++));
407 // Copy the addrmode6 operands.
408 MIB.addOperand(MI.getOperand(OpIdx++));
409 MIB.addOperand(MI.getOperand(OpIdx++));
410 // Copy the am6offset operand.
411 if (TableEntry->hasWritebackOperand)
412 MIB.addOperand(MI.getOperand(OpIdx++));
414 // For an instruction writing double-spaced subregs, the pseudo instruction
415 // has an extra operand that is a use of the super-register. Record the
416 // operand index and skip over it.
417 unsigned SrcOpIdx = 0;
418 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
421 // Copy the predicate operands.
422 MIB.addOperand(MI.getOperand(OpIdx++));
423 MIB.addOperand(MI.getOperand(OpIdx++));
425 // Copy the super-register source operand used for double-spaced subregs over
426 // to the new instruction as an implicit operand.
428 MachineOperand MO = MI.getOperand(SrcOpIdx);
429 MO.setImplicit(true);
432 // Add an implicit def for the super-register.
433 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
434 TransferImpOps(MI, MIB, MIB);
436 // Transfer memoperands.
437 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
439 MI.eraseFromParent();
442 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
443 /// operands to real VST instructions with D register operands.
444 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
445 MachineInstr &MI = *MBBI;
446 MachineBasicBlock &MBB = *MI.getParent();
448 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
449 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
450 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
451 unsigned NumRegs = TableEntry->NumRegs;
453 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
454 TII->get(TableEntry->RealOpc));
456 if (TableEntry->isUpdating)
457 MIB.addOperand(MI.getOperand(OpIdx++));
459 // Copy the addrmode6 operands.
460 MIB.addOperand(MI.getOperand(OpIdx++));
461 MIB.addOperand(MI.getOperand(OpIdx++));
462 // Copy the am6offset operand.
463 if (TableEntry->hasWritebackOperand)
464 MIB.addOperand(MI.getOperand(OpIdx++));
466 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
467 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
468 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
469 unsigned D0, D1, D2, D3;
470 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
471 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
472 if (NumRegs > 1 && TableEntry->copyAllListRegs)
473 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
474 if (NumRegs > 2 && TableEntry->copyAllListRegs)
475 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
476 if (NumRegs > 3 && TableEntry->copyAllListRegs)
477 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
479 // Copy the predicate operands.
480 MIB.addOperand(MI.getOperand(OpIdx++));
481 MIB.addOperand(MI.getOperand(OpIdx++));
483 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
484 MIB->addRegisterKilled(SrcReg, TRI, true);
485 else if (!SrcIsUndef)
486 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
487 TransferImpOps(MI, MIB, MIB);
489 // Transfer memoperands.
490 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
492 MI.eraseFromParent();
495 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
496 /// register operands to real instructions with D register operands.
497 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
498 MachineInstr &MI = *MBBI;
499 MachineBasicBlock &MBB = *MI.getParent();
501 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
502 assert(TableEntry && "NEONLdStTable lookup failed");
503 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
504 unsigned NumRegs = TableEntry->NumRegs;
505 unsigned RegElts = TableEntry->RegElts;
507 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
508 TII->get(TableEntry->RealOpc));
510 // The lane operand is always the 3rd from last operand, before the 2
511 // predicate operands.
512 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
514 // Adjust the lane and spacing as needed for Q registers.
515 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
516 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
520 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
522 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
524 bool DstIsDead = false;
525 if (TableEntry->IsLoad) {
526 DstIsDead = MI.getOperand(OpIdx).isDead();
527 DstReg = MI.getOperand(OpIdx++).getReg();
528 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
529 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
531 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
533 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
535 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
538 if (TableEntry->isUpdating)
539 MIB.addOperand(MI.getOperand(OpIdx++));
541 // Copy the addrmode6 operands.
542 MIB.addOperand(MI.getOperand(OpIdx++));
543 MIB.addOperand(MI.getOperand(OpIdx++));
544 // Copy the am6offset operand.
545 if (TableEntry->hasWritebackOperand)
546 MIB.addOperand(MI.getOperand(OpIdx++));
548 // Grab the super-register source.
549 MachineOperand MO = MI.getOperand(OpIdx++);
550 if (!TableEntry->IsLoad)
551 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
553 // Add the subregs as sources of the new instruction.
554 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
555 getKillRegState(MO.isKill()));
556 MIB.addReg(D0, SrcFlags);
558 MIB.addReg(D1, SrcFlags);
560 MIB.addReg(D2, SrcFlags);
562 MIB.addReg(D3, SrcFlags);
564 // Add the lane number operand.
568 // Copy the predicate operands.
569 MIB.addOperand(MI.getOperand(OpIdx++));
570 MIB.addOperand(MI.getOperand(OpIdx++));
572 // Copy the super-register source to be an implicit source.
573 MO.setImplicit(true);
575 if (TableEntry->IsLoad)
576 // Add an implicit def for the super-register.
577 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
578 TransferImpOps(MI, MIB, MIB);
579 // Transfer memoperands.
580 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
581 MI.eraseFromParent();
584 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
585 /// register operands to real instructions with D register operands.
586 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
587 unsigned Opc, bool IsExt) {
588 MachineInstr &MI = *MBBI;
589 MachineBasicBlock &MBB = *MI.getParent();
591 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
594 // Transfer the destination register operand.
595 MIB.addOperand(MI.getOperand(OpIdx++));
597 MIB.addOperand(MI.getOperand(OpIdx++));
599 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
600 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
601 unsigned D0, D1, D2, D3;
602 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
605 // Copy the other source register operand.
606 MIB.addOperand(MI.getOperand(OpIdx++));
608 // Copy the predicate operands.
609 MIB.addOperand(MI.getOperand(OpIdx++));
610 MIB.addOperand(MI.getOperand(OpIdx++));
612 // Add an implicit kill and use for the super-reg.
613 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
614 TransferImpOps(MI, MIB, MIB);
615 MI.eraseFromParent();
618 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
619 MachineBasicBlock::iterator &MBBI) {
620 MachineInstr &MI = *MBBI;
621 unsigned Opcode = MI.getOpcode();
622 unsigned PredReg = 0;
623 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
624 unsigned DstReg = MI.getOperand(0).getReg();
625 bool DstIsDead = MI.getOperand(0).isDead();
626 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
627 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
628 MachineInstrBuilder LO16, HI16;
630 if (!STI->hasV6T2Ops() &&
631 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
632 // Expand into a movi + orr.
633 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
634 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
635 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
638 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
639 unsigned ImmVal = (unsigned)MO.getImm();
640 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
641 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
642 LO16 = LO16.addImm(SOImmValV1);
643 HI16 = HI16.addImm(SOImmValV2);
644 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
645 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
646 LO16.addImm(Pred).addReg(PredReg).addReg(0);
647 HI16.addImm(Pred).addReg(PredReg).addReg(0);
648 TransferImpOps(MI, LO16, HI16);
649 MI.eraseFromParent();
653 unsigned LO16Opc = 0;
654 unsigned HI16Opc = 0;
655 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
656 LO16Opc = ARM::t2MOVi16;
657 HI16Opc = ARM::t2MOVTi16;
659 LO16Opc = ARM::MOVi16;
660 HI16Opc = ARM::MOVTi16;
663 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
664 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
665 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
669 unsigned Imm = MO.getImm();
670 unsigned Lo16 = Imm & 0xffff;
671 unsigned Hi16 = (Imm >> 16) & 0xffff;
672 LO16 = LO16.addImm(Lo16);
673 HI16 = HI16.addImm(Hi16);
675 const GlobalValue *GV = MO.getGlobal();
676 unsigned TF = MO.getTargetFlags();
677 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
678 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
681 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
682 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
683 LO16.addImm(Pred).addReg(PredReg);
684 HI16.addImm(Pred).addReg(PredReg);
686 TransferImpOps(MI, LO16, HI16);
687 MI.eraseFromParent();
690 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
691 MachineBasicBlock::iterator MBBI) {
692 MachineInstr &MI = *MBBI;
693 unsigned Opcode = MI.getOpcode();
699 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
700 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
701 MI.getOperand(1).getReg())
702 .addOperand(MI.getOperand(2))
703 .addImm(MI.getOperand(3).getImm()) // 'pred'
704 .addOperand(MI.getOperand(4));
706 MI.eraseFromParent();
711 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
712 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
713 MI.getOperand(1).getReg())
714 .addOperand(MI.getOperand(2))
715 .addImm(MI.getOperand(3).getImm()) // 'pred'
716 .addOperand(MI.getOperand(4))
717 .addReg(0); // 's' bit
719 MI.eraseFromParent();
723 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
724 (MI.getOperand(1).getReg()))
725 .addOperand(MI.getOperand(2))
726 .addImm(MI.getOperand(3).getImm())
727 .addImm(MI.getOperand(4).getImm()) // 'pred'
728 .addOperand(MI.getOperand(5))
729 .addReg(0); // 's' bit
731 MI.eraseFromParent();
735 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
736 (MI.getOperand(1).getReg()))
737 .addOperand(MI.getOperand(2))
738 .addOperand(MI.getOperand(3))
739 .addImm(MI.getOperand(4).getImm())
740 .addImm(MI.getOperand(5).getImm()) // 'pred'
741 .addOperand(MI.getOperand(6))
742 .addReg(0); // 's' bit
744 MI.eraseFromParent();
747 case ARM::t2MOVCCi16:
748 case ARM::MOVCCi16: {
749 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
750 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
751 MI.getOperand(1).getReg())
752 .addImm(MI.getOperand(2).getImm())
753 .addImm(MI.getOperand(3).getImm()) // 'pred'
754 .addOperand(MI.getOperand(4));
755 MI.eraseFromParent();
760 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
761 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
762 MI.getOperand(1).getReg())
763 .addImm(MI.getOperand(2).getImm())
764 .addImm(MI.getOperand(3).getImm()) // 'pred'
765 .addOperand(MI.getOperand(4))
766 .addReg(0); // 's' bit
768 MI.eraseFromParent();
773 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
774 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
775 MI.getOperand(1).getReg())
776 .addImm(MI.getOperand(2).getImm())
777 .addImm(MI.getOperand(3).getImm()) // 'pred'
778 .addOperand(MI.getOperand(4))
779 .addReg(0); // 's' bit
781 MI.eraseFromParent();
784 case ARM::t2MOVCClsl:
785 case ARM::t2MOVCClsr:
786 case ARM::t2MOVCCasr:
787 case ARM::t2MOVCCror: {
790 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
791 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
792 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
793 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
794 default: llvm_unreachable("unexpeced conditional move");
796 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
797 MI.getOperand(1).getReg())
798 .addOperand(MI.getOperand(2))
799 .addImm(MI.getOperand(3).getImm())
800 .addImm(MI.getOperand(4).getImm()) // 'pred'
801 .addOperand(MI.getOperand(5))
802 .addReg(0); // 's' bit
803 MI.eraseFromParent();
806 case ARM::Int_eh_sjlj_dispatchsetup: {
807 MachineFunction &MF = *MI.getParent()->getParent();
808 const ARMBaseInstrInfo *AII =
809 static_cast<const ARMBaseInstrInfo*>(TII);
810 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
811 // For functions using a base pointer, we rematerialize it (via the frame
812 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
813 // for us. Otherwise, expand to nothing.
814 if (RI.hasBasePointer(MF)) {
815 int32_t NumBytes = AFI->getFramePtrSpillOffset();
816 unsigned FramePtr = RI.getFrameRegister(MF);
817 assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
818 "base pointer without frame pointer?");
820 if (AFI->isThumb2Function()) {
821 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
822 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
823 } else if (AFI->isThumbFunction()) {
824 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
825 FramePtr, -NumBytes, *TII, RI);
827 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
828 FramePtr, -NumBytes, ARMCC::AL, 0,
831 // If there's dynamic realignment, adjust for it.
832 if (RI.needsStackRealignment(MF)) {
833 MachineFrameInfo *MFI = MF.getFrameInfo();
834 unsigned MaxAlign = MFI->getMaxAlignment();
835 assert (!AFI->isThumb1OnlyFunction());
836 // Emit bic r6, r6, MaxAlign
837 unsigned bicOpc = AFI->isThumbFunction() ?
838 ARM::t2BICri : ARM::BICri;
839 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
840 TII->get(bicOpc), ARM::R6)
841 .addReg(ARM::R6, RegState::Kill)
842 .addImm(MaxAlign-1)));
846 MI.eraseFromParent();
850 case ARM::MOVsrl_flag:
851 case ARM::MOVsra_flag: {
852 // These are just fancy MOVs instructions.
853 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
854 MI.getOperand(0).getReg())
855 .addOperand(MI.getOperand(1))
856 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ?
857 ARM_AM::lsr : ARM_AM::asr),
859 .addReg(ARM::CPSR, RegState::Define);
860 MI.eraseFromParent();
864 // This encodes as "MOVs Rd, Rm, rrx
865 MachineInstrBuilder MIB =
866 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
867 MI.getOperand(0).getReg())
868 .addOperand(MI.getOperand(1))
869 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
871 TransferImpOps(MI, MIB, MIB);
872 MI.eraseFromParent();
877 MachineInstrBuilder MIB =
878 BuildMI(MBB, MBBI, MI.getDebugLoc(),
879 TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
880 .addExternalSymbol("__aeabi_read_tp", 0);
882 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
883 TransferImpOps(MI, MIB, MIB);
884 MI.eraseFromParent();
887 case ARM::tLDRpci_pic:
888 case ARM::t2LDRpci_pic: {
889 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
890 ? ARM::tLDRpci : ARM::t2LDRpci;
891 unsigned DstReg = MI.getOperand(0).getReg();
892 bool DstIsDead = MI.getOperand(0).isDead();
893 MachineInstrBuilder MIB1 =
894 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
895 TII->get(NewLdOpc), DstReg)
896 .addOperand(MI.getOperand(1)));
897 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
898 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
899 TII->get(ARM::tPICADD))
900 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
902 .addOperand(MI.getOperand(2));
903 TransferImpOps(MI, MIB1, MIB2);
904 MI.eraseFromParent();
908 case ARM::LDRLIT_ga_abs:
909 case ARM::LDRLIT_ga_pcrel:
910 case ARM::LDRLIT_ga_pcrel_ldr:
911 case ARM::tLDRLIT_ga_abs:
912 case ARM::tLDRLIT_ga_pcrel: {
913 unsigned DstReg = MI.getOperand(0).getReg();
914 bool DstIsDead = MI.getOperand(0).isDead();
915 const MachineOperand &MO1 = MI.getOperand(1);
916 const GlobalValue *GV = MO1.getGlobal();
918 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
920 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
921 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
924 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICADD : ARM::PICLDR)
927 // We need a new const-pool entry to load from.
928 MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
929 unsigned ARMPCLabelIndex = 0;
930 MachineConstantPoolValue *CPV;
933 unsigned PCAdj = IsARM ? 8 : 4;
934 ARMPCLabelIndex = AFI->createPICLabelUId();
935 CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex,
936 ARMCP::CPValue, PCAdj);
938 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
940 MachineInstrBuilder MIB =
941 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
942 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
948 MachineInstrBuilder MIB =
949 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
950 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
952 .addImm(ARMPCLabelIndex);
958 MI.eraseFromParent();
961 case ARM::MOV_ga_pcrel:
962 case ARM::MOV_ga_pcrel_ldr:
963 case ARM::t2MOV_ga_pcrel: {
964 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
965 unsigned LabelId = AFI->createPICLabelUId();
966 unsigned DstReg = MI.getOperand(0).getReg();
967 bool DstIsDead = MI.getOperand(0).isDead();
968 const MachineOperand &MO1 = MI.getOperand(1);
969 const GlobalValue *GV = MO1.getGlobal();
970 unsigned TF = MO1.getTargetFlags();
971 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
972 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
973 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
974 unsigned LO16TF = TF | ARMII::MO_LO16;
975 unsigned HI16TF = TF | ARMII::MO_HI16;
976 unsigned PICAddOpc = isARM
977 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
979 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
980 TII->get(LO16Opc), DstReg)
981 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
984 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
986 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
989 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
991 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
992 .addReg(DstReg).addImm(LabelId);
994 AddDefaultPred(MIB3);
995 if (Opcode == ARM::MOV_ga_pcrel_ldr)
996 MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
998 TransferImpOps(MI, MIB1, MIB3);
999 MI.eraseFromParent();
1003 case ARM::MOVi32imm:
1004 case ARM::MOVCCi32imm:
1005 case ARM::t2MOVi32imm:
1006 case ARM::t2MOVCCi32imm:
1007 ExpandMOV32BitImm(MBB, MBBI);
1010 case ARM::SUBS_PC_LR: {
1011 MachineInstrBuilder MIB =
1012 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1014 .addOperand(MI.getOperand(0))
1015 .addOperand(MI.getOperand(1))
1016 .addOperand(MI.getOperand(2))
1017 .addReg(ARM::CPSR, RegState::Undef);
1018 TransferImpOps(MI, MIB, MIB);
1019 MI.eraseFromParent();
1022 case ARM::VLDMQIA: {
1023 unsigned NewOpc = ARM::VLDMDIA;
1024 MachineInstrBuilder MIB =
1025 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1028 // Grab the Q register destination.
1029 bool DstIsDead = MI.getOperand(OpIdx).isDead();
1030 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1032 // Copy the source register.
1033 MIB.addOperand(MI.getOperand(OpIdx++));
1035 // Copy the predicate operands.
1036 MIB.addOperand(MI.getOperand(OpIdx++));
1037 MIB.addOperand(MI.getOperand(OpIdx++));
1039 // Add the destination operands (D subregs).
1040 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1041 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1042 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1043 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1045 // Add an implicit def for the super-register.
1046 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1047 TransferImpOps(MI, MIB, MIB);
1048 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1049 MI.eraseFromParent();
1053 case ARM::VSTMQIA: {
1054 unsigned NewOpc = ARM::VSTMDIA;
1055 MachineInstrBuilder MIB =
1056 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1059 // Grab the Q register source.
1060 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1061 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1063 // Copy the destination register.
1064 MIB.addOperand(MI.getOperand(OpIdx++));
1066 // Copy the predicate operands.
1067 MIB.addOperand(MI.getOperand(OpIdx++));
1068 MIB.addOperand(MI.getOperand(OpIdx++));
1070 // Add the source operands (D subregs).
1071 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1072 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1073 MIB.addReg(D0).addReg(D1);
1075 if (SrcIsKill) // Add an implicit kill for the Q register.
1076 MIB->addRegisterKilled(SrcReg, TRI, true);
1078 TransferImpOps(MI, MIB, MIB);
1079 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1080 MI.eraseFromParent();
1084 case ARM::VLD2q8Pseudo:
1085 case ARM::VLD2q16Pseudo:
1086 case ARM::VLD2q32Pseudo:
1087 case ARM::VLD2q8PseudoWB_fixed:
1088 case ARM::VLD2q16PseudoWB_fixed:
1089 case ARM::VLD2q32PseudoWB_fixed:
1090 case ARM::VLD2q8PseudoWB_register:
1091 case ARM::VLD2q16PseudoWB_register:
1092 case ARM::VLD2q32PseudoWB_register:
1093 case ARM::VLD3d8Pseudo:
1094 case ARM::VLD3d16Pseudo:
1095 case ARM::VLD3d32Pseudo:
1096 case ARM::VLD1d64TPseudo:
1097 case ARM::VLD1d64TPseudoWB_fixed:
1098 case ARM::VLD3d8Pseudo_UPD:
1099 case ARM::VLD3d16Pseudo_UPD:
1100 case ARM::VLD3d32Pseudo_UPD:
1101 case ARM::VLD3q8Pseudo_UPD:
1102 case ARM::VLD3q16Pseudo_UPD:
1103 case ARM::VLD3q32Pseudo_UPD:
1104 case ARM::VLD3q8oddPseudo:
1105 case ARM::VLD3q16oddPseudo:
1106 case ARM::VLD3q32oddPseudo:
1107 case ARM::VLD3q8oddPseudo_UPD:
1108 case ARM::VLD3q16oddPseudo_UPD:
1109 case ARM::VLD3q32oddPseudo_UPD:
1110 case ARM::VLD4d8Pseudo:
1111 case ARM::VLD4d16Pseudo:
1112 case ARM::VLD4d32Pseudo:
1113 case ARM::VLD1d64QPseudo:
1114 case ARM::VLD1d64QPseudoWB_fixed:
1115 case ARM::VLD4d8Pseudo_UPD:
1116 case ARM::VLD4d16Pseudo_UPD:
1117 case ARM::VLD4d32Pseudo_UPD:
1118 case ARM::VLD4q8Pseudo_UPD:
1119 case ARM::VLD4q16Pseudo_UPD:
1120 case ARM::VLD4q32Pseudo_UPD:
1121 case ARM::VLD4q8oddPseudo:
1122 case ARM::VLD4q16oddPseudo:
1123 case ARM::VLD4q32oddPseudo:
1124 case ARM::VLD4q8oddPseudo_UPD:
1125 case ARM::VLD4q16oddPseudo_UPD:
1126 case ARM::VLD4q32oddPseudo_UPD:
1127 case ARM::VLD3DUPd8Pseudo:
1128 case ARM::VLD3DUPd16Pseudo:
1129 case ARM::VLD3DUPd32Pseudo:
1130 case ARM::VLD3DUPd8Pseudo_UPD:
1131 case ARM::VLD3DUPd16Pseudo_UPD:
1132 case ARM::VLD3DUPd32Pseudo_UPD:
1133 case ARM::VLD4DUPd8Pseudo:
1134 case ARM::VLD4DUPd16Pseudo:
1135 case ARM::VLD4DUPd32Pseudo:
1136 case ARM::VLD4DUPd8Pseudo_UPD:
1137 case ARM::VLD4DUPd16Pseudo_UPD:
1138 case ARM::VLD4DUPd32Pseudo_UPD:
1142 case ARM::VST2q8Pseudo:
1143 case ARM::VST2q16Pseudo:
1144 case ARM::VST2q32Pseudo:
1145 case ARM::VST2q8PseudoWB_fixed:
1146 case ARM::VST2q16PseudoWB_fixed:
1147 case ARM::VST2q32PseudoWB_fixed:
1148 case ARM::VST2q8PseudoWB_register:
1149 case ARM::VST2q16PseudoWB_register:
1150 case ARM::VST2q32PseudoWB_register:
1151 case ARM::VST3d8Pseudo:
1152 case ARM::VST3d16Pseudo:
1153 case ARM::VST3d32Pseudo:
1154 case ARM::VST1d64TPseudo:
1155 case ARM::VST3d8Pseudo_UPD:
1156 case ARM::VST3d16Pseudo_UPD:
1157 case ARM::VST3d32Pseudo_UPD:
1158 case ARM::VST1d64TPseudoWB_fixed:
1159 case ARM::VST1d64TPseudoWB_register:
1160 case ARM::VST3q8Pseudo_UPD:
1161 case ARM::VST3q16Pseudo_UPD:
1162 case ARM::VST3q32Pseudo_UPD:
1163 case ARM::VST3q8oddPseudo:
1164 case ARM::VST3q16oddPseudo:
1165 case ARM::VST3q32oddPseudo:
1166 case ARM::VST3q8oddPseudo_UPD:
1167 case ARM::VST3q16oddPseudo_UPD:
1168 case ARM::VST3q32oddPseudo_UPD:
1169 case ARM::VST4d8Pseudo:
1170 case ARM::VST4d16Pseudo:
1171 case ARM::VST4d32Pseudo:
1172 case ARM::VST1d64QPseudo:
1173 case ARM::VST4d8Pseudo_UPD:
1174 case ARM::VST4d16Pseudo_UPD:
1175 case ARM::VST4d32Pseudo_UPD:
1176 case ARM::VST1d64QPseudoWB_fixed:
1177 case ARM::VST1d64QPseudoWB_register:
1178 case ARM::VST4q8Pseudo_UPD:
1179 case ARM::VST4q16Pseudo_UPD:
1180 case ARM::VST4q32Pseudo_UPD:
1181 case ARM::VST4q8oddPseudo:
1182 case ARM::VST4q16oddPseudo:
1183 case ARM::VST4q32oddPseudo:
1184 case ARM::VST4q8oddPseudo_UPD:
1185 case ARM::VST4q16oddPseudo_UPD:
1186 case ARM::VST4q32oddPseudo_UPD:
1190 case ARM::VLD1LNq8Pseudo:
1191 case ARM::VLD1LNq16Pseudo:
1192 case ARM::VLD1LNq32Pseudo:
1193 case ARM::VLD1LNq8Pseudo_UPD:
1194 case ARM::VLD1LNq16Pseudo_UPD:
1195 case ARM::VLD1LNq32Pseudo_UPD:
1196 case ARM::VLD2LNd8Pseudo:
1197 case ARM::VLD2LNd16Pseudo:
1198 case ARM::VLD2LNd32Pseudo:
1199 case ARM::VLD2LNq16Pseudo:
1200 case ARM::VLD2LNq32Pseudo:
1201 case ARM::VLD2LNd8Pseudo_UPD:
1202 case ARM::VLD2LNd16Pseudo_UPD:
1203 case ARM::VLD2LNd32Pseudo_UPD:
1204 case ARM::VLD2LNq16Pseudo_UPD:
1205 case ARM::VLD2LNq32Pseudo_UPD:
1206 case ARM::VLD3LNd8Pseudo:
1207 case ARM::VLD3LNd16Pseudo:
1208 case ARM::VLD3LNd32Pseudo:
1209 case ARM::VLD3LNq16Pseudo:
1210 case ARM::VLD3LNq32Pseudo:
1211 case ARM::VLD3LNd8Pseudo_UPD:
1212 case ARM::VLD3LNd16Pseudo_UPD:
1213 case ARM::VLD3LNd32Pseudo_UPD:
1214 case ARM::VLD3LNq16Pseudo_UPD:
1215 case ARM::VLD3LNq32Pseudo_UPD:
1216 case ARM::VLD4LNd8Pseudo:
1217 case ARM::VLD4LNd16Pseudo:
1218 case ARM::VLD4LNd32Pseudo:
1219 case ARM::VLD4LNq16Pseudo:
1220 case ARM::VLD4LNq32Pseudo:
1221 case ARM::VLD4LNd8Pseudo_UPD:
1222 case ARM::VLD4LNd16Pseudo_UPD:
1223 case ARM::VLD4LNd32Pseudo_UPD:
1224 case ARM::VLD4LNq16Pseudo_UPD:
1225 case ARM::VLD4LNq32Pseudo_UPD:
1226 case ARM::VST1LNq8Pseudo:
1227 case ARM::VST1LNq16Pseudo:
1228 case ARM::VST1LNq32Pseudo:
1229 case ARM::VST1LNq8Pseudo_UPD:
1230 case ARM::VST1LNq16Pseudo_UPD:
1231 case ARM::VST1LNq32Pseudo_UPD:
1232 case ARM::VST2LNd8Pseudo:
1233 case ARM::VST2LNd16Pseudo:
1234 case ARM::VST2LNd32Pseudo:
1235 case ARM::VST2LNq16Pseudo:
1236 case ARM::VST2LNq32Pseudo:
1237 case ARM::VST2LNd8Pseudo_UPD:
1238 case ARM::VST2LNd16Pseudo_UPD:
1239 case ARM::VST2LNd32Pseudo_UPD:
1240 case ARM::VST2LNq16Pseudo_UPD:
1241 case ARM::VST2LNq32Pseudo_UPD:
1242 case ARM::VST3LNd8Pseudo:
1243 case ARM::VST3LNd16Pseudo:
1244 case ARM::VST3LNd32Pseudo:
1245 case ARM::VST3LNq16Pseudo:
1246 case ARM::VST3LNq32Pseudo:
1247 case ARM::VST3LNd8Pseudo_UPD:
1248 case ARM::VST3LNd16Pseudo_UPD:
1249 case ARM::VST3LNd32Pseudo_UPD:
1250 case ARM::VST3LNq16Pseudo_UPD:
1251 case ARM::VST3LNq32Pseudo_UPD:
1252 case ARM::VST4LNd8Pseudo:
1253 case ARM::VST4LNd16Pseudo:
1254 case ARM::VST4LNd32Pseudo:
1255 case ARM::VST4LNq16Pseudo:
1256 case ARM::VST4LNq32Pseudo:
1257 case ARM::VST4LNd8Pseudo_UPD:
1258 case ARM::VST4LNd16Pseudo_UPD:
1259 case ARM::VST4LNd32Pseudo_UPD:
1260 case ARM::VST4LNq16Pseudo_UPD:
1261 case ARM::VST4LNq32Pseudo_UPD:
1265 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1266 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1267 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1268 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1272 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1273 bool Modified = false;
1275 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1277 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
1278 Modified |= ExpandMI(MBB, MBBI);
1285 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1286 const TargetMachine &TM = MF.getTarget();
1287 TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
1288 TRI = TM.getRegisterInfo();
1289 STI = &TM.getSubtarget<ARMSubtarget>();
1290 AFI = MF.getInfo<ARMFunctionInfo>();
1292 bool Modified = false;
1293 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1295 Modified |= ExpandMBB(*MFI);
1296 if (VerifyARMPseudo)
1297 MF.verify(this, "After expanding ARM pseudo instructions.");
1301 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1303 FunctionPass *llvm::createARMExpandPseudoPass() {
1304 return new ARMExpandPseudo();