1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-pseudo"
19 #include "ARMAddressingModes.h"
20 #include "ARMBaseInstrInfo.h"
21 #include "ARMBaseRegisterInfo.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMRegisterInfo.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
32 class ARMExpandPseudo : public MachineFunctionPass {
35 ARMExpandPseudo() : MachineFunctionPass(ID) {}
37 const ARMBaseInstrInfo *TII;
38 const TargetRegisterInfo *TRI;
39 const ARMSubtarget *STI;
41 virtual bool runOnMachineFunction(MachineFunction &Fn);
43 virtual const char *getPassName() const {
44 return "ARM pseudo instruction expansion pass";
48 void TransferImpOps(MachineInstr &OldMI,
49 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
50 bool ExpandMBB(MachineBasicBlock &MBB);
51 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
52 void ExpandVST(MachineBasicBlock::iterator &MBBI);
53 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
54 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
55 unsigned Opc, bool IsExt, unsigned NumRegs);
57 char ARMExpandPseudo::ID = 0;
60 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
61 /// the instructions created from the expansion.
62 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
63 MachineInstrBuilder &UseMI,
64 MachineInstrBuilder &DefMI) {
65 const TargetInstrDesc &Desc = OldMI.getDesc();
66 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
68 const MachineOperand &MO = OldMI.getOperand(i);
69 assert(MO.isReg() && MO.getReg());
78 // Constants for register spacing in NEON load/store instructions.
79 // For quad-register load-lane and store-lane pseudo instructors, the
80 // spacing is initially assumed to be EvenDblSpc, and that is changed to
81 // OddDblSpc depending on the lane number operand.
88 // Entries for NEON load/store information table. The table is sorted by
89 // PseudoOpc for fast binary-search lookups.
90 struct NEONLdStTableEntry {
95 NEONRegSpacing RegSpacing;
96 unsigned char NumRegs; // D registers loaded or stored
97 unsigned char RegElts; // elements per D register; used for lane ops
99 // Comparison methods for binary search of the table.
100 bool operator<(const NEONLdStTableEntry &TE) const {
101 return PseudoOpc < TE.PseudoOpc;
103 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
104 return TE.PseudoOpc < PseudoOpc;
106 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
107 const NEONLdStTableEntry &TE) {
108 return PseudoOpc < TE.PseudoOpc;
113 static const NEONLdStTableEntry NEONLdStTable[] = {
114 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 },
115 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, EvenDblSpc, 1, 4 },
116 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 },
117 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, EvenDblSpc, 1, 2 },
118 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, EvenDblSpc, 1, 8 },
119 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, EvenDblSpc, 1, 8 },
121 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 },
122 { ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 },
123 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 },
124 { ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 },
126 { ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 },
127 { ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 },
128 { ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 },
129 { ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 },
130 { ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 },
131 { ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 },
132 { ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 },
133 { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 },
135 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 },
136 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 },
137 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 },
138 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 },
139 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 },
140 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 },
141 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 },
142 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 },
143 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 },
144 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 },
146 { ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 },
147 { ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 },
148 { ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 },
149 { ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 },
150 { ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 },
151 { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 },
153 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 },
154 { ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 },
155 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 },
156 { ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 },
157 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 },
158 { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 },
160 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 },
161 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 },
162 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 },
163 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 },
164 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 },
165 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 },
166 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 },
167 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 },
168 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 },
169 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 },
171 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 },
172 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 },
173 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 },
174 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 },
175 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 },
176 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 },
178 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 },
179 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 },
180 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 },
181 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 },
182 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 },
183 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 },
185 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 },
186 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 },
187 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 },
188 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 },
189 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 },
190 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 },
191 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 },
192 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 },
193 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 },
194 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 },
196 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 },
197 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 },
198 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 },
199 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 },
200 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 },
201 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 },
203 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 },
204 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 },
205 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 },
206 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 },
207 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 },
208 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 },
210 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, EvenDblSpc, 1, 4 },
211 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,false, true, EvenDblSpc, 1, 4 },
212 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, EvenDblSpc, 1, 2 },
213 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,false, true, EvenDblSpc, 1, 2 },
214 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, EvenDblSpc, 1, 8 },
215 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, EvenDblSpc, 1, 8 },
217 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 },
218 { ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 },
219 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 },
220 { ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 },
222 { ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 },
223 { ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 },
224 { ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 },
225 { ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 },
226 { ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 },
227 { ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 },
228 { ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 },
229 { ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 },
231 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 },
232 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 },
233 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 },
234 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 },
235 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 },
236 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 },
237 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4},
238 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4},
239 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2},
240 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2},
242 { ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 },
243 { ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 },
244 { ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 },
245 { ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 },
246 { ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 },
247 { ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 },
249 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 },
250 { ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 },
251 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 },
252 { ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 },
253 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 },
254 { ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 },
256 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 },
257 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 },
258 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 },
259 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 },
260 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 },
261 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 },
262 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4},
263 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4},
264 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2},
265 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2},
267 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 },
268 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 },
269 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 },
270 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 },
271 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 },
272 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 },
274 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 },
275 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 },
276 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 },
277 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 },
278 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 },
279 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 },
281 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 },
282 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 },
283 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 },
284 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 },
285 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 },
286 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 },
287 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4},
288 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4},
289 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2},
290 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2},
292 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 },
293 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 },
294 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 },
295 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 },
296 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 },
297 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 },
299 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 },
300 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 },
301 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 },
302 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 },
303 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 },
304 { ARM::VST4q8oddPseudo_UPD , ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 }
307 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
308 /// load or store pseudo instruction.
309 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
310 unsigned NumEntries = array_lengthof(NEONLdStTable);
313 // Make sure the table is sorted.
314 static bool TableChecked = false;
316 for (unsigned i = 0; i != NumEntries-1; ++i)
317 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
318 "NEONLdStTable is not sorted!");
323 const NEONLdStTableEntry *I =
324 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
325 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
330 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
331 /// corresponding to the specified register spacing. Not all of the results
332 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
333 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
334 const TargetRegisterInfo *TRI, unsigned &D0,
335 unsigned &D1, unsigned &D2, unsigned &D3) {
336 if (RegSpc == SingleSpc) {
337 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
338 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
339 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
340 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
341 } else if (RegSpc == EvenDblSpc) {
342 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
343 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
344 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
345 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
347 assert(RegSpc == OddDblSpc && "unknown register spacing");
348 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
349 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
350 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
351 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
355 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
356 /// operands to real VLD instructions with D register operands.
357 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
358 MachineInstr &MI = *MBBI;
359 MachineBasicBlock &MBB = *MI.getParent();
361 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
362 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
363 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
364 unsigned NumRegs = TableEntry->NumRegs;
366 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
367 TII->get(TableEntry->RealOpc));
370 bool DstIsDead = MI.getOperand(OpIdx).isDead();
371 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
372 unsigned D0, D1, D2, D3;
373 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
374 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
375 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
377 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
379 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
381 if (TableEntry->HasWriteBack)
382 MIB.addOperand(MI.getOperand(OpIdx++));
384 // Copy the addrmode6 operands.
385 MIB.addOperand(MI.getOperand(OpIdx++));
386 MIB.addOperand(MI.getOperand(OpIdx++));
387 // Copy the am6offset operand.
388 if (TableEntry->HasWriteBack)
389 MIB.addOperand(MI.getOperand(OpIdx++));
391 // For an instruction writing double-spaced subregs, the pseudo instruction
392 // has an extra operand that is a use of the super-register. Record the
393 // operand index and skip over it.
394 unsigned SrcOpIdx = 0;
395 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
398 // Copy the predicate operands.
399 MIB.addOperand(MI.getOperand(OpIdx++));
400 MIB.addOperand(MI.getOperand(OpIdx++));
402 // Copy the super-register source operand used for double-spaced subregs over
403 // to the new instruction as an implicit operand.
405 MachineOperand MO = MI.getOperand(SrcOpIdx);
406 MO.setImplicit(true);
409 // Add an implicit def for the super-register.
410 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
411 TransferImpOps(MI, MIB, MIB);
412 MI.eraseFromParent();
415 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
416 /// operands to real VST instructions with D register operands.
417 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
418 MachineInstr &MI = *MBBI;
419 MachineBasicBlock &MBB = *MI.getParent();
421 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
422 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
423 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
424 unsigned NumRegs = TableEntry->NumRegs;
426 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
427 TII->get(TableEntry->RealOpc));
429 if (TableEntry->HasWriteBack)
430 MIB.addOperand(MI.getOperand(OpIdx++));
432 // Copy the addrmode6 operands.
433 MIB.addOperand(MI.getOperand(OpIdx++));
434 MIB.addOperand(MI.getOperand(OpIdx++));
435 // Copy the am6offset operand.
436 if (TableEntry->HasWriteBack)
437 MIB.addOperand(MI.getOperand(OpIdx++));
439 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
440 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
441 unsigned D0, D1, D2, D3;
442 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
443 MIB.addReg(D0).addReg(D1);
449 // Copy the predicate operands.
450 MIB.addOperand(MI.getOperand(OpIdx++));
451 MIB.addOperand(MI.getOperand(OpIdx++));
454 // Add an implicit kill for the super-reg.
455 (*MIB).addRegisterKilled(SrcReg, TRI, true);
456 TransferImpOps(MI, MIB, MIB);
457 MI.eraseFromParent();
460 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
461 /// register operands to real instructions with D register operands.
462 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
463 MachineInstr &MI = *MBBI;
464 MachineBasicBlock &MBB = *MI.getParent();
466 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
467 assert(TableEntry && "NEONLdStTable lookup failed");
468 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
469 unsigned NumRegs = TableEntry->NumRegs;
470 unsigned RegElts = TableEntry->RegElts;
472 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
473 TII->get(TableEntry->RealOpc));
475 // The lane operand is always the 3rd from last operand, before the 2
476 // predicate operands.
477 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
479 // Adjust the lane and spacing as needed for Q registers.
480 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
481 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
485 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
487 unsigned D0, D1, D2, D3;
489 bool DstIsDead = false;
490 if (TableEntry->IsLoad) {
491 DstIsDead = MI.getOperand(OpIdx).isDead();
492 DstReg = MI.getOperand(OpIdx++).getReg();
493 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
494 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
496 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
498 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
500 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
503 if (TableEntry->HasWriteBack)
504 MIB.addOperand(MI.getOperand(OpIdx++));
506 // Copy the addrmode6 operands.
507 MIB.addOperand(MI.getOperand(OpIdx++));
508 MIB.addOperand(MI.getOperand(OpIdx++));
509 // Copy the am6offset operand.
510 if (TableEntry->HasWriteBack)
511 MIB.addOperand(MI.getOperand(OpIdx++));
513 // Grab the super-register source.
514 MachineOperand MO = MI.getOperand(OpIdx++);
515 if (!TableEntry->IsLoad)
516 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
518 // Add the subregs as sources of the new instruction.
519 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
520 getKillRegState(MO.isKill()));
521 MIB.addReg(D0, SrcFlags);
523 MIB.addReg(D1, SrcFlags);
525 MIB.addReg(D2, SrcFlags);
527 MIB.addReg(D3, SrcFlags);
529 // Add the lane number operand.
533 // Copy the predicate operands.
534 MIB.addOperand(MI.getOperand(OpIdx++));
535 MIB.addOperand(MI.getOperand(OpIdx++));
537 // Copy the super-register source to be an implicit source.
538 MO.setImplicit(true);
540 if (TableEntry->IsLoad)
541 // Add an implicit def for the super-register.
542 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
543 TransferImpOps(MI, MIB, MIB);
544 MI.eraseFromParent();
547 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
548 /// register operands to real instructions with D register operands.
549 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
550 unsigned Opc, bool IsExt, unsigned NumRegs) {
551 MachineInstr &MI = *MBBI;
552 MachineBasicBlock &MBB = *MI.getParent();
554 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
557 // Transfer the destination register operand.
558 MIB.addOperand(MI.getOperand(OpIdx++));
560 MIB.addOperand(MI.getOperand(OpIdx++));
562 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
563 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
564 unsigned D0, D1, D2, D3;
565 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
566 MIB.addReg(D0).addReg(D1);
572 // Copy the other source register operand.
573 MIB.addOperand(MI.getOperand(OpIdx++));
575 // Copy the predicate operands.
576 MIB.addOperand(MI.getOperand(OpIdx++));
577 MIB.addOperand(MI.getOperand(OpIdx++));
580 // Add an implicit kill for the super-reg.
581 (*MIB).addRegisterKilled(SrcReg, TRI, true);
582 TransferImpOps(MI, MIB, MIB);
583 MI.eraseFromParent();
586 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
587 bool Modified = false;
589 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
591 MachineInstr &MI = *MBBI;
592 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
594 bool ModifiedOp = true;
595 unsigned Opcode = MI.getOpcode();
601 case ARM::Int_eh_sjlj_dispatchsetup: {
602 MachineFunction &MF = *MI.getParent()->getParent();
603 const ARMBaseInstrInfo *AII =
604 static_cast<const ARMBaseInstrInfo*>(TII);
605 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
606 // For functions using a base pointer, we rematerialize it (via the frame
607 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
608 // for us. Otherwise, expand to nothing.
609 if (RI.hasBasePointer(MF)) {
610 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
611 int32_t NumBytes = AFI->getFramePtrSpillOffset();
612 unsigned FramePtr = RI.getFrameRegister(MF);
613 assert (RI.hasFP(MF) && "base pointer without frame pointer?");
615 if (AFI->isThumb2Function()) {
616 llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
617 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
618 } else if (AFI->isThumbFunction()) {
619 llvm::emitThumbRegPlusImmediate(MBB, MBBI, ARM::R6,
621 *TII, RI, MI.getDebugLoc());
623 llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
624 FramePtr, -NumBytes, ARMCC::AL, 0,
627 // If there's dynamic realignment, adjust for it.
628 if (RI.needsStackRealignment(MF)) {
629 MachineFrameInfo *MFI = MF.getFrameInfo();
630 unsigned MaxAlign = MFI->getMaxAlignment();
631 assert (!AFI->isThumb1OnlyFunction());
632 // Emit bic r6, r6, MaxAlign
633 unsigned bicOpc = AFI->isThumbFunction() ?
634 ARM::t2BICri : ARM::BICri;
635 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
636 TII->get(bicOpc), ARM::R6)
637 .addReg(ARM::R6, RegState::Kill)
638 .addImm(MaxAlign-1)));
642 MI.eraseFromParent();
646 case ARM::MOVsrl_flag:
647 case ARM::MOVsra_flag: {
648 // These are just fancy MOVs insructions.
649 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
650 MI.getOperand(0).getReg())
651 .addOperand(MI.getOperand(1))
653 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr
655 .addReg(ARM::CPSR, RegState::Define);
656 MI.eraseFromParent();
660 // This encodes as "MOVs Rd, Rm, rrx
661 MachineInstrBuilder MIB =
662 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
663 MI.getOperand(0).getReg())
664 .addOperand(MI.getOperand(1))
665 .addOperand(MI.getOperand(1))
666 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
668 TransferImpOps(MI, MIB, MIB);
669 MI.eraseFromParent();
672 case ARM::tLDRpci_pic:
673 case ARM::t2LDRpci_pic: {
674 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
675 ? ARM::tLDRpci : ARM::t2LDRpci;
676 unsigned DstReg = MI.getOperand(0).getReg();
677 bool DstIsDead = MI.getOperand(0).isDead();
678 MachineInstrBuilder MIB1 =
679 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
680 TII->get(NewLdOpc), DstReg)
681 .addOperand(MI.getOperand(1)));
682 (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
683 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
684 TII->get(ARM::tPICADD))
685 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
687 .addOperand(MI.getOperand(2));
688 TransferImpOps(MI, MIB1, MIB2);
689 MI.eraseFromParent();
694 case ARM::MOVCCi32imm:
695 case ARM::t2MOVi32imm:
696 case ARM::t2MOVCCi32imm: {
697 unsigned PredReg = 0;
698 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
699 unsigned DstReg = MI.getOperand(0).getReg();
700 bool DstIsDead = MI.getOperand(0).isDead();
701 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
702 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
703 MachineInstrBuilder LO16, HI16;
705 if (!STI->hasV6T2Ops() &&
706 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
707 // Expand into a movi + orr.
708 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
709 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
710 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
713 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
714 unsigned ImmVal = (unsigned)MO.getImm();
715 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
716 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
717 LO16 = LO16.addImm(SOImmValV1);
718 HI16 = HI16.addImm(SOImmValV2);
719 (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
720 (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
721 LO16.addImm(Pred).addReg(PredReg).addReg(0);
722 HI16.addImm(Pred).addReg(PredReg).addReg(0);
723 TransferImpOps(MI, LO16, HI16);
724 MI.eraseFromParent();
728 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
729 TII->get(Opcode == ARM::MOVi32imm ?
730 ARM::MOVi16 : ARM::t2MOVi16),
732 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
733 TII->get(Opcode == ARM::MOVi32imm ?
734 ARM::MOVTi16 : ARM::t2MOVTi16))
735 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
739 unsigned Imm = MO.getImm();
740 unsigned Lo16 = Imm & 0xffff;
741 unsigned Hi16 = (Imm >> 16) & 0xffff;
742 LO16 = LO16.addImm(Lo16);
743 HI16 = HI16.addImm(Hi16);
745 const GlobalValue *GV = MO.getGlobal();
746 unsigned TF = MO.getTargetFlags();
747 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
748 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
750 (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
751 (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
752 LO16.addImm(Pred).addReg(PredReg);
753 HI16.addImm(Pred).addReg(PredReg);
754 TransferImpOps(MI, LO16, HI16);
755 MI.eraseFromParent();
760 unsigned DstReg = MI.getOperand(0).getReg();
761 bool DstIsDead = MI.getOperand(0).isDead();
762 unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0);
763 unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1);
764 unsigned SrcReg = MI.getOperand(1).getReg();
765 bool SrcIsKill = MI.getOperand(1).isKill();
766 unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0);
767 unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1);
768 MachineInstrBuilder Even =
769 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
770 TII->get(ARM::VMOVQ))
772 RegState::Define | getDeadRegState(DstIsDead))
773 .addReg(EvenSrc, getKillRegState(SrcIsKill)));
774 MachineInstrBuilder Odd =
775 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
776 TII->get(ARM::VMOVQ))
778 RegState::Define | getDeadRegState(DstIsDead))
779 .addReg(OddSrc, getKillRegState(SrcIsKill)));
780 TransferImpOps(MI, Even, Odd);
781 MI.eraseFromParent();
786 MachineInstrBuilder MIB =
787 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VLDMD));
789 // Grab the Q register destination.
790 bool DstIsDead = MI.getOperand(OpIdx).isDead();
791 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
792 // Copy the addrmode4 operands.
793 MIB.addOperand(MI.getOperand(OpIdx++));
794 MIB.addOperand(MI.getOperand(OpIdx++));
795 // Copy the predicate operands.
796 MIB.addOperand(MI.getOperand(OpIdx++));
797 MIB.addOperand(MI.getOperand(OpIdx++));
798 // Add the destination operands (D subregs).
799 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
800 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
801 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
802 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
803 // Add an implicit def for the super-register.
804 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
805 TransferImpOps(MI, MIB, MIB);
806 MI.eraseFromParent();
811 MachineInstrBuilder MIB =
812 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VSTMD));
814 // Grab the Q register source.
815 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
816 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
817 // Copy the addrmode4 operands.
818 MIB.addOperand(MI.getOperand(OpIdx++));
819 MIB.addOperand(MI.getOperand(OpIdx++));
820 // Copy the predicate operands.
821 MIB.addOperand(MI.getOperand(OpIdx++));
822 MIB.addOperand(MI.getOperand(OpIdx++));
823 // Add the source operands (D subregs).
824 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
825 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
826 MIB.addReg(D0).addReg(D1);
828 // Add an implicit kill for the Q register.
829 (*MIB).addRegisterKilled(SrcReg, TRI, true);
830 TransferImpOps(MI, MIB, MIB);
831 MI.eraseFromParent();
836 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLNfq : ARM::VDUPLNfd;
837 MachineInstrBuilder MIB =
838 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
840 unsigned SrcReg = MI.getOperand(1).getReg();
841 unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
842 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
843 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
844 // The lane is [0,1] for the containing DReg superregister.
845 // Copy the dst/src register operands.
846 MIB.addOperand(MI.getOperand(OpIdx++));
849 // Add the lane select operand.
851 // Add the predicate operands.
852 MIB.addOperand(MI.getOperand(OpIdx++));
853 MIB.addOperand(MI.getOperand(OpIdx++));
855 TransferImpOps(MI, MIB, MIB);
856 MI.eraseFromParent();
860 case ARM::VLD1q8Pseudo:
861 case ARM::VLD1q16Pseudo:
862 case ARM::VLD1q32Pseudo:
863 case ARM::VLD1q64Pseudo:
864 case ARM::VLD1q8Pseudo_UPD:
865 case ARM::VLD1q16Pseudo_UPD:
866 case ARM::VLD1q32Pseudo_UPD:
867 case ARM::VLD1q64Pseudo_UPD:
868 case ARM::VLD2d8Pseudo:
869 case ARM::VLD2d16Pseudo:
870 case ARM::VLD2d32Pseudo:
871 case ARM::VLD2q8Pseudo:
872 case ARM::VLD2q16Pseudo:
873 case ARM::VLD2q32Pseudo:
874 case ARM::VLD2d8Pseudo_UPD:
875 case ARM::VLD2d16Pseudo_UPD:
876 case ARM::VLD2d32Pseudo_UPD:
877 case ARM::VLD2q8Pseudo_UPD:
878 case ARM::VLD2q16Pseudo_UPD:
879 case ARM::VLD2q32Pseudo_UPD:
880 case ARM::VLD3d8Pseudo:
881 case ARM::VLD3d16Pseudo:
882 case ARM::VLD3d32Pseudo:
883 case ARM::VLD1d64TPseudo:
884 case ARM::VLD3d8Pseudo_UPD:
885 case ARM::VLD3d16Pseudo_UPD:
886 case ARM::VLD3d32Pseudo_UPD:
887 case ARM::VLD1d64TPseudo_UPD:
888 case ARM::VLD3q8Pseudo_UPD:
889 case ARM::VLD3q16Pseudo_UPD:
890 case ARM::VLD3q32Pseudo_UPD:
891 case ARM::VLD3q8oddPseudo_UPD:
892 case ARM::VLD3q16oddPseudo_UPD:
893 case ARM::VLD3q32oddPseudo_UPD:
894 case ARM::VLD4d8Pseudo:
895 case ARM::VLD4d16Pseudo:
896 case ARM::VLD4d32Pseudo:
897 case ARM::VLD1d64QPseudo:
898 case ARM::VLD4d8Pseudo_UPD:
899 case ARM::VLD4d16Pseudo_UPD:
900 case ARM::VLD4d32Pseudo_UPD:
901 case ARM::VLD1d64QPseudo_UPD:
902 case ARM::VLD4q8Pseudo_UPD:
903 case ARM::VLD4q16Pseudo_UPD:
904 case ARM::VLD4q32Pseudo_UPD:
905 case ARM::VLD4q8oddPseudo_UPD:
906 case ARM::VLD4q16oddPseudo_UPD:
907 case ARM::VLD4q32oddPseudo_UPD:
911 case ARM::VST1q8Pseudo:
912 case ARM::VST1q16Pseudo:
913 case ARM::VST1q32Pseudo:
914 case ARM::VST1q64Pseudo:
915 case ARM::VST1q8Pseudo_UPD:
916 case ARM::VST1q16Pseudo_UPD:
917 case ARM::VST1q32Pseudo_UPD:
918 case ARM::VST1q64Pseudo_UPD:
919 case ARM::VST2d8Pseudo:
920 case ARM::VST2d16Pseudo:
921 case ARM::VST2d32Pseudo:
922 case ARM::VST2q8Pseudo:
923 case ARM::VST2q16Pseudo:
924 case ARM::VST2q32Pseudo:
925 case ARM::VST2d8Pseudo_UPD:
926 case ARM::VST2d16Pseudo_UPD:
927 case ARM::VST2d32Pseudo_UPD:
928 case ARM::VST2q8Pseudo_UPD:
929 case ARM::VST2q16Pseudo_UPD:
930 case ARM::VST2q32Pseudo_UPD:
931 case ARM::VST3d8Pseudo:
932 case ARM::VST3d16Pseudo:
933 case ARM::VST3d32Pseudo:
934 case ARM::VST1d64TPseudo:
935 case ARM::VST3d8Pseudo_UPD:
936 case ARM::VST3d16Pseudo_UPD:
937 case ARM::VST3d32Pseudo_UPD:
938 case ARM::VST1d64TPseudo_UPD:
939 case ARM::VST3q8Pseudo_UPD:
940 case ARM::VST3q16Pseudo_UPD:
941 case ARM::VST3q32Pseudo_UPD:
942 case ARM::VST3q8oddPseudo_UPD:
943 case ARM::VST3q16oddPseudo_UPD:
944 case ARM::VST3q32oddPseudo_UPD:
945 case ARM::VST4d8Pseudo:
946 case ARM::VST4d16Pseudo:
947 case ARM::VST4d32Pseudo:
948 case ARM::VST1d64QPseudo:
949 case ARM::VST4d8Pseudo_UPD:
950 case ARM::VST4d16Pseudo_UPD:
951 case ARM::VST4d32Pseudo_UPD:
952 case ARM::VST1d64QPseudo_UPD:
953 case ARM::VST4q8Pseudo_UPD:
954 case ARM::VST4q16Pseudo_UPD:
955 case ARM::VST4q32Pseudo_UPD:
956 case ARM::VST4q8oddPseudo_UPD:
957 case ARM::VST4q16oddPseudo_UPD:
958 case ARM::VST4q32oddPseudo_UPD:
962 case ARM::VLD1LNq8Pseudo:
963 case ARM::VLD1LNq16Pseudo:
964 case ARM::VLD1LNq32Pseudo:
965 case ARM::VLD1LNq8Pseudo_UPD:
966 case ARM::VLD1LNq16Pseudo_UPD:
967 case ARM::VLD1LNq32Pseudo_UPD:
968 case ARM::VLD2LNd8Pseudo:
969 case ARM::VLD2LNd16Pseudo:
970 case ARM::VLD2LNd32Pseudo:
971 case ARM::VLD2LNq16Pseudo:
972 case ARM::VLD2LNq32Pseudo:
973 case ARM::VLD2LNd8Pseudo_UPD:
974 case ARM::VLD2LNd16Pseudo_UPD:
975 case ARM::VLD2LNd32Pseudo_UPD:
976 case ARM::VLD2LNq16Pseudo_UPD:
977 case ARM::VLD2LNq32Pseudo_UPD:
978 case ARM::VLD3LNd8Pseudo:
979 case ARM::VLD3LNd16Pseudo:
980 case ARM::VLD3LNd32Pseudo:
981 case ARM::VLD3LNq16Pseudo:
982 case ARM::VLD3LNq32Pseudo:
983 case ARM::VLD3LNd8Pseudo_UPD:
984 case ARM::VLD3LNd16Pseudo_UPD:
985 case ARM::VLD3LNd32Pseudo_UPD:
986 case ARM::VLD3LNq16Pseudo_UPD:
987 case ARM::VLD3LNq32Pseudo_UPD:
988 case ARM::VLD4LNd8Pseudo:
989 case ARM::VLD4LNd16Pseudo:
990 case ARM::VLD4LNd32Pseudo:
991 case ARM::VLD4LNq16Pseudo:
992 case ARM::VLD4LNq32Pseudo:
993 case ARM::VLD4LNd8Pseudo_UPD:
994 case ARM::VLD4LNd16Pseudo_UPD:
995 case ARM::VLD4LNd32Pseudo_UPD:
996 case ARM::VLD4LNq16Pseudo_UPD:
997 case ARM::VLD4LNq32Pseudo_UPD:
998 case ARM::VST1LNq8Pseudo:
999 case ARM::VST1LNq16Pseudo:
1000 case ARM::VST1LNq32Pseudo:
1001 case ARM::VST1LNq8Pseudo_UPD:
1002 case ARM::VST1LNq16Pseudo_UPD:
1003 case ARM::VST1LNq32Pseudo_UPD:
1004 case ARM::VST2LNd8Pseudo:
1005 case ARM::VST2LNd16Pseudo:
1006 case ARM::VST2LNd32Pseudo:
1007 case ARM::VST2LNq16Pseudo:
1008 case ARM::VST2LNq32Pseudo:
1009 case ARM::VST2LNd8Pseudo_UPD:
1010 case ARM::VST2LNd16Pseudo_UPD:
1011 case ARM::VST2LNd32Pseudo_UPD:
1012 case ARM::VST2LNq16Pseudo_UPD:
1013 case ARM::VST2LNq32Pseudo_UPD:
1014 case ARM::VST3LNd8Pseudo:
1015 case ARM::VST3LNd16Pseudo:
1016 case ARM::VST3LNd32Pseudo:
1017 case ARM::VST3LNq16Pseudo:
1018 case ARM::VST3LNq32Pseudo:
1019 case ARM::VST3LNd8Pseudo_UPD:
1020 case ARM::VST3LNd16Pseudo_UPD:
1021 case ARM::VST3LNd32Pseudo_UPD:
1022 case ARM::VST3LNq16Pseudo_UPD:
1023 case ARM::VST3LNq32Pseudo_UPD:
1024 case ARM::VST4LNd8Pseudo:
1025 case ARM::VST4LNd16Pseudo:
1026 case ARM::VST4LNd32Pseudo:
1027 case ARM::VST4LNq16Pseudo:
1028 case ARM::VST4LNq32Pseudo:
1029 case ARM::VST4LNd8Pseudo_UPD:
1030 case ARM::VST4LNd16Pseudo_UPD:
1031 case ARM::VST4LNd32Pseudo_UPD:
1032 case ARM::VST4LNq16Pseudo_UPD:
1033 case ARM::VST4LNq32Pseudo_UPD:
1037 case ARM::VTBL2Pseudo:
1038 ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break;
1039 case ARM::VTBL3Pseudo:
1040 ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break;
1041 case ARM::VTBL4Pseudo:
1042 ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break;
1043 case ARM::VTBX2Pseudo:
1044 ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break;
1045 case ARM::VTBX3Pseudo:
1046 ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break;
1047 case ARM::VTBX4Pseudo:
1048 ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break;
1059 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1060 TII = static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
1061 TRI = MF.getTarget().getRegisterInfo();
1062 STI = &MF.getTarget().getSubtarget<ARMSubtarget>();
1064 bool Modified = false;
1065 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1067 Modified |= ExpandMBB(*MFI);
1071 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1073 FunctionPass *llvm::createARMExpandPseudoPass() {
1074 return new ARMExpandPseudo();