1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-pseudo"
19 #include "ARMAddressingModes.h"
20 #include "ARMBaseInstrInfo.h"
21 #include "ARMRegisterInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
28 class ARMExpandPseudo : public MachineFunctionPass {
31 ARMExpandPseudo() : MachineFunctionPass(ID) {}
33 const TargetInstrInfo *TII;
34 const TargetRegisterInfo *TRI;
36 virtual bool runOnMachineFunction(MachineFunction &Fn);
38 virtual const char *getPassName() const {
39 return "ARM pseudo instruction expansion pass";
43 void TransferImpOps(MachineInstr &OldMI,
44 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
45 bool ExpandMBB(MachineBasicBlock &MBB);
46 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
47 void ExpandVST(MachineBasicBlock::iterator &MBBI);
48 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
49 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
50 unsigned Opc, bool IsExt, unsigned NumRegs);
52 char ARMExpandPseudo::ID = 0;
55 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
56 /// the instructions created from the expansion.
57 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
58 MachineInstrBuilder &UseMI,
59 MachineInstrBuilder &DefMI) {
60 const TargetInstrDesc &Desc = OldMI.getDesc();
61 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
63 const MachineOperand &MO = OldMI.getOperand(i);
64 assert(MO.isReg() && MO.getReg());
73 // Constants for register spacing in NEON load/store instructions.
74 // For quad-register load-lane and store-lane pseudo instructors, the
75 // spacing is initially assumed to be EvenDblSpc, and that is changed to
76 // OddDblSpc depending on the lane number operand.
83 // Entries for NEON load/store information table. The table is sorted by
84 // PseudoOpc for fast binary-search lookups.
85 struct NEONLdStTableEntry {
90 NEONRegSpacing RegSpacing;
91 unsigned char NumRegs; // D registers loaded or stored
92 unsigned char RegElts; // elements per D register; used for lane ops
94 // Comparison methods for binary search of the table.
95 bool operator<(const NEONLdStTableEntry &TE) const {
96 return PseudoOpc < TE.PseudoOpc;
98 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
99 return TE.PseudoOpc < PseudoOpc;
101 friend bool ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
102 const NEONLdStTableEntry &TE) {
103 return PseudoOpc < TE.PseudoOpc;
108 static const NEONLdStTableEntry NEONLdStTable[] = {
109 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 },
110 { ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 },
111 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 },
112 { ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 },
114 { ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 },
115 { ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 },
116 { ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 },
117 { ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 },
118 { ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 },
119 { ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 },
120 { ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 },
121 { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 },
123 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 },
124 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 },
125 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 },
126 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 },
127 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 },
128 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 },
129 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 },
130 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 },
131 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 },
132 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 },
134 { ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 },
135 { ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 },
136 { ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 },
137 { ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 },
138 { ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 },
139 { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 },
141 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 },
142 { ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 },
143 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 },
144 { ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 },
145 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 },
146 { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 },
148 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 },
149 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 },
150 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 },
151 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 },
152 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 },
153 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 },
154 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 },
155 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 },
156 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 },
157 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 },
159 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 },
160 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 },
161 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 },
162 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 },
163 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 },
164 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 },
166 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 },
167 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 },
168 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 },
169 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 },
170 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 },
171 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 },
173 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 },
174 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 },
175 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 },
176 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 },
177 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 },
178 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 },
179 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 },
180 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 },
181 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 },
182 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 },
184 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 },
185 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 },
186 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 },
187 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 },
188 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 },
189 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 },
191 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 },
192 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 },
193 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 },
194 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 },
195 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 },
196 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 },
198 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 },
199 { ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 },
200 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 },
201 { ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 },
203 { ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 },
204 { ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 },
205 { ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 },
206 { ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 },
207 { ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 },
208 { ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 },
209 { ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 },
210 { ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 },
212 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 },
213 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 },
214 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 },
215 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 },
216 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 },
217 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 },
218 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4},
219 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4},
220 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2},
221 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2},
223 { ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 },
224 { ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 },
225 { ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 },
226 { ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 },
227 { ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 },
228 { ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 },
230 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 },
231 { ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 },
232 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 },
233 { ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 },
234 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 },
235 { ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 },
237 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 },
238 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 },
239 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 },
240 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 },
241 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 },
242 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 },
243 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4},
244 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4},
245 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2},
246 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2},
248 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 },
249 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 },
250 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 },
251 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 },
252 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 },
253 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 },
255 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 },
256 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 },
257 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 },
258 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 },
259 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 },
260 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 },
262 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 },
263 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 },
264 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 },
265 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 },
266 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 },
267 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 },
268 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4},
269 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4},
270 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2},
271 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2},
273 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 },
274 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 },
275 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 },
276 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 },
277 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 },
278 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 },
280 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 },
281 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 },
282 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 },
283 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 },
284 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 },
285 { ARM::VST4q8oddPseudo_UPD , ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 }
288 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
289 /// load or store pseudo instruction.
290 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
291 unsigned NumEntries = array_lengthof(NEONLdStTable);
294 // Make sure the table is sorted.
295 static bool TableChecked = false;
297 for (unsigned i = 0; i != NumEntries-1; ++i)
298 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
299 "NEONLdStTable is not sorted!");
304 const NEONLdStTableEntry *I =
305 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
306 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
311 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
312 /// corresponding to the specified register spacing. Not all of the results
313 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
314 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
315 const TargetRegisterInfo *TRI, unsigned &D0,
316 unsigned &D1, unsigned &D2, unsigned &D3) {
317 if (RegSpc == SingleSpc) {
318 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
319 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
320 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
321 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
322 } else if (RegSpc == EvenDblSpc) {
323 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
324 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
325 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
326 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
328 assert(RegSpc == OddDblSpc && "unknown register spacing");
329 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
330 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
331 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
332 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
336 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
337 /// operands to real VLD instructions with D register operands.
338 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
339 MachineInstr &MI = *MBBI;
340 MachineBasicBlock &MBB = *MI.getParent();
342 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
343 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
344 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
345 unsigned NumRegs = TableEntry->NumRegs;
347 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
348 TII->get(TableEntry->RealOpc));
351 bool DstIsDead = MI.getOperand(OpIdx).isDead();
352 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
353 unsigned D0, D1, D2, D3;
354 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
355 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
356 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
358 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
360 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
362 if (TableEntry->HasWriteBack)
363 MIB.addOperand(MI.getOperand(OpIdx++));
365 // Copy the addrmode6 operands.
366 MIB.addOperand(MI.getOperand(OpIdx++));
367 MIB.addOperand(MI.getOperand(OpIdx++));
368 // Copy the am6offset operand.
369 if (TableEntry->HasWriteBack)
370 MIB.addOperand(MI.getOperand(OpIdx++));
372 // For an instruction writing double-spaced subregs, the pseudo instruction
373 // has an extra operand that is a use of the super-register. Record the
374 // operand index and skip over it.
375 unsigned SrcOpIdx = 0;
376 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
379 // Copy the predicate operands.
380 MIB.addOperand(MI.getOperand(OpIdx++));
381 MIB.addOperand(MI.getOperand(OpIdx++));
383 // Copy the super-register source operand used for double-spaced subregs over
384 // to the new instruction as an implicit operand.
386 MachineOperand MO = MI.getOperand(SrcOpIdx);
387 MO.setImplicit(true);
390 // Add an implicit def for the super-register.
391 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
392 TransferImpOps(MI, MIB, MIB);
393 MI.eraseFromParent();
396 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
397 /// operands to real VST instructions with D register operands.
398 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
399 MachineInstr &MI = *MBBI;
400 MachineBasicBlock &MBB = *MI.getParent();
402 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
403 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
404 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
405 unsigned NumRegs = TableEntry->NumRegs;
407 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
408 TII->get(TableEntry->RealOpc));
410 if (TableEntry->HasWriteBack)
411 MIB.addOperand(MI.getOperand(OpIdx++));
413 // Copy the addrmode6 operands.
414 MIB.addOperand(MI.getOperand(OpIdx++));
415 MIB.addOperand(MI.getOperand(OpIdx++));
416 // Copy the am6offset operand.
417 if (TableEntry->HasWriteBack)
418 MIB.addOperand(MI.getOperand(OpIdx++));
420 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
421 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
422 unsigned D0, D1, D2, D3;
423 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
424 MIB.addReg(D0).addReg(D1);
430 // Copy the predicate operands.
431 MIB.addOperand(MI.getOperand(OpIdx++));
432 MIB.addOperand(MI.getOperand(OpIdx++));
435 // Add an implicit kill for the super-reg.
436 (*MIB).addRegisterKilled(SrcReg, TRI, true);
437 TransferImpOps(MI, MIB, MIB);
438 MI.eraseFromParent();
441 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
442 /// register operands to real instructions with D register operands.
443 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
444 MachineInstr &MI = *MBBI;
445 MachineBasicBlock &MBB = *MI.getParent();
447 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
448 assert(TableEntry && "NEONLdStTable lookup failed");
449 NEONRegSpacing RegSpc = TableEntry->RegSpacing;
450 unsigned NumRegs = TableEntry->NumRegs;
451 unsigned RegElts = TableEntry->RegElts;
453 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
454 TII->get(TableEntry->RealOpc));
456 // The lane operand is always the 3rd from last operand, before the 2
457 // predicate operands.
458 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
460 // Adjust the lane and spacing as needed for Q registers.
461 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
462 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
466 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
468 unsigned D0, D1, D2, D3;
470 bool DstIsDead = false;
471 if (TableEntry->IsLoad) {
472 DstIsDead = MI.getOperand(OpIdx).isDead();
473 DstReg = MI.getOperand(OpIdx++).getReg();
474 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
475 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
476 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
478 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
480 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
483 if (TableEntry->HasWriteBack)
484 MIB.addOperand(MI.getOperand(OpIdx++));
486 // Copy the addrmode6 operands.
487 MIB.addOperand(MI.getOperand(OpIdx++));
488 MIB.addOperand(MI.getOperand(OpIdx++));
489 // Copy the am6offset operand.
490 if (TableEntry->HasWriteBack)
491 MIB.addOperand(MI.getOperand(OpIdx++));
493 // Grab the super-register source.
494 MachineOperand MO = MI.getOperand(OpIdx++);
495 if (!TableEntry->IsLoad)
496 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
498 // Add the subregs as sources of the new instruction.
499 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
500 getKillRegState(MO.isKill()));
501 MIB.addReg(D0, SrcFlags).addReg(D1, SrcFlags);
503 MIB.addReg(D2, SrcFlags);
505 MIB.addReg(D3, SrcFlags);
507 // Add the lane number operand.
511 // Copy the predicate operands.
512 MIB.addOperand(MI.getOperand(OpIdx++));
513 MIB.addOperand(MI.getOperand(OpIdx++));
515 // Copy the super-register source to be an implicit source.
516 MO.setImplicit(true);
518 if (TableEntry->IsLoad)
519 // Add an implicit def for the super-register.
520 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
521 TransferImpOps(MI, MIB, MIB);
522 MI.eraseFromParent();
525 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
526 /// register operands to real instructions with D register operands.
527 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
528 unsigned Opc, bool IsExt, unsigned NumRegs) {
529 MachineInstr &MI = *MBBI;
530 MachineBasicBlock &MBB = *MI.getParent();
532 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
535 // Transfer the destination register operand.
536 MIB.addOperand(MI.getOperand(OpIdx++));
538 MIB.addOperand(MI.getOperand(OpIdx++));
540 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
541 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
542 unsigned D0, D1, D2, D3;
543 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
544 MIB.addReg(D0).addReg(D1);
550 // Copy the other source register operand.
551 MIB.addOperand(MI.getOperand(OpIdx++));
553 // Copy the predicate operands.
554 MIB.addOperand(MI.getOperand(OpIdx++));
555 MIB.addOperand(MI.getOperand(OpIdx++));
558 // Add an implicit kill for the super-reg.
559 (*MIB).addRegisterKilled(SrcReg, TRI, true);
560 TransferImpOps(MI, MIB, MIB);
561 MI.eraseFromParent();
564 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
565 bool Modified = false;
567 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
569 MachineInstr &MI = *MBBI;
570 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
572 bool ModifiedOp = true;
573 unsigned Opcode = MI.getOpcode();
579 case ARM::MOVsrl_flag:
580 case ARM::MOVsra_flag: {
581 // These are just fancy MOVs insructions.
582 MachineInstrBuilder MIB =
583 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
584 MI.getOperand(0).getReg())
585 .addOperand(MI.getOperand(1))
587 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr
589 .addReg(ARM::CPSR, getDefRegState(true));
590 MI.eraseFromParent();
594 // This encodes as "MOVs Rd, Rm, rrx
595 MachineInstrBuilder MIB =
596 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
597 MI.getOperand(0).getReg())
598 .addOperand(MI.getOperand(1))
599 .addOperand(MI.getOperand(1))
600 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
602 TransferImpOps(MI, MIB, MIB);
603 MI.eraseFromParent();
606 case ARM::tLDRpci_pic:
607 case ARM::t2LDRpci_pic: {
608 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
609 ? ARM::tLDRpci : ARM::t2LDRpci;
610 unsigned DstReg = MI.getOperand(0).getReg();
611 bool DstIsDead = MI.getOperand(0).isDead();
612 MachineInstrBuilder MIB1 =
613 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
614 TII->get(NewLdOpc), DstReg)
615 .addOperand(MI.getOperand(1)));
616 (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
617 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
618 TII->get(ARM::tPICADD))
619 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
621 .addOperand(MI.getOperand(2));
622 TransferImpOps(MI, MIB1, MIB2);
623 MI.eraseFromParent();
628 case ARM::t2MOVi32imm: {
629 unsigned PredReg = 0;
630 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
631 unsigned DstReg = MI.getOperand(0).getReg();
632 bool DstIsDead = MI.getOperand(0).isDead();
633 const MachineOperand &MO = MI.getOperand(1);
634 MachineInstrBuilder LO16, HI16;
636 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
637 TII->get(Opcode == ARM::MOVi32imm ?
638 ARM::MOVi16 : ARM::t2MOVi16),
640 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
641 TII->get(Opcode == ARM::MOVi32imm ?
642 ARM::MOVTi16 : ARM::t2MOVTi16))
643 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
647 unsigned Imm = MO.getImm();
648 unsigned Lo16 = Imm & 0xffff;
649 unsigned Hi16 = (Imm >> 16) & 0xffff;
650 LO16 = LO16.addImm(Lo16);
651 HI16 = HI16.addImm(Hi16);
653 const GlobalValue *GV = MO.getGlobal();
654 unsigned TF = MO.getTargetFlags();
655 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
656 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
658 (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
659 (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
660 LO16.addImm(Pred).addReg(PredReg);
661 HI16.addImm(Pred).addReg(PredReg);
662 TransferImpOps(MI, LO16, HI16);
663 MI.eraseFromParent();
668 unsigned DstReg = MI.getOperand(0).getReg();
669 bool DstIsDead = MI.getOperand(0).isDead();
670 unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0);
671 unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1);
672 unsigned SrcReg = MI.getOperand(1).getReg();
673 bool SrcIsKill = MI.getOperand(1).isKill();
674 unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0);
675 unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1);
676 MachineInstrBuilder Even =
677 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
678 TII->get(ARM::VMOVQ))
680 getDefRegState(true) | getDeadRegState(DstIsDead))
681 .addReg(EvenSrc, getKillRegState(SrcIsKill)));
682 MachineInstrBuilder Odd =
683 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
684 TII->get(ARM::VMOVQ))
686 getDefRegState(true) | getDeadRegState(DstIsDead))
687 .addReg(OddSrc, getKillRegState(SrcIsKill)));
688 TransferImpOps(MI, Even, Odd);
689 MI.eraseFromParent();
694 MachineInstrBuilder MIB =
695 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VLDMD));
697 // Grab the Q register destination.
698 bool DstIsDead = MI.getOperand(OpIdx).isDead();
699 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
700 // Copy the addrmode4 operands.
701 MIB.addOperand(MI.getOperand(OpIdx++));
702 MIB.addOperand(MI.getOperand(OpIdx++));
703 // Copy the predicate operands.
704 MIB.addOperand(MI.getOperand(OpIdx++));
705 MIB.addOperand(MI.getOperand(OpIdx++));
706 // Add the destination operands (D subregs).
707 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
708 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
709 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
710 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
711 // Add an implicit def for the super-register.
712 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
713 TransferImpOps(MI, MIB, MIB);
714 MI.eraseFromParent();
719 MachineInstrBuilder MIB =
720 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VSTMD));
722 // Grab the Q register source.
723 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
724 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
725 // Copy the addrmode4 operands.
726 MIB.addOperand(MI.getOperand(OpIdx++));
727 MIB.addOperand(MI.getOperand(OpIdx++));
728 // Copy the predicate operands.
729 MIB.addOperand(MI.getOperand(OpIdx++));
730 MIB.addOperand(MI.getOperand(OpIdx++));
731 // Add the source operands (D subregs).
732 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
733 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
734 MIB.addReg(D0).addReg(D1);
736 // Add an implicit kill for the Q register.
737 (*MIB).addRegisterKilled(SrcReg, TRI, true);
738 TransferImpOps(MI, MIB, MIB);
739 MI.eraseFromParent();
744 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLNfq : ARM::VDUPLNfd;
745 MachineInstrBuilder MIB =
746 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
748 unsigned SrcReg = MI.getOperand(1).getReg();
749 unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
750 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
751 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
752 // The lane is [0,1] for the containing DReg superregister.
753 // Copy the dst/src register operands.
754 MIB.addOperand(MI.getOperand(OpIdx++));
757 // Add the lane select operand.
759 // Add the predicate operands.
760 MIB.addOperand(MI.getOperand(OpIdx++));
761 MIB.addOperand(MI.getOperand(OpIdx++));
763 TransferImpOps(MI, MIB, MIB);
764 MI.eraseFromParent();
768 case ARM::VLD1q8Pseudo:
769 case ARM::VLD1q16Pseudo:
770 case ARM::VLD1q32Pseudo:
771 case ARM::VLD1q64Pseudo:
772 case ARM::VLD1q8Pseudo_UPD:
773 case ARM::VLD1q16Pseudo_UPD:
774 case ARM::VLD1q32Pseudo_UPD:
775 case ARM::VLD1q64Pseudo_UPD:
776 case ARM::VLD2d8Pseudo:
777 case ARM::VLD2d16Pseudo:
778 case ARM::VLD2d32Pseudo:
779 case ARM::VLD2q8Pseudo:
780 case ARM::VLD2q16Pseudo:
781 case ARM::VLD2q32Pseudo:
782 case ARM::VLD2d8Pseudo_UPD:
783 case ARM::VLD2d16Pseudo_UPD:
784 case ARM::VLD2d32Pseudo_UPD:
785 case ARM::VLD2q8Pseudo_UPD:
786 case ARM::VLD2q16Pseudo_UPD:
787 case ARM::VLD2q32Pseudo_UPD:
788 case ARM::VLD3d8Pseudo:
789 case ARM::VLD3d16Pseudo:
790 case ARM::VLD3d32Pseudo:
791 case ARM::VLD1d64TPseudo:
792 case ARM::VLD3d8Pseudo_UPD:
793 case ARM::VLD3d16Pseudo_UPD:
794 case ARM::VLD3d32Pseudo_UPD:
795 case ARM::VLD1d64TPseudo_UPD:
796 case ARM::VLD3q8Pseudo_UPD:
797 case ARM::VLD3q16Pseudo_UPD:
798 case ARM::VLD3q32Pseudo_UPD:
799 case ARM::VLD3q8oddPseudo_UPD:
800 case ARM::VLD3q16oddPseudo_UPD:
801 case ARM::VLD3q32oddPseudo_UPD:
802 case ARM::VLD4d8Pseudo:
803 case ARM::VLD4d16Pseudo:
804 case ARM::VLD4d32Pseudo:
805 case ARM::VLD1d64QPseudo:
806 case ARM::VLD4d8Pseudo_UPD:
807 case ARM::VLD4d16Pseudo_UPD:
808 case ARM::VLD4d32Pseudo_UPD:
809 case ARM::VLD1d64QPseudo_UPD:
810 case ARM::VLD4q8Pseudo_UPD:
811 case ARM::VLD4q16Pseudo_UPD:
812 case ARM::VLD4q32Pseudo_UPD:
813 case ARM::VLD4q8oddPseudo_UPD:
814 case ARM::VLD4q16oddPseudo_UPD:
815 case ARM::VLD4q32oddPseudo_UPD:
819 case ARM::VST1q8Pseudo:
820 case ARM::VST1q16Pseudo:
821 case ARM::VST1q32Pseudo:
822 case ARM::VST1q64Pseudo:
823 case ARM::VST1q8Pseudo_UPD:
824 case ARM::VST1q16Pseudo_UPD:
825 case ARM::VST1q32Pseudo_UPD:
826 case ARM::VST1q64Pseudo_UPD:
827 case ARM::VST2d8Pseudo:
828 case ARM::VST2d16Pseudo:
829 case ARM::VST2d32Pseudo:
830 case ARM::VST2q8Pseudo:
831 case ARM::VST2q16Pseudo:
832 case ARM::VST2q32Pseudo:
833 case ARM::VST2d8Pseudo_UPD:
834 case ARM::VST2d16Pseudo_UPD:
835 case ARM::VST2d32Pseudo_UPD:
836 case ARM::VST2q8Pseudo_UPD:
837 case ARM::VST2q16Pseudo_UPD:
838 case ARM::VST2q32Pseudo_UPD:
839 case ARM::VST3d8Pseudo:
840 case ARM::VST3d16Pseudo:
841 case ARM::VST3d32Pseudo:
842 case ARM::VST1d64TPseudo:
843 case ARM::VST3d8Pseudo_UPD:
844 case ARM::VST3d16Pseudo_UPD:
845 case ARM::VST3d32Pseudo_UPD:
846 case ARM::VST1d64TPseudo_UPD:
847 case ARM::VST3q8Pseudo_UPD:
848 case ARM::VST3q16Pseudo_UPD:
849 case ARM::VST3q32Pseudo_UPD:
850 case ARM::VST3q8oddPseudo_UPD:
851 case ARM::VST3q16oddPseudo_UPD:
852 case ARM::VST3q32oddPseudo_UPD:
853 case ARM::VST4d8Pseudo:
854 case ARM::VST4d16Pseudo:
855 case ARM::VST4d32Pseudo:
856 case ARM::VST1d64QPseudo:
857 case ARM::VST4d8Pseudo_UPD:
858 case ARM::VST4d16Pseudo_UPD:
859 case ARM::VST4d32Pseudo_UPD:
860 case ARM::VST1d64QPseudo_UPD:
861 case ARM::VST4q8Pseudo_UPD:
862 case ARM::VST4q16Pseudo_UPD:
863 case ARM::VST4q32Pseudo_UPD:
864 case ARM::VST4q8oddPseudo_UPD:
865 case ARM::VST4q16oddPseudo_UPD:
866 case ARM::VST4q32oddPseudo_UPD:
870 case ARM::VLD2LNd8Pseudo:
871 case ARM::VLD2LNd16Pseudo:
872 case ARM::VLD2LNd32Pseudo:
873 case ARM::VLD2LNq16Pseudo:
874 case ARM::VLD2LNq32Pseudo:
875 case ARM::VLD2LNd8Pseudo_UPD:
876 case ARM::VLD2LNd16Pseudo_UPD:
877 case ARM::VLD2LNd32Pseudo_UPD:
878 case ARM::VLD2LNq16Pseudo_UPD:
879 case ARM::VLD2LNq32Pseudo_UPD:
880 case ARM::VLD3LNd8Pseudo:
881 case ARM::VLD3LNd16Pseudo:
882 case ARM::VLD3LNd32Pseudo:
883 case ARM::VLD3LNq16Pseudo:
884 case ARM::VLD3LNq32Pseudo:
885 case ARM::VLD3LNd8Pseudo_UPD:
886 case ARM::VLD3LNd16Pseudo_UPD:
887 case ARM::VLD3LNd32Pseudo_UPD:
888 case ARM::VLD3LNq16Pseudo_UPD:
889 case ARM::VLD3LNq32Pseudo_UPD:
890 case ARM::VLD4LNd8Pseudo:
891 case ARM::VLD4LNd16Pseudo:
892 case ARM::VLD4LNd32Pseudo:
893 case ARM::VLD4LNq16Pseudo:
894 case ARM::VLD4LNq32Pseudo:
895 case ARM::VLD4LNd8Pseudo_UPD:
896 case ARM::VLD4LNd16Pseudo_UPD:
897 case ARM::VLD4LNd32Pseudo_UPD:
898 case ARM::VLD4LNq16Pseudo_UPD:
899 case ARM::VLD4LNq32Pseudo_UPD:
900 case ARM::VST2LNd8Pseudo:
901 case ARM::VST2LNd16Pseudo:
902 case ARM::VST2LNd32Pseudo:
903 case ARM::VST2LNq16Pseudo:
904 case ARM::VST2LNq32Pseudo:
905 case ARM::VST2LNd8Pseudo_UPD:
906 case ARM::VST2LNd16Pseudo_UPD:
907 case ARM::VST2LNd32Pseudo_UPD:
908 case ARM::VST2LNq16Pseudo_UPD:
909 case ARM::VST2LNq32Pseudo_UPD:
910 case ARM::VST3LNd8Pseudo:
911 case ARM::VST3LNd16Pseudo:
912 case ARM::VST3LNd32Pseudo:
913 case ARM::VST3LNq16Pseudo:
914 case ARM::VST3LNq32Pseudo:
915 case ARM::VST3LNd8Pseudo_UPD:
916 case ARM::VST3LNd16Pseudo_UPD:
917 case ARM::VST3LNd32Pseudo_UPD:
918 case ARM::VST3LNq16Pseudo_UPD:
919 case ARM::VST3LNq32Pseudo_UPD:
920 case ARM::VST4LNd8Pseudo:
921 case ARM::VST4LNd16Pseudo:
922 case ARM::VST4LNd32Pseudo:
923 case ARM::VST4LNq16Pseudo:
924 case ARM::VST4LNq32Pseudo:
925 case ARM::VST4LNd8Pseudo_UPD:
926 case ARM::VST4LNd16Pseudo_UPD:
927 case ARM::VST4LNd32Pseudo_UPD:
928 case ARM::VST4LNq16Pseudo_UPD:
929 case ARM::VST4LNq32Pseudo_UPD:
933 case ARM::VTBL2Pseudo:
934 ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break;
935 case ARM::VTBL3Pseudo:
936 ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break;
937 case ARM::VTBL4Pseudo:
938 ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break;
939 case ARM::VTBX2Pseudo:
940 ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break;
941 case ARM::VTBX3Pseudo:
942 ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break;
943 case ARM::VTBX4Pseudo:
944 ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break;
955 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
956 TII = MF.getTarget().getInstrInfo();
957 TRI = MF.getTarget().getRegisterInfo();
959 bool Modified = false;
960 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
962 Modified |= ExpandMBB(*MFI);
966 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
968 FunctionPass *llvm::createARMExpandPseudoPass() {
969 return new ARMExpandPseudo();