1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/GlobalVariable.h"
37 #include "llvm/IR/Instructions.h"
38 #include "llvm/IR/IntrinsicInst.h"
39 #include "llvm/IR/Module.h"
40 #include "llvm/IR/Operator.h"
41 #include "llvm/Support/CallSite.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/GetElementPtrTypeIterator.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetLowering.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetOptions.h"
51 extern cl::opt<bool> EnableARMLongCalls;
55 // All possible address modes, plus some.
56 typedef struct Address {
69 // Innocuous defaults for our address.
71 : BaseType(RegBase), Offset(0) {
76 class ARMFastISel : public FastISel {
78 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
79 /// make the right decision when generating code for different targets.
80 const ARMSubtarget *Subtarget;
82 const TargetMachine &TM;
83 const TargetInstrInfo &TII;
84 const TargetLowering &TLI;
87 // Convenience variables to avoid some queries.
92 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
93 const TargetLibraryInfo *libInfo)
94 : FastISel(funcInfo, libInfo),
95 M(const_cast<Module&>(*funcInfo.Fn->getParent())),
96 TM(funcInfo.MF->getTarget()),
97 TII(*TM.getInstrInfo()),
98 TLI(*TM.getTargetLowering()) {
99 Subtarget = &TM.getSubtarget<ARMSubtarget>();
100 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
101 isThumb2 = AFI->isThumbFunction();
102 Context = &funcInfo.Fn->getContext();
105 // Code from FastISel.cpp.
107 unsigned FastEmitInst_(unsigned MachineInstOpcode,
108 const TargetRegisterClass *RC);
109 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
110 const TargetRegisterClass *RC,
111 unsigned Op0, bool Op0IsKill);
112 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
113 const TargetRegisterClass *RC,
114 unsigned Op0, bool Op0IsKill,
115 unsigned Op1, bool Op1IsKill);
116 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
117 const TargetRegisterClass *RC,
118 unsigned Op0, bool Op0IsKill,
119 unsigned Op1, bool Op1IsKill,
120 unsigned Op2, bool Op2IsKill);
121 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
122 const TargetRegisterClass *RC,
123 unsigned Op0, bool Op0IsKill,
125 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
126 const TargetRegisterClass *RC,
127 unsigned Op0, bool Op0IsKill,
128 const ConstantFP *FPImm);
129 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
130 const TargetRegisterClass *RC,
131 unsigned Op0, bool Op0IsKill,
132 unsigned Op1, bool Op1IsKill,
134 unsigned FastEmitInst_i(unsigned MachineInstOpcode,
135 const TargetRegisterClass *RC,
137 unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
138 const TargetRegisterClass *RC,
139 uint64_t Imm1, uint64_t Imm2);
141 unsigned FastEmitInst_extractsubreg(MVT RetVT,
142 unsigned Op0, bool Op0IsKill,
145 // Backend specific FastISel code.
147 virtual bool TargetSelectInstruction(const Instruction *I);
148 virtual unsigned TargetMaterializeConstant(const Constant *C);
149 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
150 virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
152 virtual bool FastLowerArguments();
154 #include "ARMGenFastISel.inc"
156 // Instruction selection routines.
158 bool SelectLoad(const Instruction *I);
159 bool SelectStore(const Instruction *I);
160 bool SelectBranch(const Instruction *I);
161 bool SelectIndirectBr(const Instruction *I);
162 bool SelectCmp(const Instruction *I);
163 bool SelectFPExt(const Instruction *I);
164 bool SelectFPTrunc(const Instruction *I);
165 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
166 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
167 bool SelectIToFP(const Instruction *I, bool isSigned);
168 bool SelectFPToI(const Instruction *I, bool isSigned);
169 bool SelectDiv(const Instruction *I, bool isSigned);
170 bool SelectRem(const Instruction *I, bool isSigned);
171 bool SelectCall(const Instruction *I, const char *IntrMemName);
172 bool SelectIntrinsicCall(const IntrinsicInst &I);
173 bool SelectSelect(const Instruction *I);
174 bool SelectRet(const Instruction *I);
175 bool SelectTrunc(const Instruction *I);
176 bool SelectIntExt(const Instruction *I);
177 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
181 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned OpNum,
183 bool isTypeLegal(Type *Ty, MVT &VT);
184 bool isLoadTypeLegal(Type *Ty, MVT &VT);
185 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
187 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
188 unsigned Alignment = 0, bool isZExt = true,
189 bool allocReg = true);
190 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
191 unsigned Alignment = 0);
192 bool ARMComputeAddress(const Value *Obj, Address &Addr);
193 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
194 bool ARMIsMemCpySmall(uint64_t Len);
195 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
197 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
198 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
199 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
200 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
201 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
202 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
203 unsigned ARMSelectCallOp(bool UseReg);
204 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
206 // Call handling routines.
208 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
211 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
212 SmallVectorImpl<unsigned> &ArgRegs,
213 SmallVectorImpl<MVT> &ArgVTs,
214 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
215 SmallVectorImpl<unsigned> &RegArgs,
219 unsigned getLibcallReg(const Twine &Name);
220 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
221 const Instruction *I, CallingConv::ID CC,
222 unsigned &NumBytes, bool isVarArg);
223 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
225 // OptionalDef handling routines.
227 bool isARMNEONPred(const MachineInstr *MI);
228 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
229 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
230 void AddLoadStoreOperands(MVT VT, Address &Addr,
231 const MachineInstrBuilder &MIB,
232 unsigned Flags, bool useAM3);
235 } // end anonymous namespace
237 #include "ARMGenCallingConv.inc"
239 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
240 // we don't care about implicit defs here, just places we'll need to add a
241 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
242 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
243 if (!MI->hasOptionalDef())
246 // Look to see if our OptionalDef is defining CPSR or CCR.
247 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
248 const MachineOperand &MO = MI->getOperand(i);
249 if (!MO.isReg() || !MO.isDef()) continue;
250 if (MO.getReg() == ARM::CPSR)
256 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
257 const MCInstrDesc &MCID = MI->getDesc();
259 // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
260 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
261 AFI->isThumb2Function())
262 return MI->isPredicable();
264 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
265 if (MCID.OpInfo[i].isPredicate())
271 // If the machine is predicable go ahead and add the predicate operands, if
272 // it needs default CC operands add those.
273 // TODO: If we want to support thumb1 then we'll need to deal with optional
274 // CPSR defs that need to be added before the remaining operands. See s_cc_out
275 // for descriptions why.
276 const MachineInstrBuilder &
277 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
278 MachineInstr *MI = &*MIB;
280 // Do we use a predicate? or...
281 // Are we NEON in ARM mode and have a predicate operand? If so, I know
282 // we're not predicable but add it anyways.
283 if (isARMNEONPred(MI))
286 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
287 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
289 if (DefinesOptionalPredicate(MI, &CPSR)) {
298 unsigned ARMFastISel::constrainOperandRegClass(const MCInstrDesc &II,
299 unsigned Op, unsigned OpNum) {
300 if (TargetRegisterInfo::isVirtualRegister(Op)) {
301 const TargetRegisterClass *RegClass =
302 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
303 if (!MRI.constrainRegClass(Op, RegClass)) {
304 // If it's not legal to COPY between the register classes, something
305 // has gone very wrong before we got here.
306 unsigned NewOp = createResultReg(RegClass);
307 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
308 TII.get(TargetOpcode::COPY), NewOp).addReg(Op));
315 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
316 const TargetRegisterClass* RC) {
317 unsigned ResultReg = createResultReg(RC);
318 const MCInstrDesc &II = TII.get(MachineInstOpcode);
320 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
324 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
325 const TargetRegisterClass *RC,
326 unsigned Op0, bool Op0IsKill) {
327 unsigned ResultReg = createResultReg(RC);
328 const MCInstrDesc &II = TII.get(MachineInstOpcode);
330 // Make sure the input operand is sufficiently constrained to be legal
331 // for this instruction.
332 Op0 = constrainOperandRegClass(II, Op0, 1);
333 if (II.getNumDefs() >= 1) {
334 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
335 .addReg(Op0, Op0IsKill * RegState::Kill));
337 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
338 .addReg(Op0, Op0IsKill * RegState::Kill));
339 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
340 TII.get(TargetOpcode::COPY), ResultReg)
341 .addReg(II.ImplicitDefs[0]));
346 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
347 const TargetRegisterClass *RC,
348 unsigned Op0, bool Op0IsKill,
349 unsigned Op1, bool Op1IsKill) {
350 unsigned ResultReg = createResultReg(RC);
351 const MCInstrDesc &II = TII.get(MachineInstOpcode);
353 // Make sure the input operands are sufficiently constrained to be legal
354 // for this instruction.
355 Op0 = constrainOperandRegClass(II, Op0, 1);
356 Op1 = constrainOperandRegClass(II, Op1, 2);
358 if (II.getNumDefs() >= 1) {
359 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
360 .addReg(Op0, Op0IsKill * RegState::Kill)
361 .addReg(Op1, Op1IsKill * RegState::Kill));
363 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
364 .addReg(Op0, Op0IsKill * RegState::Kill)
365 .addReg(Op1, Op1IsKill * RegState::Kill));
366 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
367 TII.get(TargetOpcode::COPY), ResultReg)
368 .addReg(II.ImplicitDefs[0]));
373 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
374 const TargetRegisterClass *RC,
375 unsigned Op0, bool Op0IsKill,
376 unsigned Op1, bool Op1IsKill,
377 unsigned Op2, bool Op2IsKill) {
378 unsigned ResultReg = createResultReg(RC);
379 const MCInstrDesc &II = TII.get(MachineInstOpcode);
381 // Make sure the input operands are sufficiently constrained to be legal
382 // for this instruction.
383 Op0 = constrainOperandRegClass(II, Op0, 1);
384 Op1 = constrainOperandRegClass(II, Op1, 2);
385 Op2 = constrainOperandRegClass(II, Op1, 3);
387 if (II.getNumDefs() >= 1) {
388 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
389 .addReg(Op0, Op0IsKill * RegState::Kill)
390 .addReg(Op1, Op1IsKill * RegState::Kill)
391 .addReg(Op2, Op2IsKill * RegState::Kill));
393 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
394 .addReg(Op0, Op0IsKill * RegState::Kill)
395 .addReg(Op1, Op1IsKill * RegState::Kill)
396 .addReg(Op2, Op2IsKill * RegState::Kill));
397 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
398 TII.get(TargetOpcode::COPY), ResultReg)
399 .addReg(II.ImplicitDefs[0]));
404 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
405 const TargetRegisterClass *RC,
406 unsigned Op0, bool Op0IsKill,
408 unsigned ResultReg = createResultReg(RC);
409 const MCInstrDesc &II = TII.get(MachineInstOpcode);
411 // Make sure the input operand is sufficiently constrained to be legal
412 // for this instruction.
413 Op0 = constrainOperandRegClass(II, Op0, 1);
414 if (II.getNumDefs() >= 1) {
415 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
416 .addReg(Op0, Op0IsKill * RegState::Kill)
419 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
420 .addReg(Op0, Op0IsKill * RegState::Kill)
422 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
423 TII.get(TargetOpcode::COPY), ResultReg)
424 .addReg(II.ImplicitDefs[0]));
429 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
430 const TargetRegisterClass *RC,
431 unsigned Op0, bool Op0IsKill,
432 const ConstantFP *FPImm) {
433 unsigned ResultReg = createResultReg(RC);
434 const MCInstrDesc &II = TII.get(MachineInstOpcode);
436 // Make sure the input operand is sufficiently constrained to be legal
437 // for this instruction.
438 Op0 = constrainOperandRegClass(II, Op0, 1);
439 if (II.getNumDefs() >= 1) {
440 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
441 .addReg(Op0, Op0IsKill * RegState::Kill)
444 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
445 .addReg(Op0, Op0IsKill * RegState::Kill)
447 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
448 TII.get(TargetOpcode::COPY), ResultReg)
449 .addReg(II.ImplicitDefs[0]));
454 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
455 const TargetRegisterClass *RC,
456 unsigned Op0, bool Op0IsKill,
457 unsigned Op1, bool Op1IsKill,
459 unsigned ResultReg = createResultReg(RC);
460 const MCInstrDesc &II = TII.get(MachineInstOpcode);
462 // Make sure the input operands are sufficiently constrained to be legal
463 // for this instruction.
464 Op0 = constrainOperandRegClass(II, Op0, 1);
465 Op1 = constrainOperandRegClass(II, Op1, 2);
466 if (II.getNumDefs() >= 1) {
467 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
468 .addReg(Op0, Op0IsKill * RegState::Kill)
469 .addReg(Op1, Op1IsKill * RegState::Kill)
472 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
473 .addReg(Op0, Op0IsKill * RegState::Kill)
474 .addReg(Op1, Op1IsKill * RegState::Kill)
476 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
477 TII.get(TargetOpcode::COPY), ResultReg)
478 .addReg(II.ImplicitDefs[0]));
483 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
484 const TargetRegisterClass *RC,
486 unsigned ResultReg = createResultReg(RC);
487 const MCInstrDesc &II = TII.get(MachineInstOpcode);
489 if (II.getNumDefs() >= 1) {
490 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
493 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
495 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
496 TII.get(TargetOpcode::COPY), ResultReg)
497 .addReg(II.ImplicitDefs[0]));
502 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
503 const TargetRegisterClass *RC,
504 uint64_t Imm1, uint64_t Imm2) {
505 unsigned ResultReg = createResultReg(RC);
506 const MCInstrDesc &II = TII.get(MachineInstOpcode);
508 if (II.getNumDefs() >= 1) {
509 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
510 .addImm(Imm1).addImm(Imm2));
512 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
513 .addImm(Imm1).addImm(Imm2));
514 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
515 TII.get(TargetOpcode::COPY),
517 .addReg(II.ImplicitDefs[0]));
522 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
523 unsigned Op0, bool Op0IsKill,
525 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
526 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
527 "Cannot yet extract from physregs");
529 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
530 DL, TII.get(TargetOpcode::COPY), ResultReg)
531 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
535 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
536 // checks from the various callers.
537 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
538 if (VT == MVT::f64) return 0;
540 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
541 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
542 TII.get(ARM::VMOVSR), MoveReg)
547 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
548 if (VT == MVT::i64) return 0;
550 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
551 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
552 TII.get(ARM::VMOVRS), MoveReg)
557 // For double width floating point we need to materialize two constants
558 // (the high and the low) into integer registers then use a move to get
559 // the combined constant into an FP reg.
560 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
561 const APFloat Val = CFP->getValueAPF();
562 bool is64bit = VT == MVT::f64;
564 // This checks to see if we can use VFP3 instructions to materialize
565 // a constant, otherwise we have to go through the constant pool.
566 if (TLI.isFPImmLegal(Val, VT)) {
570 Imm = ARM_AM::getFP64Imm(Val);
573 Imm = ARM_AM::getFP32Imm(Val);
576 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
577 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
583 // Require VFP2 for loading fp constants.
584 if (!Subtarget->hasVFP2()) return false;
586 // MachineConstantPool wants an explicit alignment.
587 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
589 // TODO: Figure out if this is correct.
590 Align = TD.getTypeAllocSize(CFP->getType());
592 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
593 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
594 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
596 // The extra reg is for addrmode5.
597 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
599 .addConstantPoolIndex(Idx)
604 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
606 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
609 // If we can do this in a single instruction without a constant pool entry
611 const ConstantInt *CI = cast<ConstantInt>(C);
612 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
613 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
614 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
616 unsigned ImmReg = createResultReg(RC);
617 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
618 TII.get(Opc), ImmReg)
619 .addImm(CI->getZExtValue()));
623 // Use MVN to emit negative constants.
624 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
625 unsigned Imm = (unsigned)~(CI->getSExtValue());
626 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
627 (ARM_AM::getSOImmVal(Imm) != -1);
629 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
630 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
631 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
632 TII.get(Opc), ImmReg)
638 // Load from constant pool. For now 32-bit only.
642 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
644 // MachineConstantPool wants an explicit alignment.
645 unsigned Align = TD.getPrefTypeAlignment(C->getType());
647 // TODO: Figure out if this is correct.
648 Align = TD.getTypeAllocSize(C->getType());
650 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
653 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
654 TII.get(ARM::t2LDRpci), DestReg)
655 .addConstantPoolIndex(Idx));
657 // The extra immediate is for addrmode2.
658 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
659 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
660 TII.get(ARM::LDRcp), DestReg)
661 .addConstantPoolIndex(Idx)
667 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
668 // For now 32-bit only.
669 if (VT != MVT::i32) return 0;
671 Reloc::Model RelocM = TM.getRelocationModel();
672 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
673 const TargetRegisterClass *RC = isThumb2 ?
674 (const TargetRegisterClass*)&ARM::rGPRRegClass :
675 (const TargetRegisterClass*)&ARM::GPRRegClass;
676 unsigned DestReg = createResultReg(RC);
678 // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
679 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
680 bool IsThreadLocal = GVar && GVar->isThreadLocal();
681 if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
683 // Use movw+movt when possible, it avoids constant pool entries.
684 // Non-darwin targets only support static movt relocations in FastISel.
685 if (Subtarget->useMovt() &&
686 (Subtarget->isTargetMachO() || RelocM == Reloc::Static)) {
688 unsigned char TF = 0;
689 if (Subtarget->isTargetMachO())
690 TF = ARMII::MO_NONLAZY;
694 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
697 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
700 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
701 DestReg).addGlobalAddress(GV, 0, TF));
703 // MachineConstantPool wants an explicit alignment.
704 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
706 // TODO: Figure out if this is correct.
707 Align = TD.getTypeAllocSize(GV->getType());
710 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
711 return ARMLowerPICELF(GV, Align, VT);
714 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
715 (Subtarget->isThumb() ? 4 : 8);
716 unsigned Id = AFI->createPICLabelUId();
717 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
720 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
723 MachineInstrBuilder MIB;
725 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
726 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
727 .addConstantPoolIndex(Idx);
728 if (RelocM == Reloc::PIC_)
730 AddOptionalDefs(MIB);
732 // The extra immediate is for addrmode2.
733 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
734 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
736 .addConstantPoolIndex(Idx)
738 AddOptionalDefs(MIB);
740 if (RelocM == Reloc::PIC_) {
741 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
742 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
744 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
745 DL, TII.get(Opc), NewDestReg)
748 AddOptionalDefs(MIB);
755 MachineInstrBuilder MIB;
756 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
758 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
759 TII.get(ARM::t2LDRi12), NewDestReg)
763 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
767 DestReg = NewDestReg;
768 AddOptionalDefs(MIB);
774 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
775 EVT CEVT = TLI.getValueType(C->getType(), true);
777 // Only handle simple types.
778 if (!CEVT.isSimple()) return 0;
779 MVT VT = CEVT.getSimpleVT();
781 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
782 return ARMMaterializeFP(CFP, VT);
783 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
784 return ARMMaterializeGV(GV, VT);
785 else if (isa<ConstantInt>(C))
786 return ARMMaterializeInt(C, VT);
791 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
793 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
794 // Don't handle dynamic allocas.
795 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
798 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
800 DenseMap<const AllocaInst*, int>::iterator SI =
801 FuncInfo.StaticAllocaMap.find(AI);
803 // This will get lowered later into the correct offsets and registers
804 // via rewriteXFrameIndex.
805 if (SI != FuncInfo.StaticAllocaMap.end()) {
806 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
807 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
808 unsigned ResultReg = createResultReg(RC);
809 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
811 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
812 TII.get(Opc), ResultReg)
813 .addFrameIndex(SI->second)
821 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
822 EVT evt = TLI.getValueType(Ty, true);
824 // Only handle simple types.
825 if (evt == MVT::Other || !evt.isSimple()) return false;
826 VT = evt.getSimpleVT();
828 // Handle all legal types, i.e. a register that will directly hold this
830 return TLI.isTypeLegal(VT);
833 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
834 if (isTypeLegal(Ty, VT)) return true;
836 // If this is a type than can be sign or zero-extended to a basic operation
837 // go ahead and accept it now.
838 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
844 // Computes the address to get to an object.
845 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
846 // Some boilerplate from the X86 FastISel.
847 const User *U = NULL;
848 unsigned Opcode = Instruction::UserOp1;
849 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
850 // Don't walk into other basic blocks unless the object is an alloca from
851 // another block, otherwise it may not have a virtual register assigned.
852 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
853 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
854 Opcode = I->getOpcode();
857 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
858 Opcode = C->getOpcode();
862 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
863 if (Ty->getAddressSpace() > 255)
864 // Fast instruction selection doesn't support the special
871 case Instruction::BitCast:
872 // Look through bitcasts.
873 return ARMComputeAddress(U->getOperand(0), Addr);
874 case Instruction::IntToPtr:
875 // Look past no-op inttoptrs.
876 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
877 return ARMComputeAddress(U->getOperand(0), Addr);
879 case Instruction::PtrToInt:
880 // Look past no-op ptrtoints.
881 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
882 return ARMComputeAddress(U->getOperand(0), Addr);
884 case Instruction::GetElementPtr: {
885 Address SavedAddr = Addr;
886 int TmpOffset = Addr.Offset;
888 // Iterate through the GEP folding the constants into offsets where
890 gep_type_iterator GTI = gep_type_begin(U);
891 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
892 i != e; ++i, ++GTI) {
893 const Value *Op = *i;
894 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
895 const StructLayout *SL = TD.getStructLayout(STy);
896 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
897 TmpOffset += SL->getElementOffset(Idx);
899 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
901 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
902 // Constant-offset addressing.
903 TmpOffset += CI->getSExtValue() * S;
906 if (canFoldAddIntoGEP(U, Op)) {
907 // A compatible add with a constant operand. Fold the constant.
909 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
910 TmpOffset += CI->getSExtValue() * S;
911 // Iterate on the other operand.
912 Op = cast<AddOperator>(Op)->getOperand(0);
916 goto unsupported_gep;
921 // Try to grab the base operand now.
922 Addr.Offset = TmpOffset;
923 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
925 // We failed, restore everything and try the other options.
931 case Instruction::Alloca: {
932 const AllocaInst *AI = cast<AllocaInst>(Obj);
933 DenseMap<const AllocaInst*, int>::iterator SI =
934 FuncInfo.StaticAllocaMap.find(AI);
935 if (SI != FuncInfo.StaticAllocaMap.end()) {
936 Addr.BaseType = Address::FrameIndexBase;
937 Addr.Base.FI = SI->second;
944 // Try to get this in a register if nothing else has worked.
945 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
946 return Addr.Base.Reg != 0;
949 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
950 bool needsLowering = false;
951 switch (VT.SimpleTy) {
952 default: llvm_unreachable("Unhandled load/store type!");
958 // Integer loads/stores handle 12-bit offsets.
959 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
960 // Handle negative offsets.
961 if (needsLowering && isThumb2)
962 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
965 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
966 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
971 // Floating point operands handle 8-bit offsets.
972 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
976 // If this is a stack pointer and the offset needs to be simplified then
977 // put the alloca address into a register, set the base type back to
978 // register and continue. This should almost never happen.
979 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
980 const TargetRegisterClass *RC = isThumb2 ?
981 (const TargetRegisterClass*)&ARM::tGPRRegClass :
982 (const TargetRegisterClass*)&ARM::GPRRegClass;
983 unsigned ResultReg = createResultReg(RC);
984 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
985 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
986 TII.get(Opc), ResultReg)
987 .addFrameIndex(Addr.Base.FI)
989 Addr.Base.Reg = ResultReg;
990 Addr.BaseType = Address::RegBase;
993 // Since the offset is too large for the load/store instruction
994 // get the reg+offset into a register.
996 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
997 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
1002 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
1003 const MachineInstrBuilder &MIB,
1004 unsigned Flags, bool useAM3) {
1005 // addrmode5 output depends on the selection dag addressing dividing the
1006 // offset by 4 that it then later multiplies. Do this here as well.
1007 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
1010 // Frame base works a bit differently. Handle it separately.
1011 if (Addr.BaseType == Address::FrameIndexBase) {
1012 int FI = Addr.Base.FI;
1013 int Offset = Addr.Offset;
1014 MachineMemOperand *MMO =
1015 FuncInfo.MF->getMachineMemOperand(
1016 MachinePointerInfo::getFixedStack(FI, Offset),
1018 MFI.getObjectSize(FI),
1019 MFI.getObjectAlignment(FI));
1020 // Now add the rest of the operands.
1021 MIB.addFrameIndex(FI);
1023 // ARM halfword load/stores and signed byte loads need an additional
1026 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
1030 MIB.addImm(Addr.Offset);
1032 MIB.addMemOperand(MMO);
1034 // Now add the rest of the operands.
1035 MIB.addReg(Addr.Base.Reg);
1037 // ARM halfword load/stores and signed byte loads need an additional
1040 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
1044 MIB.addImm(Addr.Offset);
1047 AddOptionalDefs(MIB);
1050 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
1051 unsigned Alignment, bool isZExt, bool allocReg) {
1053 bool useAM3 = false;
1054 bool needVMOV = false;
1055 const TargetRegisterClass *RC;
1056 switch (VT.SimpleTy) {
1057 // This is mostly going to be Neon/vector support.
1058 default: return false;
1062 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1063 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
1065 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
1074 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1077 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1081 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1082 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
1084 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1086 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1089 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1092 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1096 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1099 Opc = ARM::t2LDRi12;
1103 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1106 if (!Subtarget->hasVFP2()) return false;
1107 // Unaligned loads need special handling. Floats require word-alignment.
1108 if (Alignment && Alignment < 4) {
1111 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1112 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1115 RC = TLI.getRegClassFor(VT);
1119 if (!Subtarget->hasVFP2()) return false;
1120 // FIXME: Unaligned loads need special handling. Doublewords require
1122 if (Alignment && Alignment < 4)
1126 RC = TLI.getRegClassFor(VT);
1129 // Simplify this down to something we can handle.
1130 ARMSimplifyAddress(Addr, VT, useAM3);
1132 // Create the base instruction, then add the operands.
1134 ResultReg = createResultReg(RC);
1135 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1136 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1137 TII.get(Opc), ResultReg);
1138 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1140 // If we had an unaligned load of a float we've converted it to an regular
1141 // load. Now we must move from the GRP to the FP register.
1143 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1144 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1145 TII.get(ARM::VMOVSR), MoveReg)
1146 .addReg(ResultReg));
1147 ResultReg = MoveReg;
1152 bool ARMFastISel::SelectLoad(const Instruction *I) {
1153 // Atomic loads need special handling.
1154 if (cast<LoadInst>(I)->isAtomic())
1157 // Verify we have a legal type before going any further.
1159 if (!isLoadTypeLegal(I->getType(), VT))
1162 // See if we can handle this address.
1164 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1167 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1169 UpdateValueMap(I, ResultReg);
1173 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1174 unsigned Alignment) {
1176 bool useAM3 = false;
1177 switch (VT.SimpleTy) {
1178 // This is mostly going to be Neon/vector support.
1179 default: return false;
1181 unsigned Res = createResultReg(isThumb2 ?
1182 (const TargetRegisterClass*)&ARM::tGPRRegClass :
1183 (const TargetRegisterClass*)&ARM::GPRRegClass);
1184 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1185 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1186 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1188 .addReg(SrcReg).addImm(1));
1190 } // Fallthrough here.
1193 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1194 StrOpc = ARM::t2STRBi8;
1196 StrOpc = ARM::t2STRBi12;
1198 StrOpc = ARM::STRBi12;
1202 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1206 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1207 StrOpc = ARM::t2STRHi8;
1209 StrOpc = ARM::t2STRHi12;
1216 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1220 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1221 StrOpc = ARM::t2STRi8;
1223 StrOpc = ARM::t2STRi12;
1225 StrOpc = ARM::STRi12;
1229 if (!Subtarget->hasVFP2()) return false;
1230 // Unaligned stores need special handling. Floats require word-alignment.
1231 if (Alignment && Alignment < 4) {
1232 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1233 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1234 TII.get(ARM::VMOVRS), MoveReg)
1238 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1240 StrOpc = ARM::VSTRS;
1244 if (!Subtarget->hasVFP2()) return false;
1245 // FIXME: Unaligned stores need special handling. Doublewords require
1247 if (Alignment && Alignment < 4)
1250 StrOpc = ARM::VSTRD;
1253 // Simplify this down to something we can handle.
1254 ARMSimplifyAddress(Addr, VT, useAM3);
1256 // Create the base instruction, then add the operands.
1257 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1258 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1261 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1265 bool ARMFastISel::SelectStore(const Instruction *I) {
1266 Value *Op0 = I->getOperand(0);
1267 unsigned SrcReg = 0;
1269 // Atomic stores need special handling.
1270 if (cast<StoreInst>(I)->isAtomic())
1273 // Verify we have a legal type before going any further.
1275 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1278 // Get the value to be stored into a register.
1279 SrcReg = getRegForValue(Op0);
1280 if (SrcReg == 0) return false;
1282 // See if we can handle this address.
1284 if (!ARMComputeAddress(I->getOperand(1), Addr))
1287 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1292 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1294 // Needs two compares...
1295 case CmpInst::FCMP_ONE:
1296 case CmpInst::FCMP_UEQ:
1298 // AL is our "false" for now. The other two need more compares.
1300 case CmpInst::ICMP_EQ:
1301 case CmpInst::FCMP_OEQ:
1303 case CmpInst::ICMP_SGT:
1304 case CmpInst::FCMP_OGT:
1306 case CmpInst::ICMP_SGE:
1307 case CmpInst::FCMP_OGE:
1309 case CmpInst::ICMP_UGT:
1310 case CmpInst::FCMP_UGT:
1312 case CmpInst::FCMP_OLT:
1314 case CmpInst::ICMP_ULE:
1315 case CmpInst::FCMP_OLE:
1317 case CmpInst::FCMP_ORD:
1319 case CmpInst::FCMP_UNO:
1321 case CmpInst::FCMP_UGE:
1323 case CmpInst::ICMP_SLT:
1324 case CmpInst::FCMP_ULT:
1326 case CmpInst::ICMP_SLE:
1327 case CmpInst::FCMP_ULE:
1329 case CmpInst::FCMP_UNE:
1330 case CmpInst::ICMP_NE:
1332 case CmpInst::ICMP_UGE:
1334 case CmpInst::ICMP_ULT:
1339 bool ARMFastISel::SelectBranch(const Instruction *I) {
1340 const BranchInst *BI = cast<BranchInst>(I);
1341 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1342 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1344 // Simple branch support.
1346 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1348 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1349 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1351 // Get the compare predicate.
1352 // Try to take advantage of fallthrough opportunities.
1353 CmpInst::Predicate Predicate = CI->getPredicate();
1354 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1355 std::swap(TBB, FBB);
1356 Predicate = CmpInst::getInversePredicate(Predicate);
1359 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1361 // We may not handle every CC for now.
1362 if (ARMPred == ARMCC::AL) return false;
1364 // Emit the compare.
1365 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1368 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1369 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1370 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1371 FastEmitBranch(FBB, DL);
1372 FuncInfo.MBB->addSuccessor(TBB);
1375 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1377 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1378 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1379 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1380 unsigned OpReg = getRegForValue(TI->getOperand(0));
1381 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1382 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1384 .addReg(OpReg).addImm(1));
1386 unsigned CCMode = ARMCC::NE;
1387 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1388 std::swap(TBB, FBB);
1392 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1393 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1394 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1396 FastEmitBranch(FBB, DL);
1397 FuncInfo.MBB->addSuccessor(TBB);
1400 } else if (const ConstantInt *CI =
1401 dyn_cast<ConstantInt>(BI->getCondition())) {
1402 uint64_t Imm = CI->getZExtValue();
1403 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1404 FastEmitBranch(Target, DL);
1408 unsigned CmpReg = getRegForValue(BI->getCondition());
1409 if (CmpReg == 0) return false;
1411 // We've been divorced from our compare! Our block was split, and
1412 // now our compare lives in a predecessor block. We musn't
1413 // re-compare here, as the children of the compare aren't guaranteed
1414 // live across the block boundary (we *could* check for this).
1415 // Regardless, the compare has been done in the predecessor block,
1416 // and it left a value for us in a virtual register. Ergo, we test
1417 // the one-bit value left in the virtual register.
1418 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1419 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1420 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1421 .addReg(CmpReg).addImm(1));
1423 unsigned CCMode = ARMCC::NE;
1424 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1425 std::swap(TBB, FBB);
1429 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1430 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1431 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1432 FastEmitBranch(FBB, DL);
1433 FuncInfo.MBB->addSuccessor(TBB);
1437 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1438 unsigned AddrReg = getRegForValue(I->getOperand(0));
1439 if (AddrReg == 0) return false;
1441 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1442 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
1445 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1446 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1447 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1452 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1454 Type *Ty = Src1Value->getType();
1455 EVT SrcEVT = TLI.getValueType(Ty, true);
1456 if (!SrcEVT.isSimple()) return false;
1457 MVT SrcVT = SrcEVT.getSimpleVT();
1459 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1460 if (isFloat && !Subtarget->hasVFP2())
1463 // Check to see if the 2nd operand is a constant that we can encode directly
1466 bool UseImm = false;
1467 bool isNegativeImm = false;
1468 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1469 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1470 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1471 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1473 const APInt &CIVal = ConstInt->getValue();
1474 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1475 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1476 // then a cmn, because there is no way to represent 2147483648 as a
1477 // signed 32-bit int.
1478 if (Imm < 0 && Imm != (int)0x80000000) {
1479 isNegativeImm = true;
1482 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1483 (ARM_AM::getSOImmVal(Imm) != -1);
1485 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1486 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1487 if (ConstFP->isZero() && !ConstFP->isNegative())
1493 bool needsExt = false;
1494 switch (SrcVT.SimpleTy) {
1495 default: return false;
1496 // TODO: Verify compares.
1499 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1503 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1509 // Intentional fall-through.
1513 CmpOpc = ARM::t2CMPrr;
1515 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1518 CmpOpc = ARM::CMPrr;
1520 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1525 unsigned SrcReg1 = getRegForValue(Src1Value);
1526 if (SrcReg1 == 0) return false;
1528 unsigned SrcReg2 = 0;
1530 SrcReg2 = getRegForValue(Src2Value);
1531 if (SrcReg2 == 0) return false;
1534 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1536 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1537 if (SrcReg1 == 0) return false;
1539 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1540 if (SrcReg2 == 0) return false;
1544 const MCInstrDesc &II = TII.get(CmpOpc);
1545 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1547 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1548 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1549 .addReg(SrcReg1).addReg(SrcReg2));
1551 MachineInstrBuilder MIB;
1552 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1555 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1558 AddOptionalDefs(MIB);
1561 // For floating point we need to move the result to a comparison register
1562 // that we can then use for branches.
1563 if (Ty->isFloatTy() || Ty->isDoubleTy())
1564 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1565 TII.get(ARM::FMSTAT)));
1569 bool ARMFastISel::SelectCmp(const Instruction *I) {
1570 const CmpInst *CI = cast<CmpInst>(I);
1572 // Get the compare predicate.
1573 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1575 // We may not handle every CC for now.
1576 if (ARMPred == ARMCC::AL) return false;
1578 // Emit the compare.
1579 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1582 // Now set a register based on the comparison. Explicitly set the predicates
1584 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1585 const TargetRegisterClass *RC = isThumb2 ?
1586 (const TargetRegisterClass*)&ARM::rGPRRegClass :
1587 (const TargetRegisterClass*)&ARM::GPRRegClass;
1588 unsigned DestReg = createResultReg(RC);
1589 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1590 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1591 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1592 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1593 .addReg(ZeroReg).addImm(1)
1594 .addImm(ARMPred).addReg(ARM::CPSR);
1596 UpdateValueMap(I, DestReg);
1600 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1601 // Make sure we have VFP and that we're extending float to double.
1602 if (!Subtarget->hasVFP2()) return false;
1604 Value *V = I->getOperand(0);
1605 if (!I->getType()->isDoubleTy() ||
1606 !V->getType()->isFloatTy()) return false;
1608 unsigned Op = getRegForValue(V);
1609 if (Op == 0) return false;
1611 unsigned Result = createResultReg(&ARM::DPRRegClass);
1612 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1613 TII.get(ARM::VCVTDS), Result)
1615 UpdateValueMap(I, Result);
1619 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1620 // Make sure we have VFP and that we're truncating double to float.
1621 if (!Subtarget->hasVFP2()) return false;
1623 Value *V = I->getOperand(0);
1624 if (!(I->getType()->isFloatTy() &&
1625 V->getType()->isDoubleTy())) return false;
1627 unsigned Op = getRegForValue(V);
1628 if (Op == 0) return false;
1630 unsigned Result = createResultReg(&ARM::SPRRegClass);
1631 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1632 TII.get(ARM::VCVTSD), Result)
1634 UpdateValueMap(I, Result);
1638 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1639 // Make sure we have VFP.
1640 if (!Subtarget->hasVFP2()) return false;
1643 Type *Ty = I->getType();
1644 if (!isTypeLegal(Ty, DstVT))
1647 Value *Src = I->getOperand(0);
1648 EVT SrcEVT = TLI.getValueType(Src->getType(), true);
1649 if (!SrcEVT.isSimple())
1651 MVT SrcVT = SrcEVT.getSimpleVT();
1652 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1655 unsigned SrcReg = getRegForValue(Src);
1656 if (SrcReg == 0) return false;
1658 // Handle sign-extension.
1659 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1660 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1661 /*isZExt*/!isSigned);
1662 if (SrcReg == 0) return false;
1665 // The conversion routine works on fp-reg to fp-reg and the operand above
1666 // was an integer, move it to the fp registers if possible.
1667 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1668 if (FP == 0) return false;
1671 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1672 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1675 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1676 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1679 UpdateValueMap(I, ResultReg);
1683 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1684 // Make sure we have VFP.
1685 if (!Subtarget->hasVFP2()) return false;
1688 Type *RetTy = I->getType();
1689 if (!isTypeLegal(RetTy, DstVT))
1692 unsigned Op = getRegForValue(I->getOperand(0));
1693 if (Op == 0) return false;
1696 Type *OpTy = I->getOperand(0)->getType();
1697 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1698 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1701 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1702 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1703 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1707 // This result needs to be in an integer register, but the conversion only
1708 // takes place in fp-regs.
1709 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1710 if (IntReg == 0) return false;
1712 UpdateValueMap(I, IntReg);
1716 bool ARMFastISel::SelectSelect(const Instruction *I) {
1718 if (!isTypeLegal(I->getType(), VT))
1721 // Things need to be register sized for register moves.
1722 if (VT != MVT::i32) return false;
1724 unsigned CondReg = getRegForValue(I->getOperand(0));
1725 if (CondReg == 0) return false;
1726 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1727 if (Op1Reg == 0) return false;
1729 // Check to see if we can use an immediate in the conditional move.
1731 bool UseImm = false;
1732 bool isNegativeImm = false;
1733 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1734 assert (VT == MVT::i32 && "Expecting an i32.");
1735 Imm = (int)ConstInt->getValue().getZExtValue();
1737 isNegativeImm = true;
1740 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1741 (ARM_AM::getSOImmVal(Imm) != -1);
1744 unsigned Op2Reg = 0;
1746 Op2Reg = getRegForValue(I->getOperand(2));
1747 if (Op2Reg == 0) return false;
1750 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1751 CondReg = constrainOperandRegClass(TII.get(CmpOpc), CondReg, 0);
1752 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1753 .addReg(CondReg).addImm(0));
1756 const TargetRegisterClass *RC;
1758 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1759 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1761 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1763 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1765 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1767 unsigned ResultReg = createResultReg(RC);
1769 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1770 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1771 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1772 .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1774 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1775 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1776 .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1778 UpdateValueMap(I, ResultReg);
1782 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1784 Type *Ty = I->getType();
1785 if (!isTypeLegal(Ty, VT))
1788 // If we have integer div support we should have selected this automagically.
1789 // In case we have a real miss go ahead and return false and we'll pick
1791 if (Subtarget->hasDivide()) return false;
1793 // Otherwise emit a libcall.
1794 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1796 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1797 else if (VT == MVT::i16)
1798 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1799 else if (VT == MVT::i32)
1800 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1801 else if (VT == MVT::i64)
1802 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1803 else if (VT == MVT::i128)
1804 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1805 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1807 return ARMEmitLibcall(I, LC);
1810 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1812 Type *Ty = I->getType();
1813 if (!isTypeLegal(Ty, VT))
1816 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1818 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1819 else if (VT == MVT::i16)
1820 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1821 else if (VT == MVT::i32)
1822 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1823 else if (VT == MVT::i64)
1824 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1825 else if (VT == MVT::i128)
1826 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1827 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1829 return ARMEmitLibcall(I, LC);
1832 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1833 EVT DestVT = TLI.getValueType(I->getType(), true);
1835 // We can get here in the case when we have a binary operation on a non-legal
1836 // type and the target independent selector doesn't know how to handle it.
1837 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1841 switch (ISDOpcode) {
1842 default: return false;
1844 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1847 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1850 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1854 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1855 if (SrcReg1 == 0) return false;
1857 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1858 // in the instruction, rather then materializing the value in a register.
1859 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1860 if (SrcReg2 == 0) return false;
1862 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1863 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1864 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1865 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1866 TII.get(Opc), ResultReg)
1867 .addReg(SrcReg1).addReg(SrcReg2));
1868 UpdateValueMap(I, ResultReg);
1872 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1873 EVT FPVT = TLI.getValueType(I->getType(), true);
1874 if (!FPVT.isSimple()) return false;
1875 MVT VT = FPVT.getSimpleVT();
1877 // We can get here in the case when we want to use NEON for our fp
1878 // operations, but can't figure out how to. Just use the vfp instructions
1880 // FIXME: It'd be nice to use NEON instructions.
1881 Type *Ty = I->getType();
1882 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1883 if (isFloat && !Subtarget->hasVFP2())
1887 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1888 switch (ISDOpcode) {
1889 default: return false;
1891 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1894 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1897 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1900 unsigned Op1 = getRegForValue(I->getOperand(0));
1901 if (Op1 == 0) return false;
1903 unsigned Op2 = getRegForValue(I->getOperand(1));
1904 if (Op2 == 0) return false;
1906 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1907 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1908 TII.get(Opc), ResultReg)
1909 .addReg(Op1).addReg(Op2));
1910 UpdateValueMap(I, ResultReg);
1914 // Call Handling Code
1916 // This is largely taken directly from CCAssignFnForNode
1917 // TODO: We may not support all of this.
1918 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1923 llvm_unreachable("Unsupported calling convention");
1924 case CallingConv::Fast:
1925 if (Subtarget->hasVFP2() && !isVarArg) {
1926 if (!Subtarget->isAAPCS_ABI())
1927 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1928 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1929 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1932 case CallingConv::C:
1933 // Use target triple & subtarget features to do actual dispatch.
1934 if (Subtarget->isAAPCS_ABI()) {
1935 if (Subtarget->hasVFP2() &&
1936 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1937 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1939 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1941 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1942 case CallingConv::ARM_AAPCS_VFP:
1944 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1945 // Fall through to soft float variant, variadic functions don't
1946 // use hard floating point ABI.
1947 case CallingConv::ARM_AAPCS:
1948 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1949 case CallingConv::ARM_APCS:
1950 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1951 case CallingConv::GHC:
1953 llvm_unreachable("Can't return in GHC call convention");
1955 return CC_ARM_APCS_GHC;
1959 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1960 SmallVectorImpl<unsigned> &ArgRegs,
1961 SmallVectorImpl<MVT> &ArgVTs,
1962 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1963 SmallVectorImpl<unsigned> &RegArgs,
1967 SmallVector<CCValAssign, 16> ArgLocs;
1968 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1969 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1970 CCAssignFnForCall(CC, false, isVarArg));
1972 // Check that we can handle all of the arguments. If we can't, then bail out
1973 // now before we add code to the MBB.
1974 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1975 CCValAssign &VA = ArgLocs[i];
1976 MVT ArgVT = ArgVTs[VA.getValNo()];
1978 // We don't handle NEON/vector parameters yet.
1979 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1982 // Now copy/store arg to correct locations.
1983 if (VA.isRegLoc() && !VA.needsCustom()) {
1985 } else if (VA.needsCustom()) {
1986 // TODO: We need custom lowering for vector (v2f64) args.
1987 if (VA.getLocVT() != MVT::f64 ||
1988 // TODO: Only handle register args for now.
1989 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1992 switch (ArgVT.SimpleTy) {
2001 if (!Subtarget->hasVFP2())
2005 if (!Subtarget->hasVFP2())
2012 // At the point, we are able to handle the call's arguments in fast isel.
2014 // Get a count of how many bytes are to be pushed on the stack.
2015 NumBytes = CCInfo.getNextStackOffset();
2017 // Issue CALLSEQ_START
2018 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2019 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2020 TII.get(AdjStackDown))
2023 // Process the args.
2024 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2025 CCValAssign &VA = ArgLocs[i];
2026 unsigned Arg = ArgRegs[VA.getValNo()];
2027 MVT ArgVT = ArgVTs[VA.getValNo()];
2029 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
2030 "We don't handle NEON/vector parameters yet.");
2032 // Handle arg promotion, etc.
2033 switch (VA.getLocInfo()) {
2034 case CCValAssign::Full: break;
2035 case CCValAssign::SExt: {
2036 MVT DestVT = VA.getLocVT();
2037 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
2038 assert (Arg != 0 && "Failed to emit a sext");
2042 case CCValAssign::AExt:
2043 // Intentional fall-through. Handle AExt and ZExt.
2044 case CCValAssign::ZExt: {
2045 MVT DestVT = VA.getLocVT();
2046 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
2047 assert (Arg != 0 && "Failed to emit a zext");
2051 case CCValAssign::BCvt: {
2052 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
2053 /*TODO: Kill=*/false);
2054 assert(BC != 0 && "Failed to emit a bitcast!");
2056 ArgVT = VA.getLocVT();
2059 default: llvm_unreachable("Unknown arg promotion!");
2062 // Now copy/store arg to correct locations.
2063 if (VA.isRegLoc() && !VA.needsCustom()) {
2064 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2067 RegArgs.push_back(VA.getLocReg());
2068 } else if (VA.needsCustom()) {
2069 // TODO: We need custom lowering for vector (v2f64) args.
2070 assert(VA.getLocVT() == MVT::f64 &&
2071 "Custom lowering for v2f64 args not available");
2073 CCValAssign &NextVA = ArgLocs[++i];
2075 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2076 "We only handle register args!");
2078 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2079 TII.get(ARM::VMOVRRD), VA.getLocReg())
2080 .addReg(NextVA.getLocReg(), RegState::Define)
2082 RegArgs.push_back(VA.getLocReg());
2083 RegArgs.push_back(NextVA.getLocReg());
2085 assert(VA.isMemLoc());
2086 // Need to store on the stack.
2088 Addr.BaseType = Address::RegBase;
2089 Addr.Base.Reg = ARM::SP;
2090 Addr.Offset = VA.getLocMemOffset();
2092 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2093 assert(EmitRet && "Could not emit a store for argument!");
2100 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2101 const Instruction *I, CallingConv::ID CC,
2102 unsigned &NumBytes, bool isVarArg) {
2103 // Issue CALLSEQ_END
2104 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2105 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2106 TII.get(AdjStackUp))
2107 .addImm(NumBytes).addImm(0));
2109 // Now the return value.
2110 if (RetVT != MVT::isVoid) {
2111 SmallVector<CCValAssign, 16> RVLocs;
2112 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2113 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2115 // Copy all of the result registers out of their specified physreg.
2116 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2117 // For this move we copy into two registers and then move into the
2118 // double fp reg we want.
2119 MVT DestVT = RVLocs[0].getValVT();
2120 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2121 unsigned ResultReg = createResultReg(DstRC);
2122 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2123 TII.get(ARM::VMOVDRR), ResultReg)
2124 .addReg(RVLocs[0].getLocReg())
2125 .addReg(RVLocs[1].getLocReg()));
2127 UsedRegs.push_back(RVLocs[0].getLocReg());
2128 UsedRegs.push_back(RVLocs[1].getLocReg());
2130 // Finally update the result.
2131 UpdateValueMap(I, ResultReg);
2133 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2134 MVT CopyVT = RVLocs[0].getValVT();
2136 // Special handling for extended integers.
2137 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2140 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2142 unsigned ResultReg = createResultReg(DstRC);
2143 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2144 ResultReg).addReg(RVLocs[0].getLocReg());
2145 UsedRegs.push_back(RVLocs[0].getLocReg());
2147 // Finally update the result.
2148 UpdateValueMap(I, ResultReg);
2155 bool ARMFastISel::SelectRet(const Instruction *I) {
2156 const ReturnInst *Ret = cast<ReturnInst>(I);
2157 const Function &F = *I->getParent()->getParent();
2159 if (!FuncInfo.CanLowerReturn)
2162 // Build a list of return value registers.
2163 SmallVector<unsigned, 4> RetRegs;
2165 CallingConv::ID CC = F.getCallingConv();
2166 if (Ret->getNumOperands() > 0) {
2167 SmallVector<ISD::OutputArg, 4> Outs;
2168 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
2170 // Analyze operands of the call, assigning locations to each operand.
2171 SmallVector<CCValAssign, 16> ValLocs;
2172 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
2173 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2176 const Value *RV = Ret->getOperand(0);
2177 unsigned Reg = getRegForValue(RV);
2181 // Only handle a single return value for now.
2182 if (ValLocs.size() != 1)
2185 CCValAssign &VA = ValLocs[0];
2187 // Don't bother handling odd stuff for now.
2188 if (VA.getLocInfo() != CCValAssign::Full)
2190 // Only handle register returns for now.
2194 unsigned SrcReg = Reg + VA.getValNo();
2195 EVT RVEVT = TLI.getValueType(RV->getType());
2196 if (!RVEVT.isSimple()) return false;
2197 MVT RVVT = RVEVT.getSimpleVT();
2198 MVT DestVT = VA.getValVT();
2199 // Special handling for extended integers.
2200 if (RVVT != DestVT) {
2201 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2204 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2206 // Perform extension if flagged as either zext or sext. Otherwise, do
2208 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2209 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2210 if (SrcReg == 0) return false;
2215 unsigned DstReg = VA.getLocReg();
2216 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2217 // Avoid a cross-class copy. This is very unlikely.
2218 if (!SrcRC->contains(DstReg))
2220 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2221 DstReg).addReg(SrcReg);
2223 // Add register to return instruction.
2224 RetRegs.push_back(VA.getLocReg());
2227 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2228 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2230 AddOptionalDefs(MIB);
2231 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2232 MIB.addReg(RetRegs[i], RegState::Implicit);
2236 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2238 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2240 return isThumb2 ? ARM::tBL : ARM::BL;
2243 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2244 // Manually compute the global's type to avoid building it when unnecessary.
2245 Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2246 EVT LCREVT = TLI.getValueType(GVTy);
2247 if (!LCREVT.isSimple()) return 0;
2249 GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
2250 GlobalValue::ExternalLinkage, 0, Name);
2251 assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2252 return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2255 // A quick function that will emit a call for a named libcall in F with the
2256 // vector of passed arguments for the Instruction in I. We can assume that we
2257 // can emit a call for any libcall we can produce. This is an abridged version
2258 // of the full call infrastructure since we won't need to worry about things
2259 // like computed function pointers or strange arguments at call sites.
2260 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2262 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2263 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2265 // Handle *simple* calls for now.
2266 Type *RetTy = I->getType();
2268 if (RetTy->isVoidTy())
2269 RetVT = MVT::isVoid;
2270 else if (!isTypeLegal(RetTy, RetVT))
2273 // Can't handle non-double multi-reg retvals.
2274 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2275 SmallVector<CCValAssign, 16> RVLocs;
2276 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
2277 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2278 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2282 // Set up the argument vectors.
2283 SmallVector<Value*, 8> Args;
2284 SmallVector<unsigned, 8> ArgRegs;
2285 SmallVector<MVT, 8> ArgVTs;
2286 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2287 Args.reserve(I->getNumOperands());
2288 ArgRegs.reserve(I->getNumOperands());
2289 ArgVTs.reserve(I->getNumOperands());
2290 ArgFlags.reserve(I->getNumOperands());
2291 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2292 Value *Op = I->getOperand(i);
2293 unsigned Arg = getRegForValue(Op);
2294 if (Arg == 0) return false;
2296 Type *ArgTy = Op->getType();
2298 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2300 ISD::ArgFlagsTy Flags;
2301 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2302 Flags.setOrigAlign(OriginalAlignment);
2305 ArgRegs.push_back(Arg);
2306 ArgVTs.push_back(ArgVT);
2307 ArgFlags.push_back(Flags);
2310 // Handle the arguments now that we've gotten them.
2311 SmallVector<unsigned, 4> RegArgs;
2313 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2314 RegArgs, CC, NumBytes, false))
2317 unsigned CalleeReg = 0;
2318 if (EnableARMLongCalls) {
2319 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2320 if (CalleeReg == 0) return false;
2324 unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
2325 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2326 DL, TII.get(CallOpc));
2327 // BL / BLX don't take a predicate, but tBL / tBLX do.
2329 AddDefaultPred(MIB);
2330 if (EnableARMLongCalls)
2331 MIB.addReg(CalleeReg);
2333 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2335 // Add implicit physical register uses to the call.
2336 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2337 MIB.addReg(RegArgs[i], RegState::Implicit);
2339 // Add a register mask with the call-preserved registers.
2340 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2341 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2343 // Finish off the call including any return values.
2344 SmallVector<unsigned, 4> UsedRegs;
2345 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2347 // Set all unused physreg defs as dead.
2348 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2353 bool ARMFastISel::SelectCall(const Instruction *I,
2354 const char *IntrMemName = 0) {
2355 const CallInst *CI = cast<CallInst>(I);
2356 const Value *Callee = CI->getCalledValue();
2358 // Can't handle inline asm.
2359 if (isa<InlineAsm>(Callee)) return false;
2361 // Allow SelectionDAG isel to handle tail calls.
2362 if (CI->isTailCall()) return false;
2364 // Check the calling convention.
2365 ImmutableCallSite CS(CI);
2366 CallingConv::ID CC = CS.getCallingConv();
2368 // TODO: Avoid some calling conventions?
2370 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2371 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2372 bool isVarArg = FTy->isVarArg();
2374 // Handle *simple* calls for now.
2375 Type *RetTy = I->getType();
2377 if (RetTy->isVoidTy())
2378 RetVT = MVT::isVoid;
2379 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2380 RetVT != MVT::i8 && RetVT != MVT::i1)
2383 // Can't handle non-double multi-reg retvals.
2384 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2385 RetVT != MVT::i16 && RetVT != MVT::i32) {
2386 SmallVector<CCValAssign, 16> RVLocs;
2387 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2388 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2389 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2393 // Set up the argument vectors.
2394 SmallVector<Value*, 8> Args;
2395 SmallVector<unsigned, 8> ArgRegs;
2396 SmallVector<MVT, 8> ArgVTs;
2397 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2398 unsigned arg_size = CS.arg_size();
2399 Args.reserve(arg_size);
2400 ArgRegs.reserve(arg_size);
2401 ArgVTs.reserve(arg_size);
2402 ArgFlags.reserve(arg_size);
2403 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2405 // If we're lowering a memory intrinsic instead of a regular call, skip the
2406 // last two arguments, which shouldn't be passed to the underlying function.
2407 if (IntrMemName && e-i <= 2)
2410 ISD::ArgFlagsTy Flags;
2411 unsigned AttrInd = i - CS.arg_begin() + 1;
2412 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2414 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2417 // FIXME: Only handle *easy* calls for now.
2418 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2419 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2420 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2421 CS.paramHasAttr(AttrInd, Attribute::ByVal))
2424 Type *ArgTy = (*i)->getType();
2426 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2430 unsigned Arg = getRegForValue(*i);
2434 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2435 Flags.setOrigAlign(OriginalAlignment);
2438 ArgRegs.push_back(Arg);
2439 ArgVTs.push_back(ArgVT);
2440 ArgFlags.push_back(Flags);
2443 // Handle the arguments now that we've gotten them.
2444 SmallVector<unsigned, 4> RegArgs;
2446 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2447 RegArgs, CC, NumBytes, isVarArg))
2450 bool UseReg = false;
2451 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2452 if (!GV || EnableARMLongCalls) UseReg = true;
2454 unsigned CalleeReg = 0;
2457 CalleeReg = getLibcallReg(IntrMemName);
2459 CalleeReg = getRegForValue(Callee);
2461 if (CalleeReg == 0) return false;
2465 unsigned CallOpc = ARMSelectCallOp(UseReg);
2466 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2467 DL, TII.get(CallOpc));
2469 unsigned char OpFlags = 0;
2471 // Add MO_PLT for global address or external symbol in the PIC relocation
2473 if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_)
2474 OpFlags = ARMII::MO_PLT;
2476 // ARM calls don't take a predicate, but tBL / tBLX do.
2478 AddDefaultPred(MIB);
2480 MIB.addReg(CalleeReg);
2481 else if (!IntrMemName)
2482 MIB.addGlobalAddress(GV, 0, OpFlags);
2484 MIB.addExternalSymbol(IntrMemName, OpFlags);
2486 // Add implicit physical register uses to the call.
2487 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2488 MIB.addReg(RegArgs[i], RegState::Implicit);
2490 // Add a register mask with the call-preserved registers.
2491 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2492 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2494 // Finish off the call including any return values.
2495 SmallVector<unsigned, 4> UsedRegs;
2496 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2499 // Set all unused physreg defs as dead.
2500 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2505 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2509 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2510 uint64_t Len, unsigned Alignment) {
2511 // Make sure we don't bloat code by inlining very large memcpy's.
2512 if (!ARMIsMemCpySmall(Len))
2517 if (!Alignment || Alignment >= 4) {
2523 assert (Len == 1 && "Expected a length of 1!");
2527 // Bound based on alignment.
2528 if (Len >= 2 && Alignment == 2)
2537 RV = ARMEmitLoad(VT, ResultReg, Src);
2538 assert (RV == true && "Should be able to handle this load.");
2539 RV = ARMEmitStore(VT, ResultReg, Dest);
2540 assert (RV == true && "Should be able to handle this store.");
2543 unsigned Size = VT.getSizeInBits()/8;
2545 Dest.Offset += Size;
2552 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2553 // FIXME: Handle more intrinsics.
2554 switch (I.getIntrinsicID()) {
2555 default: return false;
2556 case Intrinsic::frameaddress: {
2557 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2558 MFI->setFrameAddressIsTaken(true);
2561 const TargetRegisterClass *RC;
2563 LdrOpc = ARM::t2LDRi12;
2564 RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2566 LdrOpc = ARM::LDRi12;
2567 RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2570 const ARMBaseRegisterInfo *RegInfo =
2571 static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
2572 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2573 unsigned SrcReg = FramePtr;
2575 // Recursively load frame address
2581 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2583 DestReg = createResultReg(RC);
2584 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2585 TII.get(LdrOpc), DestReg)
2586 .addReg(SrcReg).addImm(0));
2589 UpdateValueMap(&I, SrcReg);
2592 case Intrinsic::memcpy:
2593 case Intrinsic::memmove: {
2594 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2595 // Don't handle volatile.
2596 if (MTI.isVolatile())
2599 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2600 // we would emit dead code because we don't currently handle memmoves.
2601 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2602 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2603 // Small memcpy's are common enough that we want to do them without a call
2605 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2606 if (ARMIsMemCpySmall(Len)) {
2608 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2609 !ARMComputeAddress(MTI.getRawSource(), Src))
2611 unsigned Alignment = MTI.getAlignment();
2612 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2617 if (!MTI.getLength()->getType()->isIntegerTy(32))
2620 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2623 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2624 return SelectCall(&I, IntrMemName);
2626 case Intrinsic::memset: {
2627 const MemSetInst &MSI = cast<MemSetInst>(I);
2628 // Don't handle volatile.
2629 if (MSI.isVolatile())
2632 if (!MSI.getLength()->getType()->isIntegerTy(32))
2635 if (MSI.getDestAddressSpace() > 255)
2638 return SelectCall(&I, "memset");
2640 case Intrinsic::trap: {
2641 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(
2642 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2648 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2649 // The high bits for a type smaller than the register size are assumed to be
2651 Value *Op = I->getOperand(0);
2654 SrcVT = TLI.getValueType(Op->getType(), true);
2655 DestVT = TLI.getValueType(I->getType(), true);
2657 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2659 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2662 unsigned SrcReg = getRegForValue(Op);
2663 if (!SrcReg) return false;
2665 // Because the high bits are undefined, a truncate doesn't generate
2667 UpdateValueMap(I, SrcReg);
2671 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2673 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2675 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2678 // Table of which combinations can be emitted as a single instruction,
2679 // and which will require two.
2680 static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2682 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2683 // ext: s z s z s z s z
2684 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2685 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2686 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2689 // Target registers for:
2690 // - For ARM can never be PC.
2691 // - For 16-bit Thumb are restricted to lower 8 registers.
2692 // - For 32-bit Thumb are restricted to non-SP and non-PC.
2693 static const TargetRegisterClass *RCTbl[2][2] = {
2694 // Instructions: Two Single
2695 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2696 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2699 // Table governing the instruction(s) to be emitted.
2700 static const struct InstructionTable {
2702 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2703 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2704 uint32_t Imm : 8; // All instructions have either a shift or a mask.
2705 } IT[2][2][3][2] = {
2706 { // Two instructions (first is left shift, second is in this table).
2707 { // ARM Opc S Shift Imm
2708 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2709 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2710 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2711 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2712 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2713 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2715 { // Thumb Opc S Shift Imm
2716 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2717 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2718 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2719 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2720 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2721 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2724 { // Single instruction.
2725 { // ARM Opc S Shift Imm
2726 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2727 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2728 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2729 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2730 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2731 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2733 { // Thumb Opc S Shift Imm
2734 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2735 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2736 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2737 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2738 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2739 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2744 unsigned SrcBits = SrcVT.getSizeInBits();
2745 unsigned DestBits = DestVT.getSizeInBits();
2747 assert((SrcBits < DestBits) && "can only extend to larger types");
2748 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2749 "other sizes unimplemented");
2750 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2751 "other sizes unimplemented");
2753 bool hasV6Ops = Subtarget->hasV6Ops();
2754 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2755 assert((Bitness < 3) && "sanity-check table bounds");
2757 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2758 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2759 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2760 unsigned Opc = ITP->Opc;
2761 assert(ARM::KILL != Opc && "Invalid table entry");
2762 unsigned hasS = ITP->hasS;
2763 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2764 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2765 "only MOVsi has shift operand addressing mode");
2766 unsigned Imm = ITP->Imm;
2768 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2769 bool setsCPSR = &ARM::tGPRRegClass == RC;
2770 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2772 // MOVsi encodes shift and immediate in shift operand addressing mode.
2773 // The following condition has the same value when emitting two
2774 // instruction sequences: both are shifts.
2775 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2777 // Either one or two instructions are emitted.
2778 // They're always of the form:
2780 // CPSR is set only by 16-bit Thumb instructions.
2781 // Predicate, if any, is AL.
2782 // S bit, if available, is always 0.
2783 // When two are emitted the first's result will feed as the second's input,
2784 // that value is then dead.
2785 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2786 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2787 ResultReg = createResultReg(RC);
2788 bool isLsl = (0 == Instr) && !isSingleInstr;
2789 unsigned Opcode = isLsl ? LSLOpc : Opc;
2790 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2791 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2792 bool isKill = 1 == Instr;
2793 MachineInstrBuilder MIB = BuildMI(
2794 *FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opcode), ResultReg);
2796 MIB.addReg(ARM::CPSR, RegState::Define);
2797 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2798 AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
2801 // Second instruction consumes the first's result.
2808 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2809 // On ARM, in general, integer casts don't involve legal types; this code
2810 // handles promotable integers.
2811 Type *DestTy = I->getType();
2812 Value *Src = I->getOperand(0);
2813 Type *SrcTy = Src->getType();
2815 bool isZExt = isa<ZExtInst>(I);
2816 unsigned SrcReg = getRegForValue(Src);
2817 if (!SrcReg) return false;
2819 EVT SrcEVT, DestEVT;
2820 SrcEVT = TLI.getValueType(SrcTy, true);
2821 DestEVT = TLI.getValueType(DestTy, true);
2822 if (!SrcEVT.isSimple()) return false;
2823 if (!DestEVT.isSimple()) return false;
2825 MVT SrcVT = SrcEVT.getSimpleVT();
2826 MVT DestVT = DestEVT.getSimpleVT();
2827 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2828 if (ResultReg == 0) return false;
2829 UpdateValueMap(I, ResultReg);
2833 bool ARMFastISel::SelectShift(const Instruction *I,
2834 ARM_AM::ShiftOpc ShiftTy) {
2835 // We handle thumb2 mode by target independent selector
2836 // or SelectionDAG ISel.
2840 // Only handle i32 now.
2841 EVT DestVT = TLI.getValueType(I->getType(), true);
2842 if (DestVT != MVT::i32)
2845 unsigned Opc = ARM::MOVsr;
2847 Value *Src2Value = I->getOperand(1);
2848 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2849 ShiftImm = CI->getZExtValue();
2851 // Fall back to selection DAG isel if the shift amount
2852 // is zero or greater than the width of the value type.
2853 if (ShiftImm == 0 || ShiftImm >=32)
2859 Value *Src1Value = I->getOperand(0);
2860 unsigned Reg1 = getRegForValue(Src1Value);
2861 if (Reg1 == 0) return false;
2864 if (Opc == ARM::MOVsr) {
2865 Reg2 = getRegForValue(Src2Value);
2866 if (Reg2 == 0) return false;
2869 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2870 if(ResultReg == 0) return false;
2872 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2873 TII.get(Opc), ResultReg)
2876 if (Opc == ARM::MOVsi)
2877 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2878 else if (Opc == ARM::MOVsr) {
2880 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2883 AddOptionalDefs(MIB);
2884 UpdateValueMap(I, ResultReg);
2888 // TODO: SoftFP support.
2889 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2891 switch (I->getOpcode()) {
2892 case Instruction::Load:
2893 return SelectLoad(I);
2894 case Instruction::Store:
2895 return SelectStore(I);
2896 case Instruction::Br:
2897 return SelectBranch(I);
2898 case Instruction::IndirectBr:
2899 return SelectIndirectBr(I);
2900 case Instruction::ICmp:
2901 case Instruction::FCmp:
2902 return SelectCmp(I);
2903 case Instruction::FPExt:
2904 return SelectFPExt(I);
2905 case Instruction::FPTrunc:
2906 return SelectFPTrunc(I);
2907 case Instruction::SIToFP:
2908 return SelectIToFP(I, /*isSigned*/ true);
2909 case Instruction::UIToFP:
2910 return SelectIToFP(I, /*isSigned*/ false);
2911 case Instruction::FPToSI:
2912 return SelectFPToI(I, /*isSigned*/ true);
2913 case Instruction::FPToUI:
2914 return SelectFPToI(I, /*isSigned*/ false);
2915 case Instruction::Add:
2916 return SelectBinaryIntOp(I, ISD::ADD);
2917 case Instruction::Or:
2918 return SelectBinaryIntOp(I, ISD::OR);
2919 case Instruction::Sub:
2920 return SelectBinaryIntOp(I, ISD::SUB);
2921 case Instruction::FAdd:
2922 return SelectBinaryFPOp(I, ISD::FADD);
2923 case Instruction::FSub:
2924 return SelectBinaryFPOp(I, ISD::FSUB);
2925 case Instruction::FMul:
2926 return SelectBinaryFPOp(I, ISD::FMUL);
2927 case Instruction::SDiv:
2928 return SelectDiv(I, /*isSigned*/ true);
2929 case Instruction::UDiv:
2930 return SelectDiv(I, /*isSigned*/ false);
2931 case Instruction::SRem:
2932 return SelectRem(I, /*isSigned*/ true);
2933 case Instruction::URem:
2934 return SelectRem(I, /*isSigned*/ false);
2935 case Instruction::Call:
2936 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2937 return SelectIntrinsicCall(*II);
2938 return SelectCall(I);
2939 case Instruction::Select:
2940 return SelectSelect(I);
2941 case Instruction::Ret:
2942 return SelectRet(I);
2943 case Instruction::Trunc:
2944 return SelectTrunc(I);
2945 case Instruction::ZExt:
2946 case Instruction::SExt:
2947 return SelectIntExt(I);
2948 case Instruction::Shl:
2949 return SelectShift(I, ARM_AM::lsl);
2950 case Instruction::LShr:
2951 return SelectShift(I, ARM_AM::lsr);
2952 case Instruction::AShr:
2953 return SelectShift(I, ARM_AM::asr);
2960 // This table describes sign- and zero-extend instructions which can be
2961 // folded into a preceding load. All of these extends have an immediate
2962 // (sometimes a mask and sometimes a shift) that's applied after
2964 const struct FoldableLoadExtendsStruct {
2965 uint16_t Opc[2]; // ARM, Thumb.
2966 uint8_t ExpectedImm;
2968 uint8_t ExpectedVT : 7;
2969 } FoldableLoadExtends[] = {
2970 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2971 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2972 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2973 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2974 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2978 /// \brief The specified machine instr operand is a vreg, and that
2979 /// vreg is being provided by the specified load instruction. If possible,
2980 /// try to fold the load as an operand to the instruction, returning true if
2982 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2983 const LoadInst *LI) {
2984 // Verify we have a legal type before going any further.
2986 if (!isLoadTypeLegal(LI->getType(), VT))
2989 // Combine load followed by zero- or sign-extend.
2990 // ldrb r1, [r0] ldrb r1, [r0]
2992 // mov r3, r2 mov r3, r1
2993 if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2995 const uint64_t Imm = MI->getOperand(2).getImm();
2999 for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends);
3001 if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&
3002 (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm &&
3003 MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) {
3005 isZExt = FoldableLoadExtends[i].isZExt;
3008 if (!Found) return false;
3010 // See if we can handle this address.
3012 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
3014 unsigned ResultReg = MI->getOperand(0).getReg();
3015 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
3017 MI->eraseFromParent();
3021 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
3022 unsigned Align, MVT VT) {
3023 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
3024 ARMConstantPoolConstant *CPV =
3025 ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
3026 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
3029 unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
3032 DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0);
3033 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
3034 TII.get(ARM::t2LDRpci), DestReg1)
3035 .addConstantPoolIndex(Idx));
3036 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
3038 // The extra immediate is for addrmode2.
3039 DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0);
3040 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
3041 DL, TII.get(ARM::LDRcp), DestReg1)
3042 .addConstantPoolIndex(Idx).addImm(0));
3043 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
3046 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
3047 if (GlobalBaseReg == 0) {
3048 GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
3049 AFI->setGlobalBaseReg(GlobalBaseReg);
3052 unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
3053 DestReg2 = constrainOperandRegClass(TII.get(Opc), DestReg2, 0);
3054 DestReg1 = constrainOperandRegClass(TII.get(Opc), DestReg1, 1);
3055 GlobalBaseReg = constrainOperandRegClass(TII.get(Opc), GlobalBaseReg, 2);
3056 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
3057 DL, TII.get(Opc), DestReg2)
3059 .addReg(GlobalBaseReg);
3062 AddOptionalDefs(MIB);
3067 bool ARMFastISel::FastLowerArguments() {
3068 if (!FuncInfo.CanLowerReturn)
3071 const Function *F = FuncInfo.Fn;
3075 CallingConv::ID CC = F->getCallingConv();
3079 case CallingConv::Fast:
3080 case CallingConv::C:
3081 case CallingConv::ARM_AAPCS_VFP:
3082 case CallingConv::ARM_AAPCS:
3083 case CallingConv::ARM_APCS:
3087 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3088 // which are passed in r0 - r3.
3090 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3091 I != E; ++I, ++Idx) {
3095 if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
3096 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
3097 F->getAttributes().hasAttribute(Idx, Attribute::ByVal))
3100 Type *ArgTy = I->getType();
3101 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3104 EVT ArgVT = TLI.getValueType(ArgTy);
3105 if (!ArgVT.isSimple()) return false;
3106 switch (ArgVT.getSimpleVT().SimpleTy) {
3117 static const uint16_t GPRArgRegs[] = {
3118 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3121 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3123 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3124 I != E; ++I, ++Idx) {
3125 unsigned SrcReg = GPRArgRegs[Idx];
3126 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3127 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3128 // Without this, EmitLiveInCopies may eliminate the livein if its only
3129 // use is a bitcast (which isn't turned into an instruction).
3130 unsigned ResultReg = createResultReg(RC);
3131 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
3132 ResultReg).addReg(DstReg, getKillRegState(true));
3133 UpdateValueMap(I, ResultReg);
3140 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3141 const TargetLibraryInfo *libInfo) {
3142 const TargetMachine &TM = funcInfo.MF->getTarget();
3144 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
3145 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
3146 bool UseFastISel = false;
3147 UseFastISel |= Subtarget->isTargetMachO() && !Subtarget->isThumb1Only();
3148 UseFastISel |= Subtarget->isTargetLinux() && !Subtarget->isThumb();
3149 UseFastISel |= Subtarget->isTargetNaCl() && !Subtarget->isThumb();
3152 // iOS always has a FP for backtracking, force other targets
3153 // to keep their FP when doing FastISel. The emitted code is
3154 // currently superior, and in cases like test-suite's lencod
3155 // FastISel isn't quite correct when FP is eliminated.
3156 TM.Options.NoFramePointerElim = true;
3157 return new ARMFastISel(funcInfo, libInfo);