1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/DataLayout.h"
34 #include "llvm/DerivedTypes.h"
35 #include "llvm/GlobalVariable.h"
36 #include "llvm/Instructions.h"
37 #include "llvm/IntrinsicInst.h"
38 #include "llvm/Module.h"
39 #include "llvm/Operator.h"
40 #include "llvm/Support/CallSite.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/GetElementPtrTypeIterator.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
50 extern cl::opt<bool> EnableARMLongCalls;
54 // All possible address modes, plus some.
55 typedef struct Address {
68 // Innocuous defaults for our address.
70 : BaseType(RegBase), Offset(0) {
75 class ARMFastISel : public FastISel {
77 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
78 /// make the right decision when generating code for different targets.
79 const ARMSubtarget *Subtarget;
80 const TargetMachine &TM;
81 const TargetInstrInfo &TII;
82 const TargetLowering &TLI;
85 // Convenience variables to avoid some queries.
90 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
91 const TargetLibraryInfo *libInfo)
92 : FastISel(funcInfo, libInfo),
93 TM(funcInfo.MF->getTarget()),
94 TII(*TM.getInstrInfo()),
95 TLI(*TM.getTargetLowering()) {
96 Subtarget = &TM.getSubtarget<ARMSubtarget>();
97 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
98 isThumb2 = AFI->isThumbFunction();
99 Context = &funcInfo.Fn->getContext();
102 // Code from FastISel.cpp.
104 unsigned FastEmitInst_(unsigned MachineInstOpcode,
105 const TargetRegisterClass *RC);
106 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
107 const TargetRegisterClass *RC,
108 unsigned Op0, bool Op0IsKill);
109 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
110 const TargetRegisterClass *RC,
111 unsigned Op0, bool Op0IsKill,
112 unsigned Op1, bool Op1IsKill);
113 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
114 const TargetRegisterClass *RC,
115 unsigned Op0, bool Op0IsKill,
116 unsigned Op1, bool Op1IsKill,
117 unsigned Op2, bool Op2IsKill);
118 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill,
122 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
123 const TargetRegisterClass *RC,
124 unsigned Op0, bool Op0IsKill,
125 const ConstantFP *FPImm);
126 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
127 const TargetRegisterClass *RC,
128 unsigned Op0, bool Op0IsKill,
129 unsigned Op1, bool Op1IsKill,
131 unsigned FastEmitInst_i(unsigned MachineInstOpcode,
132 const TargetRegisterClass *RC,
134 unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
135 const TargetRegisterClass *RC,
136 uint64_t Imm1, uint64_t Imm2);
138 unsigned FastEmitInst_extractsubreg(MVT RetVT,
139 unsigned Op0, bool Op0IsKill,
142 // Backend specific FastISel code.
144 virtual bool TargetSelectInstruction(const Instruction *I);
145 virtual unsigned TargetMaterializeConstant(const Constant *C);
146 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
147 virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
150 #include "ARMGenFastISel.inc"
152 // Instruction selection routines.
154 bool SelectLoad(const Instruction *I);
155 bool SelectStore(const Instruction *I);
156 bool SelectBranch(const Instruction *I);
157 bool SelectIndirectBr(const Instruction *I);
158 bool SelectCmp(const Instruction *I);
159 bool SelectFPExt(const Instruction *I);
160 bool SelectFPTrunc(const Instruction *I);
161 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
162 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
163 bool SelectIToFP(const Instruction *I, bool isSigned);
164 bool SelectFPToI(const Instruction *I, bool isSigned);
165 bool SelectDiv(const Instruction *I, bool isSigned);
166 bool SelectRem(const Instruction *I, bool isSigned);
167 bool SelectCall(const Instruction *I, const char *IntrMemName);
168 bool SelectIntrinsicCall(const IntrinsicInst &I);
169 bool SelectSelect(const Instruction *I);
170 bool SelectRet(const Instruction *I);
171 bool SelectTrunc(const Instruction *I);
172 bool SelectIntExt(const Instruction *I);
173 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
177 bool isTypeLegal(Type *Ty, MVT &VT);
178 bool isLoadTypeLegal(Type *Ty, MVT &VT);
179 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
181 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
182 unsigned Alignment = 0, bool isZExt = true,
183 bool allocReg = true);
184 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
185 unsigned Alignment = 0);
186 bool ARMComputeAddress(const Value *Obj, Address &Addr);
187 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
188 bool ARMIsMemCpySmall(uint64_t Len);
189 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
191 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
192 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
193 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
194 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
195 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
196 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
197 unsigned ARMSelectCallOp(bool UseReg);
198 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
200 // Call handling routines.
202 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
205 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
206 SmallVectorImpl<unsigned> &ArgRegs,
207 SmallVectorImpl<MVT> &ArgVTs,
208 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
209 SmallVectorImpl<unsigned> &RegArgs,
213 unsigned getLibcallReg(const Twine &Name);
214 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
215 const Instruction *I, CallingConv::ID CC,
216 unsigned &NumBytes, bool isVarArg);
217 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
219 // OptionalDef handling routines.
221 bool isARMNEONPred(const MachineInstr *MI);
222 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
223 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
224 void AddLoadStoreOperands(MVT VT, Address &Addr,
225 const MachineInstrBuilder &MIB,
226 unsigned Flags, bool useAM3);
229 } // end anonymous namespace
231 #include "ARMGenCallingConv.inc"
233 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
234 // we don't care about implicit defs here, just places we'll need to add a
235 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
236 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
237 if (!MI->hasOptionalDef())
240 // Look to see if our OptionalDef is defining CPSR or CCR.
241 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
242 const MachineOperand &MO = MI->getOperand(i);
243 if (!MO.isReg() || !MO.isDef()) continue;
244 if (MO.getReg() == ARM::CPSR)
250 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
251 const MCInstrDesc &MCID = MI->getDesc();
253 // If we're a thumb2 or not NEON function we were handled via isPredicable.
254 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
255 AFI->isThumb2Function())
258 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
259 if (MCID.OpInfo[i].isPredicate())
265 // If the machine is predicable go ahead and add the predicate operands, if
266 // it needs default CC operands add those.
267 // TODO: If we want to support thumb1 then we'll need to deal with optional
268 // CPSR defs that need to be added before the remaining operands. See s_cc_out
269 // for descriptions why.
270 const MachineInstrBuilder &
271 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
272 MachineInstr *MI = &*MIB;
274 // Do we use a predicate? or...
275 // Are we NEON in ARM mode and have a predicate operand? If so, I know
276 // we're not predicable but add it anyways.
277 if (TII.isPredicable(MI) || isARMNEONPred(MI))
280 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
281 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
283 if (DefinesOptionalPredicate(MI, &CPSR)) {
292 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
293 const TargetRegisterClass* RC) {
294 unsigned ResultReg = createResultReg(RC);
295 const MCInstrDesc &II = TII.get(MachineInstOpcode);
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
301 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
302 const TargetRegisterClass *RC,
303 unsigned Op0, bool Op0IsKill) {
304 unsigned ResultReg = createResultReg(RC);
305 const MCInstrDesc &II = TII.get(MachineInstOpcode);
307 if (II.getNumDefs() >= 1) {
308 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
309 .addReg(Op0, Op0IsKill * RegState::Kill));
311 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
312 .addReg(Op0, Op0IsKill * RegState::Kill));
313 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
314 TII.get(TargetOpcode::COPY), ResultReg)
315 .addReg(II.ImplicitDefs[0]));
320 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
321 const TargetRegisterClass *RC,
322 unsigned Op0, bool Op0IsKill,
323 unsigned Op1, bool Op1IsKill) {
324 unsigned ResultReg = createResultReg(RC);
325 const MCInstrDesc &II = TII.get(MachineInstOpcode);
327 if (II.getNumDefs() >= 1) {
328 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
329 .addReg(Op0, Op0IsKill * RegState::Kill)
330 .addReg(Op1, Op1IsKill * RegState::Kill));
332 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
333 .addReg(Op0, Op0IsKill * RegState::Kill)
334 .addReg(Op1, Op1IsKill * RegState::Kill));
335 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
336 TII.get(TargetOpcode::COPY), ResultReg)
337 .addReg(II.ImplicitDefs[0]));
342 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
343 const TargetRegisterClass *RC,
344 unsigned Op0, bool Op0IsKill,
345 unsigned Op1, bool Op1IsKill,
346 unsigned Op2, bool Op2IsKill) {
347 unsigned ResultReg = createResultReg(RC);
348 const MCInstrDesc &II = TII.get(MachineInstOpcode);
350 if (II.getNumDefs() >= 1) {
351 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
352 .addReg(Op0, Op0IsKill * RegState::Kill)
353 .addReg(Op1, Op1IsKill * RegState::Kill)
354 .addReg(Op2, Op2IsKill * RegState::Kill));
356 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
357 .addReg(Op0, Op0IsKill * RegState::Kill)
358 .addReg(Op1, Op1IsKill * RegState::Kill)
359 .addReg(Op2, Op2IsKill * RegState::Kill));
360 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
361 TII.get(TargetOpcode::COPY), ResultReg)
362 .addReg(II.ImplicitDefs[0]));
367 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
368 const TargetRegisterClass *RC,
369 unsigned Op0, bool Op0IsKill,
371 unsigned ResultReg = createResultReg(RC);
372 const MCInstrDesc &II = TII.get(MachineInstOpcode);
374 if (II.getNumDefs() >= 1) {
375 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
376 .addReg(Op0, Op0IsKill * RegState::Kill)
379 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
380 .addReg(Op0, Op0IsKill * RegState::Kill)
382 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
383 TII.get(TargetOpcode::COPY), ResultReg)
384 .addReg(II.ImplicitDefs[0]));
389 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
390 const TargetRegisterClass *RC,
391 unsigned Op0, bool Op0IsKill,
392 const ConstantFP *FPImm) {
393 unsigned ResultReg = createResultReg(RC);
394 const MCInstrDesc &II = TII.get(MachineInstOpcode);
396 if (II.getNumDefs() >= 1) {
397 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
398 .addReg(Op0, Op0IsKill * RegState::Kill)
401 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
402 .addReg(Op0, Op0IsKill * RegState::Kill)
404 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
405 TII.get(TargetOpcode::COPY), ResultReg)
406 .addReg(II.ImplicitDefs[0]));
411 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
412 const TargetRegisterClass *RC,
413 unsigned Op0, bool Op0IsKill,
414 unsigned Op1, bool Op1IsKill,
416 unsigned ResultReg = createResultReg(RC);
417 const MCInstrDesc &II = TII.get(MachineInstOpcode);
419 if (II.getNumDefs() >= 1) {
420 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
421 .addReg(Op0, Op0IsKill * RegState::Kill)
422 .addReg(Op1, Op1IsKill * RegState::Kill)
425 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
426 .addReg(Op0, Op0IsKill * RegState::Kill)
427 .addReg(Op1, Op1IsKill * RegState::Kill)
429 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
430 TII.get(TargetOpcode::COPY), ResultReg)
431 .addReg(II.ImplicitDefs[0]));
436 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
437 const TargetRegisterClass *RC,
439 unsigned ResultReg = createResultReg(RC);
440 const MCInstrDesc &II = TII.get(MachineInstOpcode);
442 if (II.getNumDefs() >= 1) {
443 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
446 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
449 TII.get(TargetOpcode::COPY), ResultReg)
450 .addReg(II.ImplicitDefs[0]));
455 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
456 const TargetRegisterClass *RC,
457 uint64_t Imm1, uint64_t Imm2) {
458 unsigned ResultReg = createResultReg(RC);
459 const MCInstrDesc &II = TII.get(MachineInstOpcode);
461 if (II.getNumDefs() >= 1) {
462 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
463 .addImm(Imm1).addImm(Imm2));
465 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
466 .addImm(Imm1).addImm(Imm2));
467 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
468 TII.get(TargetOpcode::COPY),
470 .addReg(II.ImplicitDefs[0]));
475 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
476 unsigned Op0, bool Op0IsKill,
478 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
479 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
480 "Cannot yet extract from physregs");
482 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
483 DL, TII.get(TargetOpcode::COPY), ResultReg)
484 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
488 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
489 // checks from the various callers.
490 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
491 if (VT == MVT::f64) return 0;
493 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
494 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
495 TII.get(ARM::VMOVSR), MoveReg)
500 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
501 if (VT == MVT::i64) return 0;
503 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
504 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
505 TII.get(ARM::VMOVRS), MoveReg)
510 // For double width floating point we need to materialize two constants
511 // (the high and the low) into integer registers then use a move to get
512 // the combined constant into an FP reg.
513 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
514 const APFloat Val = CFP->getValueAPF();
515 bool is64bit = VT == MVT::f64;
517 // This checks to see if we can use VFP3 instructions to materialize
518 // a constant, otherwise we have to go through the constant pool.
519 if (TLI.isFPImmLegal(Val, VT)) {
523 Imm = ARM_AM::getFP64Imm(Val);
526 Imm = ARM_AM::getFP32Imm(Val);
529 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
530 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
536 // Require VFP2 for loading fp constants.
537 if (!Subtarget->hasVFP2()) return false;
539 // MachineConstantPool wants an explicit alignment.
540 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
542 // TODO: Figure out if this is correct.
543 Align = TD.getTypeAllocSize(CFP->getType());
545 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
546 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
547 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
549 // The extra reg is for addrmode5.
550 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
552 .addConstantPoolIndex(Idx)
557 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
559 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
562 // If we can do this in a single instruction without a constant pool entry
564 const ConstantInt *CI = cast<ConstantInt>(C);
565 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
566 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
567 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
569 unsigned ImmReg = createResultReg(RC);
570 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
571 TII.get(Opc), ImmReg)
572 .addImm(CI->getZExtValue()));
576 // Use MVN to emit negative constants.
577 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
578 unsigned Imm = (unsigned)~(CI->getSExtValue());
579 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
580 (ARM_AM::getSOImmVal(Imm) != -1);
582 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
583 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
584 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
585 TII.get(Opc), ImmReg)
591 // Load from constant pool. For now 32-bit only.
595 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
597 // MachineConstantPool wants an explicit alignment.
598 unsigned Align = TD.getPrefTypeAlignment(C->getType());
600 // TODO: Figure out if this is correct.
601 Align = TD.getTypeAllocSize(C->getType());
603 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
606 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
607 TII.get(ARM::t2LDRpci), DestReg)
608 .addConstantPoolIndex(Idx));
610 // The extra immediate is for addrmode2.
611 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
612 TII.get(ARM::LDRcp), DestReg)
613 .addConstantPoolIndex(Idx)
619 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
620 // For now 32-bit only.
621 if (VT != MVT::i32) return 0;
623 Reloc::Model RelocM = TM.getRelocationModel();
624 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
625 const TargetRegisterClass *RC = isThumb2 ?
626 (const TargetRegisterClass*)&ARM::rGPRRegClass :
627 (const TargetRegisterClass*)&ARM::GPRRegClass;
628 unsigned DestReg = createResultReg(RC);
630 // Use movw+movt when possible, it avoids constant pool entries.
631 // Darwin targets don't support movt with Reloc::Static, see
632 // ARMTargetLowering::LowerGlobalAddressDarwin. Other targets only support
633 // static movt relocations.
634 if (Subtarget->useMovt() &&
635 Subtarget->isTargetDarwin() == (RelocM != Reloc::Static)) {
639 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
641 case Reloc::DynamicNoPIC:
642 Opc = isThumb2 ? ARM::t2MOV_ga_dyn : ARM::MOV_ga_dyn;
645 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
648 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
649 DestReg).addGlobalAddress(GV));
651 // MachineConstantPool wants an explicit alignment.
652 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
654 // TODO: Figure out if this is correct.
655 Align = TD.getTypeAllocSize(GV->getType());
658 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
659 return ARMLowerPICELF(GV, Align, VT);
662 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
663 (Subtarget->isThumb() ? 4 : 8);
664 unsigned Id = AFI->createPICLabelUId();
665 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
668 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
671 MachineInstrBuilder MIB;
673 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
674 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
675 .addConstantPoolIndex(Idx);
676 if (RelocM == Reloc::PIC_)
678 AddOptionalDefs(MIB);
680 // The extra immediate is for addrmode2.
681 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
683 .addConstantPoolIndex(Idx)
685 AddOptionalDefs(MIB);
687 if (RelocM == Reloc::PIC_) {
688 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
689 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
691 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
692 DL, TII.get(Opc), NewDestReg)
695 AddOptionalDefs(MIB);
702 MachineInstrBuilder MIB;
703 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
705 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
706 TII.get(ARM::t2LDRi12), NewDestReg)
710 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
714 DestReg = NewDestReg;
715 AddOptionalDefs(MIB);
721 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
722 EVT CEVT = TLI.getValueType(C->getType(), true);
724 // Only handle simple types.
725 if (!CEVT.isSimple()) return 0;
726 MVT VT = CEVT.getSimpleVT();
728 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
729 return ARMMaterializeFP(CFP, VT);
730 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
731 return ARMMaterializeGV(GV, VT);
732 else if (isa<ConstantInt>(C))
733 return ARMMaterializeInt(C, VT);
738 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
740 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
741 // Don't handle dynamic allocas.
742 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
745 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
747 DenseMap<const AllocaInst*, int>::iterator SI =
748 FuncInfo.StaticAllocaMap.find(AI);
750 // This will get lowered later into the correct offsets and registers
751 // via rewriteXFrameIndex.
752 if (SI != FuncInfo.StaticAllocaMap.end()) {
753 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
754 unsigned ResultReg = createResultReg(RC);
755 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
756 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
757 TII.get(Opc), ResultReg)
758 .addFrameIndex(SI->second)
766 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
767 EVT evt = TLI.getValueType(Ty, true);
769 // Only handle simple types.
770 if (evt == MVT::Other || !evt.isSimple()) return false;
771 VT = evt.getSimpleVT();
773 // Handle all legal types, i.e. a register that will directly hold this
775 return TLI.isTypeLegal(VT);
778 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
779 if (isTypeLegal(Ty, VT)) return true;
781 // If this is a type than can be sign or zero-extended to a basic operation
782 // go ahead and accept it now.
783 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
789 // Computes the address to get to an object.
790 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
791 // Some boilerplate from the X86 FastISel.
792 const User *U = NULL;
793 unsigned Opcode = Instruction::UserOp1;
794 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
795 // Don't walk into other basic blocks unless the object is an alloca from
796 // another block, otherwise it may not have a virtual register assigned.
797 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
798 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
799 Opcode = I->getOpcode();
802 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
803 Opcode = C->getOpcode();
807 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
808 if (Ty->getAddressSpace() > 255)
809 // Fast instruction selection doesn't support the special
816 case Instruction::BitCast: {
817 // Look through bitcasts.
818 return ARMComputeAddress(U->getOperand(0), Addr);
820 case Instruction::IntToPtr: {
821 // Look past no-op inttoptrs.
822 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
823 return ARMComputeAddress(U->getOperand(0), Addr);
826 case Instruction::PtrToInt: {
827 // Look past no-op ptrtoints.
828 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
829 return ARMComputeAddress(U->getOperand(0), Addr);
832 case Instruction::GetElementPtr: {
833 Address SavedAddr = Addr;
834 int TmpOffset = Addr.Offset;
836 // Iterate through the GEP folding the constants into offsets where
838 gep_type_iterator GTI = gep_type_begin(U);
839 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
840 i != e; ++i, ++GTI) {
841 const Value *Op = *i;
842 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
843 const StructLayout *SL = TD.getStructLayout(STy);
844 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
845 TmpOffset += SL->getElementOffset(Idx);
847 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
849 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
850 // Constant-offset addressing.
851 TmpOffset += CI->getSExtValue() * S;
854 if (isa<AddOperator>(Op) &&
855 (!isa<Instruction>(Op) ||
856 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
858 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
859 // An add (in the same block) with a constant operand. Fold the
862 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
863 TmpOffset += CI->getSExtValue() * S;
864 // Iterate on the other operand.
865 Op = cast<AddOperator>(Op)->getOperand(0);
869 goto unsupported_gep;
874 // Try to grab the base operand now.
875 Addr.Offset = TmpOffset;
876 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
878 // We failed, restore everything and try the other options.
884 case Instruction::Alloca: {
885 const AllocaInst *AI = cast<AllocaInst>(Obj);
886 DenseMap<const AllocaInst*, int>::iterator SI =
887 FuncInfo.StaticAllocaMap.find(AI);
888 if (SI != FuncInfo.StaticAllocaMap.end()) {
889 Addr.BaseType = Address::FrameIndexBase;
890 Addr.Base.FI = SI->second;
897 // Try to get this in a register if nothing else has worked.
898 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
899 return Addr.Base.Reg != 0;
902 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
903 bool needsLowering = false;
904 switch (VT.SimpleTy) {
905 default: llvm_unreachable("Unhandled load/store type!");
911 // Integer loads/stores handle 12-bit offsets.
912 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
913 // Handle negative offsets.
914 if (needsLowering && isThumb2)
915 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
918 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
919 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
924 // Floating point operands handle 8-bit offsets.
925 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
929 // If this is a stack pointer and the offset needs to be simplified then
930 // put the alloca address into a register, set the base type back to
931 // register and continue. This should almost never happen.
932 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
933 const TargetRegisterClass *RC = isThumb2 ?
934 (const TargetRegisterClass*)&ARM::tGPRRegClass :
935 (const TargetRegisterClass*)&ARM::GPRRegClass;
936 unsigned ResultReg = createResultReg(RC);
937 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
938 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
939 TII.get(Opc), ResultReg)
940 .addFrameIndex(Addr.Base.FI)
942 Addr.Base.Reg = ResultReg;
943 Addr.BaseType = Address::RegBase;
946 // Since the offset is too large for the load/store instruction
947 // get the reg+offset into a register.
949 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
950 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
955 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
956 const MachineInstrBuilder &MIB,
957 unsigned Flags, bool useAM3) {
958 // addrmode5 output depends on the selection dag addressing dividing the
959 // offset by 4 that it then later multiplies. Do this here as well.
960 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
963 // Frame base works a bit differently. Handle it separately.
964 if (Addr.BaseType == Address::FrameIndexBase) {
965 int FI = Addr.Base.FI;
966 int Offset = Addr.Offset;
967 MachineMemOperand *MMO =
968 FuncInfo.MF->getMachineMemOperand(
969 MachinePointerInfo::getFixedStack(FI, Offset),
971 MFI.getObjectSize(FI),
972 MFI.getObjectAlignment(FI));
973 // Now add the rest of the operands.
974 MIB.addFrameIndex(FI);
976 // ARM halfword load/stores and signed byte loads need an additional
979 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
983 MIB.addImm(Addr.Offset);
985 MIB.addMemOperand(MMO);
987 // Now add the rest of the operands.
988 MIB.addReg(Addr.Base.Reg);
990 // ARM halfword load/stores and signed byte loads need an additional
993 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
997 MIB.addImm(Addr.Offset);
1000 AddOptionalDefs(MIB);
1003 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
1004 unsigned Alignment, bool isZExt, bool allocReg) {
1006 bool useAM3 = false;
1007 bool needVMOV = false;
1008 const TargetRegisterClass *RC;
1009 switch (VT.SimpleTy) {
1010 // This is mostly going to be Neon/vector support.
1011 default: return false;
1015 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1016 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
1018 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
1027 RC = &ARM::GPRRegClass;
1030 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1034 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1035 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
1037 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1039 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1042 RC = &ARM::GPRRegClass;
1045 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1049 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1052 Opc = ARM::t2LDRi12;
1056 RC = &ARM::GPRRegClass;
1059 if (!Subtarget->hasVFP2()) return false;
1060 // Unaligned loads need special handling. Floats require word-alignment.
1061 if (Alignment && Alignment < 4) {
1064 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1065 RC = &ARM::GPRRegClass;
1068 RC = TLI.getRegClassFor(VT);
1072 if (!Subtarget->hasVFP2()) return false;
1073 // FIXME: Unaligned loads need special handling. Doublewords require
1075 if (Alignment && Alignment < 4)
1079 RC = TLI.getRegClassFor(VT);
1082 // Simplify this down to something we can handle.
1083 ARMSimplifyAddress(Addr, VT, useAM3);
1085 // Create the base instruction, then add the operands.
1087 ResultReg = createResultReg(RC);
1088 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1089 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1090 TII.get(Opc), ResultReg);
1091 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1093 // If we had an unaligned load of a float we've converted it to an regular
1094 // load. Now we must move from the GRP to the FP register.
1096 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1097 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1098 TII.get(ARM::VMOVSR), MoveReg)
1099 .addReg(ResultReg));
1100 ResultReg = MoveReg;
1105 bool ARMFastISel::SelectLoad(const Instruction *I) {
1106 // Atomic loads need special handling.
1107 if (cast<LoadInst>(I)->isAtomic())
1110 // Verify we have a legal type before going any further.
1112 if (!isLoadTypeLegal(I->getType(), VT))
1115 // See if we can handle this address.
1117 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1120 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1122 UpdateValueMap(I, ResultReg);
1126 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1127 unsigned Alignment) {
1129 bool useAM3 = false;
1130 switch (VT.SimpleTy) {
1131 // This is mostly going to be Neon/vector support.
1132 default: return false;
1134 unsigned Res = createResultReg(isThumb2 ?
1135 (const TargetRegisterClass*)&ARM::tGPRRegClass :
1136 (const TargetRegisterClass*)&ARM::GPRRegClass);
1137 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1138 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1140 .addReg(SrcReg).addImm(1));
1142 } // Fallthrough here.
1145 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1146 StrOpc = ARM::t2STRBi8;
1148 StrOpc = ARM::t2STRBi12;
1150 StrOpc = ARM::STRBi12;
1154 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1158 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1159 StrOpc = ARM::t2STRHi8;
1161 StrOpc = ARM::t2STRHi12;
1168 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1172 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1173 StrOpc = ARM::t2STRi8;
1175 StrOpc = ARM::t2STRi12;
1177 StrOpc = ARM::STRi12;
1181 if (!Subtarget->hasVFP2()) return false;
1182 // Unaligned stores need special handling. Floats require word-alignment.
1183 if (Alignment && Alignment < 4) {
1184 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1185 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1186 TII.get(ARM::VMOVRS), MoveReg)
1190 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1192 StrOpc = ARM::VSTRS;
1196 if (!Subtarget->hasVFP2()) return false;
1197 // FIXME: Unaligned stores need special handling. Doublewords require
1199 if (Alignment && Alignment < 4)
1202 StrOpc = ARM::VSTRD;
1205 // Simplify this down to something we can handle.
1206 ARMSimplifyAddress(Addr, VT, useAM3);
1208 // Create the base instruction, then add the operands.
1209 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1212 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1216 bool ARMFastISel::SelectStore(const Instruction *I) {
1217 Value *Op0 = I->getOperand(0);
1218 unsigned SrcReg = 0;
1220 // Atomic stores need special handling.
1221 if (cast<StoreInst>(I)->isAtomic())
1224 // Verify we have a legal type before going any further.
1226 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1229 // Get the value to be stored into a register.
1230 SrcReg = getRegForValue(Op0);
1231 if (SrcReg == 0) return false;
1233 // See if we can handle this address.
1235 if (!ARMComputeAddress(I->getOperand(1), Addr))
1238 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1243 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1245 // Needs two compares...
1246 case CmpInst::FCMP_ONE:
1247 case CmpInst::FCMP_UEQ:
1249 // AL is our "false" for now. The other two need more compares.
1251 case CmpInst::ICMP_EQ:
1252 case CmpInst::FCMP_OEQ:
1254 case CmpInst::ICMP_SGT:
1255 case CmpInst::FCMP_OGT:
1257 case CmpInst::ICMP_SGE:
1258 case CmpInst::FCMP_OGE:
1260 case CmpInst::ICMP_UGT:
1261 case CmpInst::FCMP_UGT:
1263 case CmpInst::FCMP_OLT:
1265 case CmpInst::ICMP_ULE:
1266 case CmpInst::FCMP_OLE:
1268 case CmpInst::FCMP_ORD:
1270 case CmpInst::FCMP_UNO:
1272 case CmpInst::FCMP_UGE:
1274 case CmpInst::ICMP_SLT:
1275 case CmpInst::FCMP_ULT:
1277 case CmpInst::ICMP_SLE:
1278 case CmpInst::FCMP_ULE:
1280 case CmpInst::FCMP_UNE:
1281 case CmpInst::ICMP_NE:
1283 case CmpInst::ICMP_UGE:
1285 case CmpInst::ICMP_ULT:
1290 bool ARMFastISel::SelectBranch(const Instruction *I) {
1291 const BranchInst *BI = cast<BranchInst>(I);
1292 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1293 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1295 // Simple branch support.
1297 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1299 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1300 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1302 // Get the compare predicate.
1303 // Try to take advantage of fallthrough opportunities.
1304 CmpInst::Predicate Predicate = CI->getPredicate();
1305 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1306 std::swap(TBB, FBB);
1307 Predicate = CmpInst::getInversePredicate(Predicate);
1310 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1312 // We may not handle every CC for now.
1313 if (ARMPred == ARMCC::AL) return false;
1315 // Emit the compare.
1316 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1319 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1320 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1321 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1322 FastEmitBranch(FBB, DL);
1323 FuncInfo.MBB->addSuccessor(TBB);
1326 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1328 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1329 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1330 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1331 unsigned OpReg = getRegForValue(TI->getOperand(0));
1332 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1334 .addReg(OpReg).addImm(1));
1336 unsigned CCMode = ARMCC::NE;
1337 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1338 std::swap(TBB, FBB);
1342 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1343 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1344 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1346 FastEmitBranch(FBB, DL);
1347 FuncInfo.MBB->addSuccessor(TBB);
1350 } else if (const ConstantInt *CI =
1351 dyn_cast<ConstantInt>(BI->getCondition())) {
1352 uint64_t Imm = CI->getZExtValue();
1353 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1354 FastEmitBranch(Target, DL);
1358 unsigned CmpReg = getRegForValue(BI->getCondition());
1359 if (CmpReg == 0) return false;
1361 // We've been divorced from our compare! Our block was split, and
1362 // now our compare lives in a predecessor block. We musn't
1363 // re-compare here, as the children of the compare aren't guaranteed
1364 // live across the block boundary (we *could* check for this).
1365 // Regardless, the compare has been done in the predecessor block,
1366 // and it left a value for us in a virtual register. Ergo, we test
1367 // the one-bit value left in the virtual register.
1368 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1369 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1370 .addReg(CmpReg).addImm(1));
1372 unsigned CCMode = ARMCC::NE;
1373 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1374 std::swap(TBB, FBB);
1378 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1379 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1380 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1381 FastEmitBranch(FBB, DL);
1382 FuncInfo.MBB->addSuccessor(TBB);
1386 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1387 unsigned AddrReg = getRegForValue(I->getOperand(0));
1388 if (AddrReg == 0) return false;
1390 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1391 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
1394 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1395 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1396 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1401 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1403 Type *Ty = Src1Value->getType();
1404 EVT SrcEVT = TLI.getValueType(Ty, true);
1405 if (!SrcEVT.isSimple()) return false;
1406 MVT SrcVT = SrcEVT.getSimpleVT();
1408 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1409 if (isFloat && !Subtarget->hasVFP2())
1412 // Check to see if the 2nd operand is a constant that we can encode directly
1415 bool UseImm = false;
1416 bool isNegativeImm = false;
1417 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1418 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1419 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1420 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1422 const APInt &CIVal = ConstInt->getValue();
1423 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1424 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1425 // then a cmn, because there is no way to represent 2147483648 as a
1426 // signed 32-bit int.
1427 if (Imm < 0 && Imm != (int)0x80000000) {
1428 isNegativeImm = true;
1431 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1432 (ARM_AM::getSOImmVal(Imm) != -1);
1434 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1435 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1436 if (ConstFP->isZero() && !ConstFP->isNegative())
1442 bool needsExt = false;
1443 switch (SrcVT.SimpleTy) {
1444 default: return false;
1445 // TODO: Verify compares.
1448 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1452 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1458 // Intentional fall-through.
1462 CmpOpc = ARM::t2CMPrr;
1464 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1467 CmpOpc = ARM::CMPrr;
1469 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1474 unsigned SrcReg1 = getRegForValue(Src1Value);
1475 if (SrcReg1 == 0) return false;
1477 unsigned SrcReg2 = 0;
1479 SrcReg2 = getRegForValue(Src2Value);
1480 if (SrcReg2 == 0) return false;
1483 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1485 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1486 if (SrcReg1 == 0) return false;
1488 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1489 if (SrcReg2 == 0) return false;
1494 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1496 .addReg(SrcReg1).addReg(SrcReg2));
1498 MachineInstrBuilder MIB;
1499 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1502 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1505 AddOptionalDefs(MIB);
1508 // For floating point we need to move the result to a comparison register
1509 // that we can then use for branches.
1510 if (Ty->isFloatTy() || Ty->isDoubleTy())
1511 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1512 TII.get(ARM::FMSTAT)));
1516 bool ARMFastISel::SelectCmp(const Instruction *I) {
1517 const CmpInst *CI = cast<CmpInst>(I);
1519 // Get the compare predicate.
1520 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1522 // We may not handle every CC for now.
1523 if (ARMPred == ARMCC::AL) return false;
1525 // Emit the compare.
1526 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1529 // Now set a register based on the comparison. Explicitly set the predicates
1531 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1532 const TargetRegisterClass *RC = isThumb2 ?
1533 (const TargetRegisterClass*)&ARM::rGPRRegClass :
1534 (const TargetRegisterClass*)&ARM::GPRRegClass;
1535 unsigned DestReg = createResultReg(RC);
1536 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1537 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1538 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1539 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1540 .addReg(ZeroReg).addImm(1)
1541 .addImm(ARMPred).addReg(ARM::CPSR);
1543 UpdateValueMap(I, DestReg);
1547 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1548 // Make sure we have VFP and that we're extending float to double.
1549 if (!Subtarget->hasVFP2()) return false;
1551 Value *V = I->getOperand(0);
1552 if (!I->getType()->isDoubleTy() ||
1553 !V->getType()->isFloatTy()) return false;
1555 unsigned Op = getRegForValue(V);
1556 if (Op == 0) return false;
1558 unsigned Result = createResultReg(&ARM::DPRRegClass);
1559 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1560 TII.get(ARM::VCVTDS), Result)
1562 UpdateValueMap(I, Result);
1566 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1567 // Make sure we have VFP and that we're truncating double to float.
1568 if (!Subtarget->hasVFP2()) return false;
1570 Value *V = I->getOperand(0);
1571 if (!(I->getType()->isFloatTy() &&
1572 V->getType()->isDoubleTy())) return false;
1574 unsigned Op = getRegForValue(V);
1575 if (Op == 0) return false;
1577 unsigned Result = createResultReg(&ARM::SPRRegClass);
1578 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1579 TII.get(ARM::VCVTSD), Result)
1581 UpdateValueMap(I, Result);
1585 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1586 // Make sure we have VFP.
1587 if (!Subtarget->hasVFP2()) return false;
1590 Type *Ty = I->getType();
1591 if (!isTypeLegal(Ty, DstVT))
1594 Value *Src = I->getOperand(0);
1595 EVT SrcEVT = TLI.getValueType(Src->getType(), true);
1596 if (!SrcEVT.isSimple())
1598 MVT SrcVT = SrcEVT.getSimpleVT();
1599 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1602 unsigned SrcReg = getRegForValue(Src);
1603 if (SrcReg == 0) return false;
1605 // Handle sign-extension.
1606 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1607 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1608 /*isZExt*/!isSigned);
1609 if (SrcReg == 0) return false;
1612 // The conversion routine works on fp-reg to fp-reg and the operand above
1613 // was an integer, move it to the fp registers if possible.
1614 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1615 if (FP == 0) return false;
1618 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1619 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1622 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1623 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1626 UpdateValueMap(I, ResultReg);
1630 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1631 // Make sure we have VFP.
1632 if (!Subtarget->hasVFP2()) return false;
1635 Type *RetTy = I->getType();
1636 if (!isTypeLegal(RetTy, DstVT))
1639 unsigned Op = getRegForValue(I->getOperand(0));
1640 if (Op == 0) return false;
1643 Type *OpTy = I->getOperand(0)->getType();
1644 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1645 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1648 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1649 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1650 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1654 // This result needs to be in an integer register, but the conversion only
1655 // takes place in fp-regs.
1656 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1657 if (IntReg == 0) return false;
1659 UpdateValueMap(I, IntReg);
1663 bool ARMFastISel::SelectSelect(const Instruction *I) {
1665 if (!isTypeLegal(I->getType(), VT))
1668 // Things need to be register sized for register moves.
1669 if (VT != MVT::i32) return false;
1671 unsigned CondReg = getRegForValue(I->getOperand(0));
1672 if (CondReg == 0) return false;
1673 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1674 if (Op1Reg == 0) return false;
1676 // Check to see if we can use an immediate in the conditional move.
1678 bool UseImm = false;
1679 bool isNegativeImm = false;
1680 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1681 assert (VT == MVT::i32 && "Expecting an i32.");
1682 Imm = (int)ConstInt->getValue().getZExtValue();
1684 isNegativeImm = true;
1687 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1688 (ARM_AM::getSOImmVal(Imm) != -1);
1691 unsigned Op2Reg = 0;
1693 Op2Reg = getRegForValue(I->getOperand(2));
1694 if (Op2Reg == 0) return false;
1697 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1698 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1699 .addReg(CondReg).addImm(0));
1702 const TargetRegisterClass *RC;
1704 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1705 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1707 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1709 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1711 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1713 unsigned ResultReg = createResultReg(RC);
1715 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1716 .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1718 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1719 .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1720 UpdateValueMap(I, ResultReg);
1724 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1726 Type *Ty = I->getType();
1727 if (!isTypeLegal(Ty, VT))
1730 // If we have integer div support we should have selected this automagically.
1731 // In case we have a real miss go ahead and return false and we'll pick
1733 if (Subtarget->hasDivide()) return false;
1735 // Otherwise emit a libcall.
1736 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1738 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1739 else if (VT == MVT::i16)
1740 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1741 else if (VT == MVT::i32)
1742 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1743 else if (VT == MVT::i64)
1744 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1745 else if (VT == MVT::i128)
1746 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1747 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1749 return ARMEmitLibcall(I, LC);
1752 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1754 Type *Ty = I->getType();
1755 if (!isTypeLegal(Ty, VT))
1758 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1760 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1761 else if (VT == MVT::i16)
1762 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1763 else if (VT == MVT::i32)
1764 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1765 else if (VT == MVT::i64)
1766 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1767 else if (VT == MVT::i128)
1768 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1769 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1771 return ARMEmitLibcall(I, LC);
1774 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1775 EVT DestVT = TLI.getValueType(I->getType(), true);
1777 // We can get here in the case when we have a binary operation on a non-legal
1778 // type and the target independent selector doesn't know how to handle it.
1779 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1783 switch (ISDOpcode) {
1784 default: return false;
1786 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1789 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1792 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1796 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1797 if (SrcReg1 == 0) return false;
1799 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1800 // in the instruction, rather then materializing the value in a register.
1801 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1802 if (SrcReg2 == 0) return false;
1804 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1805 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1806 TII.get(Opc), ResultReg)
1807 .addReg(SrcReg1).addReg(SrcReg2));
1808 UpdateValueMap(I, ResultReg);
1812 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1813 EVT FPVT = TLI.getValueType(I->getType(), true);
1814 if (!FPVT.isSimple()) return false;
1815 MVT VT = FPVT.getSimpleVT();
1817 // We can get here in the case when we want to use NEON for our fp
1818 // operations, but can't figure out how to. Just use the vfp instructions
1820 // FIXME: It'd be nice to use NEON instructions.
1821 Type *Ty = I->getType();
1822 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1823 if (isFloat && !Subtarget->hasVFP2())
1827 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1828 switch (ISDOpcode) {
1829 default: return false;
1831 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1834 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1837 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1840 unsigned Op1 = getRegForValue(I->getOperand(0));
1841 if (Op1 == 0) return false;
1843 unsigned Op2 = getRegForValue(I->getOperand(1));
1844 if (Op2 == 0) return false;
1846 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1847 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1848 TII.get(Opc), ResultReg)
1849 .addReg(Op1).addReg(Op2));
1850 UpdateValueMap(I, ResultReg);
1854 // Call Handling Code
1856 // This is largely taken directly from CCAssignFnForNode
1857 // TODO: We may not support all of this.
1858 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1863 llvm_unreachable("Unsupported calling convention");
1864 case CallingConv::Fast:
1865 if (Subtarget->hasVFP2() && !isVarArg) {
1866 if (!Subtarget->isAAPCS_ABI())
1867 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1868 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1869 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1872 case CallingConv::C:
1873 // Use target triple & subtarget features to do actual dispatch.
1874 if (Subtarget->isAAPCS_ABI()) {
1875 if (Subtarget->hasVFP2() &&
1876 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1877 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1879 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1881 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1882 case CallingConv::ARM_AAPCS_VFP:
1884 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1885 // Fall through to soft float variant, variadic functions don't
1886 // use hard floating point ABI.
1887 case CallingConv::ARM_AAPCS:
1888 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1889 case CallingConv::ARM_APCS:
1890 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1891 case CallingConv::GHC:
1893 llvm_unreachable("Can't return in GHC call convention");
1895 return CC_ARM_APCS_GHC;
1899 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1900 SmallVectorImpl<unsigned> &ArgRegs,
1901 SmallVectorImpl<MVT> &ArgVTs,
1902 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1903 SmallVectorImpl<unsigned> &RegArgs,
1907 SmallVector<CCValAssign, 16> ArgLocs;
1908 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1909 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1910 CCAssignFnForCall(CC, false, isVarArg));
1912 // Check that we can handle all of the arguments. If we can't, then bail out
1913 // now before we add code to the MBB.
1914 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1915 CCValAssign &VA = ArgLocs[i];
1916 MVT ArgVT = ArgVTs[VA.getValNo()];
1918 // We don't handle NEON/vector parameters yet.
1919 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1922 // Now copy/store arg to correct locations.
1923 if (VA.isRegLoc() && !VA.needsCustom()) {
1925 } else if (VA.needsCustom()) {
1926 // TODO: We need custom lowering for vector (v2f64) args.
1927 if (VA.getLocVT() != MVT::f64 ||
1928 // TODO: Only handle register args for now.
1929 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1932 switch (static_cast<EVT>(ArgVT).getSimpleVT().SimpleTy) {
1941 if (!Subtarget->hasVFP2())
1945 if (!Subtarget->hasVFP2())
1952 // At the point, we are able to handle the call's arguments in fast isel.
1954 // Get a count of how many bytes are to be pushed on the stack.
1955 NumBytes = CCInfo.getNextStackOffset();
1957 // Issue CALLSEQ_START
1958 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1959 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1960 TII.get(AdjStackDown))
1963 // Process the args.
1964 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1965 CCValAssign &VA = ArgLocs[i];
1966 unsigned Arg = ArgRegs[VA.getValNo()];
1967 MVT ArgVT = ArgVTs[VA.getValNo()];
1969 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1970 "We don't handle NEON/vector parameters yet.");
1972 // Handle arg promotion, etc.
1973 switch (VA.getLocInfo()) {
1974 case CCValAssign::Full: break;
1975 case CCValAssign::SExt: {
1976 MVT DestVT = VA.getLocVT();
1977 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1978 assert (Arg != 0 && "Failed to emit a sext");
1982 case CCValAssign::AExt:
1983 // Intentional fall-through. Handle AExt and ZExt.
1984 case CCValAssign::ZExt: {
1985 MVT DestVT = VA.getLocVT();
1986 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1987 assert (Arg != 0 && "Failed to emit a sext");
1991 case CCValAssign::BCvt: {
1992 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1993 /*TODO: Kill=*/false);
1994 assert(BC != 0 && "Failed to emit a bitcast!");
1996 ArgVT = VA.getLocVT();
1999 default: llvm_unreachable("Unknown arg promotion!");
2002 // Now copy/store arg to correct locations.
2003 if (VA.isRegLoc() && !VA.needsCustom()) {
2004 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2007 RegArgs.push_back(VA.getLocReg());
2008 } else if (VA.needsCustom()) {
2009 // TODO: We need custom lowering for vector (v2f64) args.
2010 assert(VA.getLocVT() == MVT::f64 &&
2011 "Custom lowering for v2f64 args not available");
2013 CCValAssign &NextVA = ArgLocs[++i];
2015 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2016 "We only handle register args!");
2018 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2019 TII.get(ARM::VMOVRRD), VA.getLocReg())
2020 .addReg(NextVA.getLocReg(), RegState::Define)
2022 RegArgs.push_back(VA.getLocReg());
2023 RegArgs.push_back(NextVA.getLocReg());
2025 assert(VA.isMemLoc());
2026 // Need to store on the stack.
2028 Addr.BaseType = Address::RegBase;
2029 Addr.Base.Reg = ARM::SP;
2030 Addr.Offset = VA.getLocMemOffset();
2032 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2033 assert(EmitRet && "Could not emit a store for argument!");
2040 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2041 const Instruction *I, CallingConv::ID CC,
2042 unsigned &NumBytes, bool isVarArg) {
2043 // Issue CALLSEQ_END
2044 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2045 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2046 TII.get(AdjStackUp))
2047 .addImm(NumBytes).addImm(0));
2049 // Now the return value.
2050 if (RetVT != MVT::isVoid) {
2051 SmallVector<CCValAssign, 16> RVLocs;
2052 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2053 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2055 // Copy all of the result registers out of their specified physreg.
2056 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2057 // For this move we copy into two registers and then move into the
2058 // double fp reg we want.
2059 MVT DestVT = RVLocs[0].getValVT();
2060 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2061 unsigned ResultReg = createResultReg(DstRC);
2062 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2063 TII.get(ARM::VMOVDRR), ResultReg)
2064 .addReg(RVLocs[0].getLocReg())
2065 .addReg(RVLocs[1].getLocReg()));
2067 UsedRegs.push_back(RVLocs[0].getLocReg());
2068 UsedRegs.push_back(RVLocs[1].getLocReg());
2070 // Finally update the result.
2071 UpdateValueMap(I, ResultReg);
2073 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2074 MVT CopyVT = RVLocs[0].getValVT();
2076 // Special handling for extended integers.
2077 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2080 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2082 unsigned ResultReg = createResultReg(DstRC);
2083 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2084 ResultReg).addReg(RVLocs[0].getLocReg());
2085 UsedRegs.push_back(RVLocs[0].getLocReg());
2087 // Finally update the result.
2088 UpdateValueMap(I, ResultReg);
2095 bool ARMFastISel::SelectRet(const Instruction *I) {
2096 const ReturnInst *Ret = cast<ReturnInst>(I);
2097 const Function &F = *I->getParent()->getParent();
2099 if (!FuncInfo.CanLowerReturn)
2102 CallingConv::ID CC = F.getCallingConv();
2103 if (Ret->getNumOperands() > 0) {
2104 SmallVector<ISD::OutputArg, 4> Outs;
2105 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
2108 // Analyze operands of the call, assigning locations to each operand.
2109 SmallVector<CCValAssign, 16> ValLocs;
2110 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
2111 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2114 const Value *RV = Ret->getOperand(0);
2115 unsigned Reg = getRegForValue(RV);
2119 // Only handle a single return value for now.
2120 if (ValLocs.size() != 1)
2123 CCValAssign &VA = ValLocs[0];
2125 // Don't bother handling odd stuff for now.
2126 if (VA.getLocInfo() != CCValAssign::Full)
2128 // Only handle register returns for now.
2132 unsigned SrcReg = Reg + VA.getValNo();
2133 EVT RVEVT = TLI.getValueType(RV->getType());
2134 if (!RVEVT.isSimple()) return false;
2135 MVT RVVT = RVEVT.getSimpleVT();
2136 MVT DestVT = VA.getValVT();
2137 // Special handling for extended integers.
2138 if (RVVT != DestVT) {
2139 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2142 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2144 // Perform extension if flagged as either zext or sext. Otherwise, do
2146 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2147 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2148 if (SrcReg == 0) return false;
2153 unsigned DstReg = VA.getLocReg();
2154 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2155 // Avoid a cross-class copy. This is very unlikely.
2156 if (!SrcRC->contains(DstReg))
2158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2159 DstReg).addReg(SrcReg);
2161 // Mark the register as live out of the function.
2162 MRI.addLiveOut(VA.getLocReg());
2165 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2166 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2171 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2173 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2175 return isThumb2 ? ARM::tBL : ARM::BL;
2178 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2179 GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false,
2180 GlobalValue::ExternalLinkage, 0, Name);
2181 EVT LCREVT = TLI.getValueType(GV->getType());
2182 if (!LCREVT.isSimple()) return 0;
2183 return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2186 // A quick function that will emit a call for a named libcall in F with the
2187 // vector of passed arguments for the Instruction in I. We can assume that we
2188 // can emit a call for any libcall we can produce. This is an abridged version
2189 // of the full call infrastructure since we won't need to worry about things
2190 // like computed function pointers or strange arguments at call sites.
2191 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2193 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2194 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2196 // Handle *simple* calls for now.
2197 Type *RetTy = I->getType();
2199 if (RetTy->isVoidTy())
2200 RetVT = MVT::isVoid;
2201 else if (!isTypeLegal(RetTy, RetVT))
2204 // Can't handle non-double multi-reg retvals.
2205 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2206 SmallVector<CCValAssign, 16> RVLocs;
2207 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
2208 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2209 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2213 // Set up the argument vectors.
2214 SmallVector<Value*, 8> Args;
2215 SmallVector<unsigned, 8> ArgRegs;
2216 SmallVector<MVT, 8> ArgVTs;
2217 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2218 Args.reserve(I->getNumOperands());
2219 ArgRegs.reserve(I->getNumOperands());
2220 ArgVTs.reserve(I->getNumOperands());
2221 ArgFlags.reserve(I->getNumOperands());
2222 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2223 Value *Op = I->getOperand(i);
2224 unsigned Arg = getRegForValue(Op);
2225 if (Arg == 0) return false;
2227 Type *ArgTy = Op->getType();
2229 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2231 ISD::ArgFlagsTy Flags;
2232 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2233 Flags.setOrigAlign(OriginalAlignment);
2236 ArgRegs.push_back(Arg);
2237 ArgVTs.push_back(ArgVT);
2238 ArgFlags.push_back(Flags);
2241 // Handle the arguments now that we've gotten them.
2242 SmallVector<unsigned, 4> RegArgs;
2244 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2245 RegArgs, CC, NumBytes, false))
2248 unsigned CalleeReg = 0;
2249 if (EnableARMLongCalls) {
2250 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2251 if (CalleeReg == 0) return false;
2255 unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
2256 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2257 DL, TII.get(CallOpc));
2258 // BL / BLX don't take a predicate, but tBL / tBLX do.
2260 AddDefaultPred(MIB);
2261 if (EnableARMLongCalls)
2262 MIB.addReg(CalleeReg);
2264 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2266 // Add implicit physical register uses to the call.
2267 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2268 MIB.addReg(RegArgs[i], RegState::Implicit);
2270 // Add a register mask with the call-preserved registers.
2271 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2272 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2274 // Finish off the call including any return values.
2275 SmallVector<unsigned, 4> UsedRegs;
2276 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2278 // Set all unused physreg defs as dead.
2279 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2284 bool ARMFastISel::SelectCall(const Instruction *I,
2285 const char *IntrMemName = 0) {
2286 const CallInst *CI = cast<CallInst>(I);
2287 const Value *Callee = CI->getCalledValue();
2289 // Can't handle inline asm.
2290 if (isa<InlineAsm>(Callee)) return false;
2292 // Allow SelectionDAG isel to handle tail calls.
2293 if (CI->isTailCall()) return false;
2295 // Check the calling convention.
2296 ImmutableCallSite CS(CI);
2297 CallingConv::ID CC = CS.getCallingConv();
2299 // TODO: Avoid some calling conventions?
2301 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2302 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2303 bool isVarArg = FTy->isVarArg();
2305 // Handle *simple* calls for now.
2306 Type *RetTy = I->getType();
2308 if (RetTy->isVoidTy())
2309 RetVT = MVT::isVoid;
2310 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2311 RetVT != MVT::i8 && RetVT != MVT::i1)
2314 // Can't handle non-double multi-reg retvals.
2315 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2316 RetVT != MVT::i16 && RetVT != MVT::i32) {
2317 SmallVector<CCValAssign, 16> RVLocs;
2318 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2319 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2320 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2324 // Set up the argument vectors.
2325 SmallVector<Value*, 8> Args;
2326 SmallVector<unsigned, 8> ArgRegs;
2327 SmallVector<MVT, 8> ArgVTs;
2328 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2329 unsigned arg_size = CS.arg_size();
2330 Args.reserve(arg_size);
2331 ArgRegs.reserve(arg_size);
2332 ArgVTs.reserve(arg_size);
2333 ArgFlags.reserve(arg_size);
2334 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2336 // If we're lowering a memory intrinsic instead of a regular call, skip the
2337 // last two arguments, which shouldn't be passed to the underlying function.
2338 if (IntrMemName && e-i <= 2)
2341 ISD::ArgFlagsTy Flags;
2342 unsigned AttrInd = i - CS.arg_begin() + 1;
2343 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2345 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2348 // FIXME: Only handle *easy* calls for now.
2349 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2350 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2351 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2352 CS.paramHasAttr(AttrInd, Attribute::ByVal))
2355 Type *ArgTy = (*i)->getType();
2357 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2361 unsigned Arg = getRegForValue(*i);
2365 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2366 Flags.setOrigAlign(OriginalAlignment);
2369 ArgRegs.push_back(Arg);
2370 ArgVTs.push_back(ArgVT);
2371 ArgFlags.push_back(Flags);
2374 // Handle the arguments now that we've gotten them.
2375 SmallVector<unsigned, 4> RegArgs;
2377 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2378 RegArgs, CC, NumBytes, isVarArg))
2381 bool UseReg = false;
2382 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2383 if (!GV || EnableARMLongCalls) UseReg = true;
2385 unsigned CalleeReg = 0;
2388 CalleeReg = getLibcallReg(IntrMemName);
2390 CalleeReg = getRegForValue(Callee);
2392 if (CalleeReg == 0) return false;
2396 unsigned CallOpc = ARMSelectCallOp(UseReg);
2397 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2398 DL, TII.get(CallOpc));
2400 // ARM calls don't take a predicate, but tBL / tBLX do.
2402 AddDefaultPred(MIB);
2404 MIB.addReg(CalleeReg);
2405 else if (!IntrMemName)
2406 MIB.addGlobalAddress(GV, 0, 0);
2408 MIB.addExternalSymbol(IntrMemName, 0);
2410 // Add implicit physical register uses to the call.
2411 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2412 MIB.addReg(RegArgs[i], RegState::Implicit);
2414 // Add a register mask with the call-preserved registers.
2415 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2416 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2418 // Finish off the call including any return values.
2419 SmallVector<unsigned, 4> UsedRegs;
2420 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2423 // Set all unused physreg defs as dead.
2424 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2429 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2433 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2434 uint64_t Len, unsigned Alignment) {
2435 // Make sure we don't bloat code by inlining very large memcpy's.
2436 if (!ARMIsMemCpySmall(Len))
2441 if (!Alignment || Alignment >= 4) {
2447 assert (Len == 1 && "Expected a length of 1!");
2451 // Bound based on alignment.
2452 if (Len >= 2 && Alignment == 2)
2455 assert (Alignment == 1 && "Expected an alignment of 1!");
2462 RV = ARMEmitLoad(VT, ResultReg, Src);
2463 assert (RV == true && "Should be able to handle this load.");
2464 RV = ARMEmitStore(VT, ResultReg, Dest);
2465 assert (RV == true && "Should be able to handle this store.");
2468 unsigned Size = VT.getSizeInBits()/8;
2470 Dest.Offset += Size;
2477 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2478 // FIXME: Handle more intrinsics.
2479 switch (I.getIntrinsicID()) {
2480 default: return false;
2481 case Intrinsic::frameaddress: {
2482 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2483 MFI->setFrameAddressIsTaken(true);
2486 const TargetRegisterClass *RC;
2488 LdrOpc = ARM::t2LDRi12;
2489 RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2491 LdrOpc = ARM::LDRi12;
2492 RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2495 const ARMBaseRegisterInfo *RegInfo =
2496 static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
2497 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2498 unsigned SrcReg = FramePtr;
2500 // Recursively load frame address
2506 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2508 DestReg = createResultReg(RC);
2509 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2510 TII.get(LdrOpc), DestReg)
2511 .addReg(SrcReg).addImm(0));
2514 UpdateValueMap(&I, SrcReg);
2517 case Intrinsic::memcpy:
2518 case Intrinsic::memmove: {
2519 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2520 // Don't handle volatile.
2521 if (MTI.isVolatile())
2524 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2525 // we would emit dead code because we don't currently handle memmoves.
2526 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2527 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2528 // Small memcpy's are common enough that we want to do them without a call
2530 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2531 if (ARMIsMemCpySmall(Len)) {
2533 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2534 !ARMComputeAddress(MTI.getRawSource(), Src))
2536 unsigned Alignment = MTI.getAlignment();
2537 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2542 if (!MTI.getLength()->getType()->isIntegerTy(32))
2545 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2548 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2549 return SelectCall(&I, IntrMemName);
2551 case Intrinsic::memset: {
2552 const MemSetInst &MSI = cast<MemSetInst>(I);
2553 // Don't handle volatile.
2554 if (MSI.isVolatile())
2557 if (!MSI.getLength()->getType()->isIntegerTy(32))
2560 if (MSI.getDestAddressSpace() > 255)
2563 return SelectCall(&I, "memset");
2565 case Intrinsic::trap: {
2566 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::TRAP));
2572 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2573 // The high bits for a type smaller than the register size are assumed to be
2575 Value *Op = I->getOperand(0);
2578 SrcVT = TLI.getValueType(Op->getType(), true);
2579 DestVT = TLI.getValueType(I->getType(), true);
2581 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2583 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2586 unsigned SrcReg = getRegForValue(Op);
2587 if (!SrcReg) return false;
2589 // Because the high bits are undefined, a truncate doesn't generate
2591 UpdateValueMap(I, SrcReg);
2595 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2597 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2601 bool isBoolZext = false;
2602 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::i32);
2603 switch (SrcVT.SimpleTy) {
2606 if (!Subtarget->hasV6Ops()) return 0;
2607 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
2609 Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
2611 Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
2614 if (!Subtarget->hasV6Ops()) return 0;
2615 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
2617 Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
2619 Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
2623 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
2624 Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
2631 unsigned ResultReg = createResultReg(RC);
2632 MachineInstrBuilder MIB;
2633 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
2639 AddOptionalDefs(MIB);
2643 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2644 // On ARM, in general, integer casts don't involve legal types; this code
2645 // handles promotable integers.
2646 Type *DestTy = I->getType();
2647 Value *Src = I->getOperand(0);
2648 Type *SrcTy = Src->getType();
2650 bool isZExt = isa<ZExtInst>(I);
2651 unsigned SrcReg = getRegForValue(Src);
2652 if (!SrcReg) return false;
2654 EVT SrcEVT, DestEVT;
2655 SrcEVT = TLI.getValueType(SrcTy, true);
2656 DestEVT = TLI.getValueType(DestTy, true);
2657 if (!SrcEVT.isSimple()) return false;
2658 if (!DestEVT.isSimple()) return false;
2660 MVT SrcVT = SrcEVT.getSimpleVT();
2661 MVT DestVT = DestEVT.getSimpleVT();
2662 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2663 if (ResultReg == 0) return false;
2664 UpdateValueMap(I, ResultReg);
2668 bool ARMFastISel::SelectShift(const Instruction *I,
2669 ARM_AM::ShiftOpc ShiftTy) {
2670 // We handle thumb2 mode by target independent selector
2671 // or SelectionDAG ISel.
2675 // Only handle i32 now.
2676 EVT DestVT = TLI.getValueType(I->getType(), true);
2677 if (DestVT != MVT::i32)
2680 unsigned Opc = ARM::MOVsr;
2682 Value *Src2Value = I->getOperand(1);
2683 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2684 ShiftImm = CI->getZExtValue();
2686 // Fall back to selection DAG isel if the shift amount
2687 // is zero or greater than the width of the value type.
2688 if (ShiftImm == 0 || ShiftImm >=32)
2694 Value *Src1Value = I->getOperand(0);
2695 unsigned Reg1 = getRegForValue(Src1Value);
2696 if (Reg1 == 0) return false;
2699 if (Opc == ARM::MOVsr) {
2700 Reg2 = getRegForValue(Src2Value);
2701 if (Reg2 == 0) return false;
2704 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2705 if(ResultReg == 0) return false;
2707 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2708 TII.get(Opc), ResultReg)
2711 if (Opc == ARM::MOVsi)
2712 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2713 else if (Opc == ARM::MOVsr) {
2715 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2718 AddOptionalDefs(MIB);
2719 UpdateValueMap(I, ResultReg);
2723 // TODO: SoftFP support.
2724 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2726 switch (I->getOpcode()) {
2727 case Instruction::Load:
2728 return SelectLoad(I);
2729 case Instruction::Store:
2730 return SelectStore(I);
2731 case Instruction::Br:
2732 return SelectBranch(I);
2733 case Instruction::IndirectBr:
2734 return SelectIndirectBr(I);
2735 case Instruction::ICmp:
2736 case Instruction::FCmp:
2737 return SelectCmp(I);
2738 case Instruction::FPExt:
2739 return SelectFPExt(I);
2740 case Instruction::FPTrunc:
2741 return SelectFPTrunc(I);
2742 case Instruction::SIToFP:
2743 return SelectIToFP(I, /*isSigned*/ true);
2744 case Instruction::UIToFP:
2745 return SelectIToFP(I, /*isSigned*/ false);
2746 case Instruction::FPToSI:
2747 return SelectFPToI(I, /*isSigned*/ true);
2748 case Instruction::FPToUI:
2749 return SelectFPToI(I, /*isSigned*/ false);
2750 case Instruction::Add:
2751 return SelectBinaryIntOp(I, ISD::ADD);
2752 case Instruction::Or:
2753 return SelectBinaryIntOp(I, ISD::OR);
2754 case Instruction::Sub:
2755 return SelectBinaryIntOp(I, ISD::SUB);
2756 case Instruction::FAdd:
2757 return SelectBinaryFPOp(I, ISD::FADD);
2758 case Instruction::FSub:
2759 return SelectBinaryFPOp(I, ISD::FSUB);
2760 case Instruction::FMul:
2761 return SelectBinaryFPOp(I, ISD::FMUL);
2762 case Instruction::SDiv:
2763 return SelectDiv(I, /*isSigned*/ true);
2764 case Instruction::UDiv:
2765 return SelectDiv(I, /*isSigned*/ false);
2766 case Instruction::SRem:
2767 return SelectRem(I, /*isSigned*/ true);
2768 case Instruction::URem:
2769 return SelectRem(I, /*isSigned*/ false);
2770 case Instruction::Call:
2771 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2772 return SelectIntrinsicCall(*II);
2773 return SelectCall(I);
2774 case Instruction::Select:
2775 return SelectSelect(I);
2776 case Instruction::Ret:
2777 return SelectRet(I);
2778 case Instruction::Trunc:
2779 return SelectTrunc(I);
2780 case Instruction::ZExt:
2781 case Instruction::SExt:
2782 return SelectIntExt(I);
2783 case Instruction::Shl:
2784 return SelectShift(I, ARM_AM::lsl);
2785 case Instruction::LShr:
2786 return SelectShift(I, ARM_AM::lsr);
2787 case Instruction::AShr:
2788 return SelectShift(I, ARM_AM::asr);
2794 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
2795 /// vreg is being provided by the specified load instruction. If possible,
2796 /// try to fold the load as an operand to the instruction, returning true if
2798 bool ARMFastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
2799 const LoadInst *LI) {
2800 // Verify we have a legal type before going any further.
2802 if (!isLoadTypeLegal(LI->getType(), VT))
2805 // Combine load followed by zero- or sign-extend.
2806 // ldrb r1, [r0] ldrb r1, [r0]
2808 // mov r3, r2 mov r3, r1
2810 switch(MI->getOpcode()) {
2811 default: return false;
2829 // See if we can handle this address.
2831 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2833 unsigned ResultReg = MI->getOperand(0).getReg();
2834 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2836 MI->eraseFromParent();
2840 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2841 unsigned Align, MVT VT) {
2842 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2843 ARMConstantPoolConstant *CPV =
2844 ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2845 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
2848 unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
2851 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2852 TII.get(ARM::t2LDRpci), DestReg1)
2853 .addConstantPoolIndex(Idx));
2854 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
2856 // The extra immediate is for addrmode2.
2857 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2858 DL, TII.get(ARM::LDRcp), DestReg1)
2859 .addConstantPoolIndex(Idx).addImm(0));
2860 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
2863 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
2864 if (GlobalBaseReg == 0) {
2865 GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
2866 AFI->setGlobalBaseReg(GlobalBaseReg);
2869 unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
2870 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2871 DL, TII.get(Opc), DestReg2)
2873 .addReg(GlobalBaseReg);
2876 AddOptionalDefs(MIB);
2882 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
2883 const TargetLibraryInfo *libInfo) {
2884 // Completely untested on non-iOS.
2885 const TargetMachine &TM = funcInfo.MF->getTarget();
2887 // Darwin and thumb1 only for now.
2888 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2889 if (Subtarget->isTargetIOS() && !Subtarget->isThumb1Only())
2890 return new ARMFastISel(funcInfo, libInfo);