1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/GetElementPtrTypeIterator.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Module.h"
43 #include "llvm/IR/Operator.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
52 extern cl::opt<bool> EnableARMLongCalls;
56 // All possible address modes, plus some.
57 typedef struct Address {
70 // Innocuous defaults for our address.
72 : BaseType(RegBase), Offset(0) {
77 class ARMFastISel final : public FastISel {
79 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
80 /// make the right decision when generating code for different targets.
81 const ARMSubtarget *Subtarget;
83 const TargetMachine &TM;
84 const TargetInstrInfo &TII;
85 const TargetLowering &TLI;
88 // Convenience variables to avoid some queries.
93 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
94 const TargetLibraryInfo *libInfo)
95 : FastISel(funcInfo, libInfo),
96 M(const_cast<Module &>(*funcInfo.Fn->getParent())),
97 TM(funcInfo.MF->getTarget()),
98 TII(*TM.getSubtargetImpl()->getInstrInfo()),
99 TLI(*TM.getSubtargetImpl()->getTargetLowering()) {
100 Subtarget = &TM.getSubtarget<ARMSubtarget>();
101 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
102 isThumb2 = AFI->isThumbFunction();
103 Context = &funcInfo.Fn->getContext();
106 // Code from FastISel.cpp.
108 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
109 const TargetRegisterClass *RC,
110 unsigned Op0, bool Op0IsKill);
111 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
112 const TargetRegisterClass *RC,
113 unsigned Op0, bool Op0IsKill,
114 unsigned Op1, bool Op1IsKill);
115 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
116 const TargetRegisterClass *RC,
117 unsigned Op0, bool Op0IsKill,
118 unsigned Op1, bool Op1IsKill,
119 unsigned Op2, bool Op2IsKill);
120 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
121 const TargetRegisterClass *RC,
122 unsigned Op0, bool Op0IsKill,
124 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
125 const TargetRegisterClass *RC,
126 unsigned Op0, bool Op0IsKill,
127 unsigned Op1, bool Op1IsKill,
129 unsigned FastEmitInst_i(unsigned MachineInstOpcode,
130 const TargetRegisterClass *RC,
133 // Backend specific FastISel code.
135 bool TargetSelectInstruction(const Instruction *I) override;
136 unsigned TargetMaterializeConstant(const Constant *C) override;
137 unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
138 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
139 const LoadInst *LI) override;
140 bool FastLowerArguments() override;
142 #include "ARMGenFastISel.inc"
144 // Instruction selection routines.
146 bool SelectLoad(const Instruction *I);
147 bool SelectStore(const Instruction *I);
148 bool SelectBranch(const Instruction *I);
149 bool SelectIndirectBr(const Instruction *I);
150 bool SelectCmp(const Instruction *I);
151 bool SelectFPExt(const Instruction *I);
152 bool SelectFPTrunc(const Instruction *I);
153 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
154 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
155 bool SelectIToFP(const Instruction *I, bool isSigned);
156 bool SelectFPToI(const Instruction *I, bool isSigned);
157 bool SelectDiv(const Instruction *I, bool isSigned);
158 bool SelectRem(const Instruction *I, bool isSigned);
159 bool SelectCall(const Instruction *I, const char *IntrMemName);
160 bool SelectIntrinsicCall(const IntrinsicInst &I);
161 bool SelectSelect(const Instruction *I);
162 bool SelectRet(const Instruction *I);
163 bool SelectTrunc(const Instruction *I);
164 bool SelectIntExt(const Instruction *I);
165 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
169 bool isTypeLegal(Type *Ty, MVT &VT);
170 bool isLoadTypeLegal(Type *Ty, MVT &VT);
171 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
173 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
174 unsigned Alignment = 0, bool isZExt = true,
175 bool allocReg = true);
176 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
177 unsigned Alignment = 0);
178 bool ARMComputeAddress(const Value *Obj, Address &Addr);
179 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
180 bool ARMIsMemCpySmall(uint64_t Len);
181 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
183 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
184 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
185 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
186 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
187 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
188 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
189 unsigned ARMSelectCallOp(bool UseReg);
190 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
192 const TargetLowering *getTargetLowering() {
193 return TM.getSubtargetImpl()->getTargetLowering();
196 // Call handling routines.
198 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
201 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
202 SmallVectorImpl<unsigned> &ArgRegs,
203 SmallVectorImpl<MVT> &ArgVTs,
204 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
205 SmallVectorImpl<unsigned> &RegArgs,
209 unsigned getLibcallReg(const Twine &Name);
210 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
211 const Instruction *I, CallingConv::ID CC,
212 unsigned &NumBytes, bool isVarArg);
213 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
215 // OptionalDef handling routines.
217 bool isARMNEONPred(const MachineInstr *MI);
218 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
219 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
220 void AddLoadStoreOperands(MVT VT, Address &Addr,
221 const MachineInstrBuilder &MIB,
222 unsigned Flags, bool useAM3);
225 } // end anonymous namespace
227 #include "ARMGenCallingConv.inc"
229 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
230 // we don't care about implicit defs here, just places we'll need to add a
231 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
232 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
233 if (!MI->hasOptionalDef())
236 // Look to see if our OptionalDef is defining CPSR or CCR.
237 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
238 const MachineOperand &MO = MI->getOperand(i);
239 if (!MO.isReg() || !MO.isDef()) continue;
240 if (MO.getReg() == ARM::CPSR)
246 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
247 const MCInstrDesc &MCID = MI->getDesc();
249 // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
250 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
251 AFI->isThumb2Function())
252 return MI->isPredicable();
254 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
255 if (MCID.OpInfo[i].isPredicate())
261 // If the machine is predicable go ahead and add the predicate operands, if
262 // it needs default CC operands add those.
263 // TODO: If we want to support thumb1 then we'll need to deal with optional
264 // CPSR defs that need to be added before the remaining operands. See s_cc_out
265 // for descriptions why.
266 const MachineInstrBuilder &
267 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
268 MachineInstr *MI = &*MIB;
270 // Do we use a predicate? or...
271 // Are we NEON in ARM mode and have a predicate operand? If so, I know
272 // we're not predicable but add it anyways.
273 if (isARMNEONPred(MI))
276 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
277 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
279 if (DefinesOptionalPredicate(MI, &CPSR)) {
288 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
289 const TargetRegisterClass *RC,
290 unsigned Op0, bool Op0IsKill) {
291 unsigned ResultReg = createResultReg(RC);
292 const MCInstrDesc &II = TII.get(MachineInstOpcode);
294 // Make sure the input operand is sufficiently constrained to be legal
295 // for this instruction.
296 Op0 = constrainOperandRegClass(II, Op0, 1);
297 if (II.getNumDefs() >= 1) {
298 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
299 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
301 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
302 .addReg(Op0, Op0IsKill * RegState::Kill));
303 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
304 TII.get(TargetOpcode::COPY), ResultReg)
305 .addReg(II.ImplicitDefs[0]));
310 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
311 const TargetRegisterClass *RC,
312 unsigned Op0, bool Op0IsKill,
313 unsigned Op1, bool Op1IsKill) {
314 unsigned ResultReg = createResultReg(RC);
315 const MCInstrDesc &II = TII.get(MachineInstOpcode);
317 // Make sure the input operands are sufficiently constrained to be legal
318 // for this instruction.
319 Op0 = constrainOperandRegClass(II, Op0, 1);
320 Op1 = constrainOperandRegClass(II, Op1, 2);
322 if (II.getNumDefs() >= 1) {
324 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
325 .addReg(Op0, Op0IsKill * RegState::Kill)
326 .addReg(Op1, Op1IsKill * RegState::Kill));
328 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
329 .addReg(Op0, Op0IsKill * RegState::Kill)
330 .addReg(Op1, Op1IsKill * RegState::Kill));
331 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
332 TII.get(TargetOpcode::COPY), ResultReg)
333 .addReg(II.ImplicitDefs[0]));
338 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
339 const TargetRegisterClass *RC,
340 unsigned Op0, bool Op0IsKill,
341 unsigned Op1, bool Op1IsKill,
342 unsigned Op2, bool Op2IsKill) {
343 unsigned ResultReg = createResultReg(RC);
344 const MCInstrDesc &II = TII.get(MachineInstOpcode);
346 // Make sure the input operands are sufficiently constrained to be legal
347 // for this instruction.
348 Op0 = constrainOperandRegClass(II, Op0, 1);
349 Op1 = constrainOperandRegClass(II, Op1, 2);
350 Op2 = constrainOperandRegClass(II, Op1, 3);
352 if (II.getNumDefs() >= 1) {
354 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
355 .addReg(Op0, Op0IsKill * RegState::Kill)
356 .addReg(Op1, Op1IsKill * RegState::Kill)
357 .addReg(Op2, Op2IsKill * RegState::Kill));
359 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
360 .addReg(Op0, Op0IsKill * RegState::Kill)
361 .addReg(Op1, Op1IsKill * RegState::Kill)
362 .addReg(Op2, Op2IsKill * RegState::Kill));
363 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
364 TII.get(TargetOpcode::COPY), ResultReg)
365 .addReg(II.ImplicitDefs[0]));
370 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
371 const TargetRegisterClass *RC,
372 unsigned Op0, bool Op0IsKill,
374 unsigned ResultReg = createResultReg(RC);
375 const MCInstrDesc &II = TII.get(MachineInstOpcode);
377 // Make sure the input operand is sufficiently constrained to be legal
378 // for this instruction.
379 Op0 = constrainOperandRegClass(II, Op0, 1);
380 if (II.getNumDefs() >= 1) {
382 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
383 .addReg(Op0, Op0IsKill * RegState::Kill)
386 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
387 .addReg(Op0, Op0IsKill * RegState::Kill)
389 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
390 TII.get(TargetOpcode::COPY), ResultReg)
391 .addReg(II.ImplicitDefs[0]));
396 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
397 const TargetRegisterClass *RC,
398 unsigned Op0, bool Op0IsKill,
399 unsigned Op1, bool Op1IsKill,
401 unsigned ResultReg = createResultReg(RC);
402 const MCInstrDesc &II = TII.get(MachineInstOpcode);
404 // Make sure the input operands are sufficiently constrained to be legal
405 // for this instruction.
406 Op0 = constrainOperandRegClass(II, Op0, 1);
407 Op1 = constrainOperandRegClass(II, Op1, 2);
408 if (II.getNumDefs() >= 1) {
410 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
411 .addReg(Op0, Op0IsKill * RegState::Kill)
412 .addReg(Op1, Op1IsKill * RegState::Kill)
415 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
416 .addReg(Op0, Op0IsKill * RegState::Kill)
417 .addReg(Op1, Op1IsKill * RegState::Kill)
419 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
420 TII.get(TargetOpcode::COPY), ResultReg)
421 .addReg(II.ImplicitDefs[0]));
426 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
427 const TargetRegisterClass *RC,
429 unsigned ResultReg = createResultReg(RC);
430 const MCInstrDesc &II = TII.get(MachineInstOpcode);
432 if (II.getNumDefs() >= 1) {
433 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
434 ResultReg).addImm(Imm));
436 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
438 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
439 TII.get(TargetOpcode::COPY), ResultReg)
440 .addReg(II.ImplicitDefs[0]));
445 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
446 // checks from the various callers.
447 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
448 if (VT == MVT::f64) return 0;
450 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
451 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
452 TII.get(ARM::VMOVSR), MoveReg)
457 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
458 if (VT == MVT::i64) return 0;
460 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
461 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
462 TII.get(ARM::VMOVRS), MoveReg)
467 // For double width floating point we need to materialize two constants
468 // (the high and the low) into integer registers then use a move to get
469 // the combined constant into an FP reg.
470 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
471 const APFloat Val = CFP->getValueAPF();
472 bool is64bit = VT == MVT::f64;
474 // This checks to see if we can use VFP3 instructions to materialize
475 // a constant, otherwise we have to go through the constant pool.
476 if (TLI.isFPImmLegal(Val, VT)) {
480 Imm = ARM_AM::getFP64Imm(Val);
483 Imm = ARM_AM::getFP32Imm(Val);
486 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
487 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
488 TII.get(Opc), DestReg).addImm(Imm));
492 // Require VFP2 for loading fp constants.
493 if (!Subtarget->hasVFP2()) return false;
495 // MachineConstantPool wants an explicit alignment.
496 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
498 // TODO: Figure out if this is correct.
499 Align = DL.getTypeAllocSize(CFP->getType());
501 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
502 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
503 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
505 // The extra reg is for addrmode5.
507 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
508 .addConstantPoolIndex(Idx)
513 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
515 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
518 // If we can do this in a single instruction without a constant pool entry
520 const ConstantInt *CI = cast<ConstantInt>(C);
521 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
522 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
523 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
525 unsigned ImmReg = createResultReg(RC);
526 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
527 TII.get(Opc), ImmReg)
528 .addImm(CI->getZExtValue()));
532 // Use MVN to emit negative constants.
533 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
534 unsigned Imm = (unsigned)~(CI->getSExtValue());
535 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
536 (ARM_AM::getSOImmVal(Imm) != -1);
538 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
539 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
541 unsigned ImmReg = createResultReg(RC);
542 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
543 TII.get(Opc), ImmReg)
549 unsigned ResultReg = 0;
550 if (Subtarget->useMovt(*FuncInfo.MF))
551 ResultReg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
556 // Load from constant pool. For now 32-bit only.
560 // MachineConstantPool wants an explicit alignment.
561 unsigned Align = DL.getPrefTypeAlignment(C->getType());
563 // TODO: Figure out if this is correct.
564 Align = DL.getTypeAllocSize(C->getType());
566 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
567 ResultReg = createResultReg(TLI.getRegClassFor(VT));
569 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
570 TII.get(ARM::t2LDRpci), ResultReg)
571 .addConstantPoolIndex(Idx));
573 // The extra immediate is for addrmode2.
574 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
575 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
576 TII.get(ARM::LDRcp), ResultReg)
577 .addConstantPoolIndex(Idx)
583 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
584 // For now 32-bit only.
585 if (VT != MVT::i32) return 0;
587 Reloc::Model RelocM = TM.getRelocationModel();
588 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
589 const TargetRegisterClass *RC = isThumb2 ?
590 (const TargetRegisterClass*)&ARM::rGPRRegClass :
591 (const TargetRegisterClass*)&ARM::GPRRegClass;
592 unsigned DestReg = createResultReg(RC);
594 // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
595 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
596 bool IsThreadLocal = GVar && GVar->isThreadLocal();
597 if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
599 // Use movw+movt when possible, it avoids constant pool entries.
600 // Non-darwin targets only support static movt relocations in FastISel.
601 if (Subtarget->useMovt(*FuncInfo.MF) &&
602 (Subtarget->isTargetMachO() || RelocM == Reloc::Static)) {
604 unsigned char TF = 0;
605 if (Subtarget->isTargetMachO())
606 TF = ARMII::MO_NONLAZY;
610 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
613 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
616 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
617 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
619 // MachineConstantPool wants an explicit alignment.
620 unsigned Align = DL.getPrefTypeAlignment(GV->getType());
622 // TODO: Figure out if this is correct.
623 Align = DL.getTypeAllocSize(GV->getType());
626 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
627 return ARMLowerPICELF(GV, Align, VT);
630 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
631 (Subtarget->isThumb() ? 4 : 8);
632 unsigned Id = AFI->createPICLabelUId();
633 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
636 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
639 MachineInstrBuilder MIB;
641 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
642 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
643 DestReg).addConstantPoolIndex(Idx);
644 if (RelocM == Reloc::PIC_)
646 AddOptionalDefs(MIB);
648 // The extra immediate is for addrmode2.
649 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
650 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
651 TII.get(ARM::LDRcp), DestReg)
652 .addConstantPoolIndex(Idx)
654 AddOptionalDefs(MIB);
656 if (RelocM == Reloc::PIC_) {
657 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
658 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
660 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
661 DbgLoc, TII.get(Opc), NewDestReg)
664 AddOptionalDefs(MIB);
671 MachineInstrBuilder MIB;
672 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
674 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
675 TII.get(ARM::t2LDRi12), NewDestReg)
679 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
680 TII.get(ARM::LDRi12), NewDestReg)
683 DestReg = NewDestReg;
684 AddOptionalDefs(MIB);
690 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
691 EVT CEVT = TLI.getValueType(C->getType(), true);
693 // Only handle simple types.
694 if (!CEVT.isSimple()) return 0;
695 MVT VT = CEVT.getSimpleVT();
697 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
698 return ARMMaterializeFP(CFP, VT);
699 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
700 return ARMMaterializeGV(GV, VT);
701 else if (isa<ConstantInt>(C))
702 return ARMMaterializeInt(C, VT);
707 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
709 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
710 // Don't handle dynamic allocas.
711 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
714 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
716 DenseMap<const AllocaInst*, int>::iterator SI =
717 FuncInfo.StaticAllocaMap.find(AI);
719 // This will get lowered later into the correct offsets and registers
720 // via rewriteXFrameIndex.
721 if (SI != FuncInfo.StaticAllocaMap.end()) {
722 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
723 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
724 unsigned ResultReg = createResultReg(RC);
725 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
727 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
728 TII.get(Opc), ResultReg)
729 .addFrameIndex(SI->second)
737 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
738 EVT evt = TLI.getValueType(Ty, true);
740 // Only handle simple types.
741 if (evt == MVT::Other || !evt.isSimple()) return false;
742 VT = evt.getSimpleVT();
744 // Handle all legal types, i.e. a register that will directly hold this
746 return TLI.isTypeLegal(VT);
749 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
750 if (isTypeLegal(Ty, VT)) return true;
752 // If this is a type than can be sign or zero-extended to a basic operation
753 // go ahead and accept it now.
754 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
760 // Computes the address to get to an object.
761 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
762 // Some boilerplate from the X86 FastISel.
763 const User *U = nullptr;
764 unsigned Opcode = Instruction::UserOp1;
765 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
766 // Don't walk into other basic blocks unless the object is an alloca from
767 // another block, otherwise it may not have a virtual register assigned.
768 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
769 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
770 Opcode = I->getOpcode();
773 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
774 Opcode = C->getOpcode();
778 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
779 if (Ty->getAddressSpace() > 255)
780 // Fast instruction selection doesn't support the special
787 case Instruction::BitCast:
788 // Look through bitcasts.
789 return ARMComputeAddress(U->getOperand(0), Addr);
790 case Instruction::IntToPtr:
791 // Look past no-op inttoptrs.
792 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
793 return ARMComputeAddress(U->getOperand(0), Addr);
795 case Instruction::PtrToInt:
796 // Look past no-op ptrtoints.
797 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
798 return ARMComputeAddress(U->getOperand(0), Addr);
800 case Instruction::GetElementPtr: {
801 Address SavedAddr = Addr;
802 int TmpOffset = Addr.Offset;
804 // Iterate through the GEP folding the constants into offsets where
806 gep_type_iterator GTI = gep_type_begin(U);
807 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
808 i != e; ++i, ++GTI) {
809 const Value *Op = *i;
810 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
811 const StructLayout *SL = DL.getStructLayout(STy);
812 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
813 TmpOffset += SL->getElementOffset(Idx);
815 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
817 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
818 // Constant-offset addressing.
819 TmpOffset += CI->getSExtValue() * S;
822 if (canFoldAddIntoGEP(U, Op)) {
823 // A compatible add with a constant operand. Fold the constant.
825 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
826 TmpOffset += CI->getSExtValue() * S;
827 // Iterate on the other operand.
828 Op = cast<AddOperator>(Op)->getOperand(0);
832 goto unsupported_gep;
837 // Try to grab the base operand now.
838 Addr.Offset = TmpOffset;
839 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
841 // We failed, restore everything and try the other options.
847 case Instruction::Alloca: {
848 const AllocaInst *AI = cast<AllocaInst>(Obj);
849 DenseMap<const AllocaInst*, int>::iterator SI =
850 FuncInfo.StaticAllocaMap.find(AI);
851 if (SI != FuncInfo.StaticAllocaMap.end()) {
852 Addr.BaseType = Address::FrameIndexBase;
853 Addr.Base.FI = SI->second;
860 // Try to get this in a register if nothing else has worked.
861 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
862 return Addr.Base.Reg != 0;
865 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
866 bool needsLowering = false;
867 switch (VT.SimpleTy) {
868 default: llvm_unreachable("Unhandled load/store type!");
874 // Integer loads/stores handle 12-bit offsets.
875 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
876 // Handle negative offsets.
877 if (needsLowering && isThumb2)
878 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
881 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
882 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
887 // Floating point operands handle 8-bit offsets.
888 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
892 // If this is a stack pointer and the offset needs to be simplified then
893 // put the alloca address into a register, set the base type back to
894 // register and continue. This should almost never happen.
895 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
896 const TargetRegisterClass *RC = isThumb2 ?
897 (const TargetRegisterClass*)&ARM::tGPRRegClass :
898 (const TargetRegisterClass*)&ARM::GPRRegClass;
899 unsigned ResultReg = createResultReg(RC);
900 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
901 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
902 TII.get(Opc), ResultReg)
903 .addFrameIndex(Addr.Base.FI)
905 Addr.Base.Reg = ResultReg;
906 Addr.BaseType = Address::RegBase;
909 // Since the offset is too large for the load/store instruction
910 // get the reg+offset into a register.
912 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
913 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
918 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
919 const MachineInstrBuilder &MIB,
920 unsigned Flags, bool useAM3) {
921 // addrmode5 output depends on the selection dag addressing dividing the
922 // offset by 4 that it then later multiplies. Do this here as well.
923 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
926 // Frame base works a bit differently. Handle it separately.
927 if (Addr.BaseType == Address::FrameIndexBase) {
928 int FI = Addr.Base.FI;
929 int Offset = Addr.Offset;
930 MachineMemOperand *MMO =
931 FuncInfo.MF->getMachineMemOperand(
932 MachinePointerInfo::getFixedStack(FI, Offset),
934 MFI.getObjectSize(FI),
935 MFI.getObjectAlignment(FI));
936 // Now add the rest of the operands.
937 MIB.addFrameIndex(FI);
939 // ARM halfword load/stores and signed byte loads need an additional
942 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
946 MIB.addImm(Addr.Offset);
948 MIB.addMemOperand(MMO);
950 // Now add the rest of the operands.
951 MIB.addReg(Addr.Base.Reg);
953 // ARM halfword load/stores and signed byte loads need an additional
956 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
960 MIB.addImm(Addr.Offset);
963 AddOptionalDefs(MIB);
966 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
967 unsigned Alignment, bool isZExt, bool allocReg) {
970 bool needVMOV = false;
971 const TargetRegisterClass *RC;
972 switch (VT.SimpleTy) {
973 // This is mostly going to be Neon/vector support.
974 default: return false;
978 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
979 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
981 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
990 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
993 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
997 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
998 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
1000 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1002 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1005 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1008 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1012 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1015 Opc = ARM::t2LDRi12;
1019 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1022 if (!Subtarget->hasVFP2()) return false;
1023 // Unaligned loads need special handling. Floats require word-alignment.
1024 if (Alignment && Alignment < 4) {
1027 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1028 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1031 RC = TLI.getRegClassFor(VT);
1035 if (!Subtarget->hasVFP2()) return false;
1036 // FIXME: Unaligned loads need special handling. Doublewords require
1038 if (Alignment && Alignment < 4)
1042 RC = TLI.getRegClassFor(VT);
1045 // Simplify this down to something we can handle.
1046 ARMSimplifyAddress(Addr, VT, useAM3);
1048 // Create the base instruction, then add the operands.
1050 ResultReg = createResultReg(RC);
1051 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1052 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1053 TII.get(Opc), ResultReg);
1054 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1056 // If we had an unaligned load of a float we've converted it to an regular
1057 // load. Now we must move from the GRP to the FP register.
1059 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1060 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1061 TII.get(ARM::VMOVSR), MoveReg)
1062 .addReg(ResultReg));
1063 ResultReg = MoveReg;
1068 bool ARMFastISel::SelectLoad(const Instruction *I) {
1069 // Atomic loads need special handling.
1070 if (cast<LoadInst>(I)->isAtomic())
1073 // Verify we have a legal type before going any further.
1075 if (!isLoadTypeLegal(I->getType(), VT))
1078 // See if we can handle this address.
1080 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1083 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1085 UpdateValueMap(I, ResultReg);
1089 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1090 unsigned Alignment) {
1092 bool useAM3 = false;
1093 switch (VT.SimpleTy) {
1094 // This is mostly going to be Neon/vector support.
1095 default: return false;
1097 unsigned Res = createResultReg(isThumb2 ?
1098 (const TargetRegisterClass*)&ARM::tGPRRegClass :
1099 (const TargetRegisterClass*)&ARM::GPRRegClass);
1100 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1101 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1102 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1104 .addReg(SrcReg).addImm(1));
1106 } // Fallthrough here.
1109 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1110 StrOpc = ARM::t2STRBi8;
1112 StrOpc = ARM::t2STRBi12;
1114 StrOpc = ARM::STRBi12;
1118 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1122 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1123 StrOpc = ARM::t2STRHi8;
1125 StrOpc = ARM::t2STRHi12;
1132 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1136 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1137 StrOpc = ARM::t2STRi8;
1139 StrOpc = ARM::t2STRi12;
1141 StrOpc = ARM::STRi12;
1145 if (!Subtarget->hasVFP2()) return false;
1146 // Unaligned stores need special handling. Floats require word-alignment.
1147 if (Alignment && Alignment < 4) {
1148 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1149 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1150 TII.get(ARM::VMOVRS), MoveReg)
1154 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1156 StrOpc = ARM::VSTRS;
1160 if (!Subtarget->hasVFP2()) return false;
1161 // FIXME: Unaligned stores need special handling. Doublewords require
1163 if (Alignment && Alignment < 4)
1166 StrOpc = ARM::VSTRD;
1169 // Simplify this down to something we can handle.
1170 ARMSimplifyAddress(Addr, VT, useAM3);
1172 // Create the base instruction, then add the operands.
1173 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1174 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1177 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1181 bool ARMFastISel::SelectStore(const Instruction *I) {
1182 Value *Op0 = I->getOperand(0);
1183 unsigned SrcReg = 0;
1185 // Atomic stores need special handling.
1186 if (cast<StoreInst>(I)->isAtomic())
1189 // Verify we have a legal type before going any further.
1191 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1194 // Get the value to be stored into a register.
1195 SrcReg = getRegForValue(Op0);
1196 if (SrcReg == 0) return false;
1198 // See if we can handle this address.
1200 if (!ARMComputeAddress(I->getOperand(1), Addr))
1203 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1208 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1210 // Needs two compares...
1211 case CmpInst::FCMP_ONE:
1212 case CmpInst::FCMP_UEQ:
1214 // AL is our "false" for now. The other two need more compares.
1216 case CmpInst::ICMP_EQ:
1217 case CmpInst::FCMP_OEQ:
1219 case CmpInst::ICMP_SGT:
1220 case CmpInst::FCMP_OGT:
1222 case CmpInst::ICMP_SGE:
1223 case CmpInst::FCMP_OGE:
1225 case CmpInst::ICMP_UGT:
1226 case CmpInst::FCMP_UGT:
1228 case CmpInst::FCMP_OLT:
1230 case CmpInst::ICMP_ULE:
1231 case CmpInst::FCMP_OLE:
1233 case CmpInst::FCMP_ORD:
1235 case CmpInst::FCMP_UNO:
1237 case CmpInst::FCMP_UGE:
1239 case CmpInst::ICMP_SLT:
1240 case CmpInst::FCMP_ULT:
1242 case CmpInst::ICMP_SLE:
1243 case CmpInst::FCMP_ULE:
1245 case CmpInst::FCMP_UNE:
1246 case CmpInst::ICMP_NE:
1248 case CmpInst::ICMP_UGE:
1250 case CmpInst::ICMP_ULT:
1255 bool ARMFastISel::SelectBranch(const Instruction *I) {
1256 const BranchInst *BI = cast<BranchInst>(I);
1257 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1258 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1260 // Simple branch support.
1262 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1264 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1265 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1267 // Get the compare predicate.
1268 // Try to take advantage of fallthrough opportunities.
1269 CmpInst::Predicate Predicate = CI->getPredicate();
1270 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1271 std::swap(TBB, FBB);
1272 Predicate = CmpInst::getInversePredicate(Predicate);
1275 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1277 // We may not handle every CC for now.
1278 if (ARMPred == ARMCC::AL) return false;
1280 // Emit the compare.
1281 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1284 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1285 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1286 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1287 FastEmitBranch(FBB, DbgLoc);
1288 FuncInfo.MBB->addSuccessor(TBB);
1291 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1293 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1294 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1295 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1296 unsigned OpReg = getRegForValue(TI->getOperand(0));
1297 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1298 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1300 .addReg(OpReg).addImm(1));
1302 unsigned CCMode = ARMCC::NE;
1303 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1304 std::swap(TBB, FBB);
1308 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1309 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1310 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1312 FastEmitBranch(FBB, DbgLoc);
1313 FuncInfo.MBB->addSuccessor(TBB);
1316 } else if (const ConstantInt *CI =
1317 dyn_cast<ConstantInt>(BI->getCondition())) {
1318 uint64_t Imm = CI->getZExtValue();
1319 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1320 FastEmitBranch(Target, DbgLoc);
1324 unsigned CmpReg = getRegForValue(BI->getCondition());
1325 if (CmpReg == 0) return false;
1327 // We've been divorced from our compare! Our block was split, and
1328 // now our compare lives in a predecessor block. We musn't
1329 // re-compare here, as the children of the compare aren't guaranteed
1330 // live across the block boundary (we *could* check for this).
1331 // Regardless, the compare has been done in the predecessor block,
1332 // and it left a value for us in a virtual register. Ergo, we test
1333 // the one-bit value left in the virtual register.
1334 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1335 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1337 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1341 unsigned CCMode = ARMCC::NE;
1342 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1343 std::swap(TBB, FBB);
1347 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1348 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1349 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1350 FastEmitBranch(FBB, DbgLoc);
1351 FuncInfo.MBB->addSuccessor(TBB);
1355 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1356 unsigned AddrReg = getRegForValue(I->getOperand(0));
1357 if (AddrReg == 0) return false;
1359 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1360 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1361 TII.get(Opc)).addReg(AddrReg));
1363 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1364 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1365 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1370 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1372 Type *Ty = Src1Value->getType();
1373 EVT SrcEVT = TLI.getValueType(Ty, true);
1374 if (!SrcEVT.isSimple()) return false;
1375 MVT SrcVT = SrcEVT.getSimpleVT();
1377 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1378 if (isFloat && !Subtarget->hasVFP2())
1381 // Check to see if the 2nd operand is a constant that we can encode directly
1384 bool UseImm = false;
1385 bool isNegativeImm = false;
1386 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1387 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1388 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1389 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1391 const APInt &CIVal = ConstInt->getValue();
1392 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1393 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1394 // then a cmn, because there is no way to represent 2147483648 as a
1395 // signed 32-bit int.
1396 if (Imm < 0 && Imm != (int)0x80000000) {
1397 isNegativeImm = true;
1400 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1401 (ARM_AM::getSOImmVal(Imm) != -1);
1403 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1404 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1405 if (ConstFP->isZero() && !ConstFP->isNegative())
1411 bool needsExt = false;
1412 switch (SrcVT.SimpleTy) {
1413 default: return false;
1414 // TODO: Verify compares.
1417 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1421 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1427 // Intentional fall-through.
1431 CmpOpc = ARM::t2CMPrr;
1433 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1436 CmpOpc = ARM::CMPrr;
1438 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1443 unsigned SrcReg1 = getRegForValue(Src1Value);
1444 if (SrcReg1 == 0) return false;
1446 unsigned SrcReg2 = 0;
1448 SrcReg2 = getRegForValue(Src2Value);
1449 if (SrcReg2 == 0) return false;
1452 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1454 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1455 if (SrcReg1 == 0) return false;
1457 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1458 if (SrcReg2 == 0) return false;
1462 const MCInstrDesc &II = TII.get(CmpOpc);
1463 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1465 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1466 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1467 .addReg(SrcReg1).addReg(SrcReg2));
1469 MachineInstrBuilder MIB;
1470 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1473 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1476 AddOptionalDefs(MIB);
1479 // For floating point we need to move the result to a comparison register
1480 // that we can then use for branches.
1481 if (Ty->isFloatTy() || Ty->isDoubleTy())
1482 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1483 TII.get(ARM::FMSTAT)));
1487 bool ARMFastISel::SelectCmp(const Instruction *I) {
1488 const CmpInst *CI = cast<CmpInst>(I);
1490 // Get the compare predicate.
1491 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1493 // We may not handle every CC for now.
1494 if (ARMPred == ARMCC::AL) return false;
1496 // Emit the compare.
1497 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1500 // Now set a register based on the comparison. Explicitly set the predicates
1502 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1503 const TargetRegisterClass *RC = isThumb2 ?
1504 (const TargetRegisterClass*)&ARM::rGPRRegClass :
1505 (const TargetRegisterClass*)&ARM::GPRRegClass;
1506 unsigned DestReg = createResultReg(RC);
1507 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1508 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1509 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1510 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
1511 .addReg(ZeroReg).addImm(1)
1512 .addImm(ARMPred).addReg(ARM::CPSR);
1514 UpdateValueMap(I, DestReg);
1518 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1519 // Make sure we have VFP and that we're extending float to double.
1520 if (!Subtarget->hasVFP2()) return false;
1522 Value *V = I->getOperand(0);
1523 if (!I->getType()->isDoubleTy() ||
1524 !V->getType()->isFloatTy()) return false;
1526 unsigned Op = getRegForValue(V);
1527 if (Op == 0) return false;
1529 unsigned Result = createResultReg(&ARM::DPRRegClass);
1530 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1531 TII.get(ARM::VCVTDS), Result)
1533 UpdateValueMap(I, Result);
1537 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1538 // Make sure we have VFP and that we're truncating double to float.
1539 if (!Subtarget->hasVFP2()) return false;
1541 Value *V = I->getOperand(0);
1542 if (!(I->getType()->isFloatTy() &&
1543 V->getType()->isDoubleTy())) return false;
1545 unsigned Op = getRegForValue(V);
1546 if (Op == 0) return false;
1548 unsigned Result = createResultReg(&ARM::SPRRegClass);
1549 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1550 TII.get(ARM::VCVTSD), Result)
1552 UpdateValueMap(I, Result);
1556 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1557 // Make sure we have VFP.
1558 if (!Subtarget->hasVFP2()) return false;
1561 Type *Ty = I->getType();
1562 if (!isTypeLegal(Ty, DstVT))
1565 Value *Src = I->getOperand(0);
1566 EVT SrcEVT = TLI.getValueType(Src->getType(), true);
1567 if (!SrcEVT.isSimple())
1569 MVT SrcVT = SrcEVT.getSimpleVT();
1570 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1573 unsigned SrcReg = getRegForValue(Src);
1574 if (SrcReg == 0) return false;
1576 // Handle sign-extension.
1577 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1578 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1579 /*isZExt*/!isSigned);
1580 if (SrcReg == 0) return false;
1583 // The conversion routine works on fp-reg to fp-reg and the operand above
1584 // was an integer, move it to the fp registers if possible.
1585 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1586 if (FP == 0) return false;
1589 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1590 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1593 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1594 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1595 TII.get(Opc), ResultReg).addReg(FP));
1596 UpdateValueMap(I, ResultReg);
1600 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1601 // Make sure we have VFP.
1602 if (!Subtarget->hasVFP2()) return false;
1605 Type *RetTy = I->getType();
1606 if (!isTypeLegal(RetTy, DstVT))
1609 unsigned Op = getRegForValue(I->getOperand(0));
1610 if (Op == 0) return false;
1613 Type *OpTy = I->getOperand(0)->getType();
1614 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1615 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1618 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1619 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1620 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1621 TII.get(Opc), ResultReg).addReg(Op));
1623 // This result needs to be in an integer register, but the conversion only
1624 // takes place in fp-regs.
1625 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1626 if (IntReg == 0) return false;
1628 UpdateValueMap(I, IntReg);
1632 bool ARMFastISel::SelectSelect(const Instruction *I) {
1634 if (!isTypeLegal(I->getType(), VT))
1637 // Things need to be register sized for register moves.
1638 if (VT != MVT::i32) return false;
1640 unsigned CondReg = getRegForValue(I->getOperand(0));
1641 if (CondReg == 0) return false;
1642 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1643 if (Op1Reg == 0) return false;
1645 // Check to see if we can use an immediate in the conditional move.
1647 bool UseImm = false;
1648 bool isNegativeImm = false;
1649 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1650 assert (VT == MVT::i32 && "Expecting an i32.");
1651 Imm = (int)ConstInt->getValue().getZExtValue();
1653 isNegativeImm = true;
1656 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1657 (ARM_AM::getSOImmVal(Imm) != -1);
1660 unsigned Op2Reg = 0;
1662 Op2Reg = getRegForValue(I->getOperand(2));
1663 if (Op2Reg == 0) return false;
1666 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1667 CondReg = constrainOperandRegClass(TII.get(CmpOpc), CondReg, 0);
1669 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
1674 const TargetRegisterClass *RC;
1676 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1677 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1679 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1681 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1683 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1685 unsigned ResultReg = createResultReg(RC);
1687 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1688 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1689 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1696 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1697 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1704 UpdateValueMap(I, ResultReg);
1708 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1710 Type *Ty = I->getType();
1711 if (!isTypeLegal(Ty, VT))
1714 // If we have integer div support we should have selected this automagically.
1715 // In case we have a real miss go ahead and return false and we'll pick
1717 if (Subtarget->hasDivide()) return false;
1719 // Otherwise emit a libcall.
1720 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1722 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1723 else if (VT == MVT::i16)
1724 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1725 else if (VT == MVT::i32)
1726 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1727 else if (VT == MVT::i64)
1728 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1729 else if (VT == MVT::i128)
1730 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1731 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1733 return ARMEmitLibcall(I, LC);
1736 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1738 Type *Ty = I->getType();
1739 if (!isTypeLegal(Ty, VT))
1742 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1744 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1745 else if (VT == MVT::i16)
1746 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1747 else if (VT == MVT::i32)
1748 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1749 else if (VT == MVT::i64)
1750 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1751 else if (VT == MVT::i128)
1752 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1753 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1755 return ARMEmitLibcall(I, LC);
1758 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1759 EVT DestVT = TLI.getValueType(I->getType(), true);
1761 // We can get here in the case when we have a binary operation on a non-legal
1762 // type and the target independent selector doesn't know how to handle it.
1763 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1767 switch (ISDOpcode) {
1768 default: return false;
1770 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1773 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1776 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1780 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1781 if (SrcReg1 == 0) return false;
1783 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1784 // in the instruction, rather then materializing the value in a register.
1785 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1786 if (SrcReg2 == 0) return false;
1788 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1789 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1790 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1791 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1792 TII.get(Opc), ResultReg)
1793 .addReg(SrcReg1).addReg(SrcReg2));
1794 UpdateValueMap(I, ResultReg);
1798 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1799 EVT FPVT = TLI.getValueType(I->getType(), true);
1800 if (!FPVT.isSimple()) return false;
1801 MVT VT = FPVT.getSimpleVT();
1803 // We can get here in the case when we want to use NEON for our fp
1804 // operations, but can't figure out how to. Just use the vfp instructions
1806 // FIXME: It'd be nice to use NEON instructions.
1807 Type *Ty = I->getType();
1808 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1809 if (isFloat && !Subtarget->hasVFP2())
1813 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1814 switch (ISDOpcode) {
1815 default: return false;
1817 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1820 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1823 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1826 unsigned Op1 = getRegForValue(I->getOperand(0));
1827 if (Op1 == 0) return false;
1829 unsigned Op2 = getRegForValue(I->getOperand(1));
1830 if (Op2 == 0) return false;
1832 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1833 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1834 TII.get(Opc), ResultReg)
1835 .addReg(Op1).addReg(Op2));
1836 UpdateValueMap(I, ResultReg);
1840 // Call Handling Code
1842 // This is largely taken directly from CCAssignFnForNode
1843 // TODO: We may not support all of this.
1844 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1849 llvm_unreachable("Unsupported calling convention");
1850 case CallingConv::Fast:
1851 if (Subtarget->hasVFP2() && !isVarArg) {
1852 if (!Subtarget->isAAPCS_ABI())
1853 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1854 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1855 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1858 case CallingConv::C:
1859 // Use target triple & subtarget features to do actual dispatch.
1860 if (Subtarget->isAAPCS_ABI()) {
1861 if (Subtarget->hasVFP2() &&
1862 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1863 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1865 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1867 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1868 case CallingConv::ARM_AAPCS_VFP:
1870 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1871 // Fall through to soft float variant, variadic functions don't
1872 // use hard floating point ABI.
1873 case CallingConv::ARM_AAPCS:
1874 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1875 case CallingConv::ARM_APCS:
1876 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1877 case CallingConv::GHC:
1879 llvm_unreachable("Can't return in GHC call convention");
1881 return CC_ARM_APCS_GHC;
1885 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1886 SmallVectorImpl<unsigned> &ArgRegs,
1887 SmallVectorImpl<MVT> &ArgVTs,
1888 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1889 SmallVectorImpl<unsigned> &RegArgs,
1893 SmallVector<CCValAssign, 16> ArgLocs;
1894 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1895 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1896 CCAssignFnForCall(CC, false, isVarArg));
1898 // Check that we can handle all of the arguments. If we can't, then bail out
1899 // now before we add code to the MBB.
1900 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1901 CCValAssign &VA = ArgLocs[i];
1902 MVT ArgVT = ArgVTs[VA.getValNo()];
1904 // We don't handle NEON/vector parameters yet.
1905 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1908 // Now copy/store arg to correct locations.
1909 if (VA.isRegLoc() && !VA.needsCustom()) {
1911 } else if (VA.needsCustom()) {
1912 // TODO: We need custom lowering for vector (v2f64) args.
1913 if (VA.getLocVT() != MVT::f64 ||
1914 // TODO: Only handle register args for now.
1915 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1918 switch (ArgVT.SimpleTy) {
1927 if (!Subtarget->hasVFP2())
1931 if (!Subtarget->hasVFP2())
1938 // At the point, we are able to handle the call's arguments in fast isel.
1940 // Get a count of how many bytes are to be pushed on the stack.
1941 NumBytes = CCInfo.getNextStackOffset();
1943 // Issue CALLSEQ_START
1944 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1945 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1946 TII.get(AdjStackDown))
1949 // Process the args.
1950 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1951 CCValAssign &VA = ArgLocs[i];
1952 const Value *ArgVal = Args[VA.getValNo()];
1953 unsigned Arg = ArgRegs[VA.getValNo()];
1954 MVT ArgVT = ArgVTs[VA.getValNo()];
1956 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1957 "We don't handle NEON/vector parameters yet.");
1959 // Handle arg promotion, etc.
1960 switch (VA.getLocInfo()) {
1961 case CCValAssign::Full: break;
1962 case CCValAssign::SExt: {
1963 MVT DestVT = VA.getLocVT();
1964 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1965 assert (Arg != 0 && "Failed to emit a sext");
1969 case CCValAssign::AExt:
1970 // Intentional fall-through. Handle AExt and ZExt.
1971 case CCValAssign::ZExt: {
1972 MVT DestVT = VA.getLocVT();
1973 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1974 assert (Arg != 0 && "Failed to emit a zext");
1978 case CCValAssign::BCvt: {
1979 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1980 /*TODO: Kill=*/false);
1981 assert(BC != 0 && "Failed to emit a bitcast!");
1983 ArgVT = VA.getLocVT();
1986 default: llvm_unreachable("Unknown arg promotion!");
1989 // Now copy/store arg to correct locations.
1990 if (VA.isRegLoc() && !VA.needsCustom()) {
1991 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1992 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
1993 RegArgs.push_back(VA.getLocReg());
1994 } else if (VA.needsCustom()) {
1995 // TODO: We need custom lowering for vector (v2f64) args.
1996 assert(VA.getLocVT() == MVT::f64 &&
1997 "Custom lowering for v2f64 args not available");
1999 CCValAssign &NextVA = ArgLocs[++i];
2001 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2002 "We only handle register args!");
2004 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2005 TII.get(ARM::VMOVRRD), VA.getLocReg())
2006 .addReg(NextVA.getLocReg(), RegState::Define)
2008 RegArgs.push_back(VA.getLocReg());
2009 RegArgs.push_back(NextVA.getLocReg());
2011 assert(VA.isMemLoc());
2012 // Need to store on the stack.
2014 // Don't emit stores for undef values.
2015 if (isa<UndefValue>(ArgVal))
2019 Addr.BaseType = Address::RegBase;
2020 Addr.Base.Reg = ARM::SP;
2021 Addr.Offset = VA.getLocMemOffset();
2023 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2024 assert(EmitRet && "Could not emit a store for argument!");
2031 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2032 const Instruction *I, CallingConv::ID CC,
2033 unsigned &NumBytes, bool isVarArg) {
2034 // Issue CALLSEQ_END
2035 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2036 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2037 TII.get(AdjStackUp))
2038 .addImm(NumBytes).addImm(0));
2040 // Now the return value.
2041 if (RetVT != MVT::isVoid) {
2042 SmallVector<CCValAssign, 16> RVLocs;
2043 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2044 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2046 // Copy all of the result registers out of their specified physreg.
2047 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2048 // For this move we copy into two registers and then move into the
2049 // double fp reg we want.
2050 MVT DestVT = RVLocs[0].getValVT();
2051 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2052 unsigned ResultReg = createResultReg(DstRC);
2053 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2054 TII.get(ARM::VMOVDRR), ResultReg)
2055 .addReg(RVLocs[0].getLocReg())
2056 .addReg(RVLocs[1].getLocReg()));
2058 UsedRegs.push_back(RVLocs[0].getLocReg());
2059 UsedRegs.push_back(RVLocs[1].getLocReg());
2061 // Finally update the result.
2062 UpdateValueMap(I, ResultReg);
2064 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2065 MVT CopyVT = RVLocs[0].getValVT();
2067 // Special handling for extended integers.
2068 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2071 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2073 unsigned ResultReg = createResultReg(DstRC);
2074 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2075 TII.get(TargetOpcode::COPY),
2076 ResultReg).addReg(RVLocs[0].getLocReg());
2077 UsedRegs.push_back(RVLocs[0].getLocReg());
2079 // Finally update the result.
2080 UpdateValueMap(I, ResultReg);
2087 bool ARMFastISel::SelectRet(const Instruction *I) {
2088 const ReturnInst *Ret = cast<ReturnInst>(I);
2089 const Function &F = *I->getParent()->getParent();
2091 if (!FuncInfo.CanLowerReturn)
2094 // Build a list of return value registers.
2095 SmallVector<unsigned, 4> RetRegs;
2097 CallingConv::ID CC = F.getCallingConv();
2098 if (Ret->getNumOperands() > 0) {
2099 SmallVector<ISD::OutputArg, 4> Outs;
2100 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
2102 // Analyze operands of the call, assigning locations to each operand.
2103 SmallVector<CCValAssign, 16> ValLocs;
2104 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2105 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2108 const Value *RV = Ret->getOperand(0);
2109 unsigned Reg = getRegForValue(RV);
2113 // Only handle a single return value for now.
2114 if (ValLocs.size() != 1)
2117 CCValAssign &VA = ValLocs[0];
2119 // Don't bother handling odd stuff for now.
2120 if (VA.getLocInfo() != CCValAssign::Full)
2122 // Only handle register returns for now.
2126 unsigned SrcReg = Reg + VA.getValNo();
2127 EVT RVEVT = TLI.getValueType(RV->getType());
2128 if (!RVEVT.isSimple()) return false;
2129 MVT RVVT = RVEVT.getSimpleVT();
2130 MVT DestVT = VA.getValVT();
2131 // Special handling for extended integers.
2132 if (RVVT != DestVT) {
2133 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2136 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2138 // Perform extension if flagged as either zext or sext. Otherwise, do
2140 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2141 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2142 if (SrcReg == 0) return false;
2147 unsigned DstReg = VA.getLocReg();
2148 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2149 // Avoid a cross-class copy. This is very unlikely.
2150 if (!SrcRC->contains(DstReg))
2152 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2153 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2155 // Add register to return instruction.
2156 RetRegs.push_back(VA.getLocReg());
2159 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2160 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2162 AddOptionalDefs(MIB);
2163 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2164 MIB.addReg(RetRegs[i], RegState::Implicit);
2168 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2170 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2172 return isThumb2 ? ARM::tBL : ARM::BL;
2175 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2176 // Manually compute the global's type to avoid building it when unnecessary.
2177 Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2178 EVT LCREVT = TLI.getValueType(GVTy);
2179 if (!LCREVT.isSimple()) return 0;
2181 GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
2182 GlobalValue::ExternalLinkage, nullptr,
2184 assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2185 return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2188 // A quick function that will emit a call for a named libcall in F with the
2189 // vector of passed arguments for the Instruction in I. We can assume that we
2190 // can emit a call for any libcall we can produce. This is an abridged version
2191 // of the full call infrastructure since we won't need to worry about things
2192 // like computed function pointers or strange arguments at call sites.
2193 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2195 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2196 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2198 // Handle *simple* calls for now.
2199 Type *RetTy = I->getType();
2201 if (RetTy->isVoidTy())
2202 RetVT = MVT::isVoid;
2203 else if (!isTypeLegal(RetTy, RetVT))
2206 // Can't handle non-double multi-reg retvals.
2207 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2208 SmallVector<CCValAssign, 16> RVLocs;
2209 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2210 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2211 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2215 // Set up the argument vectors.
2216 SmallVector<Value*, 8> Args;
2217 SmallVector<unsigned, 8> ArgRegs;
2218 SmallVector<MVT, 8> ArgVTs;
2219 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2220 Args.reserve(I->getNumOperands());
2221 ArgRegs.reserve(I->getNumOperands());
2222 ArgVTs.reserve(I->getNumOperands());
2223 ArgFlags.reserve(I->getNumOperands());
2224 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2225 Value *Op = I->getOperand(i);
2226 unsigned Arg = getRegForValue(Op);
2227 if (Arg == 0) return false;
2229 Type *ArgTy = Op->getType();
2231 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2233 ISD::ArgFlagsTy Flags;
2234 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2235 Flags.setOrigAlign(OriginalAlignment);
2238 ArgRegs.push_back(Arg);
2239 ArgVTs.push_back(ArgVT);
2240 ArgFlags.push_back(Flags);
2243 // Handle the arguments now that we've gotten them.
2244 SmallVector<unsigned, 4> RegArgs;
2246 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2247 RegArgs, CC, NumBytes, false))
2250 unsigned CalleeReg = 0;
2251 if (EnableARMLongCalls) {
2252 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2253 if (CalleeReg == 0) return false;
2257 unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
2258 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2259 DbgLoc, TII.get(CallOpc));
2260 // BL / BLX don't take a predicate, but tBL / tBLX do.
2262 AddDefaultPred(MIB);
2263 if (EnableARMLongCalls)
2264 MIB.addReg(CalleeReg);
2266 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2268 // Add implicit physical register uses to the call.
2269 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2270 MIB.addReg(RegArgs[i], RegState::Implicit);
2272 // Add a register mask with the call-preserved registers.
2273 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2274 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2276 // Finish off the call including any return values.
2277 SmallVector<unsigned, 4> UsedRegs;
2278 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2280 // Set all unused physreg defs as dead.
2281 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2286 bool ARMFastISel::SelectCall(const Instruction *I,
2287 const char *IntrMemName = nullptr) {
2288 const CallInst *CI = cast<CallInst>(I);
2289 const Value *Callee = CI->getCalledValue();
2291 // Can't handle inline asm.
2292 if (isa<InlineAsm>(Callee)) return false;
2294 // Allow SelectionDAG isel to handle tail calls.
2295 if (CI->isTailCall()) return false;
2297 // Check the calling convention.
2298 ImmutableCallSite CS(CI);
2299 CallingConv::ID CC = CS.getCallingConv();
2301 // TODO: Avoid some calling conventions?
2303 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2304 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2305 bool isVarArg = FTy->isVarArg();
2307 // Handle *simple* calls for now.
2308 Type *RetTy = I->getType();
2310 if (RetTy->isVoidTy())
2311 RetVT = MVT::isVoid;
2312 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2313 RetVT != MVT::i8 && RetVT != MVT::i1)
2316 // Can't handle non-double multi-reg retvals.
2317 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2318 RetVT != MVT::i16 && RetVT != MVT::i32) {
2319 SmallVector<CCValAssign, 16> RVLocs;
2320 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2321 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2322 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2326 // Set up the argument vectors.
2327 SmallVector<Value*, 8> Args;
2328 SmallVector<unsigned, 8> ArgRegs;
2329 SmallVector<MVT, 8> ArgVTs;
2330 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2331 unsigned arg_size = CS.arg_size();
2332 Args.reserve(arg_size);
2333 ArgRegs.reserve(arg_size);
2334 ArgVTs.reserve(arg_size);
2335 ArgFlags.reserve(arg_size);
2336 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2338 // If we're lowering a memory intrinsic instead of a regular call, skip the
2339 // last two arguments, which shouldn't be passed to the underlying function.
2340 if (IntrMemName && e-i <= 2)
2343 ISD::ArgFlagsTy Flags;
2344 unsigned AttrInd = i - CS.arg_begin() + 1;
2345 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2347 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2350 // FIXME: Only handle *easy* calls for now.
2351 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2352 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2353 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2354 CS.paramHasAttr(AttrInd, Attribute::ByVal))
2357 Type *ArgTy = (*i)->getType();
2359 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2363 unsigned Arg = getRegForValue(*i);
2367 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2368 Flags.setOrigAlign(OriginalAlignment);
2371 ArgRegs.push_back(Arg);
2372 ArgVTs.push_back(ArgVT);
2373 ArgFlags.push_back(Flags);
2376 // Handle the arguments now that we've gotten them.
2377 SmallVector<unsigned, 4> RegArgs;
2379 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2380 RegArgs, CC, NumBytes, isVarArg))
2383 bool UseReg = false;
2384 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2385 if (!GV || EnableARMLongCalls) UseReg = true;
2387 unsigned CalleeReg = 0;
2390 CalleeReg = getLibcallReg(IntrMemName);
2392 CalleeReg = getRegForValue(Callee);
2394 if (CalleeReg == 0) return false;
2398 unsigned CallOpc = ARMSelectCallOp(UseReg);
2399 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2400 DbgLoc, TII.get(CallOpc));
2402 unsigned char OpFlags = 0;
2404 // Add MO_PLT for global address or external symbol in the PIC relocation
2406 if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_)
2407 OpFlags = ARMII::MO_PLT;
2409 // ARM calls don't take a predicate, but tBL / tBLX do.
2411 AddDefaultPred(MIB);
2413 MIB.addReg(CalleeReg);
2414 else if (!IntrMemName)
2415 MIB.addGlobalAddress(GV, 0, OpFlags);
2417 MIB.addExternalSymbol(IntrMemName, OpFlags);
2419 // Add implicit physical register uses to the call.
2420 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2421 MIB.addReg(RegArgs[i], RegState::Implicit);
2423 // Add a register mask with the call-preserved registers.
2424 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2425 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2427 // Finish off the call including any return values.
2428 SmallVector<unsigned, 4> UsedRegs;
2429 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2432 // Set all unused physreg defs as dead.
2433 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2438 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2442 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2443 uint64_t Len, unsigned Alignment) {
2444 // Make sure we don't bloat code by inlining very large memcpy's.
2445 if (!ARMIsMemCpySmall(Len))
2450 if (!Alignment || Alignment >= 4) {
2456 assert (Len == 1 && "Expected a length of 1!");
2460 // Bound based on alignment.
2461 if (Len >= 2 && Alignment == 2)
2470 RV = ARMEmitLoad(VT, ResultReg, Src);
2471 assert (RV == true && "Should be able to handle this load.");
2472 RV = ARMEmitStore(VT, ResultReg, Dest);
2473 assert (RV == true && "Should be able to handle this store.");
2476 unsigned Size = VT.getSizeInBits()/8;
2478 Dest.Offset += Size;
2485 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2486 // FIXME: Handle more intrinsics.
2487 switch (I.getIntrinsicID()) {
2488 default: return false;
2489 case Intrinsic::frameaddress: {
2490 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2491 MFI->setFrameAddressIsTaken(true);
2494 const TargetRegisterClass *RC;
2496 LdrOpc = ARM::t2LDRi12;
2497 RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2499 LdrOpc = ARM::LDRi12;
2500 RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2503 const ARMBaseRegisterInfo *RegInfo =
2504 static_cast<const ARMBaseRegisterInfo *>(
2505 TM.getSubtargetImpl()->getRegisterInfo());
2506 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2507 unsigned SrcReg = FramePtr;
2509 // Recursively load frame address
2515 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2517 DestReg = createResultReg(RC);
2518 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2519 TII.get(LdrOpc), DestReg)
2520 .addReg(SrcReg).addImm(0));
2523 UpdateValueMap(&I, SrcReg);
2526 case Intrinsic::memcpy:
2527 case Intrinsic::memmove: {
2528 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2529 // Don't handle volatile.
2530 if (MTI.isVolatile())
2533 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2534 // we would emit dead code because we don't currently handle memmoves.
2535 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2536 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2537 // Small memcpy's are common enough that we want to do them without a call
2539 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2540 if (ARMIsMemCpySmall(Len)) {
2542 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2543 !ARMComputeAddress(MTI.getRawSource(), Src))
2545 unsigned Alignment = MTI.getAlignment();
2546 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2551 if (!MTI.getLength()->getType()->isIntegerTy(32))
2554 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2557 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2558 return SelectCall(&I, IntrMemName);
2560 case Intrinsic::memset: {
2561 const MemSetInst &MSI = cast<MemSetInst>(I);
2562 // Don't handle volatile.
2563 if (MSI.isVolatile())
2566 if (!MSI.getLength()->getType()->isIntegerTy(32))
2569 if (MSI.getDestAddressSpace() > 255)
2572 return SelectCall(&I, "memset");
2574 case Intrinsic::trap: {
2575 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
2576 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2582 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2583 // The high bits for a type smaller than the register size are assumed to be
2585 Value *Op = I->getOperand(0);
2588 SrcVT = TLI.getValueType(Op->getType(), true);
2589 DestVT = TLI.getValueType(I->getType(), true);
2591 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2593 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2596 unsigned SrcReg = getRegForValue(Op);
2597 if (!SrcReg) return false;
2599 // Because the high bits are undefined, a truncate doesn't generate
2601 UpdateValueMap(I, SrcReg);
2605 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2607 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2609 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2612 // Table of which combinations can be emitted as a single instruction,
2613 // and which will require two.
2614 static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2616 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2617 // ext: s z s z s z s z
2618 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2619 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2620 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2623 // Target registers for:
2624 // - For ARM can never be PC.
2625 // - For 16-bit Thumb are restricted to lower 8 registers.
2626 // - For 32-bit Thumb are restricted to non-SP and non-PC.
2627 static const TargetRegisterClass *RCTbl[2][2] = {
2628 // Instructions: Two Single
2629 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2630 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2633 // Table governing the instruction(s) to be emitted.
2634 static const struct InstructionTable {
2636 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2637 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2638 uint32_t Imm : 8; // All instructions have either a shift or a mask.
2639 } IT[2][2][3][2] = {
2640 { // Two instructions (first is left shift, second is in this table).
2641 { // ARM Opc S Shift Imm
2642 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2643 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2644 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2645 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2646 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2647 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2649 { // Thumb Opc S Shift Imm
2650 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2651 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2652 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2653 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2654 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2655 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2658 { // Single instruction.
2659 { // ARM Opc S Shift Imm
2660 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2661 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2662 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2663 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2664 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2665 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2667 { // Thumb Opc S Shift Imm
2668 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2669 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2670 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2671 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2672 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2673 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2678 unsigned SrcBits = SrcVT.getSizeInBits();
2679 unsigned DestBits = DestVT.getSizeInBits();
2681 assert((SrcBits < DestBits) && "can only extend to larger types");
2682 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2683 "other sizes unimplemented");
2684 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2685 "other sizes unimplemented");
2687 bool hasV6Ops = Subtarget->hasV6Ops();
2688 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2689 assert((Bitness < 3) && "sanity-check table bounds");
2691 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2692 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2693 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2694 unsigned Opc = ITP->Opc;
2695 assert(ARM::KILL != Opc && "Invalid table entry");
2696 unsigned hasS = ITP->hasS;
2697 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2698 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2699 "only MOVsi has shift operand addressing mode");
2700 unsigned Imm = ITP->Imm;
2702 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2703 bool setsCPSR = &ARM::tGPRRegClass == RC;
2704 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2706 // MOVsi encodes shift and immediate in shift operand addressing mode.
2707 // The following condition has the same value when emitting two
2708 // instruction sequences: both are shifts.
2709 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2711 // Either one or two instructions are emitted.
2712 // They're always of the form:
2714 // CPSR is set only by 16-bit Thumb instructions.
2715 // Predicate, if any, is AL.
2716 // S bit, if available, is always 0.
2717 // When two are emitted the first's result will feed as the second's input,
2718 // that value is then dead.
2719 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2720 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2721 ResultReg = createResultReg(RC);
2722 bool isLsl = (0 == Instr) && !isSingleInstr;
2723 unsigned Opcode = isLsl ? LSLOpc : Opc;
2724 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2725 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2726 bool isKill = 1 == Instr;
2727 MachineInstrBuilder MIB = BuildMI(
2728 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2730 MIB.addReg(ARM::CPSR, RegState::Define);
2731 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2732 AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
2735 // Second instruction consumes the first's result.
2742 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2743 // On ARM, in general, integer casts don't involve legal types; this code
2744 // handles promotable integers.
2745 Type *DestTy = I->getType();
2746 Value *Src = I->getOperand(0);
2747 Type *SrcTy = Src->getType();
2749 bool isZExt = isa<ZExtInst>(I);
2750 unsigned SrcReg = getRegForValue(Src);
2751 if (!SrcReg) return false;
2753 EVT SrcEVT, DestEVT;
2754 SrcEVT = TLI.getValueType(SrcTy, true);
2755 DestEVT = TLI.getValueType(DestTy, true);
2756 if (!SrcEVT.isSimple()) return false;
2757 if (!DestEVT.isSimple()) return false;
2759 MVT SrcVT = SrcEVT.getSimpleVT();
2760 MVT DestVT = DestEVT.getSimpleVT();
2761 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2762 if (ResultReg == 0) return false;
2763 UpdateValueMap(I, ResultReg);
2767 bool ARMFastISel::SelectShift(const Instruction *I,
2768 ARM_AM::ShiftOpc ShiftTy) {
2769 // We handle thumb2 mode by target independent selector
2770 // or SelectionDAG ISel.
2774 // Only handle i32 now.
2775 EVT DestVT = TLI.getValueType(I->getType(), true);
2776 if (DestVT != MVT::i32)
2779 unsigned Opc = ARM::MOVsr;
2781 Value *Src2Value = I->getOperand(1);
2782 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2783 ShiftImm = CI->getZExtValue();
2785 // Fall back to selection DAG isel if the shift amount
2786 // is zero or greater than the width of the value type.
2787 if (ShiftImm == 0 || ShiftImm >=32)
2793 Value *Src1Value = I->getOperand(0);
2794 unsigned Reg1 = getRegForValue(Src1Value);
2795 if (Reg1 == 0) return false;
2798 if (Opc == ARM::MOVsr) {
2799 Reg2 = getRegForValue(Src2Value);
2800 if (Reg2 == 0) return false;
2803 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2804 if(ResultReg == 0) return false;
2806 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2807 TII.get(Opc), ResultReg)
2810 if (Opc == ARM::MOVsi)
2811 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2812 else if (Opc == ARM::MOVsr) {
2814 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2817 AddOptionalDefs(MIB);
2818 UpdateValueMap(I, ResultReg);
2822 // TODO: SoftFP support.
2823 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2825 switch (I->getOpcode()) {
2826 case Instruction::Load:
2827 return SelectLoad(I);
2828 case Instruction::Store:
2829 return SelectStore(I);
2830 case Instruction::Br:
2831 return SelectBranch(I);
2832 case Instruction::IndirectBr:
2833 return SelectIndirectBr(I);
2834 case Instruction::ICmp:
2835 case Instruction::FCmp:
2836 return SelectCmp(I);
2837 case Instruction::FPExt:
2838 return SelectFPExt(I);
2839 case Instruction::FPTrunc:
2840 return SelectFPTrunc(I);
2841 case Instruction::SIToFP:
2842 return SelectIToFP(I, /*isSigned*/ true);
2843 case Instruction::UIToFP:
2844 return SelectIToFP(I, /*isSigned*/ false);
2845 case Instruction::FPToSI:
2846 return SelectFPToI(I, /*isSigned*/ true);
2847 case Instruction::FPToUI:
2848 return SelectFPToI(I, /*isSigned*/ false);
2849 case Instruction::Add:
2850 return SelectBinaryIntOp(I, ISD::ADD);
2851 case Instruction::Or:
2852 return SelectBinaryIntOp(I, ISD::OR);
2853 case Instruction::Sub:
2854 return SelectBinaryIntOp(I, ISD::SUB);
2855 case Instruction::FAdd:
2856 return SelectBinaryFPOp(I, ISD::FADD);
2857 case Instruction::FSub:
2858 return SelectBinaryFPOp(I, ISD::FSUB);
2859 case Instruction::FMul:
2860 return SelectBinaryFPOp(I, ISD::FMUL);
2861 case Instruction::SDiv:
2862 return SelectDiv(I, /*isSigned*/ true);
2863 case Instruction::UDiv:
2864 return SelectDiv(I, /*isSigned*/ false);
2865 case Instruction::SRem:
2866 return SelectRem(I, /*isSigned*/ true);
2867 case Instruction::URem:
2868 return SelectRem(I, /*isSigned*/ false);
2869 case Instruction::Call:
2870 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2871 return SelectIntrinsicCall(*II);
2872 return SelectCall(I);
2873 case Instruction::Select:
2874 return SelectSelect(I);
2875 case Instruction::Ret:
2876 return SelectRet(I);
2877 case Instruction::Trunc:
2878 return SelectTrunc(I);
2879 case Instruction::ZExt:
2880 case Instruction::SExt:
2881 return SelectIntExt(I);
2882 case Instruction::Shl:
2883 return SelectShift(I, ARM_AM::lsl);
2884 case Instruction::LShr:
2885 return SelectShift(I, ARM_AM::lsr);
2886 case Instruction::AShr:
2887 return SelectShift(I, ARM_AM::asr);
2894 // This table describes sign- and zero-extend instructions which can be
2895 // folded into a preceding load. All of these extends have an immediate
2896 // (sometimes a mask and sometimes a shift) that's applied after
2898 const struct FoldableLoadExtendsStruct {
2899 uint16_t Opc[2]; // ARM, Thumb.
2900 uint8_t ExpectedImm;
2902 uint8_t ExpectedVT : 7;
2903 } FoldableLoadExtends[] = {
2904 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2905 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2906 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2907 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2908 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2912 /// \brief The specified machine instr operand is a vreg, and that
2913 /// vreg is being provided by the specified load instruction. If possible,
2914 /// try to fold the load as an operand to the instruction, returning true if
2916 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2917 const LoadInst *LI) {
2918 // Verify we have a legal type before going any further.
2920 if (!isLoadTypeLegal(LI->getType(), VT))
2923 // Combine load followed by zero- or sign-extend.
2924 // ldrb r1, [r0] ldrb r1, [r0]
2926 // mov r3, r2 mov r3, r1
2927 if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2929 const uint64_t Imm = MI->getOperand(2).getImm();
2933 for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends);
2935 if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&
2936 (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm &&
2937 MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) {
2939 isZExt = FoldableLoadExtends[i].isZExt;
2942 if (!Found) return false;
2944 // See if we can handle this address.
2946 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2948 unsigned ResultReg = MI->getOperand(0).getReg();
2949 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2951 MI->eraseFromParent();
2955 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2956 unsigned Align, MVT VT) {
2957 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2958 ARMConstantPoolConstant *CPV =
2959 ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2960 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
2963 unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
2966 DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0);
2967 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2968 TII.get(ARM::t2LDRpci), DestReg1)
2969 .addConstantPoolIndex(Idx));
2970 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
2972 // The extra immediate is for addrmode2.
2973 DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0);
2974 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2975 DbgLoc, TII.get(ARM::LDRcp), DestReg1)
2976 .addConstantPoolIndex(Idx).addImm(0));
2977 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
2980 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
2981 if (GlobalBaseReg == 0) {
2982 GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
2983 AFI->setGlobalBaseReg(GlobalBaseReg);
2986 unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
2987 DestReg2 = constrainOperandRegClass(TII.get(Opc), DestReg2, 0);
2988 DestReg1 = constrainOperandRegClass(TII.get(Opc), DestReg1, 1);
2989 GlobalBaseReg = constrainOperandRegClass(TII.get(Opc), GlobalBaseReg, 2);
2990 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2991 DbgLoc, TII.get(Opc), DestReg2)
2993 .addReg(GlobalBaseReg);
2996 AddOptionalDefs(MIB);
3001 bool ARMFastISel::FastLowerArguments() {
3002 if (!FuncInfo.CanLowerReturn)
3005 const Function *F = FuncInfo.Fn;
3009 CallingConv::ID CC = F->getCallingConv();
3013 case CallingConv::Fast:
3014 case CallingConv::C:
3015 case CallingConv::ARM_AAPCS_VFP:
3016 case CallingConv::ARM_AAPCS:
3017 case CallingConv::ARM_APCS:
3021 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3022 // which are passed in r0 - r3.
3024 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3025 I != E; ++I, ++Idx) {
3029 if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
3030 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
3031 F->getAttributes().hasAttribute(Idx, Attribute::ByVal))
3034 Type *ArgTy = I->getType();
3035 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3038 EVT ArgVT = TLI.getValueType(ArgTy);
3039 if (!ArgVT.isSimple()) return false;
3040 switch (ArgVT.getSimpleVT().SimpleTy) {
3051 static const uint16_t GPRArgRegs[] = {
3052 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3055 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3057 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3058 I != E; ++I, ++Idx) {
3059 unsigned SrcReg = GPRArgRegs[Idx];
3060 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3061 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3062 // Without this, EmitLiveInCopies may eliminate the livein if its only
3063 // use is a bitcast (which isn't turned into an instruction).
3064 unsigned ResultReg = createResultReg(RC);
3065 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3066 TII.get(TargetOpcode::COPY),
3067 ResultReg).addReg(DstReg, getKillRegState(true));
3068 UpdateValueMap(I, ResultReg);
3075 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3076 const TargetLibraryInfo *libInfo) {
3077 const TargetMachine &TM = funcInfo.MF->getTarget();
3079 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
3080 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
3081 bool UseFastISel = false;
3082 UseFastISel |= Subtarget->isTargetMachO() && !Subtarget->isThumb1Only();
3083 UseFastISel |= Subtarget->isTargetLinux() && !Subtarget->isThumb();
3084 UseFastISel |= Subtarget->isTargetNaCl() && !Subtarget->isThumb();
3087 // iOS always has a FP for backtracking, force other targets
3088 // to keep their FP when doing FastISel. The emitted code is
3089 // currently superior, and in cases like test-suite's lencod
3090 // FastISel isn't quite correct when FP is eliminated.
3091 TM.Options.NoFramePointerElim = true;
3092 return new ARMFastISel(funcInfo, libInfo);