1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/Module.h"
28 #include "llvm/CodeGen/Analysis.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/FunctionLoweringInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineConstantPool.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/Support/CallSite.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/GetElementPtrTypeIterator.h"
40 #include "llvm/Target/TargetData.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
48 EnableARMFastISel("arm-fast-isel",
49 cl::desc("Turn on experimental ARM fast-isel support"),
50 cl::init(false), cl::Hidden);
54 class ARMFastISel : public FastISel {
56 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
57 /// make the right decision when generating code for different targets.
58 const ARMSubtarget *Subtarget;
59 const TargetMachine &TM;
60 const TargetInstrInfo &TII;
61 const TargetLowering &TLI;
62 const ARMFunctionInfo *AFI;
64 // Convenience variable to avoid checking all the time.
68 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
70 TM(funcInfo.MF->getTarget()),
71 TII(*TM.getInstrInfo()),
72 TLI(*TM.getTargetLowering()) {
73 Subtarget = &TM.getSubtarget<ARMSubtarget>();
74 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
75 isThumb = AFI->isThumbFunction();
78 // Code from FastISel.cpp.
79 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
80 const TargetRegisterClass *RC);
81 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
82 const TargetRegisterClass *RC,
83 unsigned Op0, bool Op0IsKill);
84 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
85 const TargetRegisterClass *RC,
86 unsigned Op0, bool Op0IsKill,
87 unsigned Op1, bool Op1IsKill);
88 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
89 const TargetRegisterClass *RC,
90 unsigned Op0, bool Op0IsKill,
92 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
93 const TargetRegisterClass *RC,
94 unsigned Op0, bool Op0IsKill,
95 const ConstantFP *FPImm);
96 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
97 const TargetRegisterClass *RC,
99 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
100 const TargetRegisterClass *RC,
101 unsigned Op0, bool Op0IsKill,
102 unsigned Op1, bool Op1IsKill,
104 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
105 unsigned Op0, bool Op0IsKill,
108 // Backend specific FastISel code.
109 virtual bool TargetSelectInstruction(const Instruction *I);
110 virtual unsigned TargetMaterializeConstant(const Constant *C);
112 #include "ARMGenFastISel.inc"
114 // Instruction selection routines.
116 virtual bool SelectLoad(const Instruction *I);
117 virtual bool SelectStore(const Instruction *I);
118 virtual bool SelectBranch(const Instruction *I);
119 virtual bool SelectCmp(const Instruction *I);
120 virtual bool SelectFPExt(const Instruction *I);
121 virtual bool SelectFPTrunc(const Instruction *I);
122 virtual bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
123 virtual bool SelectSIToFP(const Instruction *I);
124 virtual bool SelectFPToSI(const Instruction *I);
125 virtual bool SelectSDiv(const Instruction *I);
129 bool isTypeLegal(const Type *Ty, EVT &VT);
130 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
131 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
132 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
133 bool ARMLoadAlloca(const Instruction *I, EVT VT);
134 bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
135 bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
136 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
137 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
138 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
139 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
141 // Call handling routines.
143 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
144 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
146 // OptionalDef handling routines.
148 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
149 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
152 } // end anonymous namespace
154 #include "ARMGenCallingConv.inc"
156 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
157 // we don't care about implicit defs here, just places we'll need to add a
158 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
159 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
160 const TargetInstrDesc &TID = MI->getDesc();
161 if (!TID.hasOptionalDef())
164 // Look to see if our OptionalDef is defining CPSR or CCR.
165 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
166 const MachineOperand &MO = MI->getOperand(i);
167 if (!MO.isReg() || !MO.isDef()) continue;
168 if (MO.getReg() == ARM::CPSR)
174 // If the machine is predicable go ahead and add the predicate operands, if
175 // it needs default CC operands add those.
176 const MachineInstrBuilder &
177 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
178 MachineInstr *MI = &*MIB;
180 // Do we use a predicate?
181 if (TII.isPredicable(MI))
184 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
185 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
187 if (DefinesOptionalPredicate(MI, &CPSR)) {
196 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
197 const TargetRegisterClass* RC) {
198 unsigned ResultReg = createResultReg(RC);
199 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
201 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
205 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
206 const TargetRegisterClass *RC,
207 unsigned Op0, bool Op0IsKill) {
208 unsigned ResultReg = createResultReg(RC);
209 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
211 if (II.getNumDefs() >= 1)
212 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
213 .addReg(Op0, Op0IsKill * RegState::Kill));
215 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
216 .addReg(Op0, Op0IsKill * RegState::Kill));
217 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
218 TII.get(TargetOpcode::COPY), ResultReg)
219 .addReg(II.ImplicitDefs[0]));
224 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
225 const TargetRegisterClass *RC,
226 unsigned Op0, bool Op0IsKill,
227 unsigned Op1, bool Op1IsKill) {
228 unsigned ResultReg = createResultReg(RC);
229 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
231 if (II.getNumDefs() >= 1)
232 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
233 .addReg(Op0, Op0IsKill * RegState::Kill)
234 .addReg(Op1, Op1IsKill * RegState::Kill));
236 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
237 .addReg(Op0, Op0IsKill * RegState::Kill)
238 .addReg(Op1, Op1IsKill * RegState::Kill));
239 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
240 TII.get(TargetOpcode::COPY), ResultReg)
241 .addReg(II.ImplicitDefs[0]));
246 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
247 const TargetRegisterClass *RC,
248 unsigned Op0, bool Op0IsKill,
250 unsigned ResultReg = createResultReg(RC);
251 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
253 if (II.getNumDefs() >= 1)
254 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
255 .addReg(Op0, Op0IsKill * RegState::Kill)
258 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
259 .addReg(Op0, Op0IsKill * RegState::Kill)
261 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
262 TII.get(TargetOpcode::COPY), ResultReg)
263 .addReg(II.ImplicitDefs[0]));
268 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
269 const TargetRegisterClass *RC,
270 unsigned Op0, bool Op0IsKill,
271 const ConstantFP *FPImm) {
272 unsigned ResultReg = createResultReg(RC);
273 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
275 if (II.getNumDefs() >= 1)
276 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
277 .addReg(Op0, Op0IsKill * RegState::Kill)
280 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
281 .addReg(Op0, Op0IsKill * RegState::Kill)
283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
284 TII.get(TargetOpcode::COPY), ResultReg)
285 .addReg(II.ImplicitDefs[0]));
290 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
291 const TargetRegisterClass *RC,
292 unsigned Op0, bool Op0IsKill,
293 unsigned Op1, bool Op1IsKill,
295 unsigned ResultReg = createResultReg(RC);
296 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
298 if (II.getNumDefs() >= 1)
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
300 .addReg(Op0, Op0IsKill * RegState::Kill)
301 .addReg(Op1, Op1IsKill * RegState::Kill)
304 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
305 .addReg(Op0, Op0IsKill * RegState::Kill)
306 .addReg(Op1, Op1IsKill * RegState::Kill)
308 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
309 TII.get(TargetOpcode::COPY), ResultReg)
310 .addReg(II.ImplicitDefs[0]));
315 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
316 const TargetRegisterClass *RC,
318 unsigned ResultReg = createResultReg(RC);
319 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
321 if (II.getNumDefs() >= 1)
322 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
325 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
327 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
328 TII.get(TargetOpcode::COPY), ResultReg)
329 .addReg(II.ImplicitDefs[0]));
334 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
335 unsigned Op0, bool Op0IsKill,
337 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
338 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
339 "Cannot yet extract from physregs");
340 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
341 DL, TII.get(TargetOpcode::COPY), ResultReg)
342 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
346 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
347 // checks from the various callers.
348 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
349 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
351 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
352 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
353 TII.get(ARM::VMOVRS), MoveReg)
358 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
359 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
361 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
362 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
363 TII.get(ARM::VMOVSR), MoveReg)
368 // For double width floating point we need to materialize two constants
369 // (the high and the low) into integer registers then use a move to get
370 // the combined constant into an FP reg.
371 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
372 const APFloat Val = CFP->getValueAPF();
373 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
375 // This checks to see if we can use VFP3 instructions to materialize
376 // a constant, otherwise we have to go through the constant pool.
377 if (TLI.isFPImmLegal(Val, VT)) {
378 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
379 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
380 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
386 // Require VFP2 for loading fp constants.
387 if (!Subtarget->hasVFP2()) return false;
389 // MachineConstantPool wants an explicit alignment.
390 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
392 // TODO: Figure out if this is correct.
393 Align = TD.getTypeAllocSize(CFP->getType());
395 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
396 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
397 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
399 // The extra reg is for addrmode5.
400 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
402 .addConstantPoolIndex(Idx)
407 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
409 // For now 32-bit only.
410 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
412 // MachineConstantPool wants an explicit alignment.
413 unsigned Align = TD.getPrefTypeAlignment(C->getType());
415 // TODO: Figure out if this is correct.
416 Align = TD.getTypeAllocSize(C->getType());
418 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
419 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
422 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
423 TII.get(ARM::t2LDRpci), DestReg)
424 .addConstantPoolIndex(Idx));
426 // The extra reg and immediate are for addrmode2.
427 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
428 TII.get(ARM::LDRcp), DestReg)
429 .addConstantPoolIndex(Idx)
430 .addReg(0).addImm(0));
435 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
436 EVT VT = TLI.getValueType(C->getType(), true);
438 // Only handle simple types.
439 if (!VT.isSimple()) return 0;
441 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
442 return ARMMaterializeFP(CFP, VT);
443 return ARMMaterializeInt(C, VT);
446 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
447 VT = TLI.getValueType(Ty, true);
449 // Only handle simple types.
450 if (VT == MVT::Other || !VT.isSimple()) return false;
452 // Handle all legal types, i.e. a register that will directly hold this
454 return TLI.isTypeLegal(VT);
457 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
458 if (isTypeLegal(Ty, VT)) return true;
460 // If this is a type than can be sign or zero-extended to a basic operation
461 // go ahead and accept it now.
462 if (VT == MVT::i8 || VT == MVT::i16)
468 // Computes the Reg+Offset to get to an object.
469 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
471 // Some boilerplate from the X86 FastISel.
472 const User *U = NULL;
473 unsigned Opcode = Instruction::UserOp1;
474 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
475 // Don't walk into other basic blocks; it's possible we haven't
476 // visited them yet, so the instructions may not yet be assigned
477 // virtual registers.
478 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
480 Opcode = I->getOpcode();
482 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
483 Opcode = C->getOpcode();
487 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
488 if (Ty->getAddressSpace() > 255)
489 // Fast instruction selection doesn't support the special
496 case Instruction::Alloca: {
497 assert(false && "Alloca should have been handled earlier!");
502 // FIXME: Handle global variables.
503 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
508 // Try to get this in a register if nothing else has worked.
509 Reg = getRegForValue(Obj);
510 if (Reg == 0) return false;
512 // Since the offset may be too large for the load instruction
513 // get the reg+offset into a register.
514 // TODO: Verify the additions work, otherwise we'll need to add the
515 // offset instead of 0 to the instructions and do all sorts of operand
517 // TODO: Optimize this somewhat.
519 ARMCC::CondCodes Pred = ARMCC::AL;
520 unsigned PredReg = 0;
523 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
524 Reg, Reg, Offset, Pred, PredReg,
525 static_cast<const ARMBaseInstrInfo&>(TII));
527 assert(AFI->isThumb2Function());
528 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
529 Reg, Reg, Offset, Pred, PredReg,
530 static_cast<const ARMBaseInstrInfo&>(TII));
536 bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
537 Value *Op0 = I->getOperand(0);
539 // Verify it's an alloca.
540 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
541 DenseMap<const AllocaInst*, int>::iterator SI =
542 FuncInfo.StaticAllocaMap.find(AI);
544 if (SI != FuncInfo.StaticAllocaMap.end()) {
545 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
546 unsigned ResultReg = createResultReg(RC);
547 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
548 ResultReg, SI->second, RC,
549 TM.getRegisterInfo());
550 UpdateValueMap(I, ResultReg);
557 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
558 unsigned Reg, int Offset) {
560 assert(VT.isSimple() && "Non-simple types are invalid here!");
562 bool isFloat = false;
563 switch (VT.getSimpleVT().SimpleTy) {
565 // This is mostly going to be Neon/vector support.
568 Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
572 Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
576 Opc = isThumb ? ARM::tLDR : ARM::LDR;
588 ResultReg = createResultReg(TLI.getRegClassFor(VT));
590 // TODO: Fix the Addressing modes so that these can share some code.
591 // Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
592 // The thumb addressing mode has operands swapped from the arm addressing
593 // mode, the floating point one only has two operands.
595 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
596 TII.get(Opc), ResultReg)
597 .addReg(Reg).addImm(Offset));
599 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
600 TII.get(Opc), ResultReg)
601 .addReg(Reg).addImm(Offset).addReg(0));
603 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
604 TII.get(Opc), ResultReg)
605 .addReg(Reg).addReg(0).addImm(Offset));
609 bool ARMFastISel::SelectLoad(const Instruction *I) {
610 // Verify we have a legal type before going any further.
612 if (!isLoadTypeLegal(I->getType(), VT))
615 // If we're an alloca we know we have a frame index and can emit the load
616 // directly in short order.
617 if (ARMLoadAlloca(I, VT))
620 // Our register and offset with innocuous defaults.
624 // See if we can handle this as Reg + Offset
625 if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
629 if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
631 UpdateValueMap(I, ResultReg);
635 bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
636 Value *Op1 = I->getOperand(1);
638 // Verify it's an alloca.
639 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
640 DenseMap<const AllocaInst*, int>::iterator SI =
641 FuncInfo.StaticAllocaMap.find(AI);
643 if (SI != FuncInfo.StaticAllocaMap.end()) {
644 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
645 assert(SrcReg != 0 && "Nothing to store!");
646 TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
647 SrcReg, true /*isKill*/, SI->second, RC,
648 TM.getRegisterInfo());
655 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
656 unsigned DstReg, int Offset) {
658 bool isFloat = false;
659 switch (VT.getSimpleVT().SimpleTy) {
660 default: return false;
662 case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break;
663 case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break;
664 case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break;
666 if (!Subtarget->hasVFP2()) return false;
671 if (!Subtarget->hasVFP2()) return false;
677 // The thumb addressing mode has operands swapped from the arm addressing
678 // mode, the floating point one only has two operands.
680 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
681 TII.get(StrOpc), SrcReg)
682 .addReg(DstReg).addImm(Offset));
684 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
685 TII.get(StrOpc), SrcReg)
686 .addReg(DstReg).addImm(Offset).addReg(0));
689 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
690 TII.get(StrOpc), SrcReg)
691 .addReg(DstReg).addReg(0).addImm(Offset));
696 bool ARMFastISel::SelectStore(const Instruction *I) {
697 Value *Op0 = I->getOperand(0);
700 // Yay type legalization
702 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
705 // Get the value to be stored into a register.
706 SrcReg = getRegForValue(Op0);
710 // If we're an alloca we know we have a frame index and can emit the store
712 if (ARMStoreAlloca(I, SrcReg, VT))
715 // Our register and offset with innocuous defaults.
719 // See if we can handle this as Reg + Offset
720 if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
723 if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
728 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
730 // Needs two compares...
731 case CmpInst::FCMP_ONE:
732 case CmpInst::FCMP_UEQ:
734 assert(false && "Unhandled CmpInst::Predicate!");
736 case CmpInst::ICMP_EQ:
737 case CmpInst::FCMP_OEQ:
739 case CmpInst::ICMP_SGT:
740 case CmpInst::FCMP_OGT:
742 case CmpInst::ICMP_SGE:
743 case CmpInst::FCMP_OGE:
745 case CmpInst::ICMP_UGT:
746 case CmpInst::FCMP_UGT:
748 case CmpInst::FCMP_OLT:
750 case CmpInst::ICMP_ULE:
751 case CmpInst::FCMP_OLE:
753 case CmpInst::FCMP_ORD:
755 case CmpInst::FCMP_UNO:
757 case CmpInst::FCMP_UGE:
759 case CmpInst::ICMP_SLT:
760 case CmpInst::FCMP_ULT:
762 case CmpInst::ICMP_SLE:
763 case CmpInst::FCMP_ULE:
765 case CmpInst::FCMP_UNE:
766 case CmpInst::ICMP_NE:
768 case CmpInst::ICMP_UGE:
770 case CmpInst::ICMP_ULT:
775 bool ARMFastISel::SelectBranch(const Instruction *I) {
776 const BranchInst *BI = cast<BranchInst>(I);
777 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
778 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
780 // Simple branch support.
781 // TODO: Hopefully we've already handled the condition since we won't
782 // have left an update in the value map. See the TODO below in SelectCMP.
783 Value *Cond = BI->getCondition();
784 unsigned CondReg = getRegForValue(Cond);
785 if (CondReg == 0) return false;
787 ARMCC::CondCodes ARMPred = ARMCC::NE;
788 CmpInst *CI = dyn_cast<CmpInst>(Cond);
789 if (!CI) return false;
791 // Get the compare predicate.
792 ARMPred = getComparePred(CI->getPredicate());
794 // We may not handle every CC for now.
795 if (ARMPred == ARMCC::AL) return false;
797 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
798 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
799 .addMBB(TBB).addImm(ARMPred).addReg(CondReg);
800 FastEmitBranch(FBB, DL);
801 FuncInfo.MBB->addSuccessor(TBB);
805 bool ARMFastISel::SelectCmp(const Instruction *I) {
806 const CmpInst *CI = cast<CmpInst>(I);
809 const Type *Ty = CI->getOperand(0)->getType();
810 if (!isTypeLegal(Ty, VT))
813 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
814 if (isFloat && !Subtarget->hasVFP2())
819 switch (VT.getSimpleVT().SimpleTy) {
820 default: return false;
821 // TODO: Verify compares.
823 CmpOpc = ARM::VCMPES;
824 DestReg = ARM::FPSCR;
827 CmpOpc = ARM::VCMPED;
828 DestReg = ARM::FPSCR;
831 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
836 unsigned Arg1 = getRegForValue(CI->getOperand(0));
837 if (Arg1 == 0) return false;
839 unsigned Arg2 = getRegForValue(CI->getOperand(1));
840 if (Arg2 == 0) return false;
842 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
843 .addReg(Arg1).addReg(Arg2));
845 // For floating point we need to move the result to a comparison register
846 // that we can then use for branches.
848 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
849 TII.get(ARM::FMSTAT)));
851 // Update the value to the implicit def reg.
852 UpdateValueMap(I, DestReg);
856 bool ARMFastISel::SelectFPExt(const Instruction *I) {
857 // Make sure we have VFP and that we're extending float to double.
858 if (!Subtarget->hasVFP2()) return false;
860 Value *V = I->getOperand(0);
861 if (!I->getType()->isDoubleTy() ||
862 !V->getType()->isFloatTy()) return false;
864 unsigned Op = getRegForValue(V);
865 if (Op == 0) return false;
867 unsigned Result = createResultReg(ARM::DPRRegisterClass);
868 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
869 TII.get(ARM::VCVTDS), Result)
871 UpdateValueMap(I, Result);
875 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
876 // Make sure we have VFP and that we're truncating double to float.
877 if (!Subtarget->hasVFP2()) return false;
879 Value *V = I->getOperand(0);
880 if (!I->getType()->isFloatTy() ||
881 !V->getType()->isDoubleTy()) return false;
883 unsigned Op = getRegForValue(V);
884 if (Op == 0) return false;
886 unsigned Result = createResultReg(ARM::SPRRegisterClass);
887 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
888 TII.get(ARM::VCVTSD), Result)
890 UpdateValueMap(I, Result);
894 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
895 // Make sure we have VFP.
896 if (!Subtarget->hasVFP2()) return false;
899 const Type *Ty = I->getType();
900 if (!isTypeLegal(Ty, DstVT))
903 unsigned Op = getRegForValue(I->getOperand(0));
904 if (Op == 0) return false;
906 // The conversion routine works on fp-reg to fp-reg and the operand above
907 // was an integer, move it to the fp registers if possible.
908 unsigned FP = ARMMoveToFPReg(DstVT, Op);
909 if (FP == 0) return false;
912 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
913 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
916 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
917 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
920 UpdateValueMap(I, ResultReg);
924 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
925 // Make sure we have VFP.
926 if (!Subtarget->hasVFP2()) return false;
929 const Type *RetTy = I->getType();
930 if (!isTypeLegal(RetTy, DstVT))
933 unsigned Op = getRegForValue(I->getOperand(0));
934 if (Op == 0) return false;
937 const Type *OpTy = I->getOperand(0)->getType();
938 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
939 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
941 EVT OpVT = TLI.getValueType(OpTy, true);
943 unsigned ResultReg = createResultReg(TLI.getRegClassFor(OpVT));
944 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
948 // This result needs to be in an integer register, but the conversion only
949 // takes place in fp-regs.
950 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
951 if (IntReg == 0) return false;
953 UpdateValueMap(I, IntReg);
957 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
958 EVT VT = TLI.getValueType(I->getType(), true);
960 // We can get here in the case when we want to use NEON for our fp
961 // operations, but can't figure out how to. Just use the vfp instructions
963 // FIXME: It'd be nice to use NEON instructions.
964 const Type *Ty = I->getType();
965 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
966 if (isFloat && !Subtarget->hasVFP2())
969 unsigned Op1 = getRegForValue(I->getOperand(0));
970 if (Op1 == 0) return false;
972 unsigned Op2 = getRegForValue(I->getOperand(1));
973 if (Op2 == 0) return false;
976 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
977 VT.getSimpleVT().SimpleTy == MVT::i64;
979 default: return false;
981 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
984 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
987 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
990 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
991 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
992 TII.get(Opc), ResultReg)
993 .addReg(Op1).addReg(Op2));
994 UpdateValueMap(I, ResultReg);
998 // Call Handling Code
1000 // This is largely taken directly from CCAssignFnForNode - we don't support
1001 // varargs in FastISel so that part has been removed.
1002 // TODO: We may not support all of this.
1003 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1006 llvm_unreachable("Unsupported calling convention");
1007 case CallingConv::C:
1008 case CallingConv::Fast:
1009 // Use target triple & subtarget features to do actual dispatch.
1010 if (Subtarget->isAAPCS_ABI()) {
1011 if (Subtarget->hasVFP2() &&
1012 FloatABIType == FloatABI::Hard)
1013 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1015 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1017 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1018 case CallingConv::ARM_AAPCS_VFP:
1019 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1020 case CallingConv::ARM_AAPCS:
1021 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1022 case CallingConv::ARM_APCS:
1023 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1027 // A quick function that will emit a call for a named libcall in F with the
1028 // vector of passed arguments for the Instruction in I. We can assume that we
1029 // can emit a call for any libcall we can produce. This is an abridged version
1030 // of the full call infrastructure since we won't need to worry about things
1031 // like computed function pointers or strange arguments at call sites.
1032 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1034 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1035 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1037 // Handle *simple* calls for now.
1038 const Type *RetTy = I->getType();
1040 if (RetTy->isVoidTy())
1041 RetVT = MVT::isVoid;
1042 else if (!isTypeLegal(RetTy, RetVT))
1045 // For now we're using BLX etc on the assumption that we have v5t ops.
1046 if (!Subtarget->hasV5TOps()) return false;
1048 // Abridged from the X86 FastISel call selection mechanism
1049 SmallVector<Value*, 8> Args;
1050 SmallVector<unsigned, 8> ArgRegs;
1051 SmallVector<EVT, 8> ArgVTs;
1052 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1053 Args.reserve(I->getNumOperands());
1054 ArgRegs.reserve(I->getNumOperands());
1055 ArgVTs.reserve(I->getNumOperands());
1056 ArgFlags.reserve(I->getNumOperands());
1057 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1058 Value *Op = I->getOperand(i);
1059 unsigned Arg = getRegForValue(Op);
1060 if (Arg == 0) return false;
1062 const Type *ArgTy = Op->getType();
1064 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1066 ISD::ArgFlagsTy Flags;
1067 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1068 Flags.setOrigAlign(OriginalAlignment);
1071 ArgRegs.push_back(Arg);
1072 ArgVTs.push_back(ArgVT);
1073 ArgFlags.push_back(Flags);
1076 SmallVector<CCValAssign, 16> ArgLocs;
1077 CCState CCInfo(CC, false, TM, ArgLocs,
1078 I->getParent()->getParent()->getContext());
1079 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1081 // Get a count of how many bytes are to be pushed on the stack.
1082 unsigned NumBytes = CCInfo.getNextStackOffset();
1084 // Issue CALLSEQ_START
1085 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1086 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
1089 // Process the args.
1090 SmallVector<unsigned, 4> RegArgs;
1091 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1092 CCValAssign &VA = ArgLocs[i];
1093 unsigned Arg = ArgRegs[VA.getValNo()];
1094 EVT ArgVT = ArgVTs[VA.getValNo()];
1096 // Should we ever have to promote?
1097 switch (VA.getLocInfo()) {
1098 case CCValAssign::Full: break;
1100 assert(false && "Handle arg promotion for libcalls?");
1104 // Now copy/store arg to correct locations.
1105 if (VA.isRegLoc()) {
1106 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1109 RegArgs.push_back(VA.getLocReg());
1116 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1117 // TODO: Turn this into the table of arm call ops.
1118 MachineInstrBuilder MIB;
1121 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1123 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1124 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1125 .addExternalSymbol(TLI.getLibcallName(Call));
1127 // Add implicit physical register uses to the call.
1128 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1129 MIB.addReg(RegArgs[i]);
1131 // Issue CALLSEQ_END
1132 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1133 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
1134 .addImm(NumBytes).addImm(0);
1136 // Now the return value.
1137 SmallVector<unsigned, 4> UsedRegs;
1138 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1139 SmallVector<CCValAssign, 16> RVLocs;
1140 CCState CCInfo(CC, false, TM, RVLocs,
1141 I->getParent()->getParent()->getContext());
1142 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1144 // Copy all of the result registers out of their specified physreg.
1145 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1146 EVT CopyVT = RVLocs[0].getValVT();
1147 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1149 unsigned ResultReg = createResultReg(DstRC);
1150 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1151 ResultReg).addReg(RVLocs[0].getLocReg());
1152 UsedRegs.push_back(RVLocs[0].getLocReg());
1154 // Finally update the result.
1155 UpdateValueMap(I, ResultReg);
1158 // Set all unused physreg defs as dead.
1159 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1163 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1165 const Type *Ty = I->getType();
1166 if (!isTypeLegal(Ty, VT))
1169 // If we have integer div support we should have selected this automagically.
1170 // In case we have a real miss go ahead and return false and we'll pick
1172 if (Subtarget->hasDivide()) return false;
1174 // Otherwise emit a libcall.
1175 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1177 LC = RTLIB::SDIV_I16;
1178 else if (VT == MVT::i32)
1179 LC = RTLIB::SDIV_I32;
1180 else if (VT == MVT::i64)
1181 LC = RTLIB::SDIV_I64;
1182 else if (VT == MVT::i128)
1183 LC = RTLIB::SDIV_I128;
1184 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1186 return ARMEmitLibcall(I, LC);
1189 // TODO: SoftFP support.
1190 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1191 // No Thumb-1 for now.
1192 if (isThumb && !AFI->isThumb2Function()) return false;
1194 switch (I->getOpcode()) {
1195 case Instruction::Load:
1196 return SelectLoad(I);
1197 case Instruction::Store:
1198 return SelectStore(I);
1199 case Instruction::Br:
1200 return SelectBranch(I);
1201 case Instruction::ICmp:
1202 case Instruction::FCmp:
1203 return SelectCmp(I);
1204 case Instruction::FPExt:
1205 return SelectFPExt(I);
1206 case Instruction::FPTrunc:
1207 return SelectFPTrunc(I);
1208 case Instruction::SIToFP:
1209 return SelectSIToFP(I);
1210 case Instruction::FPToSI:
1211 return SelectFPToSI(I);
1212 case Instruction::FAdd:
1213 return SelectBinaryOp(I, ISD::FADD);
1214 case Instruction::FSub:
1215 return SelectBinaryOp(I, ISD::FSUB);
1216 case Instruction::FMul:
1217 return SelectBinaryOp(I, ISD::FMUL);
1218 case Instruction::SDiv:
1219 return SelectSDiv(I);
1226 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1227 if (EnableARMFastISel) return new ARMFastISel(funcInfo);