1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "ARMConstantPoolValue.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/IntrinsicInst.h"
29 #include "llvm/Module.h"
30 #include "llvm/Operator.h"
31 #include "llvm/CodeGen/Analysis.h"
32 #include "llvm/CodeGen/FastISel.h"
33 #include "llvm/CodeGen/FunctionLoweringInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineConstantPool.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineMemOperand.h"
39 #include "llvm/CodeGen/MachineRegisterInfo.h"
40 #include "llvm/CodeGen/PseudoSourceValue.h"
41 #include "llvm/Support/CallSite.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/GetElementPtrTypeIterator.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
53 DisableARMFastISel("disable-arm-fast-isel",
54 cl::desc("Turn off experimental ARM fast-isel support"),
55 cl::init(false), cl::Hidden);
57 extern cl::opt<bool> EnableARMLongCalls;
61 // All possible address modes, plus some.
62 typedef struct Address {
75 // Innocuous defaults for our address.
77 : BaseType(RegBase), Offset(0) {
82 class ARMFastISel : public FastISel {
84 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
85 /// make the right decision when generating code for different targets.
86 const ARMSubtarget *Subtarget;
87 const TargetMachine &TM;
88 const TargetInstrInfo &TII;
89 const TargetLowering &TLI;
92 // Convenience variables to avoid some queries.
97 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
99 TM(funcInfo.MF->getTarget()),
100 TII(*TM.getInstrInfo()),
101 TLI(*TM.getTargetLowering()) {
102 Subtarget = &TM.getSubtarget<ARMSubtarget>();
103 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
104 isThumb = AFI->isThumbFunction();
105 Context = &funcInfo.Fn->getContext();
108 // Code from FastISel.cpp.
109 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
110 const TargetRegisterClass *RC);
111 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
112 const TargetRegisterClass *RC,
113 unsigned Op0, bool Op0IsKill);
114 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
115 const TargetRegisterClass *RC,
116 unsigned Op0, bool Op0IsKill,
117 unsigned Op1, bool Op1IsKill);
118 virtual unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill,
121 unsigned Op1, bool Op1IsKill,
122 unsigned Op2, bool Op2IsKill);
123 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
124 const TargetRegisterClass *RC,
125 unsigned Op0, bool Op0IsKill,
127 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
128 const TargetRegisterClass *RC,
129 unsigned Op0, bool Op0IsKill,
130 const ConstantFP *FPImm);
131 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
132 const TargetRegisterClass *RC,
133 unsigned Op0, bool Op0IsKill,
134 unsigned Op1, bool Op1IsKill,
136 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
137 const TargetRegisterClass *RC,
139 virtual unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
140 const TargetRegisterClass *RC,
141 uint64_t Imm1, uint64_t Imm2);
143 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
144 unsigned Op0, bool Op0IsKill,
147 // Backend specific FastISel code.
148 virtual bool TargetSelectInstruction(const Instruction *I);
149 virtual unsigned TargetMaterializeConstant(const Constant *C);
150 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
152 #include "ARMGenFastISel.inc"
154 // Instruction selection routines.
156 bool SelectLoad(const Instruction *I);
157 bool SelectStore(const Instruction *I);
158 bool SelectBranch(const Instruction *I);
159 bool SelectCmp(const Instruction *I);
160 bool SelectFPExt(const Instruction *I);
161 bool SelectFPTrunc(const Instruction *I);
162 bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
163 bool SelectSIToFP(const Instruction *I);
164 bool SelectFPToSI(const Instruction *I);
165 bool SelectSDiv(const Instruction *I);
166 bool SelectSRem(const Instruction *I);
167 bool SelectCall(const Instruction *I);
168 bool SelectSelect(const Instruction *I);
169 bool SelectRet(const Instruction *I);
170 bool SelectIntCast(const Instruction *I);
174 bool isTypeLegal(Type *Ty, MVT &VT);
175 bool isLoadTypeLegal(Type *Ty, MVT &VT);
176 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
177 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
178 bool ARMComputeAddress(const Value *Obj, Address &Addr);
179 void ARMSimplifyAddress(Address &Addr, EVT VT);
180 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
181 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
182 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
183 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
184 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
185 unsigned ARMSelectCallOp(const GlobalValue *GV);
187 // Call handling routines.
189 bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
190 unsigned &ResultReg);
191 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
192 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
193 SmallVectorImpl<unsigned> &ArgRegs,
194 SmallVectorImpl<MVT> &ArgVTs,
195 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
196 SmallVectorImpl<unsigned> &RegArgs,
199 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
200 const Instruction *I, CallingConv::ID CC,
202 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
204 // OptionalDef handling routines.
206 bool isARMNEONPred(const MachineInstr *MI);
207 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
208 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
209 void AddLoadStoreOperands(EVT VT, Address &Addr,
210 const MachineInstrBuilder &MIB,
214 } // end anonymous namespace
216 #include "ARMGenCallingConv.inc"
218 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
219 // we don't care about implicit defs here, just places we'll need to add a
220 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
221 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
222 const MCInstrDesc &MCID = MI->getDesc();
223 if (!MCID.hasOptionalDef())
226 // Look to see if our OptionalDef is defining CPSR or CCR.
227 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
228 const MachineOperand &MO = MI->getOperand(i);
229 if (!MO.isReg() || !MO.isDef()) continue;
230 if (MO.getReg() == ARM::CPSR)
236 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
237 const MCInstrDesc &MCID = MI->getDesc();
239 // If we're a thumb2 or not NEON function we were handled via isPredicable.
240 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
241 AFI->isThumb2Function())
244 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
245 if (MCID.OpInfo[i].isPredicate())
251 // If the machine is predicable go ahead and add the predicate operands, if
252 // it needs default CC operands add those.
253 // TODO: If we want to support thumb1 then we'll need to deal with optional
254 // CPSR defs that need to be added before the remaining operands. See s_cc_out
255 // for descriptions why.
256 const MachineInstrBuilder &
257 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
258 MachineInstr *MI = &*MIB;
260 // Do we use a predicate? or...
261 // Are we NEON in ARM mode and have a predicate operand? If so, I know
262 // we're not predicable but add it anyways.
263 if (TII.isPredicable(MI) || isARMNEONPred(MI))
266 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
267 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
269 if (DefinesOptionalPredicate(MI, &CPSR)) {
278 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
279 const TargetRegisterClass* RC) {
280 unsigned ResultReg = createResultReg(RC);
281 const MCInstrDesc &II = TII.get(MachineInstOpcode);
283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
287 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
288 const TargetRegisterClass *RC,
289 unsigned Op0, bool Op0IsKill) {
290 unsigned ResultReg = createResultReg(RC);
291 const MCInstrDesc &II = TII.get(MachineInstOpcode);
293 if (II.getNumDefs() >= 1)
294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
295 .addReg(Op0, Op0IsKill * RegState::Kill));
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
298 .addReg(Op0, Op0IsKill * RegState::Kill));
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
300 TII.get(TargetOpcode::COPY), ResultReg)
301 .addReg(II.ImplicitDefs[0]));
306 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
307 const TargetRegisterClass *RC,
308 unsigned Op0, bool Op0IsKill,
309 unsigned Op1, bool Op1IsKill) {
310 unsigned ResultReg = createResultReg(RC);
311 const MCInstrDesc &II = TII.get(MachineInstOpcode);
313 if (II.getNumDefs() >= 1)
314 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
315 .addReg(Op0, Op0IsKill * RegState::Kill)
316 .addReg(Op1, Op1IsKill * RegState::Kill));
318 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
319 .addReg(Op0, Op0IsKill * RegState::Kill)
320 .addReg(Op1, Op1IsKill * RegState::Kill));
321 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
322 TII.get(TargetOpcode::COPY), ResultReg)
323 .addReg(II.ImplicitDefs[0]));
328 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
329 const TargetRegisterClass *RC,
330 unsigned Op0, bool Op0IsKill,
331 unsigned Op1, bool Op1IsKill,
332 unsigned Op2, bool Op2IsKill) {
333 unsigned ResultReg = createResultReg(RC);
334 const MCInstrDesc &II = TII.get(MachineInstOpcode);
336 if (II.getNumDefs() >= 1)
337 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
338 .addReg(Op0, Op0IsKill * RegState::Kill)
339 .addReg(Op1, Op1IsKill * RegState::Kill)
340 .addReg(Op2, Op2IsKill * RegState::Kill));
342 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
343 .addReg(Op0, Op0IsKill * RegState::Kill)
344 .addReg(Op1, Op1IsKill * RegState::Kill)
345 .addReg(Op2, Op2IsKill * RegState::Kill));
346 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
347 TII.get(TargetOpcode::COPY), ResultReg)
348 .addReg(II.ImplicitDefs[0]));
353 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
354 const TargetRegisterClass *RC,
355 unsigned Op0, bool Op0IsKill,
357 unsigned ResultReg = createResultReg(RC);
358 const MCInstrDesc &II = TII.get(MachineInstOpcode);
360 if (II.getNumDefs() >= 1)
361 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
362 .addReg(Op0, Op0IsKill * RegState::Kill)
365 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
366 .addReg(Op0, Op0IsKill * RegState::Kill)
368 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
369 TII.get(TargetOpcode::COPY), ResultReg)
370 .addReg(II.ImplicitDefs[0]));
375 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
376 const TargetRegisterClass *RC,
377 unsigned Op0, bool Op0IsKill,
378 const ConstantFP *FPImm) {
379 unsigned ResultReg = createResultReg(RC);
380 const MCInstrDesc &II = TII.get(MachineInstOpcode);
382 if (II.getNumDefs() >= 1)
383 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
384 .addReg(Op0, Op0IsKill * RegState::Kill)
387 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
388 .addReg(Op0, Op0IsKill * RegState::Kill)
390 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
391 TII.get(TargetOpcode::COPY), ResultReg)
392 .addReg(II.ImplicitDefs[0]));
397 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
398 const TargetRegisterClass *RC,
399 unsigned Op0, bool Op0IsKill,
400 unsigned Op1, bool Op1IsKill,
402 unsigned ResultReg = createResultReg(RC);
403 const MCInstrDesc &II = TII.get(MachineInstOpcode);
405 if (II.getNumDefs() >= 1)
406 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
407 .addReg(Op0, Op0IsKill * RegState::Kill)
408 .addReg(Op1, Op1IsKill * RegState::Kill)
411 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
412 .addReg(Op0, Op0IsKill * RegState::Kill)
413 .addReg(Op1, Op1IsKill * RegState::Kill)
415 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
416 TII.get(TargetOpcode::COPY), ResultReg)
417 .addReg(II.ImplicitDefs[0]));
422 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
423 const TargetRegisterClass *RC,
425 unsigned ResultReg = createResultReg(RC);
426 const MCInstrDesc &II = TII.get(MachineInstOpcode);
428 if (II.getNumDefs() >= 1)
429 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
432 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
434 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
435 TII.get(TargetOpcode::COPY), ResultReg)
436 .addReg(II.ImplicitDefs[0]));
441 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
442 const TargetRegisterClass *RC,
443 uint64_t Imm1, uint64_t Imm2) {
444 unsigned ResultReg = createResultReg(RC);
445 const MCInstrDesc &II = TII.get(MachineInstOpcode);
447 if (II.getNumDefs() >= 1)
448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
449 .addImm(Imm1).addImm(Imm2));
451 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
452 .addImm(Imm1).addImm(Imm2));
453 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
454 TII.get(TargetOpcode::COPY),
456 .addReg(II.ImplicitDefs[0]));
461 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
462 unsigned Op0, bool Op0IsKill,
464 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
465 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
466 "Cannot yet extract from physregs");
467 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
468 DL, TII.get(TargetOpcode::COPY), ResultReg)
469 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
473 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
474 // checks from the various callers.
475 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
476 if (VT == MVT::f64) return 0;
478 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
479 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
480 TII.get(ARM::VMOVRS), MoveReg)
485 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
486 if (VT == MVT::i64) return 0;
488 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
489 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
490 TII.get(ARM::VMOVSR), MoveReg)
495 // For double width floating point we need to materialize two constants
496 // (the high and the low) into integer registers then use a move to get
497 // the combined constant into an FP reg.
498 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
499 const APFloat Val = CFP->getValueAPF();
500 bool is64bit = VT == MVT::f64;
502 // This checks to see if we can use VFP3 instructions to materialize
503 // a constant, otherwise we have to go through the constant pool.
504 if (TLI.isFPImmLegal(Val, VT)) {
505 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
506 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
507 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
513 // Require VFP2 for loading fp constants.
514 if (!Subtarget->hasVFP2()) return false;
516 // MachineConstantPool wants an explicit alignment.
517 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
519 // TODO: Figure out if this is correct.
520 Align = TD.getTypeAllocSize(CFP->getType());
522 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
523 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
524 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
526 // The extra reg is for addrmode5.
527 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
529 .addConstantPoolIndex(Idx)
534 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
536 // For now 32-bit only.
537 if (VT != MVT::i32) return false;
539 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
541 // If we can do this in a single instruction without a constant pool entry
543 const ConstantInt *CI = cast<ConstantInt>(C);
544 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) {
545 unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16;
546 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
547 TII.get(Opc), DestReg)
548 .addImm(CI->getSExtValue()));
552 // MachineConstantPool wants an explicit alignment.
553 unsigned Align = TD.getPrefTypeAlignment(C->getType());
555 // TODO: Figure out if this is correct.
556 Align = TD.getTypeAllocSize(C->getType());
558 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
561 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
562 TII.get(ARM::t2LDRpci), DestReg)
563 .addConstantPoolIndex(Idx));
565 // The extra immediate is for addrmode2.
566 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
567 TII.get(ARM::LDRcp), DestReg)
568 .addConstantPoolIndex(Idx)
574 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
575 // For now 32-bit only.
576 if (VT != MVT::i32) return 0;
578 Reloc::Model RelocM = TM.getRelocationModel();
580 // TODO: Need more magic for ARM PIC.
581 if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
583 // MachineConstantPool wants an explicit alignment.
584 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
586 // TODO: Figure out if this is correct.
587 Align = TD.getTypeAllocSize(GV->getType());
591 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
592 unsigned Id = AFI->createPICLabelUId();
593 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
594 ARMCP::CPValue, PCAdj);
595 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
598 MachineInstrBuilder MIB;
599 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
601 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
602 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
603 .addConstantPoolIndex(Idx);
604 if (RelocM == Reloc::PIC_)
607 // The extra immediate is for addrmode2.
608 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
610 .addConstantPoolIndex(Idx)
613 AddOptionalDefs(MIB);
615 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
616 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
618 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::t2LDRi12),
623 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
627 DestReg = NewDestReg;
628 AddOptionalDefs(MIB);
634 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
635 EVT VT = TLI.getValueType(C->getType(), true);
637 // Only handle simple types.
638 if (!VT.isSimple()) return 0;
640 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
641 return ARMMaterializeFP(CFP, VT);
642 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
643 return ARMMaterializeGV(GV, VT);
644 else if (isa<ConstantInt>(C))
645 return ARMMaterializeInt(C, VT);
650 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
651 // Don't handle dynamic allocas.
652 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
655 if (!isLoadTypeLegal(AI->getType(), VT)) return false;
657 DenseMap<const AllocaInst*, int>::iterator SI =
658 FuncInfo.StaticAllocaMap.find(AI);
660 // This will get lowered later into the correct offsets and registers
661 // via rewriteXFrameIndex.
662 if (SI != FuncInfo.StaticAllocaMap.end()) {
663 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
664 unsigned ResultReg = createResultReg(RC);
665 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
666 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
667 TII.get(Opc), ResultReg)
668 .addFrameIndex(SI->second)
676 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
677 EVT evt = TLI.getValueType(Ty, true);
679 // Only handle simple types.
680 if (evt == MVT::Other || !evt.isSimple()) return false;
681 VT = evt.getSimpleVT();
683 // Handle all legal types, i.e. a register that will directly hold this
685 return TLI.isTypeLegal(VT);
688 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
689 if (isTypeLegal(Ty, VT)) return true;
691 // If this is a type than can be sign or zero-extended to a basic operation
692 // go ahead and accept it now.
693 if (VT == MVT::i8 || VT == MVT::i16)
699 // Computes the address to get to an object.
700 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
701 // Some boilerplate from the X86 FastISel.
702 const User *U = NULL;
703 unsigned Opcode = Instruction::UserOp1;
704 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
705 // Don't walk into other basic blocks unless the object is an alloca from
706 // another block, otherwise it may not have a virtual register assigned.
707 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
708 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
709 Opcode = I->getOpcode();
712 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
713 Opcode = C->getOpcode();
717 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
718 if (Ty->getAddressSpace() > 255)
719 // Fast instruction selection doesn't support the special
726 case Instruction::BitCast: {
727 // Look through bitcasts.
728 return ARMComputeAddress(U->getOperand(0), Addr);
730 case Instruction::IntToPtr: {
731 // Look past no-op inttoptrs.
732 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
733 return ARMComputeAddress(U->getOperand(0), Addr);
736 case Instruction::PtrToInt: {
737 // Look past no-op ptrtoints.
738 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
739 return ARMComputeAddress(U->getOperand(0), Addr);
742 case Instruction::GetElementPtr: {
743 Address SavedAddr = Addr;
744 int TmpOffset = Addr.Offset;
746 // Iterate through the GEP folding the constants into offsets where
748 gep_type_iterator GTI = gep_type_begin(U);
749 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
750 i != e; ++i, ++GTI) {
751 const Value *Op = *i;
752 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
753 const StructLayout *SL = TD.getStructLayout(STy);
754 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
755 TmpOffset += SL->getElementOffset(Idx);
757 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
759 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
760 // Constant-offset addressing.
761 TmpOffset += CI->getSExtValue() * S;
764 if (isa<AddOperator>(Op) &&
765 (!isa<Instruction>(Op) ||
766 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
768 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
769 // An add (in the same block) with a constant operand. Fold the
772 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
773 TmpOffset += CI->getSExtValue() * S;
774 // Iterate on the other operand.
775 Op = cast<AddOperator>(Op)->getOperand(0);
779 goto unsupported_gep;
784 // Try to grab the base operand now.
785 Addr.Offset = TmpOffset;
786 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
788 // We failed, restore everything and try the other options.
794 case Instruction::Alloca: {
795 const AllocaInst *AI = cast<AllocaInst>(Obj);
796 DenseMap<const AllocaInst*, int>::iterator SI =
797 FuncInfo.StaticAllocaMap.find(AI);
798 if (SI != FuncInfo.StaticAllocaMap.end()) {
799 Addr.BaseType = Address::FrameIndexBase;
800 Addr.Base.FI = SI->second;
807 // Materialize the global variable's address into a reg which can
808 // then be used later to load the variable.
809 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
810 unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
811 if (Tmp == 0) return false;
817 // Try to get this in a register if nothing else has worked.
818 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
819 return Addr.Base.Reg != 0;
822 void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
824 assert(VT.isSimple() && "Non-simple types are invalid here!");
826 bool needsLowering = false;
827 switch (VT.getSimpleVT().SimpleTy) {
829 assert(false && "Unhandled load/store type!");
834 // Integer loads/stores handle 12-bit offsets.
835 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
839 // Floating point operands handle 8-bit offsets.
840 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
844 // If this is a stack pointer and the offset needs to be simplified then
845 // put the alloca address into a register, set the base type back to
846 // register and continue. This should almost never happen.
847 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
848 TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
849 ARM::GPRRegisterClass;
850 unsigned ResultReg = createResultReg(RC);
851 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
852 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
853 TII.get(Opc), ResultReg)
854 .addFrameIndex(Addr.Base.FI)
856 Addr.Base.Reg = ResultReg;
857 Addr.BaseType = Address::RegBase;
860 // Since the offset is too large for the load/store instruction
861 // get the reg+offset into a register.
863 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
864 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
869 void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
870 const MachineInstrBuilder &MIB,
872 // addrmode5 output depends on the selection dag addressing dividing the
873 // offset by 4 that it then later multiplies. Do this here as well.
874 if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
875 VT.getSimpleVT().SimpleTy == MVT::f64)
878 // Frame base works a bit differently. Handle it separately.
879 if (Addr.BaseType == Address::FrameIndexBase) {
880 int FI = Addr.Base.FI;
881 int Offset = Addr.Offset;
882 MachineMemOperand *MMO =
883 FuncInfo.MF->getMachineMemOperand(
884 MachinePointerInfo::getFixedStack(FI, Offset),
886 MFI.getObjectSize(FI),
887 MFI.getObjectAlignment(FI));
888 // Now add the rest of the operands.
889 MIB.addFrameIndex(FI);
891 // ARM halfword load/stores need an additional operand.
892 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
894 MIB.addImm(Addr.Offset);
895 MIB.addMemOperand(MMO);
897 // Now add the rest of the operands.
898 MIB.addReg(Addr.Base.Reg);
900 // ARM halfword load/stores need an additional operand.
901 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
903 MIB.addImm(Addr.Offset);
905 AddOptionalDefs(MIB);
908 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
910 assert(VT.isSimple() && "Non-simple types are invalid here!");
912 TargetRegisterClass *RC;
913 switch (VT.getSimpleVT().SimpleTy) {
914 // This is mostly going to be Neon/vector support.
915 default: return false;
917 Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
918 RC = ARM::GPRRegisterClass;
921 Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
922 RC = ARM::GPRRegisterClass;
925 Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12;
926 RC = ARM::GPRRegisterClass;
930 RC = TLI.getRegClassFor(VT);
934 RC = TLI.getRegClassFor(VT);
937 // Simplify this down to something we can handle.
938 ARMSimplifyAddress(Addr, VT);
940 // Create the base instruction, then add the operands.
941 ResultReg = createResultReg(RC);
942 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
943 TII.get(Opc), ResultReg);
944 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad);
948 bool ARMFastISel::SelectLoad(const Instruction *I) {
949 // Atomic loads need special handling.
950 if (cast<LoadInst>(I)->isAtomic())
953 // Verify we have a legal type before going any further.
955 if (!isLoadTypeLegal(I->getType(), VT))
958 // See if we can handle this address.
960 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
963 if (!ARMEmitLoad(VT, ResultReg, Addr)) return false;
964 UpdateValueMap(I, ResultReg);
968 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
970 switch (VT.getSimpleVT().SimpleTy) {
971 // This is mostly going to be Neon/vector support.
972 default: return false;
974 unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass :
975 ARM::GPRRegisterClass);
976 unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
977 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
979 .addReg(SrcReg).addImm(1));
981 } // Fallthrough here.
983 StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
986 StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
989 StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
992 if (!Subtarget->hasVFP2()) return false;
996 if (!Subtarget->hasVFP2()) return false;
1000 // Simplify this down to something we can handle.
1001 ARMSimplifyAddress(Addr, VT);
1003 // Create the base instruction, then add the operands.
1004 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1006 .addReg(SrcReg, getKillRegState(true));
1007 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore);
1011 bool ARMFastISel::SelectStore(const Instruction *I) {
1012 Value *Op0 = I->getOperand(0);
1013 unsigned SrcReg = 0;
1015 // Atomic stores need special handling.
1016 if (cast<StoreInst>(I)->isAtomic())
1019 // Verify we have a legal type before going any further.
1021 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1024 // Get the value to be stored into a register.
1025 SrcReg = getRegForValue(Op0);
1026 if (SrcReg == 0) return false;
1028 // See if we can handle this address.
1030 if (!ARMComputeAddress(I->getOperand(1), Addr))
1033 if (!ARMEmitStore(VT, SrcReg, Addr)) return false;
1037 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1039 // Needs two compares...
1040 case CmpInst::FCMP_ONE:
1041 case CmpInst::FCMP_UEQ:
1043 // AL is our "false" for now. The other two need more compares.
1045 case CmpInst::ICMP_EQ:
1046 case CmpInst::FCMP_OEQ:
1048 case CmpInst::ICMP_SGT:
1049 case CmpInst::FCMP_OGT:
1051 case CmpInst::ICMP_SGE:
1052 case CmpInst::FCMP_OGE:
1054 case CmpInst::ICMP_UGT:
1055 case CmpInst::FCMP_UGT:
1057 case CmpInst::FCMP_OLT:
1059 case CmpInst::ICMP_ULE:
1060 case CmpInst::FCMP_OLE:
1062 case CmpInst::FCMP_ORD:
1064 case CmpInst::FCMP_UNO:
1066 case CmpInst::FCMP_UGE:
1068 case CmpInst::ICMP_SLT:
1069 case CmpInst::FCMP_ULT:
1071 case CmpInst::ICMP_SLE:
1072 case CmpInst::FCMP_ULE:
1074 case CmpInst::FCMP_UNE:
1075 case CmpInst::ICMP_NE:
1077 case CmpInst::ICMP_UGE:
1079 case CmpInst::ICMP_ULT:
1084 bool ARMFastISel::SelectBranch(const Instruction *I) {
1085 const BranchInst *BI = cast<BranchInst>(I);
1086 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1087 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1089 // Simple branch support.
1091 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1093 // TODO: Factor this out.
1094 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1096 Type *Ty = CI->getOperand(0)->getType();
1097 if (CI->hasOneUse() && (CI->getParent() == I->getParent())
1098 && isTypeLegal(Ty, SourceVT)) {
1099 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1100 if (isFloat && !Subtarget->hasVFP2())
1104 switch (SourceVT.SimpleTy) {
1105 default: return false;
1106 // TODO: Verify compares.
1108 CmpOpc = ARM::VCMPES;
1111 CmpOpc = ARM::VCMPED;
1114 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1118 // Get the compare predicate.
1119 // Try to take advantage of fallthrough opportunities.
1120 CmpInst::Predicate Predicate = CI->getPredicate();
1121 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1122 std::swap(TBB, FBB);
1123 Predicate = CmpInst::getInversePredicate(Predicate);
1126 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1128 // We may not handle every CC for now.
1129 if (ARMPred == ARMCC::AL) return false;
1131 unsigned Arg1 = getRegForValue(CI->getOperand(0));
1132 if (Arg1 == 0) return false;
1134 unsigned Arg2 = getRegForValue(CI->getOperand(1));
1135 if (Arg2 == 0) return false;
1137 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1139 .addReg(Arg1).addReg(Arg2));
1141 // For floating point we need to move the result to a comparison register
1142 // that we can then use for branches.
1144 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1145 TII.get(ARM::FMSTAT)));
1147 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1148 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1149 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1150 FastEmitBranch(FBB, DL);
1151 FuncInfo.MBB->addSuccessor(TBB);
1154 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1156 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1157 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1158 unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1159 unsigned OpReg = getRegForValue(TI->getOperand(0));
1160 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1162 .addReg(OpReg).addImm(1));
1164 unsigned CCMode = ARMCC::NE;
1165 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1166 std::swap(TBB, FBB);
1170 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1171 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1172 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1174 FastEmitBranch(FBB, DL);
1175 FuncInfo.MBB->addSuccessor(TBB);
1180 unsigned CmpReg = getRegForValue(BI->getCondition());
1181 if (CmpReg == 0) return false;
1183 // We've been divorced from our compare! Our block was split, and
1184 // now our compare lives in a predecessor block. We musn't
1185 // re-compare here, as the children of the compare aren't guaranteed
1186 // live across the block boundary (we *could* check for this).
1187 // Regardless, the compare has been done in the predecessor block,
1188 // and it left a value for us in a virtual register. Ergo, we test
1189 // the one-bit value left in the virtual register.
1190 unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1191 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1192 .addReg(CmpReg).addImm(1));
1194 unsigned CCMode = ARMCC::NE;
1195 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1196 std::swap(TBB, FBB);
1200 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1201 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1202 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1203 FastEmitBranch(FBB, DL);
1204 FuncInfo.MBB->addSuccessor(TBB);
1208 bool ARMFastISel::SelectCmp(const Instruction *I) {
1209 const CmpInst *CI = cast<CmpInst>(I);
1212 Type *Ty = CI->getOperand(0)->getType();
1213 if (!isTypeLegal(Ty, VT))
1216 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1217 if (isFloat && !Subtarget->hasVFP2())
1222 switch (VT.SimpleTy) {
1223 default: return false;
1224 // TODO: Verify compares.
1226 CmpOpc = ARM::VCMPES;
1227 CondReg = ARM::FPSCR;
1230 CmpOpc = ARM::VCMPED;
1231 CondReg = ARM::FPSCR;
1234 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1235 CondReg = ARM::CPSR;
1239 // Get the compare predicate.
1240 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1242 // We may not handle every CC for now.
1243 if (ARMPred == ARMCC::AL) return false;
1245 unsigned Arg1 = getRegForValue(CI->getOperand(0));
1246 if (Arg1 == 0) return false;
1248 unsigned Arg2 = getRegForValue(CI->getOperand(1));
1249 if (Arg2 == 0) return false;
1251 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1252 .addReg(Arg1).addReg(Arg2));
1254 // For floating point we need to move the result to a comparison register
1255 // that we can then use for branches.
1257 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1258 TII.get(ARM::FMSTAT)));
1260 // Now set a register based on the comparison. Explicitly set the predicates
1262 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1263 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1264 : ARM::GPRRegisterClass;
1265 unsigned DestReg = createResultReg(RC);
1267 = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1268 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1269 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1270 .addReg(ZeroReg).addImm(1)
1271 .addImm(ARMPred).addReg(CondReg);
1273 UpdateValueMap(I, DestReg);
1277 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1278 // Make sure we have VFP and that we're extending float to double.
1279 if (!Subtarget->hasVFP2()) return false;
1281 Value *V = I->getOperand(0);
1282 if (!I->getType()->isDoubleTy() ||
1283 !V->getType()->isFloatTy()) return false;
1285 unsigned Op = getRegForValue(V);
1286 if (Op == 0) return false;
1288 unsigned Result = createResultReg(ARM::DPRRegisterClass);
1289 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1290 TII.get(ARM::VCVTDS), Result)
1292 UpdateValueMap(I, Result);
1296 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1297 // Make sure we have VFP and that we're truncating double to float.
1298 if (!Subtarget->hasVFP2()) return false;
1300 Value *V = I->getOperand(0);
1301 if (!(I->getType()->isFloatTy() &&
1302 V->getType()->isDoubleTy())) return false;
1304 unsigned Op = getRegForValue(V);
1305 if (Op == 0) return false;
1307 unsigned Result = createResultReg(ARM::SPRRegisterClass);
1308 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1309 TII.get(ARM::VCVTSD), Result)
1311 UpdateValueMap(I, Result);
1315 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1316 // Make sure we have VFP.
1317 if (!Subtarget->hasVFP2()) return false;
1320 Type *Ty = I->getType();
1321 if (!isTypeLegal(Ty, DstVT))
1324 // FIXME: Handle sign-extension where necessary.
1325 if (!I->getOperand(0)->getType()->isIntegerTy(32))
1328 unsigned Op = getRegForValue(I->getOperand(0));
1329 if (Op == 0) return false;
1331 // The conversion routine works on fp-reg to fp-reg and the operand above
1332 // was an integer, move it to the fp registers if possible.
1333 unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1334 if (FP == 0) return false;
1337 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1338 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1341 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1342 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1345 UpdateValueMap(I, ResultReg);
1349 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1350 // Make sure we have VFP.
1351 if (!Subtarget->hasVFP2()) return false;
1354 Type *RetTy = I->getType();
1355 if (!isTypeLegal(RetTy, DstVT))
1358 unsigned Op = getRegForValue(I->getOperand(0));
1359 if (Op == 0) return false;
1362 Type *OpTy = I->getOperand(0)->getType();
1363 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1364 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1367 // f64->s32 or f32->s32 both need an intermediate f32 reg.
1368 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1369 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1373 // This result needs to be in an integer register, but the conversion only
1374 // takes place in fp-regs.
1375 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1376 if (IntReg == 0) return false;
1378 UpdateValueMap(I, IntReg);
1382 bool ARMFastISel::SelectSelect(const Instruction *I) {
1384 if (!isTypeLegal(I->getType(), VT))
1387 // Things need to be register sized for register moves.
1388 if (VT != MVT::i32) return false;
1389 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1391 unsigned CondReg = getRegForValue(I->getOperand(0));
1392 if (CondReg == 0) return false;
1393 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1394 if (Op1Reg == 0) return false;
1395 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1396 if (Op2Reg == 0) return false;
1398 unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1399 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1400 .addReg(CondReg).addImm(1));
1401 unsigned ResultReg = createResultReg(RC);
1402 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1403 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1404 .addReg(Op1Reg).addReg(Op2Reg)
1405 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1406 UpdateValueMap(I, ResultReg);
1410 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1412 Type *Ty = I->getType();
1413 if (!isTypeLegal(Ty, VT))
1416 // If we have integer div support we should have selected this automagically.
1417 // In case we have a real miss go ahead and return false and we'll pick
1419 if (Subtarget->hasDivide()) return false;
1421 // Otherwise emit a libcall.
1422 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1424 LC = RTLIB::SDIV_I8;
1425 else if (VT == MVT::i16)
1426 LC = RTLIB::SDIV_I16;
1427 else if (VT == MVT::i32)
1428 LC = RTLIB::SDIV_I32;
1429 else if (VT == MVT::i64)
1430 LC = RTLIB::SDIV_I64;
1431 else if (VT == MVT::i128)
1432 LC = RTLIB::SDIV_I128;
1433 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1435 return ARMEmitLibcall(I, LC);
1438 bool ARMFastISel::SelectSRem(const Instruction *I) {
1440 Type *Ty = I->getType();
1441 if (!isTypeLegal(Ty, VT))
1444 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1446 LC = RTLIB::SREM_I8;
1447 else if (VT == MVT::i16)
1448 LC = RTLIB::SREM_I16;
1449 else if (VT == MVT::i32)
1450 LC = RTLIB::SREM_I32;
1451 else if (VT == MVT::i64)
1452 LC = RTLIB::SREM_I64;
1453 else if (VT == MVT::i128)
1454 LC = RTLIB::SREM_I128;
1455 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1457 return ARMEmitLibcall(I, LC);
1460 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1461 EVT VT = TLI.getValueType(I->getType(), true);
1463 // We can get here in the case when we want to use NEON for our fp
1464 // operations, but can't figure out how to. Just use the vfp instructions
1466 // FIXME: It'd be nice to use NEON instructions.
1467 Type *Ty = I->getType();
1468 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1469 if (isFloat && !Subtarget->hasVFP2())
1472 unsigned Op1 = getRegForValue(I->getOperand(0));
1473 if (Op1 == 0) return false;
1475 unsigned Op2 = getRegForValue(I->getOperand(1));
1476 if (Op2 == 0) return false;
1479 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1480 switch (ISDOpcode) {
1481 default: return false;
1483 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1486 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1489 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1492 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1493 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1494 TII.get(Opc), ResultReg)
1495 .addReg(Op1).addReg(Op2));
1496 UpdateValueMap(I, ResultReg);
1500 // Call Handling Code
1502 bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src,
1503 EVT SrcVT, unsigned &ResultReg) {
1504 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1505 Src, /*TODO: Kill=*/false);
1514 // This is largely taken directly from CCAssignFnForNode - we don't support
1515 // varargs in FastISel so that part has been removed.
1516 // TODO: We may not support all of this.
1517 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1520 llvm_unreachable("Unsupported calling convention");
1521 case CallingConv::Fast:
1522 // Ignore fastcc. Silence compiler warnings.
1523 (void)RetFastCC_ARM_APCS;
1524 (void)FastCC_ARM_APCS;
1526 case CallingConv::C:
1527 // Use target triple & subtarget features to do actual dispatch.
1528 if (Subtarget->isAAPCS_ABI()) {
1529 if (Subtarget->hasVFP2() &&
1530 FloatABIType == FloatABI::Hard)
1531 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1533 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1535 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1536 case CallingConv::ARM_AAPCS_VFP:
1537 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1538 case CallingConv::ARM_AAPCS:
1539 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1540 case CallingConv::ARM_APCS:
1541 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1545 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1546 SmallVectorImpl<unsigned> &ArgRegs,
1547 SmallVectorImpl<MVT> &ArgVTs,
1548 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1549 SmallVectorImpl<unsigned> &RegArgs,
1551 unsigned &NumBytes) {
1552 SmallVector<CCValAssign, 16> ArgLocs;
1553 CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1554 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1556 // Get a count of how many bytes are to be pushed on the stack.
1557 NumBytes = CCInfo.getNextStackOffset();
1559 // Issue CALLSEQ_START
1560 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1561 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1562 TII.get(AdjStackDown))
1565 // Process the args.
1566 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1567 CCValAssign &VA = ArgLocs[i];
1568 unsigned Arg = ArgRegs[VA.getValNo()];
1569 MVT ArgVT = ArgVTs[VA.getValNo()];
1571 // We don't handle NEON/vector parameters yet.
1572 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1575 // Handle arg promotion, etc.
1576 switch (VA.getLocInfo()) {
1577 case CCValAssign::Full: break;
1578 case CCValAssign::SExt: {
1579 bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1581 assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
1583 ArgVT = VA.getLocVT();
1586 case CCValAssign::ZExt: {
1587 bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1589 assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
1591 ArgVT = VA.getLocVT();
1594 case CCValAssign::AExt: {
1595 bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1598 Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1601 Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1604 assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
1605 ArgVT = VA.getLocVT();
1608 case CCValAssign::BCvt: {
1609 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1610 /*TODO: Kill=*/false);
1611 assert(BC != 0 && "Failed to emit a bitcast!");
1613 ArgVT = VA.getLocVT();
1616 default: llvm_unreachable("Unknown arg promotion!");
1619 // Now copy/store arg to correct locations.
1620 if (VA.isRegLoc() && !VA.needsCustom()) {
1621 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1624 RegArgs.push_back(VA.getLocReg());
1625 } else if (VA.needsCustom()) {
1626 // TODO: We need custom lowering for vector (v2f64) args.
1627 if (VA.getLocVT() != MVT::f64) return false;
1629 CCValAssign &NextVA = ArgLocs[++i];
1631 // TODO: Only handle register args for now.
1632 if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1634 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1635 TII.get(ARM::VMOVRRD), VA.getLocReg())
1636 .addReg(NextVA.getLocReg(), RegState::Define)
1638 RegArgs.push_back(VA.getLocReg());
1639 RegArgs.push_back(NextVA.getLocReg());
1641 assert(VA.isMemLoc());
1642 // Need to store on the stack.
1644 Addr.BaseType = Address::RegBase;
1645 Addr.Base.Reg = ARM::SP;
1646 Addr.Offset = VA.getLocMemOffset();
1648 if (!ARMEmitStore(ArgVT, Arg, Addr)) return false;
1654 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1655 const Instruction *I, CallingConv::ID CC,
1656 unsigned &NumBytes) {
1657 // Issue CALLSEQ_END
1658 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1659 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1660 TII.get(AdjStackUp))
1661 .addImm(NumBytes).addImm(0));
1663 // Now the return value.
1664 if (RetVT != MVT::isVoid) {
1665 SmallVector<CCValAssign, 16> RVLocs;
1666 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1667 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1669 // Copy all of the result registers out of their specified physreg.
1670 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1671 // For this move we copy into two registers and then move into the
1672 // double fp reg we want.
1673 EVT DestVT = RVLocs[0].getValVT();
1674 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1675 unsigned ResultReg = createResultReg(DstRC);
1676 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1677 TII.get(ARM::VMOVDRR), ResultReg)
1678 .addReg(RVLocs[0].getLocReg())
1679 .addReg(RVLocs[1].getLocReg()));
1681 UsedRegs.push_back(RVLocs[0].getLocReg());
1682 UsedRegs.push_back(RVLocs[1].getLocReg());
1684 // Finally update the result.
1685 UpdateValueMap(I, ResultReg);
1687 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1688 EVT CopyVT = RVLocs[0].getValVT();
1689 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1691 unsigned ResultReg = createResultReg(DstRC);
1692 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1693 ResultReg).addReg(RVLocs[0].getLocReg());
1694 UsedRegs.push_back(RVLocs[0].getLocReg());
1696 // Finally update the result.
1697 UpdateValueMap(I, ResultReg);
1704 bool ARMFastISel::SelectRet(const Instruction *I) {
1705 const ReturnInst *Ret = cast<ReturnInst>(I);
1706 const Function &F = *I->getParent()->getParent();
1708 if (!FuncInfo.CanLowerReturn)
1714 CallingConv::ID CC = F.getCallingConv();
1715 if (Ret->getNumOperands() > 0) {
1716 SmallVector<ISD::OutputArg, 4> Outs;
1717 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
1720 // Analyze operands of the call, assigning locations to each operand.
1721 SmallVector<CCValAssign, 16> ValLocs;
1722 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, I->getContext());
1723 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
1725 const Value *RV = Ret->getOperand(0);
1726 unsigned Reg = getRegForValue(RV);
1730 // Only handle a single return value for now.
1731 if (ValLocs.size() != 1)
1734 CCValAssign &VA = ValLocs[0];
1736 // Don't bother handling odd stuff for now.
1737 if (VA.getLocInfo() != CCValAssign::Full)
1739 // Only handle register returns for now.
1742 // TODO: For now, don't try to handle cases where getLocInfo()
1743 // says Full but the types don't match.
1744 if (TLI.getValueType(RV->getType()) != VA.getValVT())
1748 unsigned SrcReg = Reg + VA.getValNo();
1749 unsigned DstReg = VA.getLocReg();
1750 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
1751 // Avoid a cross-class copy. This is very unlikely.
1752 if (!SrcRC->contains(DstReg))
1754 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1755 DstReg).addReg(SrcReg);
1757 // Mark the register as live out of the function.
1758 MRI.addLiveOut(VA.getLocReg());
1761 unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET;
1762 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1767 unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) {
1769 // Darwin needs the r9 versions of the opcodes.
1770 bool isDarwin = Subtarget->isTargetDarwin();
1772 return isDarwin ? ARM::tBLr9 : ARM::tBL;
1774 return isDarwin ? ARM::BLr9 : ARM::BL;
1778 // A quick function that will emit a call for a named libcall in F with the
1779 // vector of passed arguments for the Instruction in I. We can assume that we
1780 // can emit a call for any libcall we can produce. This is an abridged version
1781 // of the full call infrastructure since we won't need to worry about things
1782 // like computed function pointers or strange arguments at call sites.
1783 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1785 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1786 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1788 // Handle *simple* calls for now.
1789 Type *RetTy = I->getType();
1791 if (RetTy->isVoidTy())
1792 RetVT = MVT::isVoid;
1793 else if (!isTypeLegal(RetTy, RetVT))
1796 // TODO: For now if we have long calls specified we don't handle the call.
1797 if (EnableARMLongCalls) return false;
1799 // Set up the argument vectors.
1800 SmallVector<Value*, 8> Args;
1801 SmallVector<unsigned, 8> ArgRegs;
1802 SmallVector<MVT, 8> ArgVTs;
1803 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1804 Args.reserve(I->getNumOperands());
1805 ArgRegs.reserve(I->getNumOperands());
1806 ArgVTs.reserve(I->getNumOperands());
1807 ArgFlags.reserve(I->getNumOperands());
1808 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1809 Value *Op = I->getOperand(i);
1810 unsigned Arg = getRegForValue(Op);
1811 if (Arg == 0) return false;
1813 Type *ArgTy = Op->getType();
1815 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1817 ISD::ArgFlagsTy Flags;
1818 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1819 Flags.setOrigAlign(OriginalAlignment);
1822 ArgRegs.push_back(Arg);
1823 ArgVTs.push_back(ArgVT);
1824 ArgFlags.push_back(Flags);
1827 // Handle the arguments now that we've gotten them.
1828 SmallVector<unsigned, 4> RegArgs;
1830 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1833 // Issue the call, BLr9 for darwin, BL otherwise.
1834 // TODO: Turn this into the table of arm call ops.
1835 MachineInstrBuilder MIB;
1836 unsigned CallOpc = ARMSelectCallOp(NULL);
1838 // Explicitly adding the predicate here.
1839 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1841 .addExternalSymbol(TLI.getLibcallName(Call));
1843 // Explicitly adding the predicate here.
1844 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1846 .addExternalSymbol(TLI.getLibcallName(Call)));
1848 // Add implicit physical register uses to the call.
1849 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1850 MIB.addReg(RegArgs[i]);
1852 // Finish off the call including any return values.
1853 SmallVector<unsigned, 4> UsedRegs;
1854 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1856 // Set all unused physreg defs as dead.
1857 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1862 bool ARMFastISel::SelectCall(const Instruction *I) {
1863 const CallInst *CI = cast<CallInst>(I);
1864 const Value *Callee = CI->getCalledValue();
1866 // Can't handle inline asm or worry about intrinsics yet.
1867 if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1869 // Only handle global variable Callees.
1870 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1874 // Check the calling convention.
1875 ImmutableCallSite CS(CI);
1876 CallingConv::ID CC = CS.getCallingConv();
1878 // TODO: Avoid some calling conventions?
1880 // Let SDISel handle vararg functions.
1881 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1882 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1883 if (FTy->isVarArg())
1886 // Handle *simple* calls for now.
1887 Type *RetTy = I->getType();
1889 if (RetTy->isVoidTy())
1890 RetVT = MVT::isVoid;
1891 else if (!isTypeLegal(RetTy, RetVT))
1894 // TODO: For now if we have long calls specified we don't handle the call.
1895 if (EnableARMLongCalls) return false;
1897 // Set up the argument vectors.
1898 SmallVector<Value*, 8> Args;
1899 SmallVector<unsigned, 8> ArgRegs;
1900 SmallVector<MVT, 8> ArgVTs;
1901 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1902 Args.reserve(CS.arg_size());
1903 ArgRegs.reserve(CS.arg_size());
1904 ArgVTs.reserve(CS.arg_size());
1905 ArgFlags.reserve(CS.arg_size());
1906 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1908 unsigned Arg = getRegForValue(*i);
1912 ISD::ArgFlagsTy Flags;
1913 unsigned AttrInd = i - CS.arg_begin() + 1;
1914 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1916 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1919 // FIXME: Only handle *easy* calls for now.
1920 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1921 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1922 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1923 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1926 Type *ArgTy = (*i)->getType();
1928 if (!isTypeLegal(ArgTy, ArgVT))
1930 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1931 Flags.setOrigAlign(OriginalAlignment);
1934 ArgRegs.push_back(Arg);
1935 ArgVTs.push_back(ArgVT);
1936 ArgFlags.push_back(Flags);
1939 // Handle the arguments now that we've gotten them.
1940 SmallVector<unsigned, 4> RegArgs;
1942 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1945 // Issue the call, BLr9 for darwin, BL otherwise.
1946 // TODO: Turn this into the table of arm call ops.
1947 MachineInstrBuilder MIB;
1948 unsigned CallOpc = ARMSelectCallOp(GV);
1949 // Explicitly adding the predicate here.
1951 // Explicitly adding the predicate here.
1952 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1954 .addGlobalAddress(GV, 0, 0);
1956 // Explicitly adding the predicate here.
1957 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1959 .addGlobalAddress(GV, 0, 0));
1961 // Add implicit physical register uses to the call.
1962 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1963 MIB.addReg(RegArgs[i]);
1965 // Finish off the call including any return values.
1966 SmallVector<unsigned, 4> UsedRegs;
1967 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1969 // Set all unused physreg defs as dead.
1970 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1976 bool ARMFastISel::SelectIntCast(const Instruction *I) {
1977 // On ARM, in general, integer casts don't involve legal types; this code
1978 // handles promotable integers. The high bits for a type smaller than
1979 // the register size are assumed to be undefined.
1980 Type *DestTy = I->getType();
1981 Value *Op = I->getOperand(0);
1982 Type *SrcTy = Op->getType();
1985 SrcVT = TLI.getValueType(SrcTy, true);
1986 DestVT = TLI.getValueType(DestTy, true);
1988 if (isa<TruncInst>(I)) {
1989 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1991 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1994 unsigned SrcReg = getRegForValue(Op);
1995 if (!SrcReg) return false;
1997 // Because the high bits are undefined, a truncate doesn't generate
1999 UpdateValueMap(I, SrcReg);
2002 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2006 bool isZext = isa<ZExtInst>(I);
2007 bool isBoolZext = false;
2008 if (!SrcVT.isSimple())
2010 switch (SrcVT.getSimpleVT().SimpleTy) {
2011 default: return false;
2013 if (!Subtarget->hasV6Ops()) return false;
2015 Opc = isThumb ? ARM::t2UXTH : ARM::UXTH;
2017 Opc = isThumb ? ARM::t2SXTH : ARM::SXTH;
2020 if (!Subtarget->hasV6Ops()) return false;
2022 Opc = isThumb ? ARM::t2UXTB : ARM::UXTB;
2024 Opc = isThumb ? ARM::t2SXTB : ARM::SXTB;
2028 Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
2035 // FIXME: We could save an instruction in many cases by special-casing
2036 // load instructions.
2037 unsigned SrcReg = getRegForValue(Op);
2038 if (!SrcReg) return false;
2040 unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2041 MachineInstrBuilder MIB;
2042 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
2048 AddOptionalDefs(MIB);
2049 UpdateValueMap(I, DestReg);
2053 // TODO: SoftFP support.
2054 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2056 switch (I->getOpcode()) {
2057 case Instruction::Load:
2058 return SelectLoad(I);
2059 case Instruction::Store:
2060 return SelectStore(I);
2061 case Instruction::Br:
2062 return SelectBranch(I);
2063 case Instruction::ICmp:
2064 case Instruction::FCmp:
2065 return SelectCmp(I);
2066 case Instruction::FPExt:
2067 return SelectFPExt(I);
2068 case Instruction::FPTrunc:
2069 return SelectFPTrunc(I);
2070 case Instruction::SIToFP:
2071 return SelectSIToFP(I);
2072 case Instruction::FPToSI:
2073 return SelectFPToSI(I);
2074 case Instruction::FAdd:
2075 return SelectBinaryOp(I, ISD::FADD);
2076 case Instruction::FSub:
2077 return SelectBinaryOp(I, ISD::FSUB);
2078 case Instruction::FMul:
2079 return SelectBinaryOp(I, ISD::FMUL);
2080 case Instruction::SDiv:
2081 return SelectSDiv(I);
2082 case Instruction::SRem:
2083 return SelectSRem(I);
2084 case Instruction::Call:
2085 return SelectCall(I);
2086 case Instruction::Select:
2087 return SelectSelect(I);
2088 case Instruction::Ret:
2089 return SelectRet(I);
2090 case Instruction::Trunc:
2091 case Instruction::ZExt:
2092 case Instruction::SExt:
2093 return SelectIntCast(I);
2100 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
2101 // Completely untested on non-darwin.
2102 const TargetMachine &TM = funcInfo.MF->getTarget();
2104 // Darwin and thumb1 only for now.
2105 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2106 if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() &&
2107 !DisableARMFastISel)
2108 return new ARMFastISel(funcInfo);