1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/GetElementPtrTypeIterator.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Module.h"
43 #include "llvm/IR/Operator.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
54 // All possible address modes, plus some.
55 typedef struct Address {
68 // Innocuous defaults for our address.
70 : BaseType(RegBase), Offset(0) {
75 class ARMFastISel final : public FastISel {
77 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
78 /// make the right decision when generating code for different targets.
79 const ARMSubtarget *Subtarget;
81 const TargetMachine &TM;
82 const TargetInstrInfo &TII;
83 const TargetLowering &TLI;
86 // Convenience variables to avoid some queries.
91 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
92 const TargetLibraryInfo *libInfo)
93 : FastISel(funcInfo, libInfo),
95 &static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget())),
96 M(const_cast<Module &>(*funcInfo.Fn->getParent())),
97 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
98 TLI(*Subtarget->getTargetLowering()) {
99 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
100 isThumb2 = AFI->isThumbFunction();
101 Context = &funcInfo.Fn->getContext();
104 // Code from FastISel.cpp.
106 unsigned fastEmitInst_r(unsigned MachineInstOpcode,
107 const TargetRegisterClass *RC,
108 unsigned Op0, bool Op0IsKill);
109 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
110 const TargetRegisterClass *RC,
111 unsigned Op0, bool Op0IsKill,
112 unsigned Op1, bool Op1IsKill);
113 unsigned fastEmitInst_rrr(unsigned MachineInstOpcode,
114 const TargetRegisterClass *RC,
115 unsigned Op0, bool Op0IsKill,
116 unsigned Op1, bool Op1IsKill,
117 unsigned Op2, bool Op2IsKill);
118 unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill,
122 unsigned fastEmitInst_rri(unsigned MachineInstOpcode,
123 const TargetRegisterClass *RC,
124 unsigned Op0, bool Op0IsKill,
125 unsigned Op1, bool Op1IsKill,
127 unsigned fastEmitInst_i(unsigned MachineInstOpcode,
128 const TargetRegisterClass *RC,
131 // Backend specific FastISel code.
133 bool fastSelectInstruction(const Instruction *I) override;
134 unsigned fastMaterializeConstant(const Constant *C) override;
135 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
136 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
137 const LoadInst *LI) override;
138 bool fastLowerArguments() override;
140 #include "ARMGenFastISel.inc"
142 // Instruction selection routines.
144 bool SelectLoad(const Instruction *I);
145 bool SelectStore(const Instruction *I);
146 bool SelectBranch(const Instruction *I);
147 bool SelectIndirectBr(const Instruction *I);
148 bool SelectCmp(const Instruction *I);
149 bool SelectFPExt(const Instruction *I);
150 bool SelectFPTrunc(const Instruction *I);
151 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
152 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
153 bool SelectIToFP(const Instruction *I, bool isSigned);
154 bool SelectFPToI(const Instruction *I, bool isSigned);
155 bool SelectDiv(const Instruction *I, bool isSigned);
156 bool SelectRem(const Instruction *I, bool isSigned);
157 bool SelectCall(const Instruction *I, const char *IntrMemName);
158 bool SelectIntrinsicCall(const IntrinsicInst &I);
159 bool SelectSelect(const Instruction *I);
160 bool SelectRet(const Instruction *I);
161 bool SelectTrunc(const Instruction *I);
162 bool SelectIntExt(const Instruction *I);
163 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
167 bool isTypeLegal(Type *Ty, MVT &VT);
168 bool isLoadTypeLegal(Type *Ty, MVT &VT);
169 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
171 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
172 unsigned Alignment = 0, bool isZExt = true,
173 bool allocReg = true);
174 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
175 unsigned Alignment = 0);
176 bool ARMComputeAddress(const Value *Obj, Address &Addr);
177 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
178 bool ARMIsMemCpySmall(uint64_t Len);
179 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
181 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
182 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
183 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
184 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
185 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
186 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
187 unsigned ARMSelectCallOp(bool UseReg);
188 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
190 const TargetLowering *getTargetLowering() { return &TLI; }
192 // Call handling routines.
194 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
197 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
198 SmallVectorImpl<unsigned> &ArgRegs,
199 SmallVectorImpl<MVT> &ArgVTs,
200 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
201 SmallVectorImpl<unsigned> &RegArgs,
205 unsigned getLibcallReg(const Twine &Name);
206 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
207 const Instruction *I, CallingConv::ID CC,
208 unsigned &NumBytes, bool isVarArg);
209 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
211 // OptionalDef handling routines.
213 bool isARMNEONPred(const MachineInstr *MI);
214 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
215 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
216 void AddLoadStoreOperands(MVT VT, Address &Addr,
217 const MachineInstrBuilder &MIB,
218 unsigned Flags, bool useAM3);
221 } // end anonymous namespace
223 #include "ARMGenCallingConv.inc"
225 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
226 // we don't care about implicit defs here, just places we'll need to add a
227 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
228 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
229 if (!MI->hasOptionalDef())
232 // Look to see if our OptionalDef is defining CPSR or CCR.
233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
234 const MachineOperand &MO = MI->getOperand(i);
235 if (!MO.isReg() || !MO.isDef()) continue;
236 if (MO.getReg() == ARM::CPSR)
242 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
243 const MCInstrDesc &MCID = MI->getDesc();
245 // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
246 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
247 AFI->isThumb2Function())
248 return MI->isPredicable();
250 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
251 if (MCID.OpInfo[i].isPredicate())
257 // If the machine is predicable go ahead and add the predicate operands, if
258 // it needs default CC operands add those.
259 // TODO: If we want to support thumb1 then we'll need to deal with optional
260 // CPSR defs that need to be added before the remaining operands. See s_cc_out
261 // for descriptions why.
262 const MachineInstrBuilder &
263 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
264 MachineInstr *MI = &*MIB;
266 // Do we use a predicate? or...
267 // Are we NEON in ARM mode and have a predicate operand? If so, I know
268 // we're not predicable but add it anyways.
269 if (isARMNEONPred(MI))
272 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
273 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
275 if (DefinesOptionalPredicate(MI, &CPSR)) {
284 unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
285 const TargetRegisterClass *RC,
286 unsigned Op0, bool Op0IsKill) {
287 unsigned ResultReg = createResultReg(RC);
288 const MCInstrDesc &II = TII.get(MachineInstOpcode);
290 // Make sure the input operand is sufficiently constrained to be legal
291 // for this instruction.
292 Op0 = constrainOperandRegClass(II, Op0, 1);
293 if (II.getNumDefs() >= 1) {
294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
295 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
298 .addReg(Op0, Op0IsKill * RegState::Kill));
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
300 TII.get(TargetOpcode::COPY), ResultReg)
301 .addReg(II.ImplicitDefs[0]));
306 unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
307 const TargetRegisterClass *RC,
308 unsigned Op0, bool Op0IsKill,
309 unsigned Op1, bool Op1IsKill) {
310 unsigned ResultReg = createResultReg(RC);
311 const MCInstrDesc &II = TII.get(MachineInstOpcode);
313 // Make sure the input operands are sufficiently constrained to be legal
314 // for this instruction.
315 Op0 = constrainOperandRegClass(II, Op0, 1);
316 Op1 = constrainOperandRegClass(II, Op1, 2);
318 if (II.getNumDefs() >= 1) {
320 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
321 .addReg(Op0, Op0IsKill * RegState::Kill)
322 .addReg(Op1, Op1IsKill * RegState::Kill));
324 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
325 .addReg(Op0, Op0IsKill * RegState::Kill)
326 .addReg(Op1, Op1IsKill * RegState::Kill));
327 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
328 TII.get(TargetOpcode::COPY), ResultReg)
329 .addReg(II.ImplicitDefs[0]));
334 unsigned ARMFastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
335 const TargetRegisterClass *RC,
336 unsigned Op0, bool Op0IsKill,
337 unsigned Op1, bool Op1IsKill,
338 unsigned Op2, bool Op2IsKill) {
339 unsigned ResultReg = createResultReg(RC);
340 const MCInstrDesc &II = TII.get(MachineInstOpcode);
342 // Make sure the input operands are sufficiently constrained to be legal
343 // for this instruction.
344 Op0 = constrainOperandRegClass(II, Op0, 1);
345 Op1 = constrainOperandRegClass(II, Op1, 2);
346 Op2 = constrainOperandRegClass(II, Op1, 3);
348 if (II.getNumDefs() >= 1) {
350 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
351 .addReg(Op0, Op0IsKill * RegState::Kill)
352 .addReg(Op1, Op1IsKill * RegState::Kill)
353 .addReg(Op2, Op2IsKill * RegState::Kill));
355 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
356 .addReg(Op0, Op0IsKill * RegState::Kill)
357 .addReg(Op1, Op1IsKill * RegState::Kill)
358 .addReg(Op2, Op2IsKill * RegState::Kill));
359 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
360 TII.get(TargetOpcode::COPY), ResultReg)
361 .addReg(II.ImplicitDefs[0]));
366 unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
367 const TargetRegisterClass *RC,
368 unsigned Op0, bool Op0IsKill,
370 unsigned ResultReg = createResultReg(RC);
371 const MCInstrDesc &II = TII.get(MachineInstOpcode);
373 // Make sure the input operand is sufficiently constrained to be legal
374 // for this instruction.
375 Op0 = constrainOperandRegClass(II, Op0, 1);
376 if (II.getNumDefs() >= 1) {
378 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
379 .addReg(Op0, Op0IsKill * RegState::Kill)
382 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
383 .addReg(Op0, Op0IsKill * RegState::Kill)
385 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
386 TII.get(TargetOpcode::COPY), ResultReg)
387 .addReg(II.ImplicitDefs[0]));
392 unsigned ARMFastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
393 const TargetRegisterClass *RC,
394 unsigned Op0, bool Op0IsKill,
395 unsigned Op1, bool Op1IsKill,
397 unsigned ResultReg = createResultReg(RC);
398 const MCInstrDesc &II = TII.get(MachineInstOpcode);
400 // Make sure the input operands are sufficiently constrained to be legal
401 // for this instruction.
402 Op0 = constrainOperandRegClass(II, Op0, 1);
403 Op1 = constrainOperandRegClass(II, Op1, 2);
404 if (II.getNumDefs() >= 1) {
406 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
407 .addReg(Op0, Op0IsKill * RegState::Kill)
408 .addReg(Op1, Op1IsKill * RegState::Kill)
411 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
412 .addReg(Op0, Op0IsKill * RegState::Kill)
413 .addReg(Op1, Op1IsKill * RegState::Kill)
415 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
416 TII.get(TargetOpcode::COPY), ResultReg)
417 .addReg(II.ImplicitDefs[0]));
422 unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
423 const TargetRegisterClass *RC,
425 unsigned ResultReg = createResultReg(RC);
426 const MCInstrDesc &II = TII.get(MachineInstOpcode);
428 if (II.getNumDefs() >= 1) {
429 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
430 ResultReg).addImm(Imm));
432 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
434 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
435 TII.get(TargetOpcode::COPY), ResultReg)
436 .addReg(II.ImplicitDefs[0]));
441 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
442 // checks from the various callers.
443 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
444 if (VT == MVT::f64) return 0;
446 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
447 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
448 TII.get(ARM::VMOVSR), MoveReg)
453 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
454 if (VT == MVT::i64) return 0;
456 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
457 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
458 TII.get(ARM::VMOVRS), MoveReg)
463 // For double width floating point we need to materialize two constants
464 // (the high and the low) into integer registers then use a move to get
465 // the combined constant into an FP reg.
466 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
467 const APFloat Val = CFP->getValueAPF();
468 bool is64bit = VT == MVT::f64;
470 // This checks to see if we can use VFP3 instructions to materialize
471 // a constant, otherwise we have to go through the constant pool.
472 if (TLI.isFPImmLegal(Val, VT)) {
476 Imm = ARM_AM::getFP64Imm(Val);
479 Imm = ARM_AM::getFP32Imm(Val);
482 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
483 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
484 TII.get(Opc), DestReg).addImm(Imm));
488 // Require VFP2 for loading fp constants.
489 if (!Subtarget->hasVFP2()) return false;
491 // MachineConstantPool wants an explicit alignment.
492 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
494 // TODO: Figure out if this is correct.
495 Align = DL.getTypeAllocSize(CFP->getType());
497 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
498 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
499 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
501 // The extra reg is for addrmode5.
503 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
504 .addConstantPoolIndex(Idx)
509 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
511 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
514 // If we can do this in a single instruction without a constant pool entry
516 const ConstantInt *CI = cast<ConstantInt>(C);
517 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
518 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
519 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
521 unsigned ImmReg = createResultReg(RC);
522 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
523 TII.get(Opc), ImmReg)
524 .addImm(CI->getZExtValue()));
528 // Use MVN to emit negative constants.
529 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
530 unsigned Imm = (unsigned)~(CI->getSExtValue());
531 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
532 (ARM_AM::getSOImmVal(Imm) != -1);
534 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
535 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
537 unsigned ImmReg = createResultReg(RC);
538 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
539 TII.get(Opc), ImmReg)
545 unsigned ResultReg = 0;
546 if (Subtarget->useMovt(*FuncInfo.MF))
547 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
552 // Load from constant pool. For now 32-bit only.
556 // MachineConstantPool wants an explicit alignment.
557 unsigned Align = DL.getPrefTypeAlignment(C->getType());
559 // TODO: Figure out if this is correct.
560 Align = DL.getTypeAllocSize(C->getType());
562 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
563 ResultReg = createResultReg(TLI.getRegClassFor(VT));
565 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
566 TII.get(ARM::t2LDRpci), ResultReg)
567 .addConstantPoolIndex(Idx));
569 // The extra immediate is for addrmode2.
570 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
571 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
572 TII.get(ARM::LDRcp), ResultReg)
573 .addConstantPoolIndex(Idx)
579 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
580 // For now 32-bit only.
581 if (VT != MVT::i32) return 0;
583 Reloc::Model RelocM = TM.getRelocationModel();
584 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
585 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
587 unsigned DestReg = createResultReg(RC);
589 // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
590 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
591 bool IsThreadLocal = GVar && GVar->isThreadLocal();
592 if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
594 // Use movw+movt when possible, it avoids constant pool entries.
595 // Non-darwin targets only support static movt relocations in FastISel.
596 if (Subtarget->useMovt(*FuncInfo.MF) &&
597 (Subtarget->isTargetMachO() || RelocM == Reloc::Static)) {
599 unsigned char TF = 0;
600 if (Subtarget->isTargetMachO())
601 TF = ARMII::MO_NONLAZY;
605 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
608 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
611 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
612 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
614 // MachineConstantPool wants an explicit alignment.
615 unsigned Align = DL.getPrefTypeAlignment(GV->getType());
617 // TODO: Figure out if this is correct.
618 Align = DL.getTypeAllocSize(GV->getType());
621 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
622 return ARMLowerPICELF(GV, Align, VT);
625 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
626 (Subtarget->isThumb() ? 4 : 8);
627 unsigned Id = AFI->createPICLabelUId();
628 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
631 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
634 MachineInstrBuilder MIB;
636 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
637 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
638 DestReg).addConstantPoolIndex(Idx);
639 if (RelocM == Reloc::PIC_)
641 AddOptionalDefs(MIB);
643 // The extra immediate is for addrmode2.
644 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
645 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
646 TII.get(ARM::LDRcp), DestReg)
647 .addConstantPoolIndex(Idx)
649 AddOptionalDefs(MIB);
651 if (RelocM == Reloc::PIC_) {
652 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
653 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
655 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
656 DbgLoc, TII.get(Opc), NewDestReg)
659 AddOptionalDefs(MIB);
666 MachineInstrBuilder MIB;
667 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
669 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
670 TII.get(ARM::t2LDRi12), NewDestReg)
674 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
675 TII.get(ARM::LDRi12), NewDestReg)
678 DestReg = NewDestReg;
679 AddOptionalDefs(MIB);
685 unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
686 EVT CEVT = TLI.getValueType(C->getType(), true);
688 // Only handle simple types.
689 if (!CEVT.isSimple()) return 0;
690 MVT VT = CEVT.getSimpleVT();
692 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
693 return ARMMaterializeFP(CFP, VT);
694 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
695 return ARMMaterializeGV(GV, VT);
696 else if (isa<ConstantInt>(C))
697 return ARMMaterializeInt(C, VT);
702 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
704 unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
705 // Don't handle dynamic allocas.
706 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
709 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
711 DenseMap<const AllocaInst*, int>::iterator SI =
712 FuncInfo.StaticAllocaMap.find(AI);
714 // This will get lowered later into the correct offsets and registers
715 // via rewriteXFrameIndex.
716 if (SI != FuncInfo.StaticAllocaMap.end()) {
717 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
718 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
719 unsigned ResultReg = createResultReg(RC);
720 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
722 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
723 TII.get(Opc), ResultReg)
724 .addFrameIndex(SI->second)
732 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
733 EVT evt = TLI.getValueType(Ty, true);
735 // Only handle simple types.
736 if (evt == MVT::Other || !evt.isSimple()) return false;
737 VT = evt.getSimpleVT();
739 // Handle all legal types, i.e. a register that will directly hold this
741 return TLI.isTypeLegal(VT);
744 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
745 if (isTypeLegal(Ty, VT)) return true;
747 // If this is a type than can be sign or zero-extended to a basic operation
748 // go ahead and accept it now.
749 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
755 // Computes the address to get to an object.
756 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
757 // Some boilerplate from the X86 FastISel.
758 const User *U = nullptr;
759 unsigned Opcode = Instruction::UserOp1;
760 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
761 // Don't walk into other basic blocks unless the object is an alloca from
762 // another block, otherwise it may not have a virtual register assigned.
763 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
764 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
765 Opcode = I->getOpcode();
768 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
769 Opcode = C->getOpcode();
773 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
774 if (Ty->getAddressSpace() > 255)
775 // Fast instruction selection doesn't support the special
782 case Instruction::BitCast:
783 // Look through bitcasts.
784 return ARMComputeAddress(U->getOperand(0), Addr);
785 case Instruction::IntToPtr:
786 // Look past no-op inttoptrs.
787 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
788 return ARMComputeAddress(U->getOperand(0), Addr);
790 case Instruction::PtrToInt:
791 // Look past no-op ptrtoints.
792 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
793 return ARMComputeAddress(U->getOperand(0), Addr);
795 case Instruction::GetElementPtr: {
796 Address SavedAddr = Addr;
797 int TmpOffset = Addr.Offset;
799 // Iterate through the GEP folding the constants into offsets where
801 gep_type_iterator GTI = gep_type_begin(U);
802 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
803 i != e; ++i, ++GTI) {
804 const Value *Op = *i;
805 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
806 const StructLayout *SL = DL.getStructLayout(STy);
807 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
808 TmpOffset += SL->getElementOffset(Idx);
810 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
812 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
813 // Constant-offset addressing.
814 TmpOffset += CI->getSExtValue() * S;
817 if (canFoldAddIntoGEP(U, Op)) {
818 // A compatible add with a constant operand. Fold the constant.
820 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
821 TmpOffset += CI->getSExtValue() * S;
822 // Iterate on the other operand.
823 Op = cast<AddOperator>(Op)->getOperand(0);
827 goto unsupported_gep;
832 // Try to grab the base operand now.
833 Addr.Offset = TmpOffset;
834 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
836 // We failed, restore everything and try the other options.
842 case Instruction::Alloca: {
843 const AllocaInst *AI = cast<AllocaInst>(Obj);
844 DenseMap<const AllocaInst*, int>::iterator SI =
845 FuncInfo.StaticAllocaMap.find(AI);
846 if (SI != FuncInfo.StaticAllocaMap.end()) {
847 Addr.BaseType = Address::FrameIndexBase;
848 Addr.Base.FI = SI->second;
855 // Try to get this in a register if nothing else has worked.
856 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
857 return Addr.Base.Reg != 0;
860 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
861 bool needsLowering = false;
862 switch (VT.SimpleTy) {
863 default: llvm_unreachable("Unhandled load/store type!");
869 // Integer loads/stores handle 12-bit offsets.
870 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
871 // Handle negative offsets.
872 if (needsLowering && isThumb2)
873 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
876 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
877 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
882 // Floating point operands handle 8-bit offsets.
883 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
887 // If this is a stack pointer and the offset needs to be simplified then
888 // put the alloca address into a register, set the base type back to
889 // register and continue. This should almost never happen.
890 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
891 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
893 unsigned ResultReg = createResultReg(RC);
894 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
895 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
896 TII.get(Opc), ResultReg)
897 .addFrameIndex(Addr.Base.FI)
899 Addr.Base.Reg = ResultReg;
900 Addr.BaseType = Address::RegBase;
903 // Since the offset is too large for the load/store instruction
904 // get the reg+offset into a register.
906 Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
907 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
912 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
913 const MachineInstrBuilder &MIB,
914 unsigned Flags, bool useAM3) {
915 // addrmode5 output depends on the selection dag addressing dividing the
916 // offset by 4 that it then later multiplies. Do this here as well.
917 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
920 // Frame base works a bit differently. Handle it separately.
921 if (Addr.BaseType == Address::FrameIndexBase) {
922 int FI = Addr.Base.FI;
923 int Offset = Addr.Offset;
924 MachineMemOperand *MMO =
925 FuncInfo.MF->getMachineMemOperand(
926 MachinePointerInfo::getFixedStack(FI, Offset),
928 MFI.getObjectSize(FI),
929 MFI.getObjectAlignment(FI));
930 // Now add the rest of the operands.
931 MIB.addFrameIndex(FI);
933 // ARM halfword load/stores and signed byte loads need an additional
936 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
940 MIB.addImm(Addr.Offset);
942 MIB.addMemOperand(MMO);
944 // Now add the rest of the operands.
945 MIB.addReg(Addr.Base.Reg);
947 // ARM halfword load/stores and signed byte loads need an additional
950 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
954 MIB.addImm(Addr.Offset);
957 AddOptionalDefs(MIB);
960 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
961 unsigned Alignment, bool isZExt, bool allocReg) {
964 bool needVMOV = false;
965 const TargetRegisterClass *RC;
966 switch (VT.SimpleTy) {
967 // This is mostly going to be Neon/vector support.
968 default: return false;
972 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
973 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
975 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
984 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
987 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
991 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
992 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
994 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
996 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
999 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1002 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1006 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1009 Opc = ARM::t2LDRi12;
1013 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1016 if (!Subtarget->hasVFP2()) return false;
1017 // Unaligned loads need special handling. Floats require word-alignment.
1018 if (Alignment && Alignment < 4) {
1021 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1022 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1025 RC = TLI.getRegClassFor(VT);
1029 if (!Subtarget->hasVFP2()) return false;
1030 // FIXME: Unaligned loads need special handling. Doublewords require
1032 if (Alignment && Alignment < 4)
1036 RC = TLI.getRegClassFor(VT);
1039 // Simplify this down to something we can handle.
1040 ARMSimplifyAddress(Addr, VT, useAM3);
1042 // Create the base instruction, then add the operands.
1044 ResultReg = createResultReg(RC);
1045 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1046 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1047 TII.get(Opc), ResultReg);
1048 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1050 // If we had an unaligned load of a float we've converted it to an regular
1051 // load. Now we must move from the GRP to the FP register.
1053 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1054 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1055 TII.get(ARM::VMOVSR), MoveReg)
1056 .addReg(ResultReg));
1057 ResultReg = MoveReg;
1062 bool ARMFastISel::SelectLoad(const Instruction *I) {
1063 // Atomic loads need special handling.
1064 if (cast<LoadInst>(I)->isAtomic())
1067 // Verify we have a legal type before going any further.
1069 if (!isLoadTypeLegal(I->getType(), VT))
1072 // See if we can handle this address.
1074 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1077 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1079 updateValueMap(I, ResultReg);
1083 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1084 unsigned Alignment) {
1086 bool useAM3 = false;
1087 switch (VT.SimpleTy) {
1088 // This is mostly going to be Neon/vector support.
1089 default: return false;
1091 unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass
1092 : &ARM::GPRRegClass);
1093 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1094 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1095 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1097 .addReg(SrcReg).addImm(1));
1099 } // Fallthrough here.
1102 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1103 StrOpc = ARM::t2STRBi8;
1105 StrOpc = ARM::t2STRBi12;
1107 StrOpc = ARM::STRBi12;
1111 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1115 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1116 StrOpc = ARM::t2STRHi8;
1118 StrOpc = ARM::t2STRHi12;
1125 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1129 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1130 StrOpc = ARM::t2STRi8;
1132 StrOpc = ARM::t2STRi12;
1134 StrOpc = ARM::STRi12;
1138 if (!Subtarget->hasVFP2()) return false;
1139 // Unaligned stores need special handling. Floats require word-alignment.
1140 if (Alignment && Alignment < 4) {
1141 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1142 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1143 TII.get(ARM::VMOVRS), MoveReg)
1147 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1149 StrOpc = ARM::VSTRS;
1153 if (!Subtarget->hasVFP2()) return false;
1154 // FIXME: Unaligned stores need special handling. Doublewords require
1156 if (Alignment && Alignment < 4)
1159 StrOpc = ARM::VSTRD;
1162 // Simplify this down to something we can handle.
1163 ARMSimplifyAddress(Addr, VT, useAM3);
1165 // Create the base instruction, then add the operands.
1166 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1167 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1170 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1174 bool ARMFastISel::SelectStore(const Instruction *I) {
1175 Value *Op0 = I->getOperand(0);
1176 unsigned SrcReg = 0;
1178 // Atomic stores need special handling.
1179 if (cast<StoreInst>(I)->isAtomic())
1182 // Verify we have a legal type before going any further.
1184 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1187 // Get the value to be stored into a register.
1188 SrcReg = getRegForValue(Op0);
1189 if (SrcReg == 0) return false;
1191 // See if we can handle this address.
1193 if (!ARMComputeAddress(I->getOperand(1), Addr))
1196 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1201 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1203 // Needs two compares...
1204 case CmpInst::FCMP_ONE:
1205 case CmpInst::FCMP_UEQ:
1207 // AL is our "false" for now. The other two need more compares.
1209 case CmpInst::ICMP_EQ:
1210 case CmpInst::FCMP_OEQ:
1212 case CmpInst::ICMP_SGT:
1213 case CmpInst::FCMP_OGT:
1215 case CmpInst::ICMP_SGE:
1216 case CmpInst::FCMP_OGE:
1218 case CmpInst::ICMP_UGT:
1219 case CmpInst::FCMP_UGT:
1221 case CmpInst::FCMP_OLT:
1223 case CmpInst::ICMP_ULE:
1224 case CmpInst::FCMP_OLE:
1226 case CmpInst::FCMP_ORD:
1228 case CmpInst::FCMP_UNO:
1230 case CmpInst::FCMP_UGE:
1232 case CmpInst::ICMP_SLT:
1233 case CmpInst::FCMP_ULT:
1235 case CmpInst::ICMP_SLE:
1236 case CmpInst::FCMP_ULE:
1238 case CmpInst::FCMP_UNE:
1239 case CmpInst::ICMP_NE:
1241 case CmpInst::ICMP_UGE:
1243 case CmpInst::ICMP_ULT:
1248 bool ARMFastISel::SelectBranch(const Instruction *I) {
1249 const BranchInst *BI = cast<BranchInst>(I);
1250 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1251 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1253 // Simple branch support.
1255 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1257 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1258 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1260 // Get the compare predicate.
1261 // Try to take advantage of fallthrough opportunities.
1262 CmpInst::Predicate Predicate = CI->getPredicate();
1263 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1264 std::swap(TBB, FBB);
1265 Predicate = CmpInst::getInversePredicate(Predicate);
1268 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1270 // We may not handle every CC for now.
1271 if (ARMPred == ARMCC::AL) return false;
1273 // Emit the compare.
1274 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1277 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1278 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1279 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1280 fastEmitBranch(FBB, DbgLoc);
1281 FuncInfo.MBB->addSuccessor(TBB);
1284 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1286 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1287 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1288 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1289 unsigned OpReg = getRegForValue(TI->getOperand(0));
1290 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1291 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1293 .addReg(OpReg).addImm(1));
1295 unsigned CCMode = ARMCC::NE;
1296 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1297 std::swap(TBB, FBB);
1301 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1302 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1303 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1305 fastEmitBranch(FBB, DbgLoc);
1306 FuncInfo.MBB->addSuccessor(TBB);
1309 } else if (const ConstantInt *CI =
1310 dyn_cast<ConstantInt>(BI->getCondition())) {
1311 uint64_t Imm = CI->getZExtValue();
1312 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1313 fastEmitBranch(Target, DbgLoc);
1317 unsigned CmpReg = getRegForValue(BI->getCondition());
1318 if (CmpReg == 0) return false;
1320 // We've been divorced from our compare! Our block was split, and
1321 // now our compare lives in a predecessor block. We musn't
1322 // re-compare here, as the children of the compare aren't guaranteed
1323 // live across the block boundary (we *could* check for this).
1324 // Regardless, the compare has been done in the predecessor block,
1325 // and it left a value for us in a virtual register. Ergo, we test
1326 // the one-bit value left in the virtual register.
1327 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1328 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1330 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1334 unsigned CCMode = ARMCC::NE;
1335 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1336 std::swap(TBB, FBB);
1340 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1341 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1342 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1343 fastEmitBranch(FBB, DbgLoc);
1344 FuncInfo.MBB->addSuccessor(TBB);
1348 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1349 unsigned AddrReg = getRegForValue(I->getOperand(0));
1350 if (AddrReg == 0) return false;
1352 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1353 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1354 TII.get(Opc)).addReg(AddrReg));
1356 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1357 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1358 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1363 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1365 Type *Ty = Src1Value->getType();
1366 EVT SrcEVT = TLI.getValueType(Ty, true);
1367 if (!SrcEVT.isSimple()) return false;
1368 MVT SrcVT = SrcEVT.getSimpleVT();
1370 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1371 if (isFloat && !Subtarget->hasVFP2())
1374 // Check to see if the 2nd operand is a constant that we can encode directly
1377 bool UseImm = false;
1378 bool isNegativeImm = false;
1379 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1380 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1381 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1382 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1384 const APInt &CIVal = ConstInt->getValue();
1385 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1386 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1387 // then a cmn, because there is no way to represent 2147483648 as a
1388 // signed 32-bit int.
1389 if (Imm < 0 && Imm != (int)0x80000000) {
1390 isNegativeImm = true;
1393 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1394 (ARM_AM::getSOImmVal(Imm) != -1);
1396 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1397 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1398 if (ConstFP->isZero() && !ConstFP->isNegative())
1404 bool needsExt = false;
1405 switch (SrcVT.SimpleTy) {
1406 default: return false;
1407 // TODO: Verify compares.
1410 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1414 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1420 // Intentional fall-through.
1424 CmpOpc = ARM::t2CMPrr;
1426 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1429 CmpOpc = ARM::CMPrr;
1431 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1436 unsigned SrcReg1 = getRegForValue(Src1Value);
1437 if (SrcReg1 == 0) return false;
1439 unsigned SrcReg2 = 0;
1441 SrcReg2 = getRegForValue(Src2Value);
1442 if (SrcReg2 == 0) return false;
1445 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1447 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1448 if (SrcReg1 == 0) return false;
1450 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1451 if (SrcReg2 == 0) return false;
1455 const MCInstrDesc &II = TII.get(CmpOpc);
1456 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1458 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1459 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1460 .addReg(SrcReg1).addReg(SrcReg2));
1462 MachineInstrBuilder MIB;
1463 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1466 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1469 AddOptionalDefs(MIB);
1472 // For floating point we need to move the result to a comparison register
1473 // that we can then use for branches.
1474 if (Ty->isFloatTy() || Ty->isDoubleTy())
1475 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1476 TII.get(ARM::FMSTAT)));
1480 bool ARMFastISel::SelectCmp(const Instruction *I) {
1481 const CmpInst *CI = cast<CmpInst>(I);
1483 // Get the compare predicate.
1484 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1486 // We may not handle every CC for now.
1487 if (ARMPred == ARMCC::AL) return false;
1489 // Emit the compare.
1490 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1493 // Now set a register based on the comparison. Explicitly set the predicates
1495 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1496 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
1497 : &ARM::GPRRegClass;
1498 unsigned DestReg = createResultReg(RC);
1499 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1500 unsigned ZeroReg = fastMaterializeConstant(Zero);
1501 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1502 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
1503 .addReg(ZeroReg).addImm(1)
1504 .addImm(ARMPred).addReg(ARM::CPSR);
1506 updateValueMap(I, DestReg);
1510 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1511 // Make sure we have VFP and that we're extending float to double.
1512 if (!Subtarget->hasVFP2()) return false;
1514 Value *V = I->getOperand(0);
1515 if (!I->getType()->isDoubleTy() ||
1516 !V->getType()->isFloatTy()) return false;
1518 unsigned Op = getRegForValue(V);
1519 if (Op == 0) return false;
1521 unsigned Result = createResultReg(&ARM::DPRRegClass);
1522 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1523 TII.get(ARM::VCVTDS), Result)
1525 updateValueMap(I, Result);
1529 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1530 // Make sure we have VFP and that we're truncating double to float.
1531 if (!Subtarget->hasVFP2()) return false;
1533 Value *V = I->getOperand(0);
1534 if (!(I->getType()->isFloatTy() &&
1535 V->getType()->isDoubleTy())) return false;
1537 unsigned Op = getRegForValue(V);
1538 if (Op == 0) return false;
1540 unsigned Result = createResultReg(&ARM::SPRRegClass);
1541 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1542 TII.get(ARM::VCVTSD), Result)
1544 updateValueMap(I, Result);
1548 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1549 // Make sure we have VFP.
1550 if (!Subtarget->hasVFP2()) return false;
1553 Type *Ty = I->getType();
1554 if (!isTypeLegal(Ty, DstVT))
1557 Value *Src = I->getOperand(0);
1558 EVT SrcEVT = TLI.getValueType(Src->getType(), true);
1559 if (!SrcEVT.isSimple())
1561 MVT SrcVT = SrcEVT.getSimpleVT();
1562 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1565 unsigned SrcReg = getRegForValue(Src);
1566 if (SrcReg == 0) return false;
1568 // Handle sign-extension.
1569 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1570 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1571 /*isZExt*/!isSigned);
1572 if (SrcReg == 0) return false;
1575 // The conversion routine works on fp-reg to fp-reg and the operand above
1576 // was an integer, move it to the fp registers if possible.
1577 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1578 if (FP == 0) return false;
1581 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1582 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1585 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1586 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1587 TII.get(Opc), ResultReg).addReg(FP));
1588 updateValueMap(I, ResultReg);
1592 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1593 // Make sure we have VFP.
1594 if (!Subtarget->hasVFP2()) return false;
1597 Type *RetTy = I->getType();
1598 if (!isTypeLegal(RetTy, DstVT))
1601 unsigned Op = getRegForValue(I->getOperand(0));
1602 if (Op == 0) return false;
1605 Type *OpTy = I->getOperand(0)->getType();
1606 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1607 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1610 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1611 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1612 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1613 TII.get(Opc), ResultReg).addReg(Op));
1615 // This result needs to be in an integer register, but the conversion only
1616 // takes place in fp-regs.
1617 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1618 if (IntReg == 0) return false;
1620 updateValueMap(I, IntReg);
1624 bool ARMFastISel::SelectSelect(const Instruction *I) {
1626 if (!isTypeLegal(I->getType(), VT))
1629 // Things need to be register sized for register moves.
1630 if (VT != MVT::i32) return false;
1632 unsigned CondReg = getRegForValue(I->getOperand(0));
1633 if (CondReg == 0) return false;
1634 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1635 if (Op1Reg == 0) return false;
1637 // Check to see if we can use an immediate in the conditional move.
1639 bool UseImm = false;
1640 bool isNegativeImm = false;
1641 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1642 assert (VT == MVT::i32 && "Expecting an i32.");
1643 Imm = (int)ConstInt->getValue().getZExtValue();
1645 isNegativeImm = true;
1648 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1649 (ARM_AM::getSOImmVal(Imm) != -1);
1652 unsigned Op2Reg = 0;
1654 Op2Reg = getRegForValue(I->getOperand(2));
1655 if (Op2Reg == 0) return false;
1658 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1659 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
1661 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1666 const TargetRegisterClass *RC;
1668 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1669 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1671 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1673 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1675 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1677 unsigned ResultReg = createResultReg(RC);
1679 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1680 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1681 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1688 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1689 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1696 updateValueMap(I, ResultReg);
1700 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1702 Type *Ty = I->getType();
1703 if (!isTypeLegal(Ty, VT))
1706 // If we have integer div support we should have selected this automagically.
1707 // In case we have a real miss go ahead and return false and we'll pick
1709 if (Subtarget->hasDivide()) return false;
1711 // Otherwise emit a libcall.
1712 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1714 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1715 else if (VT == MVT::i16)
1716 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1717 else if (VT == MVT::i32)
1718 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1719 else if (VT == MVT::i64)
1720 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1721 else if (VT == MVT::i128)
1722 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1723 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1725 return ARMEmitLibcall(I, LC);
1728 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1730 Type *Ty = I->getType();
1731 if (!isTypeLegal(Ty, VT))
1734 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1736 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1737 else if (VT == MVT::i16)
1738 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1739 else if (VT == MVT::i32)
1740 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1741 else if (VT == MVT::i64)
1742 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1743 else if (VT == MVT::i128)
1744 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1745 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1747 return ARMEmitLibcall(I, LC);
1750 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1751 EVT DestVT = TLI.getValueType(I->getType(), true);
1753 // We can get here in the case when we have a binary operation on a non-legal
1754 // type and the target independent selector doesn't know how to handle it.
1755 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1759 switch (ISDOpcode) {
1760 default: return false;
1762 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1765 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1768 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1772 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1773 if (SrcReg1 == 0) return false;
1775 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1776 // in the instruction, rather then materializing the value in a register.
1777 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1778 if (SrcReg2 == 0) return false;
1780 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1781 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1782 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1783 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1784 TII.get(Opc), ResultReg)
1785 .addReg(SrcReg1).addReg(SrcReg2));
1786 updateValueMap(I, ResultReg);
1790 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1791 EVT FPVT = TLI.getValueType(I->getType(), true);
1792 if (!FPVT.isSimple()) return false;
1793 MVT VT = FPVT.getSimpleVT();
1795 // FIXME: Support vector types where possible.
1799 // We can get here in the case when we want to use NEON for our fp
1800 // operations, but can't figure out how to. Just use the vfp instructions
1802 // FIXME: It'd be nice to use NEON instructions.
1803 Type *Ty = I->getType();
1804 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1805 if (isFloat && !Subtarget->hasVFP2())
1809 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1810 switch (ISDOpcode) {
1811 default: return false;
1813 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1816 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1819 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1822 unsigned Op1 = getRegForValue(I->getOperand(0));
1823 if (Op1 == 0) return false;
1825 unsigned Op2 = getRegForValue(I->getOperand(1));
1826 if (Op2 == 0) return false;
1828 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1829 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1830 TII.get(Opc), ResultReg)
1831 .addReg(Op1).addReg(Op2));
1832 updateValueMap(I, ResultReg);
1836 // Call Handling Code
1838 // This is largely taken directly from CCAssignFnForNode
1839 // TODO: We may not support all of this.
1840 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1845 llvm_unreachable("Unsupported calling convention");
1846 case CallingConv::Fast:
1847 if (Subtarget->hasVFP2() && !isVarArg) {
1848 if (!Subtarget->isAAPCS_ABI())
1849 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1850 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1851 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1854 case CallingConv::C:
1855 // Use target triple & subtarget features to do actual dispatch.
1856 if (Subtarget->isAAPCS_ABI()) {
1857 if (Subtarget->hasVFP2() &&
1858 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1859 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1861 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1863 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1864 case CallingConv::ARM_AAPCS_VFP:
1866 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1867 // Fall through to soft float variant, variadic functions don't
1868 // use hard floating point ABI.
1869 case CallingConv::ARM_AAPCS:
1870 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1871 case CallingConv::ARM_APCS:
1872 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1873 case CallingConv::GHC:
1875 llvm_unreachable("Can't return in GHC call convention");
1877 return CC_ARM_APCS_GHC;
1881 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1882 SmallVectorImpl<unsigned> &ArgRegs,
1883 SmallVectorImpl<MVT> &ArgVTs,
1884 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1885 SmallVectorImpl<unsigned> &RegArgs,
1889 SmallVector<CCValAssign, 16> ArgLocs;
1890 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1891 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1892 CCAssignFnForCall(CC, false, isVarArg));
1894 // Check that we can handle all of the arguments. If we can't, then bail out
1895 // now before we add code to the MBB.
1896 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1897 CCValAssign &VA = ArgLocs[i];
1898 MVT ArgVT = ArgVTs[VA.getValNo()];
1900 // We don't handle NEON/vector parameters yet.
1901 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1904 // Now copy/store arg to correct locations.
1905 if (VA.isRegLoc() && !VA.needsCustom()) {
1907 } else if (VA.needsCustom()) {
1908 // TODO: We need custom lowering for vector (v2f64) args.
1909 if (VA.getLocVT() != MVT::f64 ||
1910 // TODO: Only handle register args for now.
1911 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1914 switch (ArgVT.SimpleTy) {
1923 if (!Subtarget->hasVFP2())
1927 if (!Subtarget->hasVFP2())
1934 // At the point, we are able to handle the call's arguments in fast isel.
1936 // Get a count of how many bytes are to be pushed on the stack.
1937 NumBytes = CCInfo.getNextStackOffset();
1939 // Issue CALLSEQ_START
1940 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1941 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1942 TII.get(AdjStackDown))
1945 // Process the args.
1946 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1947 CCValAssign &VA = ArgLocs[i];
1948 const Value *ArgVal = Args[VA.getValNo()];
1949 unsigned Arg = ArgRegs[VA.getValNo()];
1950 MVT ArgVT = ArgVTs[VA.getValNo()];
1952 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1953 "We don't handle NEON/vector parameters yet.");
1955 // Handle arg promotion, etc.
1956 switch (VA.getLocInfo()) {
1957 case CCValAssign::Full: break;
1958 case CCValAssign::SExt: {
1959 MVT DestVT = VA.getLocVT();
1960 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1961 assert (Arg != 0 && "Failed to emit a sext");
1965 case CCValAssign::AExt:
1966 // Intentional fall-through. Handle AExt and ZExt.
1967 case CCValAssign::ZExt: {
1968 MVT DestVT = VA.getLocVT();
1969 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1970 assert (Arg != 0 && "Failed to emit a zext");
1974 case CCValAssign::BCvt: {
1975 unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1976 /*TODO: Kill=*/false);
1977 assert(BC != 0 && "Failed to emit a bitcast!");
1979 ArgVT = VA.getLocVT();
1982 default: llvm_unreachable("Unknown arg promotion!");
1985 // Now copy/store arg to correct locations.
1986 if (VA.isRegLoc() && !VA.needsCustom()) {
1987 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1988 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
1989 RegArgs.push_back(VA.getLocReg());
1990 } else if (VA.needsCustom()) {
1991 // TODO: We need custom lowering for vector (v2f64) args.
1992 assert(VA.getLocVT() == MVT::f64 &&
1993 "Custom lowering for v2f64 args not available");
1995 CCValAssign &NextVA = ArgLocs[++i];
1997 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
1998 "We only handle register args!");
2000 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2001 TII.get(ARM::VMOVRRD), VA.getLocReg())
2002 .addReg(NextVA.getLocReg(), RegState::Define)
2004 RegArgs.push_back(VA.getLocReg());
2005 RegArgs.push_back(NextVA.getLocReg());
2007 assert(VA.isMemLoc());
2008 // Need to store on the stack.
2010 // Don't emit stores for undef values.
2011 if (isa<UndefValue>(ArgVal))
2015 Addr.BaseType = Address::RegBase;
2016 Addr.Base.Reg = ARM::SP;
2017 Addr.Offset = VA.getLocMemOffset();
2019 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2020 assert(EmitRet && "Could not emit a store for argument!");
2027 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2028 const Instruction *I, CallingConv::ID CC,
2029 unsigned &NumBytes, bool isVarArg) {
2030 // Issue CALLSEQ_END
2031 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2032 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2033 TII.get(AdjStackUp))
2034 .addImm(NumBytes).addImm(0));
2036 // Now the return value.
2037 if (RetVT != MVT::isVoid) {
2038 SmallVector<CCValAssign, 16> RVLocs;
2039 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2040 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2042 // Copy all of the result registers out of their specified physreg.
2043 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2044 // For this move we copy into two registers and then move into the
2045 // double fp reg we want.
2046 MVT DestVT = RVLocs[0].getValVT();
2047 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2048 unsigned ResultReg = createResultReg(DstRC);
2049 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2050 TII.get(ARM::VMOVDRR), ResultReg)
2051 .addReg(RVLocs[0].getLocReg())
2052 .addReg(RVLocs[1].getLocReg()));
2054 UsedRegs.push_back(RVLocs[0].getLocReg());
2055 UsedRegs.push_back(RVLocs[1].getLocReg());
2057 // Finally update the result.
2058 updateValueMap(I, ResultReg);
2060 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2061 MVT CopyVT = RVLocs[0].getValVT();
2063 // Special handling for extended integers.
2064 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2067 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2069 unsigned ResultReg = createResultReg(DstRC);
2070 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2071 TII.get(TargetOpcode::COPY),
2072 ResultReg).addReg(RVLocs[0].getLocReg());
2073 UsedRegs.push_back(RVLocs[0].getLocReg());
2075 // Finally update the result.
2076 updateValueMap(I, ResultReg);
2083 bool ARMFastISel::SelectRet(const Instruction *I) {
2084 const ReturnInst *Ret = cast<ReturnInst>(I);
2085 const Function &F = *I->getParent()->getParent();
2087 if (!FuncInfo.CanLowerReturn)
2090 // Build a list of return value registers.
2091 SmallVector<unsigned, 4> RetRegs;
2093 CallingConv::ID CC = F.getCallingConv();
2094 if (Ret->getNumOperands() > 0) {
2095 SmallVector<ISD::OutputArg, 4> Outs;
2096 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
2098 // Analyze operands of the call, assigning locations to each operand.
2099 SmallVector<CCValAssign, 16> ValLocs;
2100 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2101 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2104 const Value *RV = Ret->getOperand(0);
2105 unsigned Reg = getRegForValue(RV);
2109 // Only handle a single return value for now.
2110 if (ValLocs.size() != 1)
2113 CCValAssign &VA = ValLocs[0];
2115 // Don't bother handling odd stuff for now.
2116 if (VA.getLocInfo() != CCValAssign::Full)
2118 // Only handle register returns for now.
2122 unsigned SrcReg = Reg + VA.getValNo();
2123 EVT RVEVT = TLI.getValueType(RV->getType());
2124 if (!RVEVT.isSimple()) return false;
2125 MVT RVVT = RVEVT.getSimpleVT();
2126 MVT DestVT = VA.getValVT();
2127 // Special handling for extended integers.
2128 if (RVVT != DestVT) {
2129 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2132 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2134 // Perform extension if flagged as either zext or sext. Otherwise, do
2136 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2137 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2138 if (SrcReg == 0) return false;
2143 unsigned DstReg = VA.getLocReg();
2144 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2145 // Avoid a cross-class copy. This is very unlikely.
2146 if (!SrcRC->contains(DstReg))
2148 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2149 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2151 // Add register to return instruction.
2152 RetRegs.push_back(VA.getLocReg());
2155 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2156 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2158 AddOptionalDefs(MIB);
2159 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2160 MIB.addReg(RetRegs[i], RegState::Implicit);
2164 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2166 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2168 return isThumb2 ? ARM::tBL : ARM::BL;
2171 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2172 // Manually compute the global's type to avoid building it when unnecessary.
2173 Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2174 EVT LCREVT = TLI.getValueType(GVTy);
2175 if (!LCREVT.isSimple()) return 0;
2177 GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
2178 GlobalValue::ExternalLinkage, nullptr,
2180 assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2181 return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2184 // A quick function that will emit a call for a named libcall in F with the
2185 // vector of passed arguments for the Instruction in I. We can assume that we
2186 // can emit a call for any libcall we can produce. This is an abridged version
2187 // of the full call infrastructure since we won't need to worry about things
2188 // like computed function pointers or strange arguments at call sites.
2189 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2191 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2192 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2194 // Handle *simple* calls for now.
2195 Type *RetTy = I->getType();
2197 if (RetTy->isVoidTy())
2198 RetVT = MVT::isVoid;
2199 else if (!isTypeLegal(RetTy, RetVT))
2202 // Can't handle non-double multi-reg retvals.
2203 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2204 SmallVector<CCValAssign, 16> RVLocs;
2205 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2206 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2207 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2211 // Set up the argument vectors.
2212 SmallVector<Value*, 8> Args;
2213 SmallVector<unsigned, 8> ArgRegs;
2214 SmallVector<MVT, 8> ArgVTs;
2215 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2216 Args.reserve(I->getNumOperands());
2217 ArgRegs.reserve(I->getNumOperands());
2218 ArgVTs.reserve(I->getNumOperands());
2219 ArgFlags.reserve(I->getNumOperands());
2220 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2221 Value *Op = I->getOperand(i);
2222 unsigned Arg = getRegForValue(Op);
2223 if (Arg == 0) return false;
2225 Type *ArgTy = Op->getType();
2227 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2229 ISD::ArgFlagsTy Flags;
2230 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2231 Flags.setOrigAlign(OriginalAlignment);
2234 ArgRegs.push_back(Arg);
2235 ArgVTs.push_back(ArgVT);
2236 ArgFlags.push_back(Flags);
2239 // Handle the arguments now that we've gotten them.
2240 SmallVector<unsigned, 4> RegArgs;
2242 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2243 RegArgs, CC, NumBytes, false))
2246 unsigned CalleeReg = 0;
2247 if (Subtarget->genLongCalls()) {
2248 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2249 if (CalleeReg == 0) return false;
2253 unsigned CallOpc = ARMSelectCallOp(Subtarget->genLongCalls());
2254 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2255 DbgLoc, TII.get(CallOpc));
2256 // BL / BLX don't take a predicate, but tBL / tBLX do.
2258 AddDefaultPred(MIB);
2259 if (Subtarget->genLongCalls())
2260 MIB.addReg(CalleeReg);
2262 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2264 // Add implicit physical register uses to the call.
2265 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2266 MIB.addReg(RegArgs[i], RegState::Implicit);
2268 // Add a register mask with the call-preserved registers.
2269 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2270 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2272 // Finish off the call including any return values.
2273 SmallVector<unsigned, 4> UsedRegs;
2274 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2276 // Set all unused physreg defs as dead.
2277 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2282 bool ARMFastISel::SelectCall(const Instruction *I,
2283 const char *IntrMemName = nullptr) {
2284 const CallInst *CI = cast<CallInst>(I);
2285 const Value *Callee = CI->getCalledValue();
2287 // Can't handle inline asm.
2288 if (isa<InlineAsm>(Callee)) return false;
2290 // Allow SelectionDAG isel to handle tail calls.
2291 if (CI->isTailCall()) return false;
2293 // Check the calling convention.
2294 ImmutableCallSite CS(CI);
2295 CallingConv::ID CC = CS.getCallingConv();
2297 // TODO: Avoid some calling conventions?
2299 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2300 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2301 bool isVarArg = FTy->isVarArg();
2303 // Handle *simple* calls for now.
2304 Type *RetTy = I->getType();
2306 if (RetTy->isVoidTy())
2307 RetVT = MVT::isVoid;
2308 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2309 RetVT != MVT::i8 && RetVT != MVT::i1)
2312 // Can't handle non-double multi-reg retvals.
2313 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2314 RetVT != MVT::i16 && RetVT != MVT::i32) {
2315 SmallVector<CCValAssign, 16> RVLocs;
2316 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2317 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2318 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2322 // Set up the argument vectors.
2323 SmallVector<Value*, 8> Args;
2324 SmallVector<unsigned, 8> ArgRegs;
2325 SmallVector<MVT, 8> ArgVTs;
2326 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2327 unsigned arg_size = CS.arg_size();
2328 Args.reserve(arg_size);
2329 ArgRegs.reserve(arg_size);
2330 ArgVTs.reserve(arg_size);
2331 ArgFlags.reserve(arg_size);
2332 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2334 // If we're lowering a memory intrinsic instead of a regular call, skip the
2335 // last two arguments, which shouldn't be passed to the underlying function.
2336 if (IntrMemName && e-i <= 2)
2339 ISD::ArgFlagsTy Flags;
2340 unsigned AttrInd = i - CS.arg_begin() + 1;
2341 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2343 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2346 // FIXME: Only handle *easy* calls for now.
2347 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2348 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2349 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2350 CS.paramHasAttr(AttrInd, Attribute::ByVal))
2353 Type *ArgTy = (*i)->getType();
2355 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2359 unsigned Arg = getRegForValue(*i);
2363 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2364 Flags.setOrigAlign(OriginalAlignment);
2367 ArgRegs.push_back(Arg);
2368 ArgVTs.push_back(ArgVT);
2369 ArgFlags.push_back(Flags);
2372 // Handle the arguments now that we've gotten them.
2373 SmallVector<unsigned, 4> RegArgs;
2375 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2376 RegArgs, CC, NumBytes, isVarArg))
2379 bool UseReg = false;
2380 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2381 if (!GV || Subtarget->genLongCalls()) UseReg = true;
2383 unsigned CalleeReg = 0;
2386 CalleeReg = getLibcallReg(IntrMemName);
2388 CalleeReg = getRegForValue(Callee);
2390 if (CalleeReg == 0) return false;
2394 unsigned CallOpc = ARMSelectCallOp(UseReg);
2395 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2396 DbgLoc, TII.get(CallOpc));
2398 unsigned char OpFlags = 0;
2400 // Add MO_PLT for global address or external symbol in the PIC relocation
2402 if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_)
2403 OpFlags = ARMII::MO_PLT;
2405 // ARM calls don't take a predicate, but tBL / tBLX do.
2407 AddDefaultPred(MIB);
2409 MIB.addReg(CalleeReg);
2410 else if (!IntrMemName)
2411 MIB.addGlobalAddress(GV, 0, OpFlags);
2413 MIB.addExternalSymbol(IntrMemName, OpFlags);
2415 // Add implicit physical register uses to the call.
2416 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2417 MIB.addReg(RegArgs[i], RegState::Implicit);
2419 // Add a register mask with the call-preserved registers.
2420 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2421 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2423 // Finish off the call including any return values.
2424 SmallVector<unsigned, 4> UsedRegs;
2425 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2428 // Set all unused physreg defs as dead.
2429 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2434 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2438 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2439 uint64_t Len, unsigned Alignment) {
2440 // Make sure we don't bloat code by inlining very large memcpy's.
2441 if (!ARMIsMemCpySmall(Len))
2446 if (!Alignment || Alignment >= 4) {
2452 assert (Len == 1 && "Expected a length of 1!");
2456 // Bound based on alignment.
2457 if (Len >= 2 && Alignment == 2)
2466 RV = ARMEmitLoad(VT, ResultReg, Src);
2467 assert (RV == true && "Should be able to handle this load.");
2468 RV = ARMEmitStore(VT, ResultReg, Dest);
2469 assert (RV == true && "Should be able to handle this store.");
2472 unsigned Size = VT.getSizeInBits()/8;
2474 Dest.Offset += Size;
2481 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2482 // FIXME: Handle more intrinsics.
2483 switch (I.getIntrinsicID()) {
2484 default: return false;
2485 case Intrinsic::frameaddress: {
2486 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2487 MFI->setFrameAddressIsTaken(true);
2489 unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
2490 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
2491 : &ARM::GPRRegClass;
2493 const ARMBaseRegisterInfo *RegInfo =
2494 static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo());
2495 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2496 unsigned SrcReg = FramePtr;
2498 // Recursively load frame address
2504 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2506 DestReg = createResultReg(RC);
2507 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2508 TII.get(LdrOpc), DestReg)
2509 .addReg(SrcReg).addImm(0));
2512 updateValueMap(&I, SrcReg);
2515 case Intrinsic::memcpy:
2516 case Intrinsic::memmove: {
2517 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2518 // Don't handle volatile.
2519 if (MTI.isVolatile())
2522 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2523 // we would emit dead code because we don't currently handle memmoves.
2524 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2525 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2526 // Small memcpy's are common enough that we want to do them without a call
2528 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2529 if (ARMIsMemCpySmall(Len)) {
2531 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2532 !ARMComputeAddress(MTI.getRawSource(), Src))
2534 unsigned Alignment = MTI.getAlignment();
2535 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2540 if (!MTI.getLength()->getType()->isIntegerTy(32))
2543 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2546 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2547 return SelectCall(&I, IntrMemName);
2549 case Intrinsic::memset: {
2550 const MemSetInst &MSI = cast<MemSetInst>(I);
2551 // Don't handle volatile.
2552 if (MSI.isVolatile())
2555 if (!MSI.getLength()->getType()->isIntegerTy(32))
2558 if (MSI.getDestAddressSpace() > 255)
2561 return SelectCall(&I, "memset");
2563 case Intrinsic::trap: {
2564 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
2565 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2571 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2572 // The high bits for a type smaller than the register size are assumed to be
2574 Value *Op = I->getOperand(0);
2577 SrcVT = TLI.getValueType(Op->getType(), true);
2578 DestVT = TLI.getValueType(I->getType(), true);
2580 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2582 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2585 unsigned SrcReg = getRegForValue(Op);
2586 if (!SrcReg) return false;
2588 // Because the high bits are undefined, a truncate doesn't generate
2590 updateValueMap(I, SrcReg);
2594 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2596 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2598 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2601 // Table of which combinations can be emitted as a single instruction,
2602 // and which will require two.
2603 static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2605 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2606 // ext: s z s z s z s z
2607 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2608 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2609 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2612 // Target registers for:
2613 // - For ARM can never be PC.
2614 // - For 16-bit Thumb are restricted to lower 8 registers.
2615 // - For 32-bit Thumb are restricted to non-SP and non-PC.
2616 static const TargetRegisterClass *RCTbl[2][2] = {
2617 // Instructions: Two Single
2618 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2619 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2622 // Table governing the instruction(s) to be emitted.
2623 static const struct InstructionTable {
2625 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2626 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2627 uint32_t Imm : 8; // All instructions have either a shift or a mask.
2628 } IT[2][2][3][2] = {
2629 { // Two instructions (first is left shift, second is in this table).
2630 { // ARM Opc S Shift Imm
2631 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2632 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2633 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2634 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2635 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2636 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2638 { // Thumb Opc S Shift Imm
2639 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2640 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2641 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2642 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2643 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2644 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2647 { // Single instruction.
2648 { // ARM Opc S Shift Imm
2649 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2650 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2651 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2652 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2653 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2654 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2656 { // Thumb Opc S Shift Imm
2657 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2658 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2659 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2660 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2661 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2662 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2667 unsigned SrcBits = SrcVT.getSizeInBits();
2668 unsigned DestBits = DestVT.getSizeInBits();
2670 assert((SrcBits < DestBits) && "can only extend to larger types");
2671 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2672 "other sizes unimplemented");
2673 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2674 "other sizes unimplemented");
2676 bool hasV6Ops = Subtarget->hasV6Ops();
2677 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2678 assert((Bitness < 3) && "sanity-check table bounds");
2680 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2681 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2682 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2683 unsigned Opc = ITP->Opc;
2684 assert(ARM::KILL != Opc && "Invalid table entry");
2685 unsigned hasS = ITP->hasS;
2686 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2687 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2688 "only MOVsi has shift operand addressing mode");
2689 unsigned Imm = ITP->Imm;
2691 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2692 bool setsCPSR = &ARM::tGPRRegClass == RC;
2693 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2695 // MOVsi encodes shift and immediate in shift operand addressing mode.
2696 // The following condition has the same value when emitting two
2697 // instruction sequences: both are shifts.
2698 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2700 // Either one or two instructions are emitted.
2701 // They're always of the form:
2703 // CPSR is set only by 16-bit Thumb instructions.
2704 // Predicate, if any, is AL.
2705 // S bit, if available, is always 0.
2706 // When two are emitted the first's result will feed as the second's input,
2707 // that value is then dead.
2708 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2709 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2710 ResultReg = createResultReg(RC);
2711 bool isLsl = (0 == Instr) && !isSingleInstr;
2712 unsigned Opcode = isLsl ? LSLOpc : Opc;
2713 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2714 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2715 bool isKill = 1 == Instr;
2716 MachineInstrBuilder MIB = BuildMI(
2717 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2719 MIB.addReg(ARM::CPSR, RegState::Define);
2720 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2721 AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
2724 // Second instruction consumes the first's result.
2731 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2732 // On ARM, in general, integer casts don't involve legal types; this code
2733 // handles promotable integers.
2734 Type *DestTy = I->getType();
2735 Value *Src = I->getOperand(0);
2736 Type *SrcTy = Src->getType();
2738 bool isZExt = isa<ZExtInst>(I);
2739 unsigned SrcReg = getRegForValue(Src);
2740 if (!SrcReg) return false;
2742 EVT SrcEVT, DestEVT;
2743 SrcEVT = TLI.getValueType(SrcTy, true);
2744 DestEVT = TLI.getValueType(DestTy, true);
2745 if (!SrcEVT.isSimple()) return false;
2746 if (!DestEVT.isSimple()) return false;
2748 MVT SrcVT = SrcEVT.getSimpleVT();
2749 MVT DestVT = DestEVT.getSimpleVT();
2750 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2751 if (ResultReg == 0) return false;
2752 updateValueMap(I, ResultReg);
2756 bool ARMFastISel::SelectShift(const Instruction *I,
2757 ARM_AM::ShiftOpc ShiftTy) {
2758 // We handle thumb2 mode by target independent selector
2759 // or SelectionDAG ISel.
2763 // Only handle i32 now.
2764 EVT DestVT = TLI.getValueType(I->getType(), true);
2765 if (DestVT != MVT::i32)
2768 unsigned Opc = ARM::MOVsr;
2770 Value *Src2Value = I->getOperand(1);
2771 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2772 ShiftImm = CI->getZExtValue();
2774 // Fall back to selection DAG isel if the shift amount
2775 // is zero or greater than the width of the value type.
2776 if (ShiftImm == 0 || ShiftImm >=32)
2782 Value *Src1Value = I->getOperand(0);
2783 unsigned Reg1 = getRegForValue(Src1Value);
2784 if (Reg1 == 0) return false;
2787 if (Opc == ARM::MOVsr) {
2788 Reg2 = getRegForValue(Src2Value);
2789 if (Reg2 == 0) return false;
2792 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2793 if(ResultReg == 0) return false;
2795 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2796 TII.get(Opc), ResultReg)
2799 if (Opc == ARM::MOVsi)
2800 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2801 else if (Opc == ARM::MOVsr) {
2803 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2806 AddOptionalDefs(MIB);
2807 updateValueMap(I, ResultReg);
2811 // TODO: SoftFP support.
2812 bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
2814 switch (I->getOpcode()) {
2815 case Instruction::Load:
2816 return SelectLoad(I);
2817 case Instruction::Store:
2818 return SelectStore(I);
2819 case Instruction::Br:
2820 return SelectBranch(I);
2821 case Instruction::IndirectBr:
2822 return SelectIndirectBr(I);
2823 case Instruction::ICmp:
2824 case Instruction::FCmp:
2825 return SelectCmp(I);
2826 case Instruction::FPExt:
2827 return SelectFPExt(I);
2828 case Instruction::FPTrunc:
2829 return SelectFPTrunc(I);
2830 case Instruction::SIToFP:
2831 return SelectIToFP(I, /*isSigned*/ true);
2832 case Instruction::UIToFP:
2833 return SelectIToFP(I, /*isSigned*/ false);
2834 case Instruction::FPToSI:
2835 return SelectFPToI(I, /*isSigned*/ true);
2836 case Instruction::FPToUI:
2837 return SelectFPToI(I, /*isSigned*/ false);
2838 case Instruction::Add:
2839 return SelectBinaryIntOp(I, ISD::ADD);
2840 case Instruction::Or:
2841 return SelectBinaryIntOp(I, ISD::OR);
2842 case Instruction::Sub:
2843 return SelectBinaryIntOp(I, ISD::SUB);
2844 case Instruction::FAdd:
2845 return SelectBinaryFPOp(I, ISD::FADD);
2846 case Instruction::FSub:
2847 return SelectBinaryFPOp(I, ISD::FSUB);
2848 case Instruction::FMul:
2849 return SelectBinaryFPOp(I, ISD::FMUL);
2850 case Instruction::SDiv:
2851 return SelectDiv(I, /*isSigned*/ true);
2852 case Instruction::UDiv:
2853 return SelectDiv(I, /*isSigned*/ false);
2854 case Instruction::SRem:
2855 return SelectRem(I, /*isSigned*/ true);
2856 case Instruction::URem:
2857 return SelectRem(I, /*isSigned*/ false);
2858 case Instruction::Call:
2859 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2860 return SelectIntrinsicCall(*II);
2861 return SelectCall(I);
2862 case Instruction::Select:
2863 return SelectSelect(I);
2864 case Instruction::Ret:
2865 return SelectRet(I);
2866 case Instruction::Trunc:
2867 return SelectTrunc(I);
2868 case Instruction::ZExt:
2869 case Instruction::SExt:
2870 return SelectIntExt(I);
2871 case Instruction::Shl:
2872 return SelectShift(I, ARM_AM::lsl);
2873 case Instruction::LShr:
2874 return SelectShift(I, ARM_AM::lsr);
2875 case Instruction::AShr:
2876 return SelectShift(I, ARM_AM::asr);
2883 // This table describes sign- and zero-extend instructions which can be
2884 // folded into a preceding load. All of these extends have an immediate
2885 // (sometimes a mask and sometimes a shift) that's applied after
2887 const struct FoldableLoadExtendsStruct {
2888 uint16_t Opc[2]; // ARM, Thumb.
2889 uint8_t ExpectedImm;
2891 uint8_t ExpectedVT : 7;
2892 } FoldableLoadExtends[] = {
2893 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2894 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2895 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2896 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2897 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2901 /// \brief The specified machine instr operand is a vreg, and that
2902 /// vreg is being provided by the specified load instruction. If possible,
2903 /// try to fold the load as an operand to the instruction, returning true if
2905 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2906 const LoadInst *LI) {
2907 // Verify we have a legal type before going any further.
2909 if (!isLoadTypeLegal(LI->getType(), VT))
2912 // Combine load followed by zero- or sign-extend.
2913 // ldrb r1, [r0] ldrb r1, [r0]
2915 // mov r3, r2 mov r3, r1
2916 if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2918 const uint64_t Imm = MI->getOperand(2).getImm();
2922 for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends);
2924 if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&
2925 (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm &&
2926 MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) {
2928 isZExt = FoldableLoadExtends[i].isZExt;
2931 if (!Found) return false;
2933 // See if we can handle this address.
2935 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2937 unsigned ResultReg = MI->getOperand(0).getReg();
2938 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2940 MI->eraseFromParent();
2944 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2945 unsigned Align, MVT VT) {
2946 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2947 ARMConstantPoolConstant *CPV =
2948 ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2949 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
2952 unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
2955 DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0);
2956 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2957 TII.get(ARM::t2LDRpci), DestReg1)
2958 .addConstantPoolIndex(Idx));
2959 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
2961 // The extra immediate is for addrmode2.
2962 DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0);
2963 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2964 DbgLoc, TII.get(ARM::LDRcp), DestReg1)
2965 .addConstantPoolIndex(Idx).addImm(0));
2966 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
2969 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
2970 if (GlobalBaseReg == 0) {
2971 GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
2972 AFI->setGlobalBaseReg(GlobalBaseReg);
2975 unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
2976 DestReg2 = constrainOperandRegClass(TII.get(Opc), DestReg2, 0);
2977 DestReg1 = constrainOperandRegClass(TII.get(Opc), DestReg1, 1);
2978 GlobalBaseReg = constrainOperandRegClass(TII.get(Opc), GlobalBaseReg, 2);
2979 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2980 DbgLoc, TII.get(Opc), DestReg2)
2982 .addReg(GlobalBaseReg);
2985 AddOptionalDefs(MIB);
2990 bool ARMFastISel::fastLowerArguments() {
2991 if (!FuncInfo.CanLowerReturn)
2994 const Function *F = FuncInfo.Fn;
2998 CallingConv::ID CC = F->getCallingConv();
3002 case CallingConv::Fast:
3003 case CallingConv::C:
3004 case CallingConv::ARM_AAPCS_VFP:
3005 case CallingConv::ARM_AAPCS:
3006 case CallingConv::ARM_APCS:
3010 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3011 // which are passed in r0 - r3.
3013 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3014 I != E; ++I, ++Idx) {
3018 if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
3019 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
3020 F->getAttributes().hasAttribute(Idx, Attribute::ByVal))
3023 Type *ArgTy = I->getType();
3024 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3027 EVT ArgVT = TLI.getValueType(ArgTy);
3028 if (!ArgVT.isSimple()) return false;
3029 switch (ArgVT.getSimpleVT().SimpleTy) {
3040 static const uint16_t GPRArgRegs[] = {
3041 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3044 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3046 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3047 I != E; ++I, ++Idx) {
3048 unsigned SrcReg = GPRArgRegs[Idx];
3049 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3050 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3051 // Without this, EmitLiveInCopies may eliminate the livein if its only
3052 // use is a bitcast (which isn't turned into an instruction).
3053 unsigned ResultReg = createResultReg(RC);
3054 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3055 TII.get(TargetOpcode::COPY),
3056 ResultReg).addReg(DstReg, getKillRegState(true));
3057 updateValueMap(I, ResultReg);
3064 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3065 const TargetLibraryInfo *libInfo) {
3066 if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
3067 return new ARMFastISel(funcInfo, libInfo);