1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/DataLayout.h"
34 #include "llvm/DerivedTypes.h"
35 #include "llvm/GlobalVariable.h"
36 #include "llvm/Instructions.h"
37 #include "llvm/IntrinsicInst.h"
38 #include "llvm/Module.h"
39 #include "llvm/Operator.h"
40 #include "llvm/Support/CallSite.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/GetElementPtrTypeIterator.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
50 extern cl::opt<bool> EnableARMLongCalls;
54 // All possible address modes, plus some.
55 typedef struct Address {
68 // Innocuous defaults for our address.
70 : BaseType(RegBase), Offset(0) {
75 class ARMFastISel : public FastISel {
77 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
78 /// make the right decision when generating code for different targets.
79 const ARMSubtarget *Subtarget;
80 const TargetMachine &TM;
81 const TargetInstrInfo &TII;
82 const TargetLowering &TLI;
85 // Convenience variables to avoid some queries.
90 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
91 const TargetLibraryInfo *libInfo)
92 : FastISel(funcInfo, libInfo),
93 TM(funcInfo.MF->getTarget()),
94 TII(*TM.getInstrInfo()),
95 TLI(*TM.getTargetLowering()) {
96 Subtarget = &TM.getSubtarget<ARMSubtarget>();
97 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
98 isThumb2 = AFI->isThumbFunction();
99 Context = &funcInfo.Fn->getContext();
102 // Code from FastISel.cpp.
104 unsigned FastEmitInst_(unsigned MachineInstOpcode,
105 const TargetRegisterClass *RC);
106 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
107 const TargetRegisterClass *RC,
108 unsigned Op0, bool Op0IsKill);
109 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
110 const TargetRegisterClass *RC,
111 unsigned Op0, bool Op0IsKill,
112 unsigned Op1, bool Op1IsKill);
113 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
114 const TargetRegisterClass *RC,
115 unsigned Op0, bool Op0IsKill,
116 unsigned Op1, bool Op1IsKill,
117 unsigned Op2, bool Op2IsKill);
118 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill,
122 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
123 const TargetRegisterClass *RC,
124 unsigned Op0, bool Op0IsKill,
125 const ConstantFP *FPImm);
126 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
127 const TargetRegisterClass *RC,
128 unsigned Op0, bool Op0IsKill,
129 unsigned Op1, bool Op1IsKill,
131 unsigned FastEmitInst_i(unsigned MachineInstOpcode,
132 const TargetRegisterClass *RC,
134 unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
135 const TargetRegisterClass *RC,
136 uint64_t Imm1, uint64_t Imm2);
138 unsigned FastEmitInst_extractsubreg(MVT RetVT,
139 unsigned Op0, bool Op0IsKill,
142 // Backend specific FastISel code.
144 virtual bool TargetSelectInstruction(const Instruction *I);
145 virtual unsigned TargetMaterializeConstant(const Constant *C);
146 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
147 virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
150 #include "ARMGenFastISel.inc"
152 // Instruction selection routines.
154 bool SelectLoad(const Instruction *I);
155 bool SelectStore(const Instruction *I);
156 bool SelectBranch(const Instruction *I);
157 bool SelectIndirectBr(const Instruction *I);
158 bool SelectCmp(const Instruction *I);
159 bool SelectFPExt(const Instruction *I);
160 bool SelectFPTrunc(const Instruction *I);
161 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
162 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
163 bool SelectIToFP(const Instruction *I, bool isSigned);
164 bool SelectFPToI(const Instruction *I, bool isSigned);
165 bool SelectDiv(const Instruction *I, bool isSigned);
166 bool SelectRem(const Instruction *I, bool isSigned);
167 bool SelectCall(const Instruction *I, const char *IntrMemName);
168 bool SelectIntrinsicCall(const IntrinsicInst &I);
169 bool SelectSelect(const Instruction *I);
170 bool SelectRet(const Instruction *I);
171 bool SelectTrunc(const Instruction *I);
172 bool SelectIntExt(const Instruction *I);
173 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
177 bool isTypeLegal(Type *Ty, MVT &VT);
178 bool isLoadTypeLegal(Type *Ty, MVT &VT);
179 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
181 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
182 unsigned Alignment = 0, bool isZExt = true,
183 bool allocReg = true);
184 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
185 unsigned Alignment = 0);
186 bool ARMComputeAddress(const Value *Obj, Address &Addr);
187 void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
188 bool ARMIsMemCpySmall(uint64_t Len);
189 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
191 unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
192 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
193 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
194 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
195 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
196 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
197 unsigned ARMSelectCallOp(bool UseReg);
198 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, EVT VT);
200 // Call handling routines.
202 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
205 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
206 SmallVectorImpl<unsigned> &ArgRegs,
207 SmallVectorImpl<MVT> &ArgVTs,
208 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
209 SmallVectorImpl<unsigned> &RegArgs,
213 unsigned getLibcallReg(const Twine &Name);
214 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
215 const Instruction *I, CallingConv::ID CC,
216 unsigned &NumBytes, bool isVarArg);
217 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
219 // OptionalDef handling routines.
221 bool isARMNEONPred(const MachineInstr *MI);
222 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
223 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
224 void AddLoadStoreOperands(EVT VT, Address &Addr,
225 const MachineInstrBuilder &MIB,
226 unsigned Flags, bool useAM3);
229 } // end anonymous namespace
231 #include "ARMGenCallingConv.inc"
233 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
234 // we don't care about implicit defs here, just places we'll need to add a
235 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
236 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
237 if (!MI->hasOptionalDef())
240 // Look to see if our OptionalDef is defining CPSR or CCR.
241 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
242 const MachineOperand &MO = MI->getOperand(i);
243 if (!MO.isReg() || !MO.isDef()) continue;
244 if (MO.getReg() == ARM::CPSR)
250 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
251 const MCInstrDesc &MCID = MI->getDesc();
253 // If we're a thumb2 or not NEON function we were handled via isPredicable.
254 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
255 AFI->isThumb2Function())
258 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
259 if (MCID.OpInfo[i].isPredicate())
265 // If the machine is predicable go ahead and add the predicate operands, if
266 // it needs default CC operands add those.
267 // TODO: If we want to support thumb1 then we'll need to deal with optional
268 // CPSR defs that need to be added before the remaining operands. See s_cc_out
269 // for descriptions why.
270 const MachineInstrBuilder &
271 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
272 MachineInstr *MI = &*MIB;
274 // Do we use a predicate? or...
275 // Are we NEON in ARM mode and have a predicate operand? If so, I know
276 // we're not predicable but add it anyways.
277 if (TII.isPredicable(MI) || isARMNEONPred(MI))
280 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
281 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
283 if (DefinesOptionalPredicate(MI, &CPSR)) {
292 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
293 const TargetRegisterClass* RC) {
294 unsigned ResultReg = createResultReg(RC);
295 const MCInstrDesc &II = TII.get(MachineInstOpcode);
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
301 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
302 const TargetRegisterClass *RC,
303 unsigned Op0, bool Op0IsKill) {
304 unsigned ResultReg = createResultReg(RC);
305 const MCInstrDesc &II = TII.get(MachineInstOpcode);
307 if (II.getNumDefs() >= 1) {
308 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
309 .addReg(Op0, Op0IsKill * RegState::Kill));
311 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
312 .addReg(Op0, Op0IsKill * RegState::Kill));
313 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
314 TII.get(TargetOpcode::COPY), ResultReg)
315 .addReg(II.ImplicitDefs[0]));
320 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
321 const TargetRegisterClass *RC,
322 unsigned Op0, bool Op0IsKill,
323 unsigned Op1, bool Op1IsKill) {
324 unsigned ResultReg = createResultReg(RC);
325 const MCInstrDesc &II = TII.get(MachineInstOpcode);
327 if (II.getNumDefs() >= 1) {
328 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
329 .addReg(Op0, Op0IsKill * RegState::Kill)
330 .addReg(Op1, Op1IsKill * RegState::Kill));
332 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
333 .addReg(Op0, Op0IsKill * RegState::Kill)
334 .addReg(Op1, Op1IsKill * RegState::Kill));
335 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
336 TII.get(TargetOpcode::COPY), ResultReg)
337 .addReg(II.ImplicitDefs[0]));
342 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
343 const TargetRegisterClass *RC,
344 unsigned Op0, bool Op0IsKill,
345 unsigned Op1, bool Op1IsKill,
346 unsigned Op2, bool Op2IsKill) {
347 unsigned ResultReg = createResultReg(RC);
348 const MCInstrDesc &II = TII.get(MachineInstOpcode);
350 if (II.getNumDefs() >= 1) {
351 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
352 .addReg(Op0, Op0IsKill * RegState::Kill)
353 .addReg(Op1, Op1IsKill * RegState::Kill)
354 .addReg(Op2, Op2IsKill * RegState::Kill));
356 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
357 .addReg(Op0, Op0IsKill * RegState::Kill)
358 .addReg(Op1, Op1IsKill * RegState::Kill)
359 .addReg(Op2, Op2IsKill * RegState::Kill));
360 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
361 TII.get(TargetOpcode::COPY), ResultReg)
362 .addReg(II.ImplicitDefs[0]));
367 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
368 const TargetRegisterClass *RC,
369 unsigned Op0, bool Op0IsKill,
371 unsigned ResultReg = createResultReg(RC);
372 const MCInstrDesc &II = TII.get(MachineInstOpcode);
374 if (II.getNumDefs() >= 1) {
375 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
376 .addReg(Op0, Op0IsKill * RegState::Kill)
379 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
380 .addReg(Op0, Op0IsKill * RegState::Kill)
382 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
383 TII.get(TargetOpcode::COPY), ResultReg)
384 .addReg(II.ImplicitDefs[0]));
389 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
390 const TargetRegisterClass *RC,
391 unsigned Op0, bool Op0IsKill,
392 const ConstantFP *FPImm) {
393 unsigned ResultReg = createResultReg(RC);
394 const MCInstrDesc &II = TII.get(MachineInstOpcode);
396 if (II.getNumDefs() >= 1) {
397 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
398 .addReg(Op0, Op0IsKill * RegState::Kill)
401 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
402 .addReg(Op0, Op0IsKill * RegState::Kill)
404 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
405 TII.get(TargetOpcode::COPY), ResultReg)
406 .addReg(II.ImplicitDefs[0]));
411 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
412 const TargetRegisterClass *RC,
413 unsigned Op0, bool Op0IsKill,
414 unsigned Op1, bool Op1IsKill,
416 unsigned ResultReg = createResultReg(RC);
417 const MCInstrDesc &II = TII.get(MachineInstOpcode);
419 if (II.getNumDefs() >= 1) {
420 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
421 .addReg(Op0, Op0IsKill * RegState::Kill)
422 .addReg(Op1, Op1IsKill * RegState::Kill)
425 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
426 .addReg(Op0, Op0IsKill * RegState::Kill)
427 .addReg(Op1, Op1IsKill * RegState::Kill)
429 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
430 TII.get(TargetOpcode::COPY), ResultReg)
431 .addReg(II.ImplicitDefs[0]));
436 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
437 const TargetRegisterClass *RC,
439 unsigned ResultReg = createResultReg(RC);
440 const MCInstrDesc &II = TII.get(MachineInstOpcode);
442 if (II.getNumDefs() >= 1) {
443 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
446 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
449 TII.get(TargetOpcode::COPY), ResultReg)
450 .addReg(II.ImplicitDefs[0]));
455 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
456 const TargetRegisterClass *RC,
457 uint64_t Imm1, uint64_t Imm2) {
458 unsigned ResultReg = createResultReg(RC);
459 const MCInstrDesc &II = TII.get(MachineInstOpcode);
461 if (II.getNumDefs() >= 1) {
462 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
463 .addImm(Imm1).addImm(Imm2));
465 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
466 .addImm(Imm1).addImm(Imm2));
467 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
468 TII.get(TargetOpcode::COPY),
470 .addReg(II.ImplicitDefs[0]));
475 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
476 unsigned Op0, bool Op0IsKill,
478 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
479 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
480 "Cannot yet extract from physregs");
482 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
483 DL, TII.get(TargetOpcode::COPY), ResultReg)
484 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
488 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
489 // checks from the various callers.
490 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
491 if (VT == MVT::f64) return 0;
493 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
494 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
495 TII.get(ARM::VMOVSR), MoveReg)
500 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
501 if (VT == MVT::i64) return 0;
503 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
504 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
505 TII.get(ARM::VMOVRS), MoveReg)
510 // For double width floating point we need to materialize two constants
511 // (the high and the low) into integer registers then use a move to get
512 // the combined constant into an FP reg.
513 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
514 const APFloat Val = CFP->getValueAPF();
515 bool is64bit = VT == MVT::f64;
517 // This checks to see if we can use VFP3 instructions to materialize
518 // a constant, otherwise we have to go through the constant pool.
519 if (TLI.isFPImmLegal(Val, VT)) {
523 Imm = ARM_AM::getFP64Imm(Val);
526 Imm = ARM_AM::getFP32Imm(Val);
529 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
530 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
536 // Require VFP2 for loading fp constants.
537 if (!Subtarget->hasVFP2()) return false;
539 // MachineConstantPool wants an explicit alignment.
540 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
542 // TODO: Figure out if this is correct.
543 Align = TD.getTypeAllocSize(CFP->getType());
545 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
546 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
547 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
549 // The extra reg is for addrmode5.
550 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
552 .addConstantPoolIndex(Idx)
557 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
559 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
562 // If we can do this in a single instruction without a constant pool entry
564 const ConstantInt *CI = cast<ConstantInt>(C);
565 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
566 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
567 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
569 unsigned ImmReg = createResultReg(RC);
570 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
571 TII.get(Opc), ImmReg)
572 .addImm(CI->getZExtValue()));
576 // Use MVN to emit negative constants.
577 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
578 unsigned Imm = (unsigned)~(CI->getSExtValue());
579 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
580 (ARM_AM::getSOImmVal(Imm) != -1);
582 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
583 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
584 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
585 TII.get(Opc), ImmReg)
591 // Load from constant pool. For now 32-bit only.
595 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
597 // MachineConstantPool wants an explicit alignment.
598 unsigned Align = TD.getPrefTypeAlignment(C->getType());
600 // TODO: Figure out if this is correct.
601 Align = TD.getTypeAllocSize(C->getType());
603 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
606 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
607 TII.get(ARM::t2LDRpci), DestReg)
608 .addConstantPoolIndex(Idx));
610 // The extra immediate is for addrmode2.
611 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
612 TII.get(ARM::LDRcp), DestReg)
613 .addConstantPoolIndex(Idx)
619 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
620 // For now 32-bit only.
621 if (VT != MVT::i32) return 0;
623 Reloc::Model RelocM = TM.getRelocationModel();
624 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
625 const TargetRegisterClass *RC = isThumb2 ?
626 (const TargetRegisterClass*)&ARM::rGPRRegClass :
627 (const TargetRegisterClass*)&ARM::GPRRegClass;
628 unsigned DestReg = createResultReg(RC);
630 // Use movw+movt when possible, it avoids constant pool entries.
631 // Darwin targets don't support movt with Reloc::Static, see
632 // ARMTargetLowering::LowerGlobalAddressDarwin. Other targets only support
633 // static movt relocations.
634 if (Subtarget->useMovt() &&
635 Subtarget->isTargetDarwin() == (RelocM != Reloc::Static)) {
639 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
641 case Reloc::DynamicNoPIC:
642 Opc = isThumb2 ? ARM::t2MOV_ga_dyn : ARM::MOV_ga_dyn;
645 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
648 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
649 DestReg).addGlobalAddress(GV));
651 // MachineConstantPool wants an explicit alignment.
652 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
654 // TODO: Figure out if this is correct.
655 Align = TD.getTypeAllocSize(GV->getType());
658 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
659 return ARMLowerPICELF(GV, Align, VT);
662 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
663 (Subtarget->isThumb() ? 4 : 8);
664 unsigned Id = AFI->createPICLabelUId();
665 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
668 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
671 MachineInstrBuilder MIB;
673 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
674 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
675 .addConstantPoolIndex(Idx);
676 if (RelocM == Reloc::PIC_)
678 AddOptionalDefs(MIB);
680 // The extra immediate is for addrmode2.
681 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
683 .addConstantPoolIndex(Idx)
685 AddOptionalDefs(MIB);
687 if (RelocM == Reloc::PIC_) {
688 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
689 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
691 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
692 DL, TII.get(Opc), NewDestReg)
695 AddOptionalDefs(MIB);
702 MachineInstrBuilder MIB;
703 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
705 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
706 TII.get(ARM::t2LDRi12), NewDestReg)
710 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
714 DestReg = NewDestReg;
715 AddOptionalDefs(MIB);
721 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
722 EVT VT = TLI.getValueType(C->getType(), true);
724 // Only handle simple types.
725 if (!VT.isSimple()) return 0;
727 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
728 return ARMMaterializeFP(CFP, VT);
729 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
730 return ARMMaterializeGV(GV, VT);
731 else if (isa<ConstantInt>(C))
732 return ARMMaterializeInt(C, VT);
737 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
739 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
740 // Don't handle dynamic allocas.
741 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
744 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
746 DenseMap<const AllocaInst*, int>::iterator SI =
747 FuncInfo.StaticAllocaMap.find(AI);
749 // This will get lowered later into the correct offsets and registers
750 // via rewriteXFrameIndex.
751 if (SI != FuncInfo.StaticAllocaMap.end()) {
752 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
753 unsigned ResultReg = createResultReg(RC);
754 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
755 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
756 TII.get(Opc), ResultReg)
757 .addFrameIndex(SI->second)
765 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
766 EVT evt = TLI.getValueType(Ty, true);
768 // Only handle simple types.
769 if (evt == MVT::Other || !evt.isSimple()) return false;
770 VT = evt.getSimpleVT();
772 // Handle all legal types, i.e. a register that will directly hold this
774 return TLI.isTypeLegal(VT);
777 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
778 if (isTypeLegal(Ty, VT)) return true;
780 // If this is a type than can be sign or zero-extended to a basic operation
781 // go ahead and accept it now.
782 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
788 // Computes the address to get to an object.
789 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
790 // Some boilerplate from the X86 FastISel.
791 const User *U = NULL;
792 unsigned Opcode = Instruction::UserOp1;
793 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
794 // Don't walk into other basic blocks unless the object is an alloca from
795 // another block, otherwise it may not have a virtual register assigned.
796 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
797 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
798 Opcode = I->getOpcode();
801 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
802 Opcode = C->getOpcode();
806 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
807 if (Ty->getAddressSpace() > 255)
808 // Fast instruction selection doesn't support the special
815 case Instruction::BitCast: {
816 // Look through bitcasts.
817 return ARMComputeAddress(U->getOperand(0), Addr);
819 case Instruction::IntToPtr: {
820 // Look past no-op inttoptrs.
821 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
822 return ARMComputeAddress(U->getOperand(0), Addr);
825 case Instruction::PtrToInt: {
826 // Look past no-op ptrtoints.
827 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
828 return ARMComputeAddress(U->getOperand(0), Addr);
831 case Instruction::GetElementPtr: {
832 Address SavedAddr = Addr;
833 int TmpOffset = Addr.Offset;
835 // Iterate through the GEP folding the constants into offsets where
837 gep_type_iterator GTI = gep_type_begin(U);
838 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
839 i != e; ++i, ++GTI) {
840 const Value *Op = *i;
841 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
842 const StructLayout *SL = TD.getStructLayout(STy);
843 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
844 TmpOffset += SL->getElementOffset(Idx);
846 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
848 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
849 // Constant-offset addressing.
850 TmpOffset += CI->getSExtValue() * S;
853 if (isa<AddOperator>(Op) &&
854 (!isa<Instruction>(Op) ||
855 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
857 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
858 // An add (in the same block) with a constant operand. Fold the
861 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
862 TmpOffset += CI->getSExtValue() * S;
863 // Iterate on the other operand.
864 Op = cast<AddOperator>(Op)->getOperand(0);
868 goto unsupported_gep;
873 // Try to grab the base operand now.
874 Addr.Offset = TmpOffset;
875 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
877 // We failed, restore everything and try the other options.
883 case Instruction::Alloca: {
884 const AllocaInst *AI = cast<AllocaInst>(Obj);
885 DenseMap<const AllocaInst*, int>::iterator SI =
886 FuncInfo.StaticAllocaMap.find(AI);
887 if (SI != FuncInfo.StaticAllocaMap.end()) {
888 Addr.BaseType = Address::FrameIndexBase;
889 Addr.Base.FI = SI->second;
896 // Try to get this in a register if nothing else has worked.
897 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
898 return Addr.Base.Reg != 0;
901 void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) {
903 assert(VT.isSimple() && "Non-simple types are invalid here!");
905 bool needsLowering = false;
906 switch (VT.getSimpleVT().SimpleTy) {
907 default: llvm_unreachable("Unhandled load/store type!");
913 // Integer loads/stores handle 12-bit offsets.
914 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
915 // Handle negative offsets.
916 if (needsLowering && isThumb2)
917 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
920 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
921 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
926 // Floating point operands handle 8-bit offsets.
927 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
931 // If this is a stack pointer and the offset needs to be simplified then
932 // put the alloca address into a register, set the base type back to
933 // register and continue. This should almost never happen.
934 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
935 const TargetRegisterClass *RC = isThumb2 ?
936 (const TargetRegisterClass*)&ARM::tGPRRegClass :
937 (const TargetRegisterClass*)&ARM::GPRRegClass;
938 unsigned ResultReg = createResultReg(RC);
939 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
940 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
941 TII.get(Opc), ResultReg)
942 .addFrameIndex(Addr.Base.FI)
944 Addr.Base.Reg = ResultReg;
945 Addr.BaseType = Address::RegBase;
948 // Since the offset is too large for the load/store instruction
949 // get the reg+offset into a register.
951 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
952 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
957 void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
958 const MachineInstrBuilder &MIB,
959 unsigned Flags, bool useAM3) {
960 // addrmode5 output depends on the selection dag addressing dividing the
961 // offset by 4 that it then later multiplies. Do this here as well.
962 if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
963 VT.getSimpleVT().SimpleTy == MVT::f64)
966 // Frame base works a bit differently. Handle it separately.
967 if (Addr.BaseType == Address::FrameIndexBase) {
968 int FI = Addr.Base.FI;
969 int Offset = Addr.Offset;
970 MachineMemOperand *MMO =
971 FuncInfo.MF->getMachineMemOperand(
972 MachinePointerInfo::getFixedStack(FI, Offset),
974 MFI.getObjectSize(FI),
975 MFI.getObjectAlignment(FI));
976 // Now add the rest of the operands.
977 MIB.addFrameIndex(FI);
979 // ARM halfword load/stores and signed byte loads need an additional
982 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
986 MIB.addImm(Addr.Offset);
988 MIB.addMemOperand(MMO);
990 // Now add the rest of the operands.
991 MIB.addReg(Addr.Base.Reg);
993 // ARM halfword load/stores and signed byte loads need an additional
996 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
1000 MIB.addImm(Addr.Offset);
1003 AddOptionalDefs(MIB);
1006 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
1007 unsigned Alignment, bool isZExt, bool allocReg) {
1008 assert(VT.isSimple() && "Non-simple types are invalid here!");
1010 bool useAM3 = false;
1011 bool needVMOV = false;
1012 const TargetRegisterClass *RC;
1013 switch (VT.getSimpleVT().SimpleTy) {
1014 // This is mostly going to be Neon/vector support.
1015 default: return false;
1019 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1020 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
1022 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
1031 RC = &ARM::GPRRegClass;
1034 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1038 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1039 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
1041 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1043 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1046 RC = &ARM::GPRRegClass;
1049 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1053 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1056 Opc = ARM::t2LDRi12;
1060 RC = &ARM::GPRRegClass;
1063 if (!Subtarget->hasVFP2()) return false;
1064 // Unaligned loads need special handling. Floats require word-alignment.
1065 if (Alignment && Alignment < 4) {
1068 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1069 RC = &ARM::GPRRegClass;
1072 RC = TLI.getRegClassFor(VT);
1076 if (!Subtarget->hasVFP2()) return false;
1077 // FIXME: Unaligned loads need special handling. Doublewords require
1079 if (Alignment && Alignment < 4)
1083 RC = TLI.getRegClassFor(VT);
1086 // Simplify this down to something we can handle.
1087 ARMSimplifyAddress(Addr, VT, useAM3);
1089 // Create the base instruction, then add the operands.
1091 ResultReg = createResultReg(RC);
1092 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1093 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1094 TII.get(Opc), ResultReg);
1095 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1097 // If we had an unaligned load of a float we've converted it to an regular
1098 // load. Now we must move from the GRP to the FP register.
1100 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1101 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1102 TII.get(ARM::VMOVSR), MoveReg)
1103 .addReg(ResultReg));
1104 ResultReg = MoveReg;
1109 bool ARMFastISel::SelectLoad(const Instruction *I) {
1110 // Atomic loads need special handling.
1111 if (cast<LoadInst>(I)->isAtomic())
1114 // Verify we have a legal type before going any further.
1116 if (!isLoadTypeLegal(I->getType(), VT))
1119 // See if we can handle this address.
1121 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1124 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1126 UpdateValueMap(I, ResultReg);
1130 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
1131 unsigned Alignment) {
1133 bool useAM3 = false;
1134 switch (VT.getSimpleVT().SimpleTy) {
1135 // This is mostly going to be Neon/vector support.
1136 default: return false;
1138 unsigned Res = createResultReg(isThumb2 ?
1139 (const TargetRegisterClass*)&ARM::tGPRRegClass :
1140 (const TargetRegisterClass*)&ARM::GPRRegClass);
1141 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1142 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1144 .addReg(SrcReg).addImm(1));
1146 } // Fallthrough here.
1149 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1150 StrOpc = ARM::t2STRBi8;
1152 StrOpc = ARM::t2STRBi12;
1154 StrOpc = ARM::STRBi12;
1158 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1162 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1163 StrOpc = ARM::t2STRHi8;
1165 StrOpc = ARM::t2STRHi12;
1172 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1176 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1177 StrOpc = ARM::t2STRi8;
1179 StrOpc = ARM::t2STRi12;
1181 StrOpc = ARM::STRi12;
1185 if (!Subtarget->hasVFP2()) return false;
1186 // Unaligned stores need special handling. Floats require word-alignment.
1187 if (Alignment && Alignment < 4) {
1188 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1189 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1190 TII.get(ARM::VMOVRS), MoveReg)
1194 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1196 StrOpc = ARM::VSTRS;
1200 if (!Subtarget->hasVFP2()) return false;
1201 // FIXME: Unaligned stores need special handling. Doublewords require
1203 if (Alignment && Alignment < 4)
1206 StrOpc = ARM::VSTRD;
1209 // Simplify this down to something we can handle.
1210 ARMSimplifyAddress(Addr, VT, useAM3);
1212 // Create the base instruction, then add the operands.
1213 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1216 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1220 bool ARMFastISel::SelectStore(const Instruction *I) {
1221 Value *Op0 = I->getOperand(0);
1222 unsigned SrcReg = 0;
1224 // Atomic stores need special handling.
1225 if (cast<StoreInst>(I)->isAtomic())
1228 // Verify we have a legal type before going any further.
1230 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1233 // Get the value to be stored into a register.
1234 SrcReg = getRegForValue(Op0);
1235 if (SrcReg == 0) return false;
1237 // See if we can handle this address.
1239 if (!ARMComputeAddress(I->getOperand(1), Addr))
1242 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1247 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1249 // Needs two compares...
1250 case CmpInst::FCMP_ONE:
1251 case CmpInst::FCMP_UEQ:
1253 // AL is our "false" for now. The other two need more compares.
1255 case CmpInst::ICMP_EQ:
1256 case CmpInst::FCMP_OEQ:
1258 case CmpInst::ICMP_SGT:
1259 case CmpInst::FCMP_OGT:
1261 case CmpInst::ICMP_SGE:
1262 case CmpInst::FCMP_OGE:
1264 case CmpInst::ICMP_UGT:
1265 case CmpInst::FCMP_UGT:
1267 case CmpInst::FCMP_OLT:
1269 case CmpInst::ICMP_ULE:
1270 case CmpInst::FCMP_OLE:
1272 case CmpInst::FCMP_ORD:
1274 case CmpInst::FCMP_UNO:
1276 case CmpInst::FCMP_UGE:
1278 case CmpInst::ICMP_SLT:
1279 case CmpInst::FCMP_ULT:
1281 case CmpInst::ICMP_SLE:
1282 case CmpInst::FCMP_ULE:
1284 case CmpInst::FCMP_UNE:
1285 case CmpInst::ICMP_NE:
1287 case CmpInst::ICMP_UGE:
1289 case CmpInst::ICMP_ULT:
1294 bool ARMFastISel::SelectBranch(const Instruction *I) {
1295 const BranchInst *BI = cast<BranchInst>(I);
1296 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1297 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1299 // Simple branch support.
1301 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1303 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1304 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1306 // Get the compare predicate.
1307 // Try to take advantage of fallthrough opportunities.
1308 CmpInst::Predicate Predicate = CI->getPredicate();
1309 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1310 std::swap(TBB, FBB);
1311 Predicate = CmpInst::getInversePredicate(Predicate);
1314 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1316 // We may not handle every CC for now.
1317 if (ARMPred == ARMCC::AL) return false;
1319 // Emit the compare.
1320 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1323 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1324 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1325 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1326 FastEmitBranch(FBB, DL);
1327 FuncInfo.MBB->addSuccessor(TBB);
1330 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1332 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1333 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1334 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1335 unsigned OpReg = getRegForValue(TI->getOperand(0));
1336 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1338 .addReg(OpReg).addImm(1));
1340 unsigned CCMode = ARMCC::NE;
1341 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1342 std::swap(TBB, FBB);
1346 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1347 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1348 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1350 FastEmitBranch(FBB, DL);
1351 FuncInfo.MBB->addSuccessor(TBB);
1354 } else if (const ConstantInt *CI =
1355 dyn_cast<ConstantInt>(BI->getCondition())) {
1356 uint64_t Imm = CI->getZExtValue();
1357 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1358 FastEmitBranch(Target, DL);
1362 unsigned CmpReg = getRegForValue(BI->getCondition());
1363 if (CmpReg == 0) return false;
1365 // We've been divorced from our compare! Our block was split, and
1366 // now our compare lives in a predecessor block. We musn't
1367 // re-compare here, as the children of the compare aren't guaranteed
1368 // live across the block boundary (we *could* check for this).
1369 // Regardless, the compare has been done in the predecessor block,
1370 // and it left a value for us in a virtual register. Ergo, we test
1371 // the one-bit value left in the virtual register.
1372 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1373 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1374 .addReg(CmpReg).addImm(1));
1376 unsigned CCMode = ARMCC::NE;
1377 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1378 std::swap(TBB, FBB);
1382 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1383 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1384 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1385 FastEmitBranch(FBB, DL);
1386 FuncInfo.MBB->addSuccessor(TBB);
1390 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1391 unsigned AddrReg = getRegForValue(I->getOperand(0));
1392 if (AddrReg == 0) return false;
1394 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1395 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
1398 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1399 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1400 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1405 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1407 Type *Ty = Src1Value->getType();
1408 EVT SrcVT = TLI.getValueType(Ty, true);
1409 if (!SrcVT.isSimple()) return false;
1411 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1412 if (isFloat && !Subtarget->hasVFP2())
1415 // Check to see if the 2nd operand is a constant that we can encode directly
1418 bool UseImm = false;
1419 bool isNegativeImm = false;
1420 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1421 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1422 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1423 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1425 const APInt &CIVal = ConstInt->getValue();
1426 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1427 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1428 // then a cmn, because there is no way to represent 2147483648 as a
1429 // signed 32-bit int.
1430 if (Imm < 0 && Imm != (int)0x80000000) {
1431 isNegativeImm = true;
1434 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1435 (ARM_AM::getSOImmVal(Imm) != -1);
1437 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1438 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1439 if (ConstFP->isZero() && !ConstFP->isNegative())
1445 bool needsExt = false;
1446 switch (SrcVT.getSimpleVT().SimpleTy) {
1447 default: return false;
1448 // TODO: Verify compares.
1451 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1455 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1461 // Intentional fall-through.
1465 CmpOpc = ARM::t2CMPrr;
1467 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1470 CmpOpc = ARM::CMPrr;
1472 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1477 unsigned SrcReg1 = getRegForValue(Src1Value);
1478 if (SrcReg1 == 0) return false;
1480 unsigned SrcReg2 = 0;
1482 SrcReg2 = getRegForValue(Src2Value);
1483 if (SrcReg2 == 0) return false;
1486 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1488 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1489 if (SrcReg1 == 0) return false;
1491 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1492 if (SrcReg2 == 0) return false;
1497 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1499 .addReg(SrcReg1).addReg(SrcReg2));
1501 MachineInstrBuilder MIB;
1502 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1505 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1508 AddOptionalDefs(MIB);
1511 // For floating point we need to move the result to a comparison register
1512 // that we can then use for branches.
1513 if (Ty->isFloatTy() || Ty->isDoubleTy())
1514 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1515 TII.get(ARM::FMSTAT)));
1519 bool ARMFastISel::SelectCmp(const Instruction *I) {
1520 const CmpInst *CI = cast<CmpInst>(I);
1522 // Get the compare predicate.
1523 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1525 // We may not handle every CC for now.
1526 if (ARMPred == ARMCC::AL) return false;
1528 // Emit the compare.
1529 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1532 // Now set a register based on the comparison. Explicitly set the predicates
1534 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1535 const TargetRegisterClass *RC = isThumb2 ?
1536 (const TargetRegisterClass*)&ARM::rGPRRegClass :
1537 (const TargetRegisterClass*)&ARM::GPRRegClass;
1538 unsigned DestReg = createResultReg(RC);
1539 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1540 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1541 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1542 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1543 .addReg(ZeroReg).addImm(1)
1544 .addImm(ARMPred).addReg(ARM::CPSR);
1546 UpdateValueMap(I, DestReg);
1550 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1551 // Make sure we have VFP and that we're extending float to double.
1552 if (!Subtarget->hasVFP2()) return false;
1554 Value *V = I->getOperand(0);
1555 if (!I->getType()->isDoubleTy() ||
1556 !V->getType()->isFloatTy()) return false;
1558 unsigned Op = getRegForValue(V);
1559 if (Op == 0) return false;
1561 unsigned Result = createResultReg(&ARM::DPRRegClass);
1562 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1563 TII.get(ARM::VCVTDS), Result)
1565 UpdateValueMap(I, Result);
1569 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1570 // Make sure we have VFP and that we're truncating double to float.
1571 if (!Subtarget->hasVFP2()) return false;
1573 Value *V = I->getOperand(0);
1574 if (!(I->getType()->isFloatTy() &&
1575 V->getType()->isDoubleTy())) return false;
1577 unsigned Op = getRegForValue(V);
1578 if (Op == 0) return false;
1580 unsigned Result = createResultReg(&ARM::SPRRegClass);
1581 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1582 TII.get(ARM::VCVTSD), Result)
1584 UpdateValueMap(I, Result);
1588 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1589 // Make sure we have VFP.
1590 if (!Subtarget->hasVFP2()) return false;
1593 Type *Ty = I->getType();
1594 if (!isTypeLegal(Ty, DstVT))
1597 Value *Src = I->getOperand(0);
1598 EVT SrcVT = TLI.getValueType(Src->getType(), true);
1599 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1602 unsigned SrcReg = getRegForValue(Src);
1603 if (SrcReg == 0) return false;
1605 // Handle sign-extension.
1606 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1607 EVT DestVT = MVT::i32;
1608 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT,
1609 /*isZExt*/!isSigned);
1610 if (SrcReg == 0) return false;
1613 // The conversion routine works on fp-reg to fp-reg and the operand above
1614 // was an integer, move it to the fp registers if possible.
1615 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1616 if (FP == 0) return false;
1619 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1620 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1623 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1624 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1627 UpdateValueMap(I, ResultReg);
1631 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1632 // Make sure we have VFP.
1633 if (!Subtarget->hasVFP2()) return false;
1636 Type *RetTy = I->getType();
1637 if (!isTypeLegal(RetTy, DstVT))
1640 unsigned Op = getRegForValue(I->getOperand(0));
1641 if (Op == 0) return false;
1644 Type *OpTy = I->getOperand(0)->getType();
1645 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1646 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1649 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1650 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1651 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1655 // This result needs to be in an integer register, but the conversion only
1656 // takes place in fp-regs.
1657 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1658 if (IntReg == 0) return false;
1660 UpdateValueMap(I, IntReg);
1664 bool ARMFastISel::SelectSelect(const Instruction *I) {
1666 if (!isTypeLegal(I->getType(), VT))
1669 // Things need to be register sized for register moves.
1670 if (VT != MVT::i32) return false;
1672 unsigned CondReg = getRegForValue(I->getOperand(0));
1673 if (CondReg == 0) return false;
1674 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1675 if (Op1Reg == 0) return false;
1677 // Check to see if we can use an immediate in the conditional move.
1679 bool UseImm = false;
1680 bool isNegativeImm = false;
1681 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1682 assert (VT == MVT::i32 && "Expecting an i32.");
1683 Imm = (int)ConstInt->getValue().getZExtValue();
1685 isNegativeImm = true;
1688 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1689 (ARM_AM::getSOImmVal(Imm) != -1);
1692 unsigned Op2Reg = 0;
1694 Op2Reg = getRegForValue(I->getOperand(2));
1695 if (Op2Reg == 0) return false;
1698 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1699 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1700 .addReg(CondReg).addImm(0));
1703 const TargetRegisterClass *RC;
1705 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1706 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1708 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1710 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1712 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1714 unsigned ResultReg = createResultReg(RC);
1716 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1717 .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1719 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1720 .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1721 UpdateValueMap(I, ResultReg);
1725 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1727 Type *Ty = I->getType();
1728 if (!isTypeLegal(Ty, VT))
1731 // If we have integer div support we should have selected this automagically.
1732 // In case we have a real miss go ahead and return false and we'll pick
1734 if (Subtarget->hasDivide()) return false;
1736 // Otherwise emit a libcall.
1737 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1739 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1740 else if (VT == MVT::i16)
1741 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1742 else if (VT == MVT::i32)
1743 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1744 else if (VT == MVT::i64)
1745 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1746 else if (VT == MVT::i128)
1747 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1748 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1750 return ARMEmitLibcall(I, LC);
1753 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1755 Type *Ty = I->getType();
1756 if (!isTypeLegal(Ty, VT))
1759 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1761 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1762 else if (VT == MVT::i16)
1763 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1764 else if (VT == MVT::i32)
1765 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1766 else if (VT == MVT::i64)
1767 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1768 else if (VT == MVT::i128)
1769 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1770 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1772 return ARMEmitLibcall(I, LC);
1775 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1776 EVT DestVT = TLI.getValueType(I->getType(), true);
1778 // We can get here in the case when we have a binary operation on a non-legal
1779 // type and the target independent selector doesn't know how to handle it.
1780 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1784 switch (ISDOpcode) {
1785 default: return false;
1787 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1790 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1793 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1797 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1798 if (SrcReg1 == 0) return false;
1800 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1801 // in the instruction, rather then materializing the value in a register.
1802 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1803 if (SrcReg2 == 0) return false;
1805 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1806 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1807 TII.get(Opc), ResultReg)
1808 .addReg(SrcReg1).addReg(SrcReg2));
1809 UpdateValueMap(I, ResultReg);
1813 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1814 EVT VT = TLI.getValueType(I->getType(), true);
1816 // We can get here in the case when we want to use NEON for our fp
1817 // operations, but can't figure out how to. Just use the vfp instructions
1819 // FIXME: It'd be nice to use NEON instructions.
1820 Type *Ty = I->getType();
1821 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1822 if (isFloat && !Subtarget->hasVFP2())
1826 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1827 switch (ISDOpcode) {
1828 default: return false;
1830 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1833 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1836 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1839 unsigned Op1 = getRegForValue(I->getOperand(0));
1840 if (Op1 == 0) return false;
1842 unsigned Op2 = getRegForValue(I->getOperand(1));
1843 if (Op2 == 0) return false;
1845 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1846 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1847 TII.get(Opc), ResultReg)
1848 .addReg(Op1).addReg(Op2));
1849 UpdateValueMap(I, ResultReg);
1853 // Call Handling Code
1855 // This is largely taken directly from CCAssignFnForNode
1856 // TODO: We may not support all of this.
1857 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1862 llvm_unreachable("Unsupported calling convention");
1863 case CallingConv::Fast:
1864 if (Subtarget->hasVFP2() && !isVarArg) {
1865 if (!Subtarget->isAAPCS_ABI())
1866 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1867 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1868 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1871 case CallingConv::C:
1872 // Use target triple & subtarget features to do actual dispatch.
1873 if (Subtarget->isAAPCS_ABI()) {
1874 if (Subtarget->hasVFP2() &&
1875 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1876 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1878 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1880 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1881 case CallingConv::ARM_AAPCS_VFP:
1883 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1884 // Fall through to soft float variant, variadic functions don't
1885 // use hard floating point ABI.
1886 case CallingConv::ARM_AAPCS:
1887 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1888 case CallingConv::ARM_APCS:
1889 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1890 case CallingConv::GHC:
1892 llvm_unreachable("Can't return in GHC call convention");
1894 return CC_ARM_APCS_GHC;
1898 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1899 SmallVectorImpl<unsigned> &ArgRegs,
1900 SmallVectorImpl<MVT> &ArgVTs,
1901 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1902 SmallVectorImpl<unsigned> &RegArgs,
1906 SmallVector<CCValAssign, 16> ArgLocs;
1907 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1908 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1909 CCAssignFnForCall(CC, false, isVarArg));
1911 // Check that we can handle all of the arguments. If we can't, then bail out
1912 // now before we add code to the MBB.
1913 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1914 CCValAssign &VA = ArgLocs[i];
1915 MVT ArgVT = ArgVTs[VA.getValNo()];
1917 // We don't handle NEON/vector parameters yet.
1918 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1921 // Now copy/store arg to correct locations.
1922 if (VA.isRegLoc() && !VA.needsCustom()) {
1924 } else if (VA.needsCustom()) {
1925 // TODO: We need custom lowering for vector (v2f64) args.
1926 if (VA.getLocVT() != MVT::f64 ||
1927 // TODO: Only handle register args for now.
1928 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1931 switch (static_cast<EVT>(ArgVT).getSimpleVT().SimpleTy) {
1940 if (!Subtarget->hasVFP2())
1944 if (!Subtarget->hasVFP2())
1951 // At the point, we are able to handle the call's arguments in fast isel.
1953 // Get a count of how many bytes are to be pushed on the stack.
1954 NumBytes = CCInfo.getNextStackOffset();
1956 // Issue CALLSEQ_START
1957 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1958 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1959 TII.get(AdjStackDown))
1962 // Process the args.
1963 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1964 CCValAssign &VA = ArgLocs[i];
1965 unsigned Arg = ArgRegs[VA.getValNo()];
1966 MVT ArgVT = ArgVTs[VA.getValNo()];
1968 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1969 "We don't handle NEON/vector parameters yet.");
1971 // Handle arg promotion, etc.
1972 switch (VA.getLocInfo()) {
1973 case CCValAssign::Full: break;
1974 case CCValAssign::SExt: {
1975 MVT DestVT = VA.getLocVT();
1976 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1977 assert (Arg != 0 && "Failed to emit a sext");
1981 case CCValAssign::AExt:
1982 // Intentional fall-through. Handle AExt and ZExt.
1983 case CCValAssign::ZExt: {
1984 MVT DestVT = VA.getLocVT();
1985 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1986 assert (Arg != 0 && "Failed to emit a sext");
1990 case CCValAssign::BCvt: {
1991 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1992 /*TODO: Kill=*/false);
1993 assert(BC != 0 && "Failed to emit a bitcast!");
1995 ArgVT = VA.getLocVT();
1998 default: llvm_unreachable("Unknown arg promotion!");
2001 // Now copy/store arg to correct locations.
2002 if (VA.isRegLoc() && !VA.needsCustom()) {
2003 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2006 RegArgs.push_back(VA.getLocReg());
2007 } else if (VA.needsCustom()) {
2008 // TODO: We need custom lowering for vector (v2f64) args.
2009 assert(VA.getLocVT() == MVT::f64 &&
2010 "Custom lowering for v2f64 args not available");
2012 CCValAssign &NextVA = ArgLocs[++i];
2014 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2015 "We only handle register args!");
2017 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2018 TII.get(ARM::VMOVRRD), VA.getLocReg())
2019 .addReg(NextVA.getLocReg(), RegState::Define)
2021 RegArgs.push_back(VA.getLocReg());
2022 RegArgs.push_back(NextVA.getLocReg());
2024 assert(VA.isMemLoc());
2025 // Need to store on the stack.
2027 Addr.BaseType = Address::RegBase;
2028 Addr.Base.Reg = ARM::SP;
2029 Addr.Offset = VA.getLocMemOffset();
2031 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2032 assert(EmitRet && "Could not emit a store for argument!");
2039 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2040 const Instruction *I, CallingConv::ID CC,
2041 unsigned &NumBytes, bool isVarArg) {
2042 // Issue CALLSEQ_END
2043 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2044 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2045 TII.get(AdjStackUp))
2046 .addImm(NumBytes).addImm(0));
2048 // Now the return value.
2049 if (RetVT != MVT::isVoid) {
2050 SmallVector<CCValAssign, 16> RVLocs;
2051 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2052 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2054 // Copy all of the result registers out of their specified physreg.
2055 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2056 // For this move we copy into two registers and then move into the
2057 // double fp reg we want.
2058 EVT DestVT = RVLocs[0].getValVT();
2059 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2060 unsigned ResultReg = createResultReg(DstRC);
2061 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2062 TII.get(ARM::VMOVDRR), ResultReg)
2063 .addReg(RVLocs[0].getLocReg())
2064 .addReg(RVLocs[1].getLocReg()));
2066 UsedRegs.push_back(RVLocs[0].getLocReg());
2067 UsedRegs.push_back(RVLocs[1].getLocReg());
2069 // Finally update the result.
2070 UpdateValueMap(I, ResultReg);
2072 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2073 EVT CopyVT = RVLocs[0].getValVT();
2075 // Special handling for extended integers.
2076 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2079 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2081 unsigned ResultReg = createResultReg(DstRC);
2082 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2083 ResultReg).addReg(RVLocs[0].getLocReg());
2084 UsedRegs.push_back(RVLocs[0].getLocReg());
2086 // Finally update the result.
2087 UpdateValueMap(I, ResultReg);
2094 bool ARMFastISel::SelectRet(const Instruction *I) {
2095 const ReturnInst *Ret = cast<ReturnInst>(I);
2096 const Function &F = *I->getParent()->getParent();
2098 if (!FuncInfo.CanLowerReturn)
2101 CallingConv::ID CC = F.getCallingConv();
2102 if (Ret->getNumOperands() > 0) {
2103 SmallVector<ISD::OutputArg, 4> Outs;
2104 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
2107 // Analyze operands of the call, assigning locations to each operand.
2108 SmallVector<CCValAssign, 16> ValLocs;
2109 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
2110 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2113 const Value *RV = Ret->getOperand(0);
2114 unsigned Reg = getRegForValue(RV);
2118 // Only handle a single return value for now.
2119 if (ValLocs.size() != 1)
2122 CCValAssign &VA = ValLocs[0];
2124 // Don't bother handling odd stuff for now.
2125 if (VA.getLocInfo() != CCValAssign::Full)
2127 // Only handle register returns for now.
2131 unsigned SrcReg = Reg + VA.getValNo();
2132 EVT RVVT = TLI.getValueType(RV->getType());
2133 EVT DestVT = VA.getValVT();
2134 // Special handling for extended integers.
2135 if (RVVT != DestVT) {
2136 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2139 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2141 // Perform extension if flagged as either zext or sext. Otherwise, do
2143 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2144 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2145 if (SrcReg == 0) return false;
2150 unsigned DstReg = VA.getLocReg();
2151 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2152 // Avoid a cross-class copy. This is very unlikely.
2153 if (!SrcRC->contains(DstReg))
2155 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2156 DstReg).addReg(SrcReg);
2158 // Mark the register as live out of the function.
2159 MRI.addLiveOut(VA.getLocReg());
2162 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2163 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2168 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2170 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2172 return isThumb2 ? ARM::tBL : ARM::BL;
2175 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2176 GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false,
2177 GlobalValue::ExternalLinkage, 0, Name);
2178 return ARMMaterializeGV(GV, TLI.getValueType(GV->getType()));
2181 // A quick function that will emit a call for a named libcall in F with the
2182 // vector of passed arguments for the Instruction in I. We can assume that we
2183 // can emit a call for any libcall we can produce. This is an abridged version
2184 // of the full call infrastructure since we won't need to worry about things
2185 // like computed function pointers or strange arguments at call sites.
2186 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2188 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2189 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2191 // Handle *simple* calls for now.
2192 Type *RetTy = I->getType();
2194 if (RetTy->isVoidTy())
2195 RetVT = MVT::isVoid;
2196 else if (!isTypeLegal(RetTy, RetVT))
2199 // Can't handle non-double multi-reg retvals.
2200 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2201 SmallVector<CCValAssign, 16> RVLocs;
2202 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
2203 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2204 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2208 // Set up the argument vectors.
2209 SmallVector<Value*, 8> Args;
2210 SmallVector<unsigned, 8> ArgRegs;
2211 SmallVector<MVT, 8> ArgVTs;
2212 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2213 Args.reserve(I->getNumOperands());
2214 ArgRegs.reserve(I->getNumOperands());
2215 ArgVTs.reserve(I->getNumOperands());
2216 ArgFlags.reserve(I->getNumOperands());
2217 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2218 Value *Op = I->getOperand(i);
2219 unsigned Arg = getRegForValue(Op);
2220 if (Arg == 0) return false;
2222 Type *ArgTy = Op->getType();
2224 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2226 ISD::ArgFlagsTy Flags;
2227 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2228 Flags.setOrigAlign(OriginalAlignment);
2231 ArgRegs.push_back(Arg);
2232 ArgVTs.push_back(ArgVT);
2233 ArgFlags.push_back(Flags);
2236 // Handle the arguments now that we've gotten them.
2237 SmallVector<unsigned, 4> RegArgs;
2239 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2240 RegArgs, CC, NumBytes, false))
2243 unsigned CalleeReg = 0;
2244 if (EnableARMLongCalls) {
2245 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2246 if (CalleeReg == 0) return false;
2250 unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
2251 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2252 DL, TII.get(CallOpc));
2253 // BL / BLX don't take a predicate, but tBL / tBLX do.
2255 AddDefaultPred(MIB);
2256 if (EnableARMLongCalls)
2257 MIB.addReg(CalleeReg);
2259 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2261 // Add implicit physical register uses to the call.
2262 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2263 MIB.addReg(RegArgs[i], RegState::Implicit);
2265 // Add a register mask with the call-preserved registers.
2266 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2267 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2269 // Finish off the call including any return values.
2270 SmallVector<unsigned, 4> UsedRegs;
2271 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2273 // Set all unused physreg defs as dead.
2274 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2279 bool ARMFastISel::SelectCall(const Instruction *I,
2280 const char *IntrMemName = 0) {
2281 const CallInst *CI = cast<CallInst>(I);
2282 const Value *Callee = CI->getCalledValue();
2284 // Can't handle inline asm.
2285 if (isa<InlineAsm>(Callee)) return false;
2287 // Allow SelectionDAG isel to handle tail calls.
2288 if (CI->isTailCall()) return false;
2290 // Check the calling convention.
2291 ImmutableCallSite CS(CI);
2292 CallingConv::ID CC = CS.getCallingConv();
2294 // TODO: Avoid some calling conventions?
2296 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2297 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2298 bool isVarArg = FTy->isVarArg();
2300 // Handle *simple* calls for now.
2301 Type *RetTy = I->getType();
2303 if (RetTy->isVoidTy())
2304 RetVT = MVT::isVoid;
2305 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2306 RetVT != MVT::i8 && RetVT != MVT::i1)
2309 // Can't handle non-double multi-reg retvals.
2310 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2311 RetVT != MVT::i16 && RetVT != MVT::i32) {
2312 SmallVector<CCValAssign, 16> RVLocs;
2313 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2314 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2315 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2319 // Set up the argument vectors.
2320 SmallVector<Value*, 8> Args;
2321 SmallVector<unsigned, 8> ArgRegs;
2322 SmallVector<MVT, 8> ArgVTs;
2323 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2324 unsigned arg_size = CS.arg_size();
2325 Args.reserve(arg_size);
2326 ArgRegs.reserve(arg_size);
2327 ArgVTs.reserve(arg_size);
2328 ArgFlags.reserve(arg_size);
2329 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2331 // If we're lowering a memory intrinsic instead of a regular call, skip the
2332 // last two arguments, which shouldn't be passed to the underlying function.
2333 if (IntrMemName && e-i <= 2)
2336 ISD::ArgFlagsTy Flags;
2337 unsigned AttrInd = i - CS.arg_begin() + 1;
2338 if (CS.paramHasAttr(AttrInd, Attributes::SExt))
2340 if (CS.paramHasAttr(AttrInd, Attributes::ZExt))
2343 // FIXME: Only handle *easy* calls for now.
2344 if (CS.paramHasAttr(AttrInd, Attributes::InReg) ||
2345 CS.paramHasAttr(AttrInd, Attributes::StructRet) ||
2346 CS.paramHasAttr(AttrInd, Attributes::Nest) ||
2347 CS.paramHasAttr(AttrInd, Attributes::ByVal))
2350 Type *ArgTy = (*i)->getType();
2352 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2356 unsigned Arg = getRegForValue(*i);
2360 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2361 Flags.setOrigAlign(OriginalAlignment);
2364 ArgRegs.push_back(Arg);
2365 ArgVTs.push_back(ArgVT);
2366 ArgFlags.push_back(Flags);
2369 // Handle the arguments now that we've gotten them.
2370 SmallVector<unsigned, 4> RegArgs;
2372 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2373 RegArgs, CC, NumBytes, isVarArg))
2376 bool UseReg = false;
2377 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2378 if (!GV || EnableARMLongCalls) UseReg = true;
2380 unsigned CalleeReg = 0;
2383 CalleeReg = getLibcallReg(IntrMemName);
2385 CalleeReg = getRegForValue(Callee);
2387 if (CalleeReg == 0) return false;
2391 unsigned CallOpc = ARMSelectCallOp(UseReg);
2392 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2393 DL, TII.get(CallOpc));
2395 // ARM calls don't take a predicate, but tBL / tBLX do.
2397 AddDefaultPred(MIB);
2399 MIB.addReg(CalleeReg);
2400 else if (!IntrMemName)
2401 MIB.addGlobalAddress(GV, 0, 0);
2403 MIB.addExternalSymbol(IntrMemName, 0);
2405 // Add implicit physical register uses to the call.
2406 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2407 MIB.addReg(RegArgs[i], RegState::Implicit);
2409 // Add a register mask with the call-preserved registers.
2410 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2411 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2413 // Finish off the call including any return values.
2414 SmallVector<unsigned, 4> UsedRegs;
2415 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2418 // Set all unused physreg defs as dead.
2419 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2424 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2428 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2429 uint64_t Len, unsigned Alignment) {
2430 // Make sure we don't bloat code by inlining very large memcpy's.
2431 if (!ARMIsMemCpySmall(Len))
2436 if (!Alignment || Alignment >= 4) {
2442 assert (Len == 1 && "Expected a length of 1!");
2446 // Bound based on alignment.
2447 if (Len >= 2 && Alignment == 2)
2450 assert (Alignment == 1 && "Expected an alignment of 1!");
2457 RV = ARMEmitLoad(VT, ResultReg, Src);
2458 assert (RV == true && "Should be able to handle this load.");
2459 RV = ARMEmitStore(VT, ResultReg, Dest);
2460 assert (RV == true && "Should be able to handle this store.");
2463 unsigned Size = VT.getSizeInBits()/8;
2465 Dest.Offset += Size;
2472 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2473 // FIXME: Handle more intrinsics.
2474 switch (I.getIntrinsicID()) {
2475 default: return false;
2476 case Intrinsic::frameaddress: {
2477 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2478 MFI->setFrameAddressIsTaken(true);
2481 const TargetRegisterClass *RC;
2483 LdrOpc = ARM::t2LDRi12;
2484 RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2486 LdrOpc = ARM::LDRi12;
2487 RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2490 const ARMBaseRegisterInfo *RegInfo =
2491 static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
2492 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2493 unsigned SrcReg = FramePtr;
2495 // Recursively load frame address
2501 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2503 DestReg = createResultReg(RC);
2504 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2505 TII.get(LdrOpc), DestReg)
2506 .addReg(SrcReg).addImm(0));
2509 UpdateValueMap(&I, SrcReg);
2512 case Intrinsic::memcpy:
2513 case Intrinsic::memmove: {
2514 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2515 // Don't handle volatile.
2516 if (MTI.isVolatile())
2519 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2520 // we would emit dead code because we don't currently handle memmoves.
2521 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2522 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2523 // Small memcpy's are common enough that we want to do them without a call
2525 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2526 if (ARMIsMemCpySmall(Len)) {
2528 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2529 !ARMComputeAddress(MTI.getRawSource(), Src))
2531 unsigned Alignment = MTI.getAlignment();
2532 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2537 if (!MTI.getLength()->getType()->isIntegerTy(32))
2540 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2543 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2544 return SelectCall(&I, IntrMemName);
2546 case Intrinsic::memset: {
2547 const MemSetInst &MSI = cast<MemSetInst>(I);
2548 // Don't handle volatile.
2549 if (MSI.isVolatile())
2552 if (!MSI.getLength()->getType()->isIntegerTy(32))
2555 if (MSI.getDestAddressSpace() > 255)
2558 return SelectCall(&I, "memset");
2560 case Intrinsic::trap: {
2561 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::TRAP));
2567 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2568 // The high bits for a type smaller than the register size are assumed to be
2570 Value *Op = I->getOperand(0);
2573 SrcVT = TLI.getValueType(Op->getType(), true);
2574 DestVT = TLI.getValueType(I->getType(), true);
2576 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2578 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2581 unsigned SrcReg = getRegForValue(Op);
2582 if (!SrcReg) return false;
2584 // Because the high bits are undefined, a truncate doesn't generate
2586 UpdateValueMap(I, SrcReg);
2590 unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
2592 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2596 bool isBoolZext = false;
2597 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::i32);
2598 if (!SrcVT.isSimple()) return 0;
2599 switch (SrcVT.getSimpleVT().SimpleTy) {
2602 if (!Subtarget->hasV6Ops()) return 0;
2603 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
2605 Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
2607 Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
2610 if (!Subtarget->hasV6Ops()) return 0;
2611 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
2613 Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
2615 Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
2619 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
2620 Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
2627 unsigned ResultReg = createResultReg(RC);
2628 MachineInstrBuilder MIB;
2629 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
2635 AddOptionalDefs(MIB);
2639 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2640 // On ARM, in general, integer casts don't involve legal types; this code
2641 // handles promotable integers.
2642 Type *DestTy = I->getType();
2643 Value *Src = I->getOperand(0);
2644 Type *SrcTy = Src->getType();
2647 SrcVT = TLI.getValueType(SrcTy, true);
2648 DestVT = TLI.getValueType(DestTy, true);
2650 bool isZExt = isa<ZExtInst>(I);
2651 unsigned SrcReg = getRegForValue(Src);
2652 if (!SrcReg) return false;
2654 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2655 if (ResultReg == 0) return false;
2656 UpdateValueMap(I, ResultReg);
2660 bool ARMFastISel::SelectShift(const Instruction *I,
2661 ARM_AM::ShiftOpc ShiftTy) {
2662 // We handle thumb2 mode by target independent selector
2663 // or SelectionDAG ISel.
2667 // Only handle i32 now.
2668 EVT DestVT = TLI.getValueType(I->getType(), true);
2669 if (DestVT != MVT::i32)
2672 unsigned Opc = ARM::MOVsr;
2674 Value *Src2Value = I->getOperand(1);
2675 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2676 ShiftImm = CI->getZExtValue();
2678 // Fall back to selection DAG isel if the shift amount
2679 // is zero or greater than the width of the value type.
2680 if (ShiftImm == 0 || ShiftImm >=32)
2686 Value *Src1Value = I->getOperand(0);
2687 unsigned Reg1 = getRegForValue(Src1Value);
2688 if (Reg1 == 0) return false;
2691 if (Opc == ARM::MOVsr) {
2692 Reg2 = getRegForValue(Src2Value);
2693 if (Reg2 == 0) return false;
2696 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2697 if(ResultReg == 0) return false;
2699 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2700 TII.get(Opc), ResultReg)
2703 if (Opc == ARM::MOVsi)
2704 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2705 else if (Opc == ARM::MOVsr) {
2707 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2710 AddOptionalDefs(MIB);
2711 UpdateValueMap(I, ResultReg);
2715 // TODO: SoftFP support.
2716 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2718 switch (I->getOpcode()) {
2719 case Instruction::Load:
2720 return SelectLoad(I);
2721 case Instruction::Store:
2722 return SelectStore(I);
2723 case Instruction::Br:
2724 return SelectBranch(I);
2725 case Instruction::IndirectBr:
2726 return SelectIndirectBr(I);
2727 case Instruction::ICmp:
2728 case Instruction::FCmp:
2729 return SelectCmp(I);
2730 case Instruction::FPExt:
2731 return SelectFPExt(I);
2732 case Instruction::FPTrunc:
2733 return SelectFPTrunc(I);
2734 case Instruction::SIToFP:
2735 return SelectIToFP(I, /*isSigned*/ true);
2736 case Instruction::UIToFP:
2737 return SelectIToFP(I, /*isSigned*/ false);
2738 case Instruction::FPToSI:
2739 return SelectFPToI(I, /*isSigned*/ true);
2740 case Instruction::FPToUI:
2741 return SelectFPToI(I, /*isSigned*/ false);
2742 case Instruction::Add:
2743 return SelectBinaryIntOp(I, ISD::ADD);
2744 case Instruction::Or:
2745 return SelectBinaryIntOp(I, ISD::OR);
2746 case Instruction::Sub:
2747 return SelectBinaryIntOp(I, ISD::SUB);
2748 case Instruction::FAdd:
2749 return SelectBinaryFPOp(I, ISD::FADD);
2750 case Instruction::FSub:
2751 return SelectBinaryFPOp(I, ISD::FSUB);
2752 case Instruction::FMul:
2753 return SelectBinaryFPOp(I, ISD::FMUL);
2754 case Instruction::SDiv:
2755 return SelectDiv(I, /*isSigned*/ true);
2756 case Instruction::UDiv:
2757 return SelectDiv(I, /*isSigned*/ false);
2758 case Instruction::SRem:
2759 return SelectRem(I, /*isSigned*/ true);
2760 case Instruction::URem:
2761 return SelectRem(I, /*isSigned*/ false);
2762 case Instruction::Call:
2763 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2764 return SelectIntrinsicCall(*II);
2765 return SelectCall(I);
2766 case Instruction::Select:
2767 return SelectSelect(I);
2768 case Instruction::Ret:
2769 return SelectRet(I);
2770 case Instruction::Trunc:
2771 return SelectTrunc(I);
2772 case Instruction::ZExt:
2773 case Instruction::SExt:
2774 return SelectIntExt(I);
2775 case Instruction::Shl:
2776 return SelectShift(I, ARM_AM::lsl);
2777 case Instruction::LShr:
2778 return SelectShift(I, ARM_AM::lsr);
2779 case Instruction::AShr:
2780 return SelectShift(I, ARM_AM::asr);
2786 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
2787 /// vreg is being provided by the specified load instruction. If possible,
2788 /// try to fold the load as an operand to the instruction, returning true if
2790 bool ARMFastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
2791 const LoadInst *LI) {
2792 // Verify we have a legal type before going any further.
2794 if (!isLoadTypeLegal(LI->getType(), VT))
2797 // Combine load followed by zero- or sign-extend.
2798 // ldrb r1, [r0] ldrb r1, [r0]
2800 // mov r3, r2 mov r3, r1
2802 switch(MI->getOpcode()) {
2803 default: return false;
2821 // See if we can handle this address.
2823 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2825 unsigned ResultReg = MI->getOperand(0).getReg();
2826 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2828 MI->eraseFromParent();
2832 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2833 unsigned Align, EVT VT) {
2834 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2835 ARMConstantPoolConstant *CPV =
2836 ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2837 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
2840 unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
2843 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2844 TII.get(ARM::t2LDRpci), DestReg1)
2845 .addConstantPoolIndex(Idx));
2846 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
2848 // The extra immediate is for addrmode2.
2849 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2850 DL, TII.get(ARM::LDRcp), DestReg1)
2851 .addConstantPoolIndex(Idx).addImm(0));
2852 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
2855 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
2856 if (GlobalBaseReg == 0) {
2857 GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
2858 AFI->setGlobalBaseReg(GlobalBaseReg);
2861 unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
2862 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2863 DL, TII.get(Opc), DestReg2)
2865 .addReg(GlobalBaseReg);
2868 AddOptionalDefs(MIB);
2874 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
2875 const TargetLibraryInfo *libInfo) {
2876 // Completely untested on non-iOS.
2877 const TargetMachine &TM = funcInfo.MF->getTarget();
2879 // Darwin and thumb1 only for now.
2880 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2881 if (Subtarget->isTargetIOS() && !Subtarget->isThumb1Only())
2882 return new ARMFastISel(funcInfo, libInfo);