1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMRegisterInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/Analysis.h"
27 #include "llvm/CodeGen/FastISel.h"
28 #include "llvm/CodeGen/FunctionLoweringInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineConstantPool.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/Support/CallSite.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/GetElementPtrTypeIterator.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
46 EnableARMFastISel("arm-fast-isel",
47 cl::desc("Turn on experimental ARM fast-isel support"),
48 cl::init(false), cl::Hidden);
52 class ARMFastISel : public FastISel {
54 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
55 /// make the right decision when generating code for different targets.
56 const ARMSubtarget *Subtarget;
57 const TargetMachine &TM;
58 const TargetInstrInfo &TII;
59 const TargetLowering &TLI;
60 const ARMFunctionInfo *AFI;
62 // Convenience variable to avoid checking all the time.
66 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
68 TM(funcInfo.MF->getTarget()),
69 TII(*TM.getInstrInfo()),
70 TLI(*TM.getTargetLowering()) {
71 Subtarget = &TM.getSubtarget<ARMSubtarget>();
72 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
73 isThumb = AFI->isThumbFunction();
76 // Code from FastISel.cpp.
77 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
78 const TargetRegisterClass *RC);
79 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
80 const TargetRegisterClass *RC,
81 unsigned Op0, bool Op0IsKill);
82 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
83 const TargetRegisterClass *RC,
84 unsigned Op0, bool Op0IsKill,
85 unsigned Op1, bool Op1IsKill);
86 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
87 const TargetRegisterClass *RC,
88 unsigned Op0, bool Op0IsKill,
90 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
91 const TargetRegisterClass *RC,
92 unsigned Op0, bool Op0IsKill,
93 const ConstantFP *FPImm);
94 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
95 const TargetRegisterClass *RC,
97 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
98 const TargetRegisterClass *RC,
99 unsigned Op0, bool Op0IsKill,
100 unsigned Op1, bool Op1IsKill,
102 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
103 unsigned Op0, bool Op0IsKill,
106 // Backend specific FastISel code.
107 virtual bool TargetSelectInstruction(const Instruction *I);
108 virtual unsigned TargetMaterializeConstant(const Constant *C);
110 #include "ARMGenFastISel.inc"
112 // Instruction selection routines.
113 virtual bool ARMSelectLoad(const Instruction *I);
114 virtual bool ARMSelectStore(const Instruction *I);
115 virtual bool ARMSelectBranch(const Instruction *I);
116 virtual bool ARMSelectCmp(const Instruction *I);
117 virtual bool ARMSelectFPExt(const Instruction *I);
118 virtual bool ARMSelectFPTrunc(const Instruction *I);
119 virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
120 virtual bool ARMSelectSIToFP(const Instruction *I);
121 virtual bool ARMSelectFPToSI(const Instruction *I);
125 bool isTypeLegal(const Type *Ty, EVT &VT);
126 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
127 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
128 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
129 bool ARMLoadAlloca(const Instruction *I, EVT VT);
130 bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
131 bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
132 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
133 unsigned ARMMaterializeInt(const Constant *C);
134 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
135 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
137 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
138 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
141 } // end anonymous namespace
143 // #include "ARMGenCallingConv.inc"
145 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
146 // we don't care about implicit defs here, just places we'll need to add a
147 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
148 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
149 const TargetInstrDesc &TID = MI->getDesc();
150 if (!TID.hasOptionalDef())
153 // Look to see if our OptionalDef is defining CPSR or CCR.
154 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
155 const MachineOperand &MO = MI->getOperand(i);
156 if (!MO.isReg() || !MO.isDef()) continue;
157 if (MO.getReg() == ARM::CPSR)
163 // If the machine is predicable go ahead and add the predicate operands, if
164 // it needs default CC operands add those.
165 const MachineInstrBuilder &
166 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
167 MachineInstr *MI = &*MIB;
169 // Do we use a predicate?
170 if (TII.isPredicable(MI))
173 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
174 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
176 if (DefinesOptionalPredicate(MI, &CPSR)) {
185 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
186 const TargetRegisterClass* RC) {
187 unsigned ResultReg = createResultReg(RC);
188 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
190 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
194 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
195 const TargetRegisterClass *RC,
196 unsigned Op0, bool Op0IsKill) {
197 unsigned ResultReg = createResultReg(RC);
198 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
200 if (II.getNumDefs() >= 1)
201 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
202 .addReg(Op0, Op0IsKill * RegState::Kill));
204 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
205 .addReg(Op0, Op0IsKill * RegState::Kill));
206 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
207 TII.get(TargetOpcode::COPY), ResultReg)
208 .addReg(II.ImplicitDefs[0]));
213 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
214 const TargetRegisterClass *RC,
215 unsigned Op0, bool Op0IsKill,
216 unsigned Op1, bool Op1IsKill) {
217 unsigned ResultReg = createResultReg(RC);
218 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
220 if (II.getNumDefs() >= 1)
221 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
222 .addReg(Op0, Op0IsKill * RegState::Kill)
223 .addReg(Op1, Op1IsKill * RegState::Kill));
225 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
226 .addReg(Op0, Op0IsKill * RegState::Kill)
227 .addReg(Op1, Op1IsKill * RegState::Kill));
228 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
229 TII.get(TargetOpcode::COPY), ResultReg)
230 .addReg(II.ImplicitDefs[0]));
235 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
236 const TargetRegisterClass *RC,
237 unsigned Op0, bool Op0IsKill,
239 unsigned ResultReg = createResultReg(RC);
240 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
242 if (II.getNumDefs() >= 1)
243 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
244 .addReg(Op0, Op0IsKill * RegState::Kill)
247 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
248 .addReg(Op0, Op0IsKill * RegState::Kill)
250 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
251 TII.get(TargetOpcode::COPY), ResultReg)
252 .addReg(II.ImplicitDefs[0]));
257 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
258 const TargetRegisterClass *RC,
259 unsigned Op0, bool Op0IsKill,
260 const ConstantFP *FPImm) {
261 unsigned ResultReg = createResultReg(RC);
262 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
264 if (II.getNumDefs() >= 1)
265 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
266 .addReg(Op0, Op0IsKill * RegState::Kill)
269 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
270 .addReg(Op0, Op0IsKill * RegState::Kill)
272 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
273 TII.get(TargetOpcode::COPY), ResultReg)
274 .addReg(II.ImplicitDefs[0]));
279 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
280 const TargetRegisterClass *RC,
281 unsigned Op0, bool Op0IsKill,
282 unsigned Op1, bool Op1IsKill,
284 unsigned ResultReg = createResultReg(RC);
285 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
287 if (II.getNumDefs() >= 1)
288 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
289 .addReg(Op0, Op0IsKill * RegState::Kill)
290 .addReg(Op1, Op1IsKill * RegState::Kill)
293 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
294 .addReg(Op0, Op0IsKill * RegState::Kill)
295 .addReg(Op1, Op1IsKill * RegState::Kill)
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
298 TII.get(TargetOpcode::COPY), ResultReg)
299 .addReg(II.ImplicitDefs[0]));
304 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
305 const TargetRegisterClass *RC,
307 unsigned ResultReg = createResultReg(RC);
308 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
310 if (II.getNumDefs() >= 1)
311 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
314 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
316 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
317 TII.get(TargetOpcode::COPY), ResultReg)
318 .addReg(II.ImplicitDefs[0]));
323 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
324 unsigned Op0, bool Op0IsKill,
326 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
327 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
328 "Cannot yet extract from physregs");
329 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
330 DL, TII.get(TargetOpcode::COPY), ResultReg)
331 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
335 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
336 // Don't worry about 64-bit now.
337 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
339 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
340 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
341 TII.get(ARM::VMOVRS), MoveReg)
346 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
347 // Don't worry about 64-bit now.
348 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
350 // If we have a floating point constant we expect it in a floating point
352 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
353 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
354 TII.get(ARM::VMOVSR), MoveReg)
359 // For double width floating point we need to materialize two constants
360 // (the high and the low) into integer registers then use a move to get
361 // the combined constant into an FP reg.
362 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
363 const APFloat Val = CFP->getValueAPF();
364 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
366 // This checks to see if we can use VFP3 instructions to materialize
367 // a constant, otherwise we have to go through the constant pool.
368 if (TLI.isFPImmLegal(Val, VT)) {
369 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
370 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
371 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
377 // No 64-bit at the moment.
378 if (is64bit) return 0;
380 // Load this from the constant pool.
381 unsigned DestReg = ARMMaterializeInt(cast<Constant>(CFP));
383 // If we have a floating point constant we expect it in a floating point
385 return ARMMoveToFPReg(VT, DestReg);
388 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) {
389 // MachineConstantPool wants an explicit alignment.
390 unsigned Align = TD.getPrefTypeAlignment(C->getType());
392 // TODO: Figure out if this is correct.
393 Align = TD.getTypeAllocSize(C->getType());
395 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
397 unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
399 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
400 TII.get(ARM::t2LDRpci))
401 .addReg(DestReg).addConstantPoolIndex(Idx));
403 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
405 .addReg(DestReg).addConstantPoolIndex(Idx)
406 .addReg(0).addImm(0));
411 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
412 EVT VT = TLI.getValueType(C->getType(), true);
414 // Only handle simple types.
415 if (!VT.isSimple()) return 0;
417 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
418 return ARMMaterializeFP(CFP, VT);
419 return ARMMaterializeInt(C);
422 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
423 VT = TLI.getValueType(Ty, true);
425 // Only handle simple types.
426 if (VT == MVT::Other || !VT.isSimple()) return false;
428 // Handle all legal types, i.e. a register that will directly hold this
430 return TLI.isTypeLegal(VT);
433 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
434 if (isTypeLegal(Ty, VT)) return true;
436 // If this is a type than can be sign or zero-extended to a basic operation
437 // go ahead and accept it now.
438 if (VT == MVT::i8 || VT == MVT::i16)
444 // Computes the Reg+Offset to get to an object.
445 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
447 // Some boilerplate from the X86 FastISel.
448 const User *U = NULL;
449 unsigned Opcode = Instruction::UserOp1;
450 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
451 // Don't walk into other basic blocks; it's possible we haven't
452 // visited them yet, so the instructions may not yet be assigned
453 // virtual registers.
454 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
457 Opcode = I->getOpcode();
459 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
460 Opcode = C->getOpcode();
464 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
465 if (Ty->getAddressSpace() > 255)
466 // Fast instruction selection doesn't support the special
472 //errs() << "Failing Opcode is: " << *Op1 << "\n";
474 case Instruction::Alloca: {
475 assert(false && "Alloca should have been handled earlier!");
480 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
481 //errs() << "Failing GV is: " << GV << "\n";
486 // Try to get this in a register if nothing else has worked.
487 Reg = getRegForValue(Obj);
488 if (Reg == 0) return false;
490 // Since the offset may be too large for the load instruction
491 // get the reg+offset into a register.
492 // TODO: Verify the additions work, otherwise we'll need to add the
493 // offset instead of 0 to the instructions and do all sorts of operand
495 // TODO: Optimize this somewhat.
497 ARMCC::CondCodes Pred = ARMCC::AL;
498 unsigned PredReg = 0;
501 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
502 Reg, Reg, Offset, Pred, PredReg,
503 static_cast<const ARMBaseInstrInfo&>(TII));
505 assert(AFI->isThumb2Function());
506 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
507 Reg, Reg, Offset, Pred, PredReg,
508 static_cast<const ARMBaseInstrInfo&>(TII));
515 bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
516 Value *Op0 = I->getOperand(0);
518 // Verify it's an alloca.
519 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
520 DenseMap<const AllocaInst*, int>::iterator SI =
521 FuncInfo.StaticAllocaMap.find(AI);
523 if (SI != FuncInfo.StaticAllocaMap.end()) {
524 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
525 unsigned ResultReg = createResultReg(RC);
526 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
527 ResultReg, SI->second, RC,
528 TM.getRegisterInfo());
529 UpdateValueMap(I, ResultReg);
536 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
537 unsigned Reg, int Offset) {
539 assert(VT.isSimple() && "Non-simple types are invalid here!");
542 switch (VT.getSimpleVT().SimpleTy) {
544 assert(false && "Trying to emit for an unhandled type!");
547 Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
551 Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
555 Opc = isThumb ? ARM::tLDR : ARM::LDR;
559 ResultReg = createResultReg(TLI.getRegClassFor(VT));
561 // TODO: Fix the Addressing modes so that these can share some code.
562 // Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
564 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
565 TII.get(Opc), ResultReg)
566 .addReg(Reg).addImm(Offset).addReg(0));
568 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
569 TII.get(Opc), ResultReg)
570 .addReg(Reg).addReg(0).addImm(Offset));
574 bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
575 Value *Op1 = I->getOperand(1);
577 // Verify it's an alloca.
578 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
579 DenseMap<const AllocaInst*, int>::iterator SI =
580 FuncInfo.StaticAllocaMap.find(AI);
582 if (SI != FuncInfo.StaticAllocaMap.end()) {
583 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
584 assert(SrcReg != 0 && "Nothing to store!");
585 TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
586 SrcReg, true /*isKill*/, SI->second, RC,
587 TM.getRegisterInfo());
594 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
595 unsigned DstReg, int Offset) {
597 switch (VT.getSimpleVT().SimpleTy) {
598 default: return false;
600 case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break;
601 case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break;
602 case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break;
604 if (!Subtarget->hasVFP2()) return false;
608 if (!Subtarget->hasVFP2()) return false;
614 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
615 TII.get(StrOpc), SrcReg)
616 .addReg(DstReg).addImm(Offset).addReg(0));
618 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
619 TII.get(StrOpc), SrcReg)
620 .addReg(DstReg).addReg(0).addImm(Offset));
625 bool ARMFastISel::ARMSelectStore(const Instruction *I) {
626 Value *Op0 = I->getOperand(0);
629 // Yay type legalization
631 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
634 // Get the value to be stored into a register.
635 SrcReg = getRegForValue(Op0);
639 // If we're an alloca we know we have a frame index and can emit the store
641 if (ARMStoreAlloca(I, SrcReg, VT))
644 // Our register and offset with innocuous defaults.
648 // See if we can handle this as Reg + Offset
649 if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
652 if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
657 bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
658 // Verify we have a legal type before going any further.
660 if (!isLoadTypeLegal(I->getType(), VT))
663 // If we're an alloca we know we have a frame index and can emit the load
664 // directly in short order.
665 if (ARMLoadAlloca(I, VT))
668 // Our register and offset with innocuous defaults.
672 // See if we can handle this as Reg + Offset
673 if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
677 if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
679 UpdateValueMap(I, ResultReg);
683 bool ARMFastISel::ARMSelectBranch(const Instruction *I) {
684 const BranchInst *BI = cast<BranchInst>(I);
685 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
686 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
688 // Simple branch support.
689 unsigned CondReg = getRegForValue(BI->getCondition());
690 if (CondReg == 0) return false;
692 unsigned CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
693 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
694 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
695 .addReg(CondReg).addReg(CondReg));
696 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
697 .addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
698 FastEmitBranch(FBB, DL);
699 FuncInfo.MBB->addSuccessor(TBB);
703 bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
704 const CmpInst *CI = cast<CmpInst>(I);
707 const Type *Ty = CI->getOperand(0)->getType();
708 if (!isTypeLegal(Ty, VT))
711 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
712 if (isFloat && !Subtarget->hasVFP2())
716 switch (VT.getSimpleVT().SimpleTy) {
717 default: return false;
718 // TODO: Verify compares.
720 CmpOpc = ARM::VCMPES;
723 CmpOpc = ARM::VCMPED;
726 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
730 unsigned Arg1 = getRegForValue(CI->getOperand(0));
731 if (Arg1 == 0) return false;
733 unsigned Arg2 = getRegForValue(CI->getOperand(1));
734 if (Arg2 == 0) return false;
736 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
737 .addReg(Arg1).addReg(Arg2));
739 // For floating point we need to move the result to a register we can
740 // actually do something with.
742 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
743 TII.get(ARM::FMSTAT)));
745 // TODO: How to update the value map when there's no result reg?
749 bool ARMFastISel::ARMSelectFPExt(const Instruction *I) {
750 // Make sure we have VFP and that we're extending float to double.
751 if (!Subtarget->hasVFP2()) return false;
753 Value *V = I->getOperand(0);
754 if (!I->getType()->isDoubleTy() ||
755 !V->getType()->isFloatTy()) return false;
757 unsigned Op = getRegForValue(V);
758 if (Op == 0) return false;
760 unsigned Result = createResultReg(ARM::DPRRegisterClass);
762 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
763 TII.get(ARM::VCVTDS), Result)
765 UpdateValueMap(I, Result);
769 bool ARMFastISel::ARMSelectFPTrunc(const Instruction *I) {
770 // Make sure we have VFP and that we're truncating double to float.
771 if (!Subtarget->hasVFP2()) return false;
773 Value *V = I->getOperand(0);
774 if (!I->getType()->isFloatTy() ||
775 !V->getType()->isDoubleTy()) return false;
777 unsigned Op = getRegForValue(V);
778 if (Op == 0) return false;
780 unsigned Result = createResultReg(ARM::SPRRegisterClass);
782 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
783 TII.get(ARM::VCVTSD), Result)
785 UpdateValueMap(I, Result);
789 bool ARMFastISel::ARMSelectSIToFP(const Instruction *I) {
790 // Make sure we have VFP.
791 if (!Subtarget->hasVFP2()) return false;
794 const Type *Ty = I->getType();
795 if (!isTypeLegal(Ty, DstVT))
798 unsigned Op = getRegForValue(I->getOperand(0));
799 if (Op == 0) return false;
801 // The conversion routine works on fp-reg to fp-reg.
802 unsigned FP = ARMMoveToFPReg(DstVT, Op);
803 if (FP == 0) return false;
806 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
807 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
810 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
811 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
814 UpdateValueMap(I, ResultReg);
818 bool ARMFastISel::ARMSelectFPToSI(const Instruction *I) {
819 // Make sure we have VFP.
820 if (!Subtarget->hasVFP2()) return false;
823 const Type *RetTy = I->getType();
824 if (!isTypeLegal(RetTy, VT))
827 unsigned Op = getRegForValue(I->getOperand(0));
828 if (Op == 0) return false;
831 const Type *OpTy = I->getOperand(0)->getType();
832 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
833 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
835 EVT OpVT = TLI.getValueType(OpTy, true);
837 unsigned ResultReg = createResultReg(TLI.getRegClassFor(OpVT));
838 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
842 // This result needs to be in an integer register, but the conversion only
843 // takes place in fp-regs.
844 unsigned IntReg = ARMMoveToIntReg(VT, ResultReg);
845 if (IntReg == 0) return false;
847 UpdateValueMap(I, IntReg);
851 bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
852 EVT VT = TLI.getValueType(I->getType(), true);
854 // We can get here in the case when we want to use NEON for our fp
855 // operations, but can't figure out how to. Just use the vfp instructions
857 // FIXME: It'd be nice to use NEON instructions.
858 const Type *Ty = I->getType();
859 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
860 if (isFloat && !Subtarget->hasVFP2())
863 unsigned Op1 = getRegForValue(I->getOperand(0));
864 if (Op1 == 0) return false;
866 unsigned Op2 = getRegForValue(I->getOperand(1));
867 if (Op2 == 0) return false;
870 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
871 VT.getSimpleVT().SimpleTy == MVT::i64;
873 default: return false;
875 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
878 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
881 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
884 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
885 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
886 TII.get(Opc), ResultReg)
887 .addReg(Op1).addReg(Op2));
888 UpdateValueMap(I, ResultReg);
892 // TODO: SoftFP support.
893 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
894 // No Thumb-1 for now.
895 if (isThumb && !AFI->isThumb2Function()) return false;
897 switch (I->getOpcode()) {
898 case Instruction::Load:
899 return ARMSelectLoad(I);
900 case Instruction::Store:
901 return ARMSelectStore(I);
902 case Instruction::Br:
903 return ARMSelectBranch(I);
904 case Instruction::ICmp:
905 case Instruction::FCmp:
906 return ARMSelectCmp(I);
907 case Instruction::FPExt:
908 return ARMSelectFPExt(I);
909 case Instruction::FPTrunc:
910 return ARMSelectFPTrunc(I);
911 case Instruction::SIToFP:
912 return ARMSelectSIToFP(I);
913 case Instruction::FPToSI:
914 return ARMSelectFPToSI(I);
915 case Instruction::FAdd:
916 return ARMSelectBinaryOp(I, ISD::FADD);
917 case Instruction::FSub:
918 return ARMSelectBinaryOp(I, ISD::FSUB);
919 case Instruction::FMul:
920 return ARMSelectBinaryOp(I, ISD::FMUL);
927 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
928 if (EnableARMFastISel) return new ARMFastISel(funcInfo);