1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "ARMConstantPoolValue.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/IntrinsicInst.h"
29 #include "llvm/Module.h"
30 #include "llvm/Operator.h"
31 #include "llvm/CodeGen/Analysis.h"
32 #include "llvm/CodeGen/FastISel.h"
33 #include "llvm/CodeGen/FunctionLoweringInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineConstantPool.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineMemOperand.h"
39 #include "llvm/CodeGen/MachineRegisterInfo.h"
40 #include "llvm/Support/CallSite.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/GetElementPtrTypeIterator.h"
44 #include "llvm/Target/TargetData.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetLowering.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetOptions.h"
52 DisableARMFastISel("disable-arm-fast-isel",
53 cl::desc("Turn off experimental ARM fast-isel support"),
54 cl::init(false), cl::Hidden);
56 extern cl::opt<bool> EnableARMLongCalls;
60 // All possible address modes, plus some.
61 typedef struct Address {
74 // Innocuous defaults for our address.
76 : BaseType(RegBase), Offset(0) {
81 class ARMFastISel : public FastISel {
83 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
84 /// make the right decision when generating code for different targets.
85 const ARMSubtarget *Subtarget;
86 const TargetMachine &TM;
87 const TargetInstrInfo &TII;
88 const TargetLowering &TLI;
91 // Convenience variables to avoid some queries.
96 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
98 TM(funcInfo.MF->getTarget()),
99 TII(*TM.getInstrInfo()),
100 TLI(*TM.getTargetLowering()) {
101 Subtarget = &TM.getSubtarget<ARMSubtarget>();
102 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
103 isThumb2 = AFI->isThumbFunction();
104 Context = &funcInfo.Fn->getContext();
107 // Code from FastISel.cpp.
108 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
109 const TargetRegisterClass *RC);
110 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
111 const TargetRegisterClass *RC,
112 unsigned Op0, bool Op0IsKill);
113 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
114 const TargetRegisterClass *RC,
115 unsigned Op0, bool Op0IsKill,
116 unsigned Op1, bool Op1IsKill);
117 virtual unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
118 const TargetRegisterClass *RC,
119 unsigned Op0, bool Op0IsKill,
120 unsigned Op1, bool Op1IsKill,
121 unsigned Op2, bool Op2IsKill);
122 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
123 const TargetRegisterClass *RC,
124 unsigned Op0, bool Op0IsKill,
126 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
127 const TargetRegisterClass *RC,
128 unsigned Op0, bool Op0IsKill,
129 const ConstantFP *FPImm);
130 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
131 const TargetRegisterClass *RC,
132 unsigned Op0, bool Op0IsKill,
133 unsigned Op1, bool Op1IsKill,
135 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
136 const TargetRegisterClass *RC,
138 virtual unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
139 const TargetRegisterClass *RC,
140 uint64_t Imm1, uint64_t Imm2);
142 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
143 unsigned Op0, bool Op0IsKill,
146 // Backend specific FastISel code.
147 virtual bool TargetSelectInstruction(const Instruction *I);
148 virtual unsigned TargetMaterializeConstant(const Constant *C);
149 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
150 virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
153 #include "ARMGenFastISel.inc"
155 // Instruction selection routines.
157 bool SelectLoad(const Instruction *I);
158 bool SelectStore(const Instruction *I);
159 bool SelectBranch(const Instruction *I);
160 bool SelectCmp(const Instruction *I);
161 bool SelectFPExt(const Instruction *I);
162 bool SelectFPTrunc(const Instruction *I);
163 bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
164 bool SelectSIToFP(const Instruction *I);
165 bool SelectFPToSI(const Instruction *I);
166 bool SelectSDiv(const Instruction *I);
167 bool SelectSRem(const Instruction *I);
168 bool SelectCall(const Instruction *I, const char *IntrMemName);
169 bool SelectIntrinsicCall(const IntrinsicInst &I);
170 bool SelectSelect(const Instruction *I);
171 bool SelectRet(const Instruction *I);
172 bool SelectTrunc(const Instruction *I);
173 bool SelectIntExt(const Instruction *I);
177 bool isTypeLegal(Type *Ty, MVT &VT);
178 bool isLoadTypeLegal(Type *Ty, MVT &VT);
179 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
181 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, bool isZExt,
184 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
185 unsigned Alignment = 0);
186 bool ARMComputeAddress(const Value *Obj, Address &Addr);
187 void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
188 bool ARMIsMemCpySmall(uint64_t Len);
189 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len);
190 unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
191 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
192 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
193 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
194 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
195 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
196 unsigned ARMSelectCallOp(const GlobalValue *GV);
198 // Call handling routines.
200 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
201 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
202 SmallVectorImpl<unsigned> &ArgRegs,
203 SmallVectorImpl<MVT> &ArgVTs,
204 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
205 SmallVectorImpl<unsigned> &RegArgs,
208 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
209 const Instruction *I, CallingConv::ID CC,
211 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
213 // OptionalDef handling routines.
215 bool isARMNEONPred(const MachineInstr *MI);
216 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
217 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
218 void AddLoadStoreOperands(EVT VT, Address &Addr,
219 const MachineInstrBuilder &MIB,
220 unsigned Flags, bool useAM3);
223 } // end anonymous namespace
225 #include "ARMGenCallingConv.inc"
227 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
228 // we don't care about implicit defs here, just places we'll need to add a
229 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
230 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
231 if (!MI->hasOptionalDef())
234 // Look to see if our OptionalDef is defining CPSR or CCR.
235 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
236 const MachineOperand &MO = MI->getOperand(i);
237 if (!MO.isReg() || !MO.isDef()) continue;
238 if (MO.getReg() == ARM::CPSR)
244 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
245 const MCInstrDesc &MCID = MI->getDesc();
247 // If we're a thumb2 or not NEON function we were handled via isPredicable.
248 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
249 AFI->isThumb2Function())
252 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
253 if (MCID.OpInfo[i].isPredicate())
259 // If the machine is predicable go ahead and add the predicate operands, if
260 // it needs default CC operands add those.
261 // TODO: If we want to support thumb1 then we'll need to deal with optional
262 // CPSR defs that need to be added before the remaining operands. See s_cc_out
263 // for descriptions why.
264 const MachineInstrBuilder &
265 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
266 MachineInstr *MI = &*MIB;
268 // Do we use a predicate? or...
269 // Are we NEON in ARM mode and have a predicate operand? If so, I know
270 // we're not predicable but add it anyways.
271 if (TII.isPredicable(MI) || isARMNEONPred(MI))
274 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
275 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
277 if (DefinesOptionalPredicate(MI, &CPSR)) {
286 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
287 const TargetRegisterClass* RC) {
288 unsigned ResultReg = createResultReg(RC);
289 const MCInstrDesc &II = TII.get(MachineInstOpcode);
291 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
295 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
296 const TargetRegisterClass *RC,
297 unsigned Op0, bool Op0IsKill) {
298 unsigned ResultReg = createResultReg(RC);
299 const MCInstrDesc &II = TII.get(MachineInstOpcode);
301 if (II.getNumDefs() >= 1)
302 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
303 .addReg(Op0, Op0IsKill * RegState::Kill));
305 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
306 .addReg(Op0, Op0IsKill * RegState::Kill));
307 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
308 TII.get(TargetOpcode::COPY), ResultReg)
309 .addReg(II.ImplicitDefs[0]));
314 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
315 const TargetRegisterClass *RC,
316 unsigned Op0, bool Op0IsKill,
317 unsigned Op1, bool Op1IsKill) {
318 unsigned ResultReg = createResultReg(RC);
319 const MCInstrDesc &II = TII.get(MachineInstOpcode);
321 if (II.getNumDefs() >= 1)
322 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
323 .addReg(Op0, Op0IsKill * RegState::Kill)
324 .addReg(Op1, Op1IsKill * RegState::Kill));
326 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
327 .addReg(Op0, Op0IsKill * RegState::Kill)
328 .addReg(Op1, Op1IsKill * RegState::Kill));
329 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
330 TII.get(TargetOpcode::COPY), ResultReg)
331 .addReg(II.ImplicitDefs[0]));
336 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
337 const TargetRegisterClass *RC,
338 unsigned Op0, bool Op0IsKill,
339 unsigned Op1, bool Op1IsKill,
340 unsigned Op2, bool Op2IsKill) {
341 unsigned ResultReg = createResultReg(RC);
342 const MCInstrDesc &II = TII.get(MachineInstOpcode);
344 if (II.getNumDefs() >= 1)
345 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
346 .addReg(Op0, Op0IsKill * RegState::Kill)
347 .addReg(Op1, Op1IsKill * RegState::Kill)
348 .addReg(Op2, Op2IsKill * RegState::Kill));
350 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
351 .addReg(Op0, Op0IsKill * RegState::Kill)
352 .addReg(Op1, Op1IsKill * RegState::Kill)
353 .addReg(Op2, Op2IsKill * RegState::Kill));
354 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
355 TII.get(TargetOpcode::COPY), ResultReg)
356 .addReg(II.ImplicitDefs[0]));
361 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
362 const TargetRegisterClass *RC,
363 unsigned Op0, bool Op0IsKill,
365 unsigned ResultReg = createResultReg(RC);
366 const MCInstrDesc &II = TII.get(MachineInstOpcode);
368 if (II.getNumDefs() >= 1)
369 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
370 .addReg(Op0, Op0IsKill * RegState::Kill)
373 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
374 .addReg(Op0, Op0IsKill * RegState::Kill)
376 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
377 TII.get(TargetOpcode::COPY), ResultReg)
378 .addReg(II.ImplicitDefs[0]));
383 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
384 const TargetRegisterClass *RC,
385 unsigned Op0, bool Op0IsKill,
386 const ConstantFP *FPImm) {
387 unsigned ResultReg = createResultReg(RC);
388 const MCInstrDesc &II = TII.get(MachineInstOpcode);
390 if (II.getNumDefs() >= 1)
391 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
392 .addReg(Op0, Op0IsKill * RegState::Kill)
395 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
396 .addReg(Op0, Op0IsKill * RegState::Kill)
398 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
399 TII.get(TargetOpcode::COPY), ResultReg)
400 .addReg(II.ImplicitDefs[0]));
405 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
406 const TargetRegisterClass *RC,
407 unsigned Op0, bool Op0IsKill,
408 unsigned Op1, bool Op1IsKill,
410 unsigned ResultReg = createResultReg(RC);
411 const MCInstrDesc &II = TII.get(MachineInstOpcode);
413 if (II.getNumDefs() >= 1)
414 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
415 .addReg(Op0, Op0IsKill * RegState::Kill)
416 .addReg(Op1, Op1IsKill * RegState::Kill)
419 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
420 .addReg(Op0, Op0IsKill * RegState::Kill)
421 .addReg(Op1, Op1IsKill * RegState::Kill)
423 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
424 TII.get(TargetOpcode::COPY), ResultReg)
425 .addReg(II.ImplicitDefs[0]));
430 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
431 const TargetRegisterClass *RC,
433 unsigned ResultReg = createResultReg(RC);
434 const MCInstrDesc &II = TII.get(MachineInstOpcode);
436 if (II.getNumDefs() >= 1)
437 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
440 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
442 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
443 TII.get(TargetOpcode::COPY), ResultReg)
444 .addReg(II.ImplicitDefs[0]));
449 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
450 const TargetRegisterClass *RC,
451 uint64_t Imm1, uint64_t Imm2) {
452 unsigned ResultReg = createResultReg(RC);
453 const MCInstrDesc &II = TII.get(MachineInstOpcode);
455 if (II.getNumDefs() >= 1)
456 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
457 .addImm(Imm1).addImm(Imm2));
459 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
460 .addImm(Imm1).addImm(Imm2));
461 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
462 TII.get(TargetOpcode::COPY),
464 .addReg(II.ImplicitDefs[0]));
469 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
470 unsigned Op0, bool Op0IsKill,
472 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
473 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
474 "Cannot yet extract from physregs");
475 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
476 DL, TII.get(TargetOpcode::COPY), ResultReg)
477 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
481 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
482 // checks from the various callers.
483 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
484 if (VT == MVT::f64) return 0;
486 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
487 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
488 TII.get(ARM::VMOVRS), MoveReg)
493 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
494 if (VT == MVT::i64) return 0;
496 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
497 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
498 TII.get(ARM::VMOVSR), MoveReg)
503 // For double width floating point we need to materialize two constants
504 // (the high and the low) into integer registers then use a move to get
505 // the combined constant into an FP reg.
506 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
507 const APFloat Val = CFP->getValueAPF();
508 bool is64bit = VT == MVT::f64;
510 // This checks to see if we can use VFP3 instructions to materialize
511 // a constant, otherwise we have to go through the constant pool.
512 if (TLI.isFPImmLegal(Val, VT)) {
516 Imm = ARM_AM::getFP64Imm(Val);
519 Imm = ARM_AM::getFP32Imm(Val);
522 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
523 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
529 // Require VFP2 for loading fp constants.
530 if (!Subtarget->hasVFP2()) return false;
532 // MachineConstantPool wants an explicit alignment.
533 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
535 // TODO: Figure out if this is correct.
536 Align = TD.getTypeAllocSize(CFP->getType());
538 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
539 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
540 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
542 // The extra reg is for addrmode5.
543 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
545 .addConstantPoolIndex(Idx)
550 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
552 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
555 // If we can do this in a single instruction without a constant pool entry
557 const ConstantInt *CI = cast<ConstantInt>(C);
558 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
559 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
560 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
561 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
562 TII.get(Opc), ImmReg)
563 .addImm(CI->getZExtValue()));
567 // Use MVN to emit negative constants.
568 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
569 unsigned Imm = (unsigned)~(CI->getSExtValue());
570 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
571 (ARM_AM::getSOImmVal(Imm) != -1);
573 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
574 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
575 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
576 TII.get(Opc), ImmReg)
582 // Load from constant pool. For now 32-bit only.
586 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
588 // MachineConstantPool wants an explicit alignment.
589 unsigned Align = TD.getPrefTypeAlignment(C->getType());
591 // TODO: Figure out if this is correct.
592 Align = TD.getTypeAllocSize(C->getType());
594 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
597 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
598 TII.get(ARM::t2LDRpci), DestReg)
599 .addConstantPoolIndex(Idx));
601 // The extra immediate is for addrmode2.
602 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
603 TII.get(ARM::LDRcp), DestReg)
604 .addConstantPoolIndex(Idx)
610 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
611 // For now 32-bit only.
612 if (VT != MVT::i32) return 0;
614 Reloc::Model RelocM = TM.getRelocationModel();
616 // TODO: Need more magic for ARM PIC.
617 if (!isThumb2 && (RelocM == Reloc::PIC_)) return 0;
619 // MachineConstantPool wants an explicit alignment.
620 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
622 // TODO: Figure out if this is correct.
623 Align = TD.getTypeAllocSize(GV->getType());
627 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
628 unsigned Id = AFI->createPICLabelUId();
629 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
632 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
635 MachineInstrBuilder MIB;
636 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
638 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
639 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
640 .addConstantPoolIndex(Idx);
641 if (RelocM == Reloc::PIC_)
644 // The extra immediate is for addrmode2.
645 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
647 .addConstantPoolIndex(Idx)
650 AddOptionalDefs(MIB);
652 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
653 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
655 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
656 TII.get(ARM::t2LDRi12), NewDestReg)
660 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
664 DestReg = NewDestReg;
665 AddOptionalDefs(MIB);
671 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
672 EVT VT = TLI.getValueType(C->getType(), true);
674 // Only handle simple types.
675 if (!VT.isSimple()) return 0;
677 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
678 return ARMMaterializeFP(CFP, VT);
679 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
680 return ARMMaterializeGV(GV, VT);
681 else if (isa<ConstantInt>(C))
682 return ARMMaterializeInt(C, VT);
687 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
689 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
690 // Don't handle dynamic allocas.
691 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
694 if (!isLoadTypeLegal(AI->getType(), VT)) return false;
696 DenseMap<const AllocaInst*, int>::iterator SI =
697 FuncInfo.StaticAllocaMap.find(AI);
699 // This will get lowered later into the correct offsets and registers
700 // via rewriteXFrameIndex.
701 if (SI != FuncInfo.StaticAllocaMap.end()) {
702 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
703 unsigned ResultReg = createResultReg(RC);
704 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
705 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
706 TII.get(Opc), ResultReg)
707 .addFrameIndex(SI->second)
715 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
716 EVT evt = TLI.getValueType(Ty, true);
718 // Only handle simple types.
719 if (evt == MVT::Other || !evt.isSimple()) return false;
720 VT = evt.getSimpleVT();
722 // Handle all legal types, i.e. a register that will directly hold this
724 return TLI.isTypeLegal(VT);
727 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
728 if (isTypeLegal(Ty, VT)) return true;
730 // If this is a type than can be sign or zero-extended to a basic operation
731 // go ahead and accept it now.
732 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
738 // Computes the address to get to an object.
739 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
740 // Some boilerplate from the X86 FastISel.
741 const User *U = NULL;
742 unsigned Opcode = Instruction::UserOp1;
743 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
744 // Don't walk into other basic blocks unless the object is an alloca from
745 // another block, otherwise it may not have a virtual register assigned.
746 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
747 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
748 Opcode = I->getOpcode();
751 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
752 Opcode = C->getOpcode();
756 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
757 if (Ty->getAddressSpace() > 255)
758 // Fast instruction selection doesn't support the special
765 case Instruction::BitCast: {
766 // Look through bitcasts.
767 return ARMComputeAddress(U->getOperand(0), Addr);
769 case Instruction::IntToPtr: {
770 // Look past no-op inttoptrs.
771 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
772 return ARMComputeAddress(U->getOperand(0), Addr);
775 case Instruction::PtrToInt: {
776 // Look past no-op ptrtoints.
777 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
778 return ARMComputeAddress(U->getOperand(0), Addr);
781 case Instruction::GetElementPtr: {
782 Address SavedAddr = Addr;
783 int TmpOffset = Addr.Offset;
785 // Iterate through the GEP folding the constants into offsets where
787 gep_type_iterator GTI = gep_type_begin(U);
788 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
789 i != e; ++i, ++GTI) {
790 const Value *Op = *i;
791 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
792 const StructLayout *SL = TD.getStructLayout(STy);
793 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
794 TmpOffset += SL->getElementOffset(Idx);
796 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
798 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
799 // Constant-offset addressing.
800 TmpOffset += CI->getSExtValue() * S;
803 if (isa<AddOperator>(Op) &&
804 (!isa<Instruction>(Op) ||
805 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
807 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
808 // An add (in the same block) with a constant operand. Fold the
811 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
812 TmpOffset += CI->getSExtValue() * S;
813 // Iterate on the other operand.
814 Op = cast<AddOperator>(Op)->getOperand(0);
818 goto unsupported_gep;
823 // Try to grab the base operand now.
824 Addr.Offset = TmpOffset;
825 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
827 // We failed, restore everything and try the other options.
833 case Instruction::Alloca: {
834 const AllocaInst *AI = cast<AllocaInst>(Obj);
835 DenseMap<const AllocaInst*, int>::iterator SI =
836 FuncInfo.StaticAllocaMap.find(AI);
837 if (SI != FuncInfo.StaticAllocaMap.end()) {
838 Addr.BaseType = Address::FrameIndexBase;
839 Addr.Base.FI = SI->second;
846 // Materialize the global variable's address into a reg which can
847 // then be used later to load the variable.
848 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
849 unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
850 if (Tmp == 0) return false;
856 // Try to get this in a register if nothing else has worked.
857 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
858 return Addr.Base.Reg != 0;
861 void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) {
863 assert(VT.isSimple() && "Non-simple types are invalid here!");
865 bool needsLowering = false;
866 switch (VT.getSimpleVT().SimpleTy) {
868 assert(false && "Unhandled load/store type!");
875 // Integer loads/stores handle 12-bit offsets.
876 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
877 // Handle negative offsets.
878 if (needsLowering && isThumb2)
879 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
882 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
883 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
888 // Floating point operands handle 8-bit offsets.
889 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
893 // If this is a stack pointer and the offset needs to be simplified then
894 // put the alloca address into a register, set the base type back to
895 // register and continue. This should almost never happen.
896 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
897 TargetRegisterClass *RC = isThumb2 ? ARM::tGPRRegisterClass :
898 ARM::GPRRegisterClass;
899 unsigned ResultReg = createResultReg(RC);
900 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
901 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
902 TII.get(Opc), ResultReg)
903 .addFrameIndex(Addr.Base.FI)
905 Addr.Base.Reg = ResultReg;
906 Addr.BaseType = Address::RegBase;
909 // Since the offset is too large for the load/store instruction
910 // get the reg+offset into a register.
912 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
913 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
918 void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
919 const MachineInstrBuilder &MIB,
920 unsigned Flags, bool useAM3) {
921 // addrmode5 output depends on the selection dag addressing dividing the
922 // offset by 4 that it then later multiplies. Do this here as well.
923 if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
924 VT.getSimpleVT().SimpleTy == MVT::f64)
927 // Frame base works a bit differently. Handle it separately.
928 if (Addr.BaseType == Address::FrameIndexBase) {
929 int FI = Addr.Base.FI;
930 int Offset = Addr.Offset;
931 MachineMemOperand *MMO =
932 FuncInfo.MF->getMachineMemOperand(
933 MachinePointerInfo::getFixedStack(FI, Offset),
935 MFI.getObjectSize(FI),
936 MFI.getObjectAlignment(FI));
937 // Now add the rest of the operands.
938 MIB.addFrameIndex(FI);
940 // ARM halfword load/stores and signed byte loads need an additional
943 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
947 MIB.addImm(Addr.Offset);
949 MIB.addMemOperand(MMO);
951 // Now add the rest of the operands.
952 MIB.addReg(Addr.Base.Reg);
954 // ARM halfword load/stores and signed byte loads need an additional
957 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
961 MIB.addImm(Addr.Offset);
964 AddOptionalDefs(MIB);
967 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
968 bool isZExt = true, bool allocReg = true) {
969 assert(VT.isSimple() && "Non-simple types are invalid here!");
972 TargetRegisterClass *RC;
973 switch (VT.getSimpleVT().SimpleTy) {
974 // This is mostly going to be Neon/vector support.
975 default: return false;
979 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
980 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
982 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
991 RC = ARM::GPRRegisterClass;
995 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
996 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
998 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1000 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1003 RC = ARM::GPRRegisterClass;
1007 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1010 Opc = ARM::t2LDRi12;
1014 RC = ARM::GPRRegisterClass;
1018 RC = TLI.getRegClassFor(VT);
1022 RC = TLI.getRegClassFor(VT);
1025 // Simplify this down to something we can handle.
1026 ARMSimplifyAddress(Addr, VT, useAM3);
1028 // Create the base instruction, then add the operands.
1030 ResultReg = createResultReg(RC);
1031 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1032 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1033 TII.get(Opc), ResultReg);
1034 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1038 bool ARMFastISel::SelectLoad(const Instruction *I) {
1039 // Atomic loads need special handling.
1040 if (cast<LoadInst>(I)->isAtomic())
1043 // Verify we have a legal type before going any further.
1045 if (!isLoadTypeLegal(I->getType(), VT))
1048 // See if we can handle this address.
1050 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1053 if (!ARMEmitLoad(VT, ResultReg, Addr)) return false;
1054 UpdateValueMap(I, ResultReg);
1058 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
1059 unsigned Alignment) {
1061 bool useAM3 = false;
1062 switch (VT.getSimpleVT().SimpleTy) {
1063 // This is mostly going to be Neon/vector support.
1064 default: return false;
1066 unsigned Res = createResultReg(isThumb2 ? ARM::tGPRRegisterClass :
1067 ARM::GPRRegisterClass);
1068 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1069 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1071 .addReg(SrcReg).addImm(1));
1073 } // Fallthrough here.
1076 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1077 StrOpc = ARM::t2STRBi8;
1079 StrOpc = ARM::t2STRBi12;
1081 StrOpc = ARM::STRBi12;
1086 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1087 StrOpc = ARM::t2STRHi8;
1089 StrOpc = ARM::t2STRHi12;
1097 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1098 StrOpc = ARM::t2STRi8;
1100 StrOpc = ARM::t2STRi12;
1102 StrOpc = ARM::STRi12;
1106 if (!Subtarget->hasVFP2()) return false;
1107 StrOpc = ARM::VSTRS;
1108 // Unaligned stores need special handling. Floats require word-alignment.
1109 if (Alignment && Alignment < 4) {
1110 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1111 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1112 TII.get(ARM::VMOVRS), MoveReg)
1116 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1120 if (!Subtarget->hasVFP2()) return false;
1121 // FIXME: Unaligned stores need special handling. Doublewords require
1123 if (Alignment && Alignment < 4) {
1126 StrOpc = ARM::VSTRD;
1129 // Simplify this down to something we can handle.
1130 ARMSimplifyAddress(Addr, VT, useAM3);
1132 // Create the base instruction, then add the operands.
1133 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1136 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1140 bool ARMFastISel::SelectStore(const Instruction *I) {
1141 Value *Op0 = I->getOperand(0);
1142 unsigned SrcReg = 0;
1144 // Atomic stores need special handling.
1145 if (cast<StoreInst>(I)->isAtomic())
1148 // Verify we have a legal type before going any further.
1150 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1153 // Get the value to be stored into a register.
1154 SrcReg = getRegForValue(Op0);
1155 if (SrcReg == 0) return false;
1157 // See if we can handle this address.
1159 if (!ARMComputeAddress(I->getOperand(1), Addr))
1162 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1167 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1169 // Needs two compares...
1170 case CmpInst::FCMP_ONE:
1171 case CmpInst::FCMP_UEQ:
1173 // AL is our "false" for now. The other two need more compares.
1175 case CmpInst::ICMP_EQ:
1176 case CmpInst::FCMP_OEQ:
1178 case CmpInst::ICMP_SGT:
1179 case CmpInst::FCMP_OGT:
1181 case CmpInst::ICMP_SGE:
1182 case CmpInst::FCMP_OGE:
1184 case CmpInst::ICMP_UGT:
1185 case CmpInst::FCMP_UGT:
1187 case CmpInst::FCMP_OLT:
1189 case CmpInst::ICMP_ULE:
1190 case CmpInst::FCMP_OLE:
1192 case CmpInst::FCMP_ORD:
1194 case CmpInst::FCMP_UNO:
1196 case CmpInst::FCMP_UGE:
1198 case CmpInst::ICMP_SLT:
1199 case CmpInst::FCMP_ULT:
1201 case CmpInst::ICMP_SLE:
1202 case CmpInst::FCMP_ULE:
1204 case CmpInst::FCMP_UNE:
1205 case CmpInst::ICMP_NE:
1207 case CmpInst::ICMP_UGE:
1209 case CmpInst::ICMP_ULT:
1214 bool ARMFastISel::SelectBranch(const Instruction *I) {
1215 const BranchInst *BI = cast<BranchInst>(I);
1216 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1217 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1219 // Simple branch support.
1221 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1223 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1224 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1226 // Get the compare predicate.
1227 // Try to take advantage of fallthrough opportunities.
1228 CmpInst::Predicate Predicate = CI->getPredicate();
1229 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1230 std::swap(TBB, FBB);
1231 Predicate = CmpInst::getInversePredicate(Predicate);
1234 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1236 // We may not handle every CC for now.
1237 if (ARMPred == ARMCC::AL) return false;
1239 // Emit the compare.
1240 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1243 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1244 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1245 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1246 FastEmitBranch(FBB, DL);
1247 FuncInfo.MBB->addSuccessor(TBB);
1250 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1252 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1253 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1254 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1255 unsigned OpReg = getRegForValue(TI->getOperand(0));
1256 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1258 .addReg(OpReg).addImm(1));
1260 unsigned CCMode = ARMCC::NE;
1261 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1262 std::swap(TBB, FBB);
1266 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1267 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1268 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1270 FastEmitBranch(FBB, DL);
1271 FuncInfo.MBB->addSuccessor(TBB);
1274 } else if (const ConstantInt *CI =
1275 dyn_cast<ConstantInt>(BI->getCondition())) {
1276 uint64_t Imm = CI->getZExtValue();
1277 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1278 FastEmitBranch(Target, DL);
1282 unsigned CmpReg = getRegForValue(BI->getCondition());
1283 if (CmpReg == 0) return false;
1285 // We've been divorced from our compare! Our block was split, and
1286 // now our compare lives in a predecessor block. We musn't
1287 // re-compare here, as the children of the compare aren't guaranteed
1288 // live across the block boundary (we *could* check for this).
1289 // Regardless, the compare has been done in the predecessor block,
1290 // and it left a value for us in a virtual register. Ergo, we test
1291 // the one-bit value left in the virtual register.
1292 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1293 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1294 .addReg(CmpReg).addImm(1));
1296 unsigned CCMode = ARMCC::NE;
1297 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1298 std::swap(TBB, FBB);
1302 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1303 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1304 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1305 FastEmitBranch(FBB, DL);
1306 FuncInfo.MBB->addSuccessor(TBB);
1310 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1312 Type *Ty = Src1Value->getType();
1313 EVT SrcVT = TLI.getValueType(Ty, true);
1314 if (!SrcVT.isSimple()) return false;
1316 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1317 if (isFloat && !Subtarget->hasVFP2())
1320 // Check to see if the 2nd operand is a constant that we can encode directly
1323 bool UseImm = false;
1324 bool isNegativeImm = false;
1325 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1326 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1327 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1328 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1330 const APInt &CIVal = ConstInt->getValue();
1331 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1333 isNegativeImm = true;
1336 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1337 (ARM_AM::getSOImmVal(Imm) != -1);
1339 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1340 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1341 if (ConstFP->isZero() && !ConstFP->isNegative())
1347 bool needsExt = false;
1348 switch (SrcVT.getSimpleVT().SimpleTy) {
1349 default: return false;
1350 // TODO: Verify compares.
1353 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1357 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1363 // Intentional fall-through.
1367 CmpOpc = ARM::t2CMPrr;
1369 CmpOpc = isNegativeImm ? ARM::t2CMNzri : ARM::t2CMPri;
1372 CmpOpc = ARM::CMPrr;
1374 CmpOpc = isNegativeImm ? ARM::CMNzri : ARM::CMPri;
1379 unsigned SrcReg1 = getRegForValue(Src1Value);
1380 if (SrcReg1 == 0) return false;
1382 unsigned SrcReg2 = 0;
1384 SrcReg2 = getRegForValue(Src2Value);
1385 if (SrcReg2 == 0) return false;
1388 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1391 ResultReg = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1392 if (ResultReg == 0) return false;
1393 SrcReg1 = ResultReg;
1395 ResultReg = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1396 if (ResultReg == 0) return false;
1397 SrcReg2 = ResultReg;
1402 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1404 .addReg(SrcReg1).addReg(SrcReg2));
1406 MachineInstrBuilder MIB;
1407 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1410 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1413 AddOptionalDefs(MIB);
1416 // For floating point we need to move the result to a comparison register
1417 // that we can then use for branches.
1418 if (Ty->isFloatTy() || Ty->isDoubleTy())
1419 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1420 TII.get(ARM::FMSTAT)));
1424 bool ARMFastISel::SelectCmp(const Instruction *I) {
1425 const CmpInst *CI = cast<CmpInst>(I);
1426 Type *Ty = CI->getOperand(0)->getType();
1428 // Get the compare predicate.
1429 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1431 // We may not handle every CC for now.
1432 if (ARMPred == ARMCC::AL) return false;
1434 // Emit the compare.
1435 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1438 // Now set a register based on the comparison. Explicitly set the predicates
1440 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1441 TargetRegisterClass *RC = isThumb2 ? ARM::rGPRRegisterClass
1442 : ARM::GPRRegisterClass;
1443 unsigned DestReg = createResultReg(RC);
1444 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1445 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1446 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1447 unsigned CondReg = isFloat ? ARM::FPSCR : ARM::CPSR;
1448 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1449 .addReg(ZeroReg).addImm(1)
1450 .addImm(ARMPred).addReg(CondReg);
1452 UpdateValueMap(I, DestReg);
1456 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1457 // Make sure we have VFP and that we're extending float to double.
1458 if (!Subtarget->hasVFP2()) return false;
1460 Value *V = I->getOperand(0);
1461 if (!I->getType()->isDoubleTy() ||
1462 !V->getType()->isFloatTy()) return false;
1464 unsigned Op = getRegForValue(V);
1465 if (Op == 0) return false;
1467 unsigned Result = createResultReg(ARM::DPRRegisterClass);
1468 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1469 TII.get(ARM::VCVTDS), Result)
1471 UpdateValueMap(I, Result);
1475 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1476 // Make sure we have VFP and that we're truncating double to float.
1477 if (!Subtarget->hasVFP2()) return false;
1479 Value *V = I->getOperand(0);
1480 if (!(I->getType()->isFloatTy() &&
1481 V->getType()->isDoubleTy())) return false;
1483 unsigned Op = getRegForValue(V);
1484 if (Op == 0) return false;
1486 unsigned Result = createResultReg(ARM::SPRRegisterClass);
1487 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1488 TII.get(ARM::VCVTSD), Result)
1490 UpdateValueMap(I, Result);
1494 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1495 // Make sure we have VFP.
1496 if (!Subtarget->hasVFP2()) return false;
1499 Type *Ty = I->getType();
1500 if (!isTypeLegal(Ty, DstVT))
1503 Value *Src = I->getOperand(0);
1504 EVT SrcVT = TLI.getValueType(Src->getType(), true);
1505 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1508 unsigned SrcReg = getRegForValue(Src);
1509 if (SrcReg == 0) return false;
1511 // Handle sign-extension.
1512 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1513 EVT DestVT = MVT::i32;
1514 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, /*isZExt*/ false);
1515 if (ResultReg == 0) return false;
1519 // The conversion routine works on fp-reg to fp-reg and the operand above
1520 // was an integer, move it to the fp registers if possible.
1521 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1522 if (FP == 0) return false;
1525 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1526 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1529 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1530 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1533 UpdateValueMap(I, ResultReg);
1537 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1538 // Make sure we have VFP.
1539 if (!Subtarget->hasVFP2()) return false;
1542 Type *RetTy = I->getType();
1543 if (!isTypeLegal(RetTy, DstVT))
1546 unsigned Op = getRegForValue(I->getOperand(0));
1547 if (Op == 0) return false;
1550 Type *OpTy = I->getOperand(0)->getType();
1551 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1552 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1555 // f64->s32 or f32->s32 both need an intermediate f32 reg.
1556 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1557 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1561 // This result needs to be in an integer register, but the conversion only
1562 // takes place in fp-regs.
1563 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1564 if (IntReg == 0) return false;
1566 UpdateValueMap(I, IntReg);
1570 bool ARMFastISel::SelectSelect(const Instruction *I) {
1572 if (!isTypeLegal(I->getType(), VT))
1575 // Things need to be register sized for register moves.
1576 if (VT != MVT::i32) return false;
1577 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1579 unsigned CondReg = getRegForValue(I->getOperand(0));
1580 if (CondReg == 0) return false;
1581 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1582 if (Op1Reg == 0) return false;
1584 // Check to see if we can use an immediate in the conditional move.
1586 bool UseImm = false;
1587 bool isNegativeImm = false;
1588 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1589 assert (VT == MVT::i32 && "Expecting an i32.");
1590 Imm = (int)ConstInt->getValue().getZExtValue();
1592 isNegativeImm = true;
1595 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1596 (ARM_AM::getSOImmVal(Imm) != -1);
1599 unsigned Op2Reg = 0;
1601 Op2Reg = getRegForValue(I->getOperand(2));
1602 if (Op2Reg == 0) return false;
1605 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1606 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1607 .addReg(CondReg).addImm(0));
1611 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1613 if (!isNegativeImm) {
1614 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1616 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1619 unsigned ResultReg = createResultReg(RC);
1621 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1622 .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1624 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1625 .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1626 UpdateValueMap(I, ResultReg);
1630 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1632 Type *Ty = I->getType();
1633 if (!isTypeLegal(Ty, VT))
1636 // If we have integer div support we should have selected this automagically.
1637 // In case we have a real miss go ahead and return false and we'll pick
1639 if (Subtarget->hasDivide()) return false;
1641 // Otherwise emit a libcall.
1642 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1644 LC = RTLIB::SDIV_I8;
1645 else if (VT == MVT::i16)
1646 LC = RTLIB::SDIV_I16;
1647 else if (VT == MVT::i32)
1648 LC = RTLIB::SDIV_I32;
1649 else if (VT == MVT::i64)
1650 LC = RTLIB::SDIV_I64;
1651 else if (VT == MVT::i128)
1652 LC = RTLIB::SDIV_I128;
1653 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1655 return ARMEmitLibcall(I, LC);
1658 bool ARMFastISel::SelectSRem(const Instruction *I) {
1660 Type *Ty = I->getType();
1661 if (!isTypeLegal(Ty, VT))
1664 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1666 LC = RTLIB::SREM_I8;
1667 else if (VT == MVT::i16)
1668 LC = RTLIB::SREM_I16;
1669 else if (VT == MVT::i32)
1670 LC = RTLIB::SREM_I32;
1671 else if (VT == MVT::i64)
1672 LC = RTLIB::SREM_I64;
1673 else if (VT == MVT::i128)
1674 LC = RTLIB::SREM_I128;
1675 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1677 return ARMEmitLibcall(I, LC);
1680 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1681 EVT VT = TLI.getValueType(I->getType(), true);
1683 // We can get here in the case when we want to use NEON for our fp
1684 // operations, but can't figure out how to. Just use the vfp instructions
1686 // FIXME: It'd be nice to use NEON instructions.
1687 Type *Ty = I->getType();
1688 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1689 if (isFloat && !Subtarget->hasVFP2())
1693 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1694 switch (ISDOpcode) {
1695 default: return false;
1697 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1700 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1703 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1706 unsigned Op1 = getRegForValue(I->getOperand(0));
1707 if (Op1 == 0) return false;
1709 unsigned Op2 = getRegForValue(I->getOperand(1));
1710 if (Op2 == 0) return false;
1712 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1713 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1714 TII.get(Opc), ResultReg)
1715 .addReg(Op1).addReg(Op2));
1716 UpdateValueMap(I, ResultReg);
1720 // Call Handling Code
1722 // This is largely taken directly from CCAssignFnForNode - we don't support
1723 // varargs in FastISel so that part has been removed.
1724 // TODO: We may not support all of this.
1725 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1728 llvm_unreachable("Unsupported calling convention");
1729 case CallingConv::Fast:
1730 // Ignore fastcc. Silence compiler warnings.
1731 (void)RetFastCC_ARM_APCS;
1732 (void)FastCC_ARM_APCS;
1734 case CallingConv::C:
1735 // Use target triple & subtarget features to do actual dispatch.
1736 if (Subtarget->isAAPCS_ABI()) {
1737 if (Subtarget->hasVFP2() &&
1738 TM.Options.FloatABIType == FloatABI::Hard)
1739 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1741 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1743 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1744 case CallingConv::ARM_AAPCS_VFP:
1745 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1746 case CallingConv::ARM_AAPCS:
1747 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1748 case CallingConv::ARM_APCS:
1749 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1753 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1754 SmallVectorImpl<unsigned> &ArgRegs,
1755 SmallVectorImpl<MVT> &ArgVTs,
1756 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1757 SmallVectorImpl<unsigned> &RegArgs,
1759 unsigned &NumBytes) {
1760 SmallVector<CCValAssign, 16> ArgLocs;
1761 CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1762 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1764 // Get a count of how many bytes are to be pushed on the stack.
1765 NumBytes = CCInfo.getNextStackOffset();
1767 // Issue CALLSEQ_START
1768 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1769 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1770 TII.get(AdjStackDown))
1773 // Process the args.
1774 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1775 CCValAssign &VA = ArgLocs[i];
1776 unsigned Arg = ArgRegs[VA.getValNo()];
1777 MVT ArgVT = ArgVTs[VA.getValNo()];
1779 // We don't handle NEON/vector parameters yet.
1780 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1783 // Handle arg promotion, etc.
1784 switch (VA.getLocInfo()) {
1785 case CCValAssign::Full: break;
1786 case CCValAssign::SExt: {
1787 MVT DestVT = VA.getLocVT();
1788 unsigned ResultReg = ARMEmitIntExt(ArgVT, Arg, DestVT,
1790 assert (ResultReg != 0 && "Failed to emit a sext");
1795 case CCValAssign::AExt:
1796 // Intentional fall-through. Handle AExt and ZExt.
1797 case CCValAssign::ZExt: {
1798 MVT DestVT = VA.getLocVT();
1799 unsigned ResultReg = ARMEmitIntExt(ArgVT, Arg, DestVT,
1801 assert (ResultReg != 0 && "Failed to emit a sext");
1806 case CCValAssign::BCvt: {
1807 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1808 /*TODO: Kill=*/false);
1809 assert(BC != 0 && "Failed to emit a bitcast!");
1811 ArgVT = VA.getLocVT();
1814 default: llvm_unreachable("Unknown arg promotion!");
1817 // Now copy/store arg to correct locations.
1818 if (VA.isRegLoc() && !VA.needsCustom()) {
1819 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1822 RegArgs.push_back(VA.getLocReg());
1823 } else if (VA.needsCustom()) {
1824 // TODO: We need custom lowering for vector (v2f64) args.
1825 if (VA.getLocVT() != MVT::f64) return false;
1827 CCValAssign &NextVA = ArgLocs[++i];
1829 // TODO: Only handle register args for now.
1830 if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1832 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1833 TII.get(ARM::VMOVRRD), VA.getLocReg())
1834 .addReg(NextVA.getLocReg(), RegState::Define)
1836 RegArgs.push_back(VA.getLocReg());
1837 RegArgs.push_back(NextVA.getLocReg());
1839 assert(VA.isMemLoc());
1840 // Need to store on the stack.
1842 Addr.BaseType = Address::RegBase;
1843 Addr.Base.Reg = ARM::SP;
1844 Addr.Offset = VA.getLocMemOffset();
1846 if (!ARMEmitStore(ArgVT, Arg, Addr)) return false;
1852 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1853 const Instruction *I, CallingConv::ID CC,
1854 unsigned &NumBytes) {
1855 // Issue CALLSEQ_END
1856 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1857 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1858 TII.get(AdjStackUp))
1859 .addImm(NumBytes).addImm(0));
1861 // Now the return value.
1862 if (RetVT != MVT::isVoid) {
1863 SmallVector<CCValAssign, 16> RVLocs;
1864 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1865 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1867 // Copy all of the result registers out of their specified physreg.
1868 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1869 // For this move we copy into two registers and then move into the
1870 // double fp reg we want.
1871 EVT DestVT = RVLocs[0].getValVT();
1872 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1873 unsigned ResultReg = createResultReg(DstRC);
1874 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1875 TII.get(ARM::VMOVDRR), ResultReg)
1876 .addReg(RVLocs[0].getLocReg())
1877 .addReg(RVLocs[1].getLocReg()));
1879 UsedRegs.push_back(RVLocs[0].getLocReg());
1880 UsedRegs.push_back(RVLocs[1].getLocReg());
1882 // Finally update the result.
1883 UpdateValueMap(I, ResultReg);
1885 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1886 EVT CopyVT = RVLocs[0].getValVT();
1888 // Special handling for extended integers.
1889 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1892 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1894 unsigned ResultReg = createResultReg(DstRC);
1895 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1896 ResultReg).addReg(RVLocs[0].getLocReg());
1897 UsedRegs.push_back(RVLocs[0].getLocReg());
1899 // Finally update the result.
1900 UpdateValueMap(I, ResultReg);
1907 bool ARMFastISel::SelectRet(const Instruction *I) {
1908 const ReturnInst *Ret = cast<ReturnInst>(I);
1909 const Function &F = *I->getParent()->getParent();
1911 if (!FuncInfo.CanLowerReturn)
1917 CallingConv::ID CC = F.getCallingConv();
1918 if (Ret->getNumOperands() > 0) {
1919 SmallVector<ISD::OutputArg, 4> Outs;
1920 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
1923 // Analyze operands of the call, assigning locations to each operand.
1924 SmallVector<CCValAssign, 16> ValLocs;
1925 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
1926 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
1928 const Value *RV = Ret->getOperand(0);
1929 unsigned Reg = getRegForValue(RV);
1933 // Only handle a single return value for now.
1934 if (ValLocs.size() != 1)
1937 CCValAssign &VA = ValLocs[0];
1939 // Don't bother handling odd stuff for now.
1940 if (VA.getLocInfo() != CCValAssign::Full)
1942 // Only handle register returns for now.
1946 unsigned SrcReg = Reg + VA.getValNo();
1947 EVT RVVT = TLI.getValueType(RV->getType());
1948 EVT DestVT = VA.getValVT();
1949 // Special handling for extended integers.
1950 if (RVVT != DestVT) {
1951 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1954 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
1957 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
1959 bool isZExt = Outs[0].Flags.isZExt();
1960 unsigned ResultReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, isZExt);
1961 if (ResultReg == 0) return false;
1966 unsigned DstReg = VA.getLocReg();
1967 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
1968 // Avoid a cross-class copy. This is very unlikely.
1969 if (!SrcRC->contains(DstReg))
1971 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1972 DstReg).addReg(SrcReg);
1974 // Mark the register as live out of the function.
1975 MRI.addLiveOut(VA.getLocReg());
1978 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
1979 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1984 unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) {
1986 // Darwin needs the r9 versions of the opcodes.
1987 bool isDarwin = Subtarget->isTargetDarwin();
1989 return isDarwin ? ARM::tBLr9 : ARM::tBL;
1991 return isDarwin ? ARM::BLr9 : ARM::BL;
1995 // A quick function that will emit a call for a named libcall in F with the
1996 // vector of passed arguments for the Instruction in I. We can assume that we
1997 // can emit a call for any libcall we can produce. This is an abridged version
1998 // of the full call infrastructure since we won't need to worry about things
1999 // like computed function pointers or strange arguments at call sites.
2000 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2002 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2003 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2005 // Handle *simple* calls for now.
2006 Type *RetTy = I->getType();
2008 if (RetTy->isVoidTy())
2009 RetVT = MVT::isVoid;
2010 else if (!isTypeLegal(RetTy, RetVT))
2013 // TODO: For now if we have long calls specified we don't handle the call.
2014 if (EnableARMLongCalls) return false;
2016 // Set up the argument vectors.
2017 SmallVector<Value*, 8> Args;
2018 SmallVector<unsigned, 8> ArgRegs;
2019 SmallVector<MVT, 8> ArgVTs;
2020 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2021 Args.reserve(I->getNumOperands());
2022 ArgRegs.reserve(I->getNumOperands());
2023 ArgVTs.reserve(I->getNumOperands());
2024 ArgFlags.reserve(I->getNumOperands());
2025 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2026 Value *Op = I->getOperand(i);
2027 unsigned Arg = getRegForValue(Op);
2028 if (Arg == 0) return false;
2030 Type *ArgTy = Op->getType();
2032 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2034 ISD::ArgFlagsTy Flags;
2035 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2036 Flags.setOrigAlign(OriginalAlignment);
2039 ArgRegs.push_back(Arg);
2040 ArgVTs.push_back(ArgVT);
2041 ArgFlags.push_back(Flags);
2044 // Handle the arguments now that we've gotten them.
2045 SmallVector<unsigned, 4> RegArgs;
2047 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
2050 // Issue the call, BLr9 for darwin, BL otherwise.
2051 // TODO: Turn this into the table of arm call ops.
2052 MachineInstrBuilder MIB;
2053 unsigned CallOpc = ARMSelectCallOp(NULL);
2055 // Explicitly adding the predicate here.
2056 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2058 .addExternalSymbol(TLI.getLibcallName(Call));
2060 // Explicitly adding the predicate here.
2061 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2063 .addExternalSymbol(TLI.getLibcallName(Call)));
2065 // Add implicit physical register uses to the call.
2066 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2067 MIB.addReg(RegArgs[i]);
2069 // Finish off the call including any return values.
2070 SmallVector<unsigned, 4> UsedRegs;
2071 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
2073 // Set all unused physreg defs as dead.
2074 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2079 bool ARMFastISel::SelectCall(const Instruction *I,
2080 const char *IntrMemName = 0) {
2081 const CallInst *CI = cast<CallInst>(I);
2082 const Value *Callee = CI->getCalledValue();
2084 // Can't handle inline asm.
2085 if (isa<InlineAsm>(Callee)) return false;
2087 // Only handle global variable Callees.
2088 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2092 // Check the calling convention.
2093 ImmutableCallSite CS(CI);
2094 CallingConv::ID CC = CS.getCallingConv();
2096 // TODO: Avoid some calling conventions?
2098 // Let SDISel handle vararg functions.
2099 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2100 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2101 if (FTy->isVarArg())
2104 // Handle *simple* calls for now.
2105 Type *RetTy = I->getType();
2107 if (RetTy->isVoidTy())
2108 RetVT = MVT::isVoid;
2109 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2110 RetVT != MVT::i8 && RetVT != MVT::i1)
2113 // TODO: For now if we have long calls specified we don't handle the call.
2114 if (EnableARMLongCalls) return false;
2116 // Set up the argument vectors.
2117 SmallVector<Value*, 8> Args;
2118 SmallVector<unsigned, 8> ArgRegs;
2119 SmallVector<MVT, 8> ArgVTs;
2120 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2121 Args.reserve(CS.arg_size());
2122 ArgRegs.reserve(CS.arg_size());
2123 ArgVTs.reserve(CS.arg_size());
2124 ArgFlags.reserve(CS.arg_size());
2125 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2127 // If we're lowering a memory intrinsic instead of a regular call, skip the
2128 // last two arguments, which shouldn't be passed to the underlying function.
2129 if (IntrMemName && e-i <= 2)
2132 ISD::ArgFlagsTy Flags;
2133 unsigned AttrInd = i - CS.arg_begin() + 1;
2134 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2136 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2139 // FIXME: Only handle *easy* calls for now.
2140 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2141 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2142 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2143 CS.paramHasAttr(AttrInd, Attribute::ByVal))
2146 Type *ArgTy = (*i)->getType();
2148 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2152 unsigned Arg = getRegForValue(*i);
2156 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2157 Flags.setOrigAlign(OriginalAlignment);
2160 ArgRegs.push_back(Arg);
2161 ArgVTs.push_back(ArgVT);
2162 ArgFlags.push_back(Flags);
2165 // Handle the arguments now that we've gotten them.
2166 SmallVector<unsigned, 4> RegArgs;
2168 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
2171 // Issue the call, BLr9 for darwin, BL otherwise.
2172 // TODO: Turn this into the table of arm call ops.
2173 MachineInstrBuilder MIB;
2174 unsigned CallOpc = ARMSelectCallOp(GV);
2175 // Explicitly adding the predicate here.
2177 // Explicitly adding the predicate here.
2178 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2181 MIB.addGlobalAddress(GV, 0, 0);
2183 MIB.addExternalSymbol(IntrMemName, 0);
2186 // Explicitly adding the predicate here.
2187 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2189 .addGlobalAddress(GV, 0, 0));
2191 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2193 .addExternalSymbol(IntrMemName, 0));
2196 // Add implicit physical register uses to the call.
2197 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2198 MIB.addReg(RegArgs[i]);
2200 // Finish off the call including any return values.
2201 SmallVector<unsigned, 4> UsedRegs;
2202 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
2204 // Set all unused physreg defs as dead.
2205 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2210 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2214 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len) {
2215 // Make sure we don't bloat code by inlining very large memcpy's.
2216 if (!ARMIsMemCpySmall(Len))
2219 // We don't care about alignment here since we just emit integer accesses.
2233 RV = ARMEmitLoad(VT, ResultReg, Src);
2234 assert (RV = true && "Should be able to handle this load.");
2235 RV = ARMEmitStore(VT, ResultReg, Dest);
2236 assert (RV = true && "Should be able to handle this store.");
2238 unsigned Size = VT.getSizeInBits()/8;
2240 Dest.Offset += Size;
2247 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2248 // FIXME: Handle more intrinsics.
2249 switch (I.getIntrinsicID()) {
2250 default: return false;
2251 case Intrinsic::memcpy:
2252 case Intrinsic::memmove: {
2253 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2254 // Don't handle volatile.
2255 if (MTI.isVolatile())
2258 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2259 // we would emit dead code because we don't currently handle memmoves.
2260 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2261 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2262 // Small memcpy's are common enough that we want to do them without a call
2264 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2265 if (ARMIsMemCpySmall(Len)) {
2267 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2268 !ARMComputeAddress(MTI.getRawSource(), Src))
2270 if (ARMTryEmitSmallMemCpy(Dest, Src, Len))
2275 if (!MTI.getLength()->getType()->isIntegerTy(32))
2278 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2281 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2282 return SelectCall(&I, IntrMemName);
2284 case Intrinsic::memset: {
2285 const MemSetInst &MSI = cast<MemSetInst>(I);
2286 // Don't handle volatile.
2287 if (MSI.isVolatile())
2290 if (!MSI.getLength()->getType()->isIntegerTy(32))
2293 if (MSI.getDestAddressSpace() > 255)
2296 return SelectCall(&I, "memset");
2302 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2303 // The high bits for a type smaller than the register size are assumed to be
2305 Value *Op = I->getOperand(0);
2308 SrcVT = TLI.getValueType(Op->getType(), true);
2309 DestVT = TLI.getValueType(I->getType(), true);
2311 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2313 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2316 unsigned SrcReg = getRegForValue(Op);
2317 if (!SrcReg) return false;
2319 // Because the high bits are undefined, a truncate doesn't generate
2321 UpdateValueMap(I, SrcReg);
2325 unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
2327 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2331 bool isBoolZext = false;
2332 if (!SrcVT.isSimple()) return 0;
2333 switch (SrcVT.getSimpleVT().SimpleTy) {
2336 if (!Subtarget->hasV6Ops()) return 0;
2338 Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
2340 Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
2343 if (!Subtarget->hasV6Ops()) return 0;
2345 Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
2347 Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
2351 Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
2358 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2359 MachineInstrBuilder MIB;
2360 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
2366 AddOptionalDefs(MIB);
2370 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2371 // On ARM, in general, integer casts don't involve legal types; this code
2372 // handles promotable integers.
2373 Type *DestTy = I->getType();
2374 Value *Src = I->getOperand(0);
2375 Type *SrcTy = Src->getType();
2378 SrcVT = TLI.getValueType(SrcTy, true);
2379 DestVT = TLI.getValueType(DestTy, true);
2381 bool isZExt = isa<ZExtInst>(I);
2382 unsigned SrcReg = getRegForValue(Src);
2383 if (!SrcReg) return false;
2385 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2386 if (ResultReg == 0) return false;
2387 UpdateValueMap(I, ResultReg);
2391 // TODO: SoftFP support.
2392 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2394 switch (I->getOpcode()) {
2395 case Instruction::Load:
2396 return SelectLoad(I);
2397 case Instruction::Store:
2398 return SelectStore(I);
2399 case Instruction::Br:
2400 return SelectBranch(I);
2401 case Instruction::ICmp:
2402 case Instruction::FCmp:
2403 return SelectCmp(I);
2404 case Instruction::FPExt:
2405 return SelectFPExt(I);
2406 case Instruction::FPTrunc:
2407 return SelectFPTrunc(I);
2408 case Instruction::SIToFP:
2409 return SelectSIToFP(I);
2410 case Instruction::FPToSI:
2411 return SelectFPToSI(I);
2412 case Instruction::FAdd:
2413 return SelectBinaryOp(I, ISD::FADD);
2414 case Instruction::FSub:
2415 return SelectBinaryOp(I, ISD::FSUB);
2416 case Instruction::FMul:
2417 return SelectBinaryOp(I, ISD::FMUL);
2418 case Instruction::SDiv:
2419 return SelectSDiv(I);
2420 case Instruction::SRem:
2421 return SelectSRem(I);
2422 case Instruction::Call:
2423 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2424 return SelectIntrinsicCall(*II);
2425 return SelectCall(I);
2426 case Instruction::Select:
2427 return SelectSelect(I);
2428 case Instruction::Ret:
2429 return SelectRet(I);
2430 case Instruction::Trunc:
2431 return SelectTrunc(I);
2432 case Instruction::ZExt:
2433 case Instruction::SExt:
2434 return SelectIntExt(I);
2440 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
2441 /// vreg is being provided by the specified load instruction. If possible,
2442 /// try to fold the load as an operand to the instruction, returning true if
2444 bool ARMFastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
2445 const LoadInst *LI) {
2446 // Verify we have a legal type before going any further.
2448 if (!isLoadTypeLegal(LI->getType(), VT))
2451 // Combine load followed by zero- or sign-extend.
2452 // ldrb r1, [r0] ldrb r1, [r0]
2454 // mov r3, r2 mov r3, r1
2456 switch(MI->getOpcode()) {
2457 default: return false;
2475 // See if we can handle this address.
2477 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2479 unsigned ResultReg = MI->getOperand(0).getReg();
2480 if (!ARMEmitLoad(VT, ResultReg, Addr, isZExt, false))
2482 MI->eraseFromParent();
2487 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
2488 // Completely untested on non-darwin.
2489 const TargetMachine &TM = funcInfo.MF->getTarget();
2491 // Darwin and thumb1 only for now.
2492 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2493 if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() &&
2494 !DisableARMFastISel)
2495 return new ARMFastISel(funcInfo);