1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMAddressingModes.h"
18 #include "ARMBaseInstrInfo.h"
19 #include "ARMCallingConv.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMSubtarget.h"
23 #include "ARMConstantPoolValue.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/IntrinsicInst.h"
29 #include "llvm/Module.h"
30 #include "llvm/Operator.h"
31 #include "llvm/CodeGen/Analysis.h"
32 #include "llvm/CodeGen/FastISel.h"
33 #include "llvm/CodeGen/FunctionLoweringInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineConstantPool.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineMemOperand.h"
39 #include "llvm/CodeGen/MachineRegisterInfo.h"
40 #include "llvm/CodeGen/PseudoSourceValue.h"
41 #include "llvm/Support/CallSite.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/GetElementPtrTypeIterator.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
53 DisableARMFastISel("disable-arm-fast-isel",
54 cl::desc("Turn off experimental ARM fast-isel support"),
55 cl::init(false), cl::Hidden);
57 extern cl::opt<bool> EnableARMLongCalls;
61 // All possible address modes, plus some.
62 typedef struct Address {
75 // Innocuous defaults for our address.
77 : BaseType(RegBase), Offset(0) {
82 class ARMFastISel : public FastISel {
84 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
85 /// make the right decision when generating code for different targets.
86 const ARMSubtarget *Subtarget;
87 const TargetMachine &TM;
88 const TargetInstrInfo &TII;
89 const TargetLowering &TLI;
92 // Convenience variables to avoid some queries.
97 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
99 TM(funcInfo.MF->getTarget()),
100 TII(*TM.getInstrInfo()),
101 TLI(*TM.getTargetLowering()) {
102 Subtarget = &TM.getSubtarget<ARMSubtarget>();
103 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
104 isThumb = AFI->isThumbFunction();
105 Context = &funcInfo.Fn->getContext();
108 // Code from FastISel.cpp.
109 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
110 const TargetRegisterClass *RC);
111 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
112 const TargetRegisterClass *RC,
113 unsigned Op0, bool Op0IsKill);
114 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
115 const TargetRegisterClass *RC,
116 unsigned Op0, bool Op0IsKill,
117 unsigned Op1, bool Op1IsKill);
118 virtual unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill,
121 unsigned Op1, bool Op1IsKill,
122 unsigned Op2, bool Op2IsKill);
123 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
124 const TargetRegisterClass *RC,
125 unsigned Op0, bool Op0IsKill,
127 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
128 const TargetRegisterClass *RC,
129 unsigned Op0, bool Op0IsKill,
130 const ConstantFP *FPImm);
131 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
132 const TargetRegisterClass *RC,
133 unsigned Op0, bool Op0IsKill,
134 unsigned Op1, bool Op1IsKill,
136 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
137 const TargetRegisterClass *RC,
139 virtual unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
140 const TargetRegisterClass *RC,
141 uint64_t Imm1, uint64_t Imm2);
143 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
144 unsigned Op0, bool Op0IsKill,
147 // Backend specific FastISel code.
148 virtual bool TargetSelectInstruction(const Instruction *I);
149 virtual unsigned TargetMaterializeConstant(const Constant *C);
150 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
152 #include "ARMGenFastISel.inc"
154 // Instruction selection routines.
156 bool SelectLoad(const Instruction *I);
157 bool SelectStore(const Instruction *I);
158 bool SelectBranch(const Instruction *I);
159 bool SelectCmp(const Instruction *I);
160 bool SelectFPExt(const Instruction *I);
161 bool SelectFPTrunc(const Instruction *I);
162 bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
163 bool SelectSIToFP(const Instruction *I);
164 bool SelectFPToSI(const Instruction *I);
165 bool SelectSDiv(const Instruction *I);
166 bool SelectSRem(const Instruction *I);
167 bool SelectCall(const Instruction *I);
168 bool SelectSelect(const Instruction *I);
169 bool SelectRet(const Instruction *I);
170 bool SelectIntCast(const Instruction *I);
174 bool isTypeLegal(const Type *Ty, MVT &VT);
175 bool isLoadTypeLegal(const Type *Ty, MVT &VT);
176 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
177 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
178 bool ARMComputeAddress(const Value *Obj, Address &Addr);
179 void ARMSimplifyAddress(Address &Addr, EVT VT);
180 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
181 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
182 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
183 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
184 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
185 unsigned ARMSelectCallOp(const GlobalValue *GV);
187 // Call handling routines.
189 bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
190 unsigned &ResultReg);
191 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
192 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
193 SmallVectorImpl<unsigned> &ArgRegs,
194 SmallVectorImpl<MVT> &ArgVTs,
195 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
196 SmallVectorImpl<unsigned> &RegArgs,
199 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
200 const Instruction *I, CallingConv::ID CC,
202 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
204 // OptionalDef handling routines.
206 bool isARMNEONPred(const MachineInstr *MI);
207 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
208 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
209 void AddLoadStoreOperands(EVT VT, Address &Addr,
210 const MachineInstrBuilder &MIB);
213 } // end anonymous namespace
215 #include "ARMGenCallingConv.inc"
217 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
218 // we don't care about implicit defs here, just places we'll need to add a
219 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
220 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
221 const TargetInstrDesc &TID = MI->getDesc();
222 if (!TID.hasOptionalDef())
225 // Look to see if our OptionalDef is defining CPSR or CCR.
226 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
227 const MachineOperand &MO = MI->getOperand(i);
228 if (!MO.isReg() || !MO.isDef()) continue;
229 if (MO.getReg() == ARM::CPSR)
235 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
236 const TargetInstrDesc &TID = MI->getDesc();
238 // If we're a thumb2 or not NEON function we were handled via isPredicable.
239 if ((TID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
240 AFI->isThumb2Function())
243 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i)
244 if (TID.OpInfo[i].isPredicate())
250 // If the machine is predicable go ahead and add the predicate operands, if
251 // it needs default CC operands add those.
252 // TODO: If we want to support thumb1 then we'll need to deal with optional
253 // CPSR defs that need to be added before the remaining operands. See s_cc_out
254 // for descriptions why.
255 const MachineInstrBuilder &
256 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
257 MachineInstr *MI = &*MIB;
259 // Do we use a predicate? or...
260 // Are we NEON in ARM mode and have a predicate operand? If so, I know
261 // we're not predicable but add it anyways.
262 if (TII.isPredicable(MI) || isARMNEONPred(MI))
265 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
266 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
268 if (DefinesOptionalPredicate(MI, &CPSR)) {
277 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
278 const TargetRegisterClass* RC) {
279 unsigned ResultReg = createResultReg(RC);
280 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
282 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
286 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
287 const TargetRegisterClass *RC,
288 unsigned Op0, bool Op0IsKill) {
289 unsigned ResultReg = createResultReg(RC);
290 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
292 if (II.getNumDefs() >= 1)
293 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
294 .addReg(Op0, Op0IsKill * RegState::Kill));
296 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
297 .addReg(Op0, Op0IsKill * RegState::Kill));
298 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
299 TII.get(TargetOpcode::COPY), ResultReg)
300 .addReg(II.ImplicitDefs[0]));
305 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
306 const TargetRegisterClass *RC,
307 unsigned Op0, bool Op0IsKill,
308 unsigned Op1, bool Op1IsKill) {
309 unsigned ResultReg = createResultReg(RC);
310 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
312 if (II.getNumDefs() >= 1)
313 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
314 .addReg(Op0, Op0IsKill * RegState::Kill)
315 .addReg(Op1, Op1IsKill * RegState::Kill));
317 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
318 .addReg(Op0, Op0IsKill * RegState::Kill)
319 .addReg(Op1, Op1IsKill * RegState::Kill));
320 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
321 TII.get(TargetOpcode::COPY), ResultReg)
322 .addReg(II.ImplicitDefs[0]));
327 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
328 const TargetRegisterClass *RC,
329 unsigned Op0, bool Op0IsKill,
330 unsigned Op1, bool Op1IsKill,
331 unsigned Op2, bool Op2IsKill) {
332 unsigned ResultReg = createResultReg(RC);
333 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
335 if (II.getNumDefs() >= 1)
336 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
337 .addReg(Op0, Op0IsKill * RegState::Kill)
338 .addReg(Op1, Op1IsKill * RegState::Kill)
339 .addReg(Op2, Op2IsKill * RegState::Kill));
341 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
342 .addReg(Op0, Op0IsKill * RegState::Kill)
343 .addReg(Op1, Op1IsKill * RegState::Kill)
344 .addReg(Op2, Op2IsKill * RegState::Kill));
345 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
346 TII.get(TargetOpcode::COPY), ResultReg)
347 .addReg(II.ImplicitDefs[0]));
352 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
353 const TargetRegisterClass *RC,
354 unsigned Op0, bool Op0IsKill,
356 unsigned ResultReg = createResultReg(RC);
357 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
359 if (II.getNumDefs() >= 1)
360 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
361 .addReg(Op0, Op0IsKill * RegState::Kill)
364 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
365 .addReg(Op0, Op0IsKill * RegState::Kill)
367 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
368 TII.get(TargetOpcode::COPY), ResultReg)
369 .addReg(II.ImplicitDefs[0]));
374 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
375 const TargetRegisterClass *RC,
376 unsigned Op0, bool Op0IsKill,
377 const ConstantFP *FPImm) {
378 unsigned ResultReg = createResultReg(RC);
379 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
381 if (II.getNumDefs() >= 1)
382 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
383 .addReg(Op0, Op0IsKill * RegState::Kill)
386 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
387 .addReg(Op0, Op0IsKill * RegState::Kill)
389 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
390 TII.get(TargetOpcode::COPY), ResultReg)
391 .addReg(II.ImplicitDefs[0]));
396 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
397 const TargetRegisterClass *RC,
398 unsigned Op0, bool Op0IsKill,
399 unsigned Op1, bool Op1IsKill,
401 unsigned ResultReg = createResultReg(RC);
402 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
404 if (II.getNumDefs() >= 1)
405 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
406 .addReg(Op0, Op0IsKill * RegState::Kill)
407 .addReg(Op1, Op1IsKill * RegState::Kill)
410 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
411 .addReg(Op0, Op0IsKill * RegState::Kill)
412 .addReg(Op1, Op1IsKill * RegState::Kill)
414 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
415 TII.get(TargetOpcode::COPY), ResultReg)
416 .addReg(II.ImplicitDefs[0]));
421 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
422 const TargetRegisterClass *RC,
424 unsigned ResultReg = createResultReg(RC);
425 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
427 if (II.getNumDefs() >= 1)
428 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
431 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
433 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
434 TII.get(TargetOpcode::COPY), ResultReg)
435 .addReg(II.ImplicitDefs[0]));
440 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
441 const TargetRegisterClass *RC,
442 uint64_t Imm1, uint64_t Imm2) {
443 unsigned ResultReg = createResultReg(RC);
444 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
446 if (II.getNumDefs() >= 1)
447 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
448 .addImm(Imm1).addImm(Imm2));
450 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
451 .addImm(Imm1).addImm(Imm2));
452 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
453 TII.get(TargetOpcode::COPY),
455 .addReg(II.ImplicitDefs[0]));
460 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
461 unsigned Op0, bool Op0IsKill,
463 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
464 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
465 "Cannot yet extract from physregs");
466 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
467 DL, TII.get(TargetOpcode::COPY), ResultReg)
468 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
472 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
473 // checks from the various callers.
474 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
475 if (VT == MVT::f64) return 0;
477 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
478 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
479 TII.get(ARM::VMOVRS), MoveReg)
484 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
485 if (VT == MVT::i64) return 0;
487 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
488 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
489 TII.get(ARM::VMOVSR), MoveReg)
494 // For double width floating point we need to materialize two constants
495 // (the high and the low) into integer registers then use a move to get
496 // the combined constant into an FP reg.
497 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
498 const APFloat Val = CFP->getValueAPF();
499 bool is64bit = VT == MVT::f64;
501 // This checks to see if we can use VFP3 instructions to materialize
502 // a constant, otherwise we have to go through the constant pool.
503 if (TLI.isFPImmLegal(Val, VT)) {
504 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
505 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
506 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
512 // Require VFP2 for loading fp constants.
513 if (!Subtarget->hasVFP2()) return false;
515 // MachineConstantPool wants an explicit alignment.
516 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
518 // TODO: Figure out if this is correct.
519 Align = TD.getTypeAllocSize(CFP->getType());
521 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
522 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
523 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
525 // The extra reg is for addrmode5.
526 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
528 .addConstantPoolIndex(Idx)
533 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
535 // For now 32-bit only.
536 if (VT != MVT::i32) return false;
538 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
540 // If we can do this in a single instruction without a constant pool entry
542 const ConstantInt *CI = cast<ConstantInt>(C);
543 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) {
544 unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16;
545 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
546 TII.get(Opc), DestReg)
547 .addImm(CI->getSExtValue()));
551 // MachineConstantPool wants an explicit alignment.
552 unsigned Align = TD.getPrefTypeAlignment(C->getType());
554 // TODO: Figure out if this is correct.
555 Align = TD.getTypeAllocSize(C->getType());
557 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
560 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
561 TII.get(ARM::t2LDRpci), DestReg)
562 .addConstantPoolIndex(Idx));
564 // The extra immediate is for addrmode2.
565 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
566 TII.get(ARM::LDRcp), DestReg)
567 .addConstantPoolIndex(Idx)
573 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
574 // For now 32-bit only.
575 if (VT != MVT::i32) return 0;
577 Reloc::Model RelocM = TM.getRelocationModel();
579 // TODO: No external globals for now.
580 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
582 // TODO: Need more magic for ARM PIC.
583 if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
585 // MachineConstantPool wants an explicit alignment.
586 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
588 // TODO: Figure out if this is correct.
589 Align = TD.getTypeAllocSize(GV->getType());
593 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
594 unsigned Id = AFI->createPICLabelUId();
595 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
596 ARMCP::CPValue, PCAdj);
597 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
600 MachineInstrBuilder MIB;
601 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
603 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
604 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
605 .addConstantPoolIndex(Idx);
606 if (RelocM == Reloc::PIC_)
609 // The extra immediate is for addrmode2.
610 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
612 .addConstantPoolIndex(Idx)
615 AddOptionalDefs(MIB);
619 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
620 EVT VT = TLI.getValueType(C->getType(), true);
622 // Only handle simple types.
623 if (!VT.isSimple()) return 0;
625 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
626 return ARMMaterializeFP(CFP, VT);
627 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
628 return ARMMaterializeGV(GV, VT);
629 else if (isa<ConstantInt>(C))
630 return ARMMaterializeInt(C, VT);
635 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
636 // Don't handle dynamic allocas.
637 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
640 if (!isLoadTypeLegal(AI->getType(), VT)) return false;
642 DenseMap<const AllocaInst*, int>::iterator SI =
643 FuncInfo.StaticAllocaMap.find(AI);
645 // This will get lowered later into the correct offsets and registers
646 // via rewriteXFrameIndex.
647 if (SI != FuncInfo.StaticAllocaMap.end()) {
648 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
649 unsigned ResultReg = createResultReg(RC);
650 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
651 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
652 TII.get(Opc), ResultReg)
653 .addFrameIndex(SI->second)
661 bool ARMFastISel::isTypeLegal(const Type *Ty, MVT &VT) {
662 EVT evt = TLI.getValueType(Ty, true);
664 // Only handle simple types.
665 if (evt == MVT::Other || !evt.isSimple()) return false;
666 VT = evt.getSimpleVT();
668 // Handle all legal types, i.e. a register that will directly hold this
670 return TLI.isTypeLegal(VT);
673 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, MVT &VT) {
674 if (isTypeLegal(Ty, VT)) return true;
676 // If this is a type than can be sign or zero-extended to a basic operation
677 // go ahead and accept it now.
678 if (VT == MVT::i8 || VT == MVT::i16)
684 // Computes the address to get to an object.
685 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
686 // Some boilerplate from the X86 FastISel.
687 const User *U = NULL;
688 unsigned Opcode = Instruction::UserOp1;
689 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
690 // Don't walk into other basic blocks unless the object is an alloca from
691 // another block, otherwise it may not have a virtual register assigned.
692 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
693 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
694 Opcode = I->getOpcode();
697 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
698 Opcode = C->getOpcode();
702 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
703 if (Ty->getAddressSpace() > 255)
704 // Fast instruction selection doesn't support the special
711 case Instruction::BitCast: {
712 // Look through bitcasts.
713 return ARMComputeAddress(U->getOperand(0), Addr);
715 case Instruction::IntToPtr: {
716 // Look past no-op inttoptrs.
717 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
718 return ARMComputeAddress(U->getOperand(0), Addr);
721 case Instruction::PtrToInt: {
722 // Look past no-op ptrtoints.
723 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
724 return ARMComputeAddress(U->getOperand(0), Addr);
727 case Instruction::GetElementPtr: {
728 Address SavedAddr = Addr;
729 int TmpOffset = Addr.Offset;
731 // Iterate through the GEP folding the constants into offsets where
733 gep_type_iterator GTI = gep_type_begin(U);
734 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
735 i != e; ++i, ++GTI) {
736 const Value *Op = *i;
737 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
738 const StructLayout *SL = TD.getStructLayout(STy);
739 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
740 TmpOffset += SL->getElementOffset(Idx);
742 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
744 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
745 // Constant-offset addressing.
746 TmpOffset += CI->getSExtValue() * S;
749 if (isa<AddOperator>(Op) &&
750 (!isa<Instruction>(Op) ||
751 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
753 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
754 // An add (in the same block) with a constant operand. Fold the
757 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
758 TmpOffset += CI->getSExtValue() * S;
759 // Iterate on the other operand.
760 Op = cast<AddOperator>(Op)->getOperand(0);
764 goto unsupported_gep;
769 // Try to grab the base operand now.
770 Addr.Offset = TmpOffset;
771 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
773 // We failed, restore everything and try the other options.
779 case Instruction::Alloca: {
780 const AllocaInst *AI = cast<AllocaInst>(Obj);
781 DenseMap<const AllocaInst*, int>::iterator SI =
782 FuncInfo.StaticAllocaMap.find(AI);
783 if (SI != FuncInfo.StaticAllocaMap.end()) {
784 Addr.BaseType = Address::FrameIndexBase;
785 Addr.Base.FI = SI->second;
792 // Materialize the global variable's address into a reg which can
793 // then be used later to load the variable.
794 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
795 unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
796 if (Tmp == 0) return false;
802 // Try to get this in a register if nothing else has worked.
803 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
804 return Addr.Base.Reg != 0;
807 void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
809 assert(VT.isSimple() && "Non-simple types are invalid here!");
811 bool needsLowering = false;
812 switch (VT.getSimpleVT().SimpleTy) {
814 assert(false && "Unhandled load/store type!");
819 // Integer loads/stores handle 12-bit offsets.
820 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
824 // Floating point operands handle 8-bit offsets.
825 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
829 // If this is a stack pointer and the offset needs to be simplified then
830 // put the alloca address into a register, set the base type back to
831 // register and continue. This should almost never happen.
832 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
833 TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
834 ARM::GPRRegisterClass;
835 unsigned ResultReg = createResultReg(RC);
836 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
837 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
838 TII.get(Opc), ResultReg)
839 .addFrameIndex(Addr.Base.FI)
841 Addr.Base.Reg = ResultReg;
842 Addr.BaseType = Address::RegBase;
845 // Since the offset is too large for the load/store instruction
846 // get the reg+offset into a register.
848 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
849 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
854 void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
855 const MachineInstrBuilder &MIB) {
856 // addrmode5 output depends on the selection dag addressing dividing the
857 // offset by 4 that it then later multiplies. Do this here as well.
858 if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
859 VT.getSimpleVT().SimpleTy == MVT::f64)
862 // Frame base works a bit differently. Handle it separately.
863 if (Addr.BaseType == Address::FrameIndexBase) {
864 int FI = Addr.Base.FI;
865 int Offset = Addr.Offset;
866 MachineMemOperand *MMO =
867 FuncInfo.MF->getMachineMemOperand(
868 MachinePointerInfo::getFixedStack(FI, Offset),
869 MachineMemOperand::MOLoad,
870 MFI.getObjectSize(FI),
871 MFI.getObjectAlignment(FI));
872 // Now add the rest of the operands.
873 MIB.addFrameIndex(FI);
875 // ARM halfword load/stores need an additional operand.
876 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
878 MIB.addImm(Addr.Offset);
879 MIB.addMemOperand(MMO);
881 // Now add the rest of the operands.
882 MIB.addReg(Addr.Base.Reg);
884 // ARM halfword load/stores need an additional operand.
885 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
887 MIB.addImm(Addr.Offset);
889 AddOptionalDefs(MIB);
892 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
894 assert(VT.isSimple() && "Non-simple types are invalid here!");
896 TargetRegisterClass *RC;
897 switch (VT.getSimpleVT().SimpleTy) {
898 // This is mostly going to be Neon/vector support.
899 default: return false;
901 Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
902 RC = ARM::GPRRegisterClass;
905 Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
906 RC = ARM::GPRRegisterClass;
909 Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12;
910 RC = ARM::GPRRegisterClass;
914 RC = TLI.getRegClassFor(VT);
918 RC = TLI.getRegClassFor(VT);
921 // Simplify this down to something we can handle.
922 ARMSimplifyAddress(Addr, VT);
924 // Create the base instruction, then add the operands.
925 ResultReg = createResultReg(RC);
926 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
927 TII.get(Opc), ResultReg);
928 AddLoadStoreOperands(VT, Addr, MIB);
932 bool ARMFastISel::SelectLoad(const Instruction *I) {
933 // Verify we have a legal type before going any further.
935 if (!isLoadTypeLegal(I->getType(), VT))
938 // See if we can handle this address.
940 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
943 if (!ARMEmitLoad(VT, ResultReg, Addr)) return false;
944 UpdateValueMap(I, ResultReg);
948 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
950 switch (VT.getSimpleVT().SimpleTy) {
951 // This is mostly going to be Neon/vector support.
952 default: return false;
954 unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass :
955 ARM::GPRRegisterClass);
956 unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
957 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
959 .addReg(SrcReg).addImm(1));
961 } // Fallthrough here.
963 StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
966 StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
969 StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
972 if (!Subtarget->hasVFP2()) return false;
976 if (!Subtarget->hasVFP2()) return false;
980 // Simplify this down to something we can handle.
981 ARMSimplifyAddress(Addr, VT);
983 // Create the base instruction, then add the operands.
984 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
986 .addReg(SrcReg, getKillRegState(true));
987 AddLoadStoreOperands(VT, Addr, MIB);
991 bool ARMFastISel::SelectStore(const Instruction *I) {
992 Value *Op0 = I->getOperand(0);
995 // Verify we have a legal type before going any further.
997 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1000 // Get the value to be stored into a register.
1001 SrcReg = getRegForValue(Op0);
1002 if (SrcReg == 0) return false;
1004 // See if we can handle this address.
1006 if (!ARMComputeAddress(I->getOperand(1), Addr))
1009 if (!ARMEmitStore(VT, SrcReg, Addr)) return false;
1013 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1015 // Needs two compares...
1016 case CmpInst::FCMP_ONE:
1017 case CmpInst::FCMP_UEQ:
1019 // AL is our "false" for now. The other two need more compares.
1021 case CmpInst::ICMP_EQ:
1022 case CmpInst::FCMP_OEQ:
1024 case CmpInst::ICMP_SGT:
1025 case CmpInst::FCMP_OGT:
1027 case CmpInst::ICMP_SGE:
1028 case CmpInst::FCMP_OGE:
1030 case CmpInst::ICMP_UGT:
1031 case CmpInst::FCMP_UGT:
1033 case CmpInst::FCMP_OLT:
1035 case CmpInst::ICMP_ULE:
1036 case CmpInst::FCMP_OLE:
1038 case CmpInst::FCMP_ORD:
1040 case CmpInst::FCMP_UNO:
1042 case CmpInst::FCMP_UGE:
1044 case CmpInst::ICMP_SLT:
1045 case CmpInst::FCMP_ULT:
1047 case CmpInst::ICMP_SLE:
1048 case CmpInst::FCMP_ULE:
1050 case CmpInst::FCMP_UNE:
1051 case CmpInst::ICMP_NE:
1053 case CmpInst::ICMP_UGE:
1055 case CmpInst::ICMP_ULT:
1060 bool ARMFastISel::SelectBranch(const Instruction *I) {
1061 const BranchInst *BI = cast<BranchInst>(I);
1062 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1063 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1065 // Simple branch support.
1067 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1069 // TODO: Factor this out.
1070 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1072 const Type *Ty = CI->getOperand(0)->getType();
1073 if (CI->hasOneUse() && (CI->getParent() == I->getParent())
1074 && isTypeLegal(Ty, SourceVT)) {
1075 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1076 if (isFloat && !Subtarget->hasVFP2())
1080 switch (SourceVT.SimpleTy) {
1081 default: return false;
1082 // TODO: Verify compares.
1084 CmpOpc = ARM::VCMPES;
1087 CmpOpc = ARM::VCMPED;
1090 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1094 // Get the compare predicate.
1095 // Try to take advantage of fallthrough opportunities.
1096 CmpInst::Predicate Predicate = CI->getPredicate();
1097 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1098 std::swap(TBB, FBB);
1099 Predicate = CmpInst::getInversePredicate(Predicate);
1102 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1104 // We may not handle every CC for now.
1105 if (ARMPred == ARMCC::AL) return false;
1107 unsigned Arg1 = getRegForValue(CI->getOperand(0));
1108 if (Arg1 == 0) return false;
1110 unsigned Arg2 = getRegForValue(CI->getOperand(1));
1111 if (Arg2 == 0) return false;
1113 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1115 .addReg(Arg1).addReg(Arg2));
1117 // For floating point we need to move the result to a comparison register
1118 // that we can then use for branches.
1120 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1121 TII.get(ARM::FMSTAT)));
1123 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1124 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1125 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1126 FastEmitBranch(FBB, DL);
1127 FuncInfo.MBB->addSuccessor(TBB);
1130 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1132 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1133 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1134 unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1135 unsigned OpReg = getRegForValue(TI->getOperand(0));
1136 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1138 .addReg(OpReg).addImm(1));
1140 unsigned CCMode = ARMCC::NE;
1141 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1142 std::swap(TBB, FBB);
1146 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1147 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1148 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1150 FastEmitBranch(FBB, DL);
1151 FuncInfo.MBB->addSuccessor(TBB);
1156 unsigned CmpReg = getRegForValue(BI->getCondition());
1157 if (CmpReg == 0) return false;
1159 // We've been divorced from our compare! Our block was split, and
1160 // now our compare lives in a predecessor block. We musn't
1161 // re-compare here, as the children of the compare aren't guaranteed
1162 // live across the block boundary (we *could* check for this).
1163 // Regardless, the compare has been done in the predecessor block,
1164 // and it left a value for us in a virtual register. Ergo, we test
1165 // the one-bit value left in the virtual register.
1166 unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1167 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1168 .addReg(CmpReg).addImm(1));
1170 unsigned CCMode = ARMCC::NE;
1171 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1172 std::swap(TBB, FBB);
1176 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1177 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1178 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1179 FastEmitBranch(FBB, DL);
1180 FuncInfo.MBB->addSuccessor(TBB);
1184 bool ARMFastISel::SelectCmp(const Instruction *I) {
1185 const CmpInst *CI = cast<CmpInst>(I);
1188 const Type *Ty = CI->getOperand(0)->getType();
1189 if (!isTypeLegal(Ty, VT))
1192 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1193 if (isFloat && !Subtarget->hasVFP2())
1198 switch (VT.SimpleTy) {
1199 default: return false;
1200 // TODO: Verify compares.
1202 CmpOpc = ARM::VCMPES;
1203 CondReg = ARM::FPSCR;
1206 CmpOpc = ARM::VCMPED;
1207 CondReg = ARM::FPSCR;
1210 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1211 CondReg = ARM::CPSR;
1215 // Get the compare predicate.
1216 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1218 // We may not handle every CC for now.
1219 if (ARMPred == ARMCC::AL) return false;
1221 unsigned Arg1 = getRegForValue(CI->getOperand(0));
1222 if (Arg1 == 0) return false;
1224 unsigned Arg2 = getRegForValue(CI->getOperand(1));
1225 if (Arg2 == 0) return false;
1227 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1228 .addReg(Arg1).addReg(Arg2));
1230 // For floating point we need to move the result to a comparison register
1231 // that we can then use for branches.
1233 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1234 TII.get(ARM::FMSTAT)));
1236 // Now set a register based on the comparison. Explicitly set the predicates
1238 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1239 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1240 : ARM::GPRRegisterClass;
1241 unsigned DestReg = createResultReg(RC);
1243 = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1244 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1245 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1246 .addReg(ZeroReg).addImm(1)
1247 .addImm(ARMPred).addReg(CondReg);
1249 UpdateValueMap(I, DestReg);
1253 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1254 // Make sure we have VFP and that we're extending float to double.
1255 if (!Subtarget->hasVFP2()) return false;
1257 Value *V = I->getOperand(0);
1258 if (!I->getType()->isDoubleTy() ||
1259 !V->getType()->isFloatTy()) return false;
1261 unsigned Op = getRegForValue(V);
1262 if (Op == 0) return false;
1264 unsigned Result = createResultReg(ARM::DPRRegisterClass);
1265 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1266 TII.get(ARM::VCVTDS), Result)
1268 UpdateValueMap(I, Result);
1272 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1273 // Make sure we have VFP and that we're truncating double to float.
1274 if (!Subtarget->hasVFP2()) return false;
1276 Value *V = I->getOperand(0);
1277 if (!(I->getType()->isFloatTy() &&
1278 V->getType()->isDoubleTy())) return false;
1280 unsigned Op = getRegForValue(V);
1281 if (Op == 0) return false;
1283 unsigned Result = createResultReg(ARM::SPRRegisterClass);
1284 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1285 TII.get(ARM::VCVTSD), Result)
1287 UpdateValueMap(I, Result);
1291 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1292 // Make sure we have VFP.
1293 if (!Subtarget->hasVFP2()) return false;
1296 const Type *Ty = I->getType();
1297 if (!isTypeLegal(Ty, DstVT))
1300 // FIXME: Handle sign-extension where necessary.
1301 if (!I->getOperand(0)->getType()->isIntegerTy(32))
1304 unsigned Op = getRegForValue(I->getOperand(0));
1305 if (Op == 0) return false;
1307 // The conversion routine works on fp-reg to fp-reg and the operand above
1308 // was an integer, move it to the fp registers if possible.
1309 unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1310 if (FP == 0) return false;
1313 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1314 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1317 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1318 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1321 UpdateValueMap(I, ResultReg);
1325 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1326 // Make sure we have VFP.
1327 if (!Subtarget->hasVFP2()) return false;
1330 const Type *RetTy = I->getType();
1331 if (!isTypeLegal(RetTy, DstVT))
1334 unsigned Op = getRegForValue(I->getOperand(0));
1335 if (Op == 0) return false;
1338 const Type *OpTy = I->getOperand(0)->getType();
1339 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1340 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1343 // f64->s32 or f32->s32 both need an intermediate f32 reg.
1344 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1345 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1349 // This result needs to be in an integer register, but the conversion only
1350 // takes place in fp-regs.
1351 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1352 if (IntReg == 0) return false;
1354 UpdateValueMap(I, IntReg);
1358 bool ARMFastISel::SelectSelect(const Instruction *I) {
1360 if (!isTypeLegal(I->getType(), VT))
1363 // Things need to be register sized for register moves.
1364 if (VT != MVT::i32) return false;
1365 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1367 unsigned CondReg = getRegForValue(I->getOperand(0));
1368 if (CondReg == 0) return false;
1369 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1370 if (Op1Reg == 0) return false;
1371 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1372 if (Op2Reg == 0) return false;
1374 unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1375 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1376 .addReg(CondReg).addImm(1));
1377 unsigned ResultReg = createResultReg(RC);
1378 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1379 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1380 .addReg(Op1Reg).addReg(Op2Reg)
1381 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1382 UpdateValueMap(I, ResultReg);
1386 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1388 const Type *Ty = I->getType();
1389 if (!isTypeLegal(Ty, VT))
1392 // If we have integer div support we should have selected this automagically.
1393 // In case we have a real miss go ahead and return false and we'll pick
1395 if (Subtarget->hasDivide()) return false;
1397 // Otherwise emit a libcall.
1398 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1400 LC = RTLIB::SDIV_I8;
1401 else if (VT == MVT::i16)
1402 LC = RTLIB::SDIV_I16;
1403 else if (VT == MVT::i32)
1404 LC = RTLIB::SDIV_I32;
1405 else if (VT == MVT::i64)
1406 LC = RTLIB::SDIV_I64;
1407 else if (VT == MVT::i128)
1408 LC = RTLIB::SDIV_I128;
1409 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1411 return ARMEmitLibcall(I, LC);
1414 bool ARMFastISel::SelectSRem(const Instruction *I) {
1416 const Type *Ty = I->getType();
1417 if (!isTypeLegal(Ty, VT))
1420 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1422 LC = RTLIB::SREM_I8;
1423 else if (VT == MVT::i16)
1424 LC = RTLIB::SREM_I16;
1425 else if (VT == MVT::i32)
1426 LC = RTLIB::SREM_I32;
1427 else if (VT == MVT::i64)
1428 LC = RTLIB::SREM_I64;
1429 else if (VT == MVT::i128)
1430 LC = RTLIB::SREM_I128;
1431 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1433 return ARMEmitLibcall(I, LC);
1436 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1437 EVT VT = TLI.getValueType(I->getType(), true);
1439 // We can get here in the case when we want to use NEON for our fp
1440 // operations, but can't figure out how to. Just use the vfp instructions
1442 // FIXME: It'd be nice to use NEON instructions.
1443 const Type *Ty = I->getType();
1444 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1445 if (isFloat && !Subtarget->hasVFP2())
1448 unsigned Op1 = getRegForValue(I->getOperand(0));
1449 if (Op1 == 0) return false;
1451 unsigned Op2 = getRegForValue(I->getOperand(1));
1452 if (Op2 == 0) return false;
1455 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1456 switch (ISDOpcode) {
1457 default: return false;
1459 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1462 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1465 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1468 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1469 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1470 TII.get(Opc), ResultReg)
1471 .addReg(Op1).addReg(Op2));
1472 UpdateValueMap(I, ResultReg);
1476 // Call Handling Code
1478 bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src,
1479 EVT SrcVT, unsigned &ResultReg) {
1480 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1481 Src, /*TODO: Kill=*/false);
1490 // This is largely taken directly from CCAssignFnForNode - we don't support
1491 // varargs in FastISel so that part has been removed.
1492 // TODO: We may not support all of this.
1493 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1496 llvm_unreachable("Unsupported calling convention");
1497 case CallingConv::Fast:
1498 // Ignore fastcc. Silence compiler warnings.
1499 (void)RetFastCC_ARM_APCS;
1500 (void)FastCC_ARM_APCS;
1502 case CallingConv::C:
1503 // Use target triple & subtarget features to do actual dispatch.
1504 if (Subtarget->isAAPCS_ABI()) {
1505 if (Subtarget->hasVFP2() &&
1506 FloatABIType == FloatABI::Hard)
1507 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1509 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1511 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1512 case CallingConv::ARM_AAPCS_VFP:
1513 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1514 case CallingConv::ARM_AAPCS:
1515 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1516 case CallingConv::ARM_APCS:
1517 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1521 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1522 SmallVectorImpl<unsigned> &ArgRegs,
1523 SmallVectorImpl<MVT> &ArgVTs,
1524 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1525 SmallVectorImpl<unsigned> &RegArgs,
1527 unsigned &NumBytes) {
1528 SmallVector<CCValAssign, 16> ArgLocs;
1529 CCState CCInfo(CC, false, TM, ArgLocs, *Context);
1530 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1532 // Get a count of how many bytes are to be pushed on the stack.
1533 NumBytes = CCInfo.getNextStackOffset();
1535 // Issue CALLSEQ_START
1536 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1537 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1538 TII.get(AdjStackDown))
1541 // Process the args.
1542 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1543 CCValAssign &VA = ArgLocs[i];
1544 unsigned Arg = ArgRegs[VA.getValNo()];
1545 MVT ArgVT = ArgVTs[VA.getValNo()];
1547 // We don't handle NEON/vector parameters yet.
1548 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1551 // Handle arg promotion, etc.
1552 switch (VA.getLocInfo()) {
1553 case CCValAssign::Full: break;
1554 case CCValAssign::SExt: {
1555 bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1557 assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
1559 ArgVT = VA.getLocVT();
1562 case CCValAssign::ZExt: {
1563 bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1565 assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
1567 ArgVT = VA.getLocVT();
1570 case CCValAssign::AExt: {
1571 bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1574 Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1577 Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1580 assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
1581 ArgVT = VA.getLocVT();
1584 case CCValAssign::BCvt: {
1585 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1586 /*TODO: Kill=*/false);
1587 assert(BC != 0 && "Failed to emit a bitcast!");
1589 ArgVT = VA.getLocVT();
1592 default: llvm_unreachable("Unknown arg promotion!");
1595 // Now copy/store arg to correct locations.
1596 if (VA.isRegLoc() && !VA.needsCustom()) {
1597 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1600 RegArgs.push_back(VA.getLocReg());
1601 } else if (VA.needsCustom()) {
1602 // TODO: We need custom lowering for vector (v2f64) args.
1603 if (VA.getLocVT() != MVT::f64) return false;
1605 CCValAssign &NextVA = ArgLocs[++i];
1607 // TODO: Only handle register args for now.
1608 if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1610 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1611 TII.get(ARM::VMOVRRD), VA.getLocReg())
1612 .addReg(NextVA.getLocReg(), RegState::Define)
1614 RegArgs.push_back(VA.getLocReg());
1615 RegArgs.push_back(NextVA.getLocReg());
1617 assert(VA.isMemLoc());
1618 // Need to store on the stack.
1620 Addr.BaseType = Address::RegBase;
1621 Addr.Base.Reg = ARM::SP;
1622 Addr.Offset = VA.getLocMemOffset();
1624 if (!ARMEmitStore(ArgVT, Arg, Addr)) return false;
1630 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1631 const Instruction *I, CallingConv::ID CC,
1632 unsigned &NumBytes) {
1633 // Issue CALLSEQ_END
1634 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1635 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1636 TII.get(AdjStackUp))
1637 .addImm(NumBytes).addImm(0));
1639 // Now the return value.
1640 if (RetVT != MVT::isVoid) {
1641 SmallVector<CCValAssign, 16> RVLocs;
1642 CCState CCInfo(CC, false, TM, RVLocs, *Context);
1643 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1645 // Copy all of the result registers out of their specified physreg.
1646 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1647 // For this move we copy into two registers and then move into the
1648 // double fp reg we want.
1649 EVT DestVT = RVLocs[0].getValVT();
1650 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1651 unsigned ResultReg = createResultReg(DstRC);
1652 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1653 TII.get(ARM::VMOVDRR), ResultReg)
1654 .addReg(RVLocs[0].getLocReg())
1655 .addReg(RVLocs[1].getLocReg()));
1657 UsedRegs.push_back(RVLocs[0].getLocReg());
1658 UsedRegs.push_back(RVLocs[1].getLocReg());
1660 // Finally update the result.
1661 UpdateValueMap(I, ResultReg);
1663 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1664 EVT CopyVT = RVLocs[0].getValVT();
1665 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1667 unsigned ResultReg = createResultReg(DstRC);
1668 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1669 ResultReg).addReg(RVLocs[0].getLocReg());
1670 UsedRegs.push_back(RVLocs[0].getLocReg());
1672 // Finally update the result.
1673 UpdateValueMap(I, ResultReg);
1680 bool ARMFastISel::SelectRet(const Instruction *I) {
1681 const ReturnInst *Ret = cast<ReturnInst>(I);
1682 const Function &F = *I->getParent()->getParent();
1684 if (!FuncInfo.CanLowerReturn)
1690 CallingConv::ID CC = F.getCallingConv();
1691 if (Ret->getNumOperands() > 0) {
1692 SmallVector<ISD::OutputArg, 4> Outs;
1693 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
1696 // Analyze operands of the call, assigning locations to each operand.
1697 SmallVector<CCValAssign, 16> ValLocs;
1698 CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext());
1699 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
1701 const Value *RV = Ret->getOperand(0);
1702 unsigned Reg = getRegForValue(RV);
1706 // Only handle a single return value for now.
1707 if (ValLocs.size() != 1)
1710 CCValAssign &VA = ValLocs[0];
1712 // Don't bother handling odd stuff for now.
1713 if (VA.getLocInfo() != CCValAssign::Full)
1715 // Only handle register returns for now.
1718 // TODO: For now, don't try to handle cases where getLocInfo()
1719 // says Full but the types don't match.
1720 if (TLI.getValueType(RV->getType()) != VA.getValVT())
1724 unsigned SrcReg = Reg + VA.getValNo();
1725 unsigned DstReg = VA.getLocReg();
1726 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
1727 // Avoid a cross-class copy. This is very unlikely.
1728 if (!SrcRC->contains(DstReg))
1730 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1731 DstReg).addReg(SrcReg);
1733 // Mark the register as live out of the function.
1734 MRI.addLiveOut(VA.getLocReg());
1737 unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET;
1738 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1743 unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) {
1745 // Darwin needs the r9 versions of the opcodes.
1746 bool isDarwin = Subtarget->isTargetDarwin();
1748 return isDarwin ? ARM::tBLr9 : ARM::tBL;
1750 return isDarwin ? ARM::BLr9 : ARM::BL;
1754 // A quick function that will emit a call for a named libcall in F with the
1755 // vector of passed arguments for the Instruction in I. We can assume that we
1756 // can emit a call for any libcall we can produce. This is an abridged version
1757 // of the full call infrastructure since we won't need to worry about things
1758 // like computed function pointers or strange arguments at call sites.
1759 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1761 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1762 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1764 // Handle *simple* calls for now.
1765 const Type *RetTy = I->getType();
1767 if (RetTy->isVoidTy())
1768 RetVT = MVT::isVoid;
1769 else if (!isTypeLegal(RetTy, RetVT))
1772 // TODO: For now if we have long calls specified we don't handle the call.
1773 if (EnableARMLongCalls) return false;
1775 // Set up the argument vectors.
1776 SmallVector<Value*, 8> Args;
1777 SmallVector<unsigned, 8> ArgRegs;
1778 SmallVector<MVT, 8> ArgVTs;
1779 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1780 Args.reserve(I->getNumOperands());
1781 ArgRegs.reserve(I->getNumOperands());
1782 ArgVTs.reserve(I->getNumOperands());
1783 ArgFlags.reserve(I->getNumOperands());
1784 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1785 Value *Op = I->getOperand(i);
1786 unsigned Arg = getRegForValue(Op);
1787 if (Arg == 0) return false;
1789 const Type *ArgTy = Op->getType();
1791 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1793 ISD::ArgFlagsTy Flags;
1794 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1795 Flags.setOrigAlign(OriginalAlignment);
1798 ArgRegs.push_back(Arg);
1799 ArgVTs.push_back(ArgVT);
1800 ArgFlags.push_back(Flags);
1803 // Handle the arguments now that we've gotten them.
1804 SmallVector<unsigned, 4> RegArgs;
1806 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1809 // Issue the call, BLr9 for darwin, BL otherwise.
1810 // TODO: Turn this into the table of arm call ops.
1811 MachineInstrBuilder MIB;
1812 unsigned CallOpc = ARMSelectCallOp(NULL);
1814 // Explicitly adding the predicate here.
1815 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1817 .addExternalSymbol(TLI.getLibcallName(Call));
1819 // Explicitly adding the predicate here.
1820 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1822 .addExternalSymbol(TLI.getLibcallName(Call)));
1824 // Add implicit physical register uses to the call.
1825 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1826 MIB.addReg(RegArgs[i]);
1828 // Finish off the call including any return values.
1829 SmallVector<unsigned, 4> UsedRegs;
1830 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1832 // Set all unused physreg defs as dead.
1833 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1838 bool ARMFastISel::SelectCall(const Instruction *I) {
1839 const CallInst *CI = cast<CallInst>(I);
1840 const Value *Callee = CI->getCalledValue();
1842 // Can't handle inline asm or worry about intrinsics yet.
1843 if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1845 // Only handle global variable Callees.
1846 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1850 // Check the calling convention.
1851 ImmutableCallSite CS(CI);
1852 CallingConv::ID CC = CS.getCallingConv();
1854 // TODO: Avoid some calling conventions?
1856 // Let SDISel handle vararg functions.
1857 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1858 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1859 if (FTy->isVarArg())
1862 // Handle *simple* calls for now.
1863 const Type *RetTy = I->getType();
1865 if (RetTy->isVoidTy())
1866 RetVT = MVT::isVoid;
1867 else if (!isTypeLegal(RetTy, RetVT))
1870 // TODO: For now if we have long calls specified we don't handle the call.
1871 if (EnableARMLongCalls) return false;
1873 // Set up the argument vectors.
1874 SmallVector<Value*, 8> Args;
1875 SmallVector<unsigned, 8> ArgRegs;
1876 SmallVector<MVT, 8> ArgVTs;
1877 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1878 Args.reserve(CS.arg_size());
1879 ArgRegs.reserve(CS.arg_size());
1880 ArgVTs.reserve(CS.arg_size());
1881 ArgFlags.reserve(CS.arg_size());
1882 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1884 unsigned Arg = getRegForValue(*i);
1888 ISD::ArgFlagsTy Flags;
1889 unsigned AttrInd = i - CS.arg_begin() + 1;
1890 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1892 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1895 // FIXME: Only handle *easy* calls for now.
1896 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1897 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1898 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1899 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1902 const Type *ArgTy = (*i)->getType();
1904 if (!isTypeLegal(ArgTy, ArgVT))
1906 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1907 Flags.setOrigAlign(OriginalAlignment);
1910 ArgRegs.push_back(Arg);
1911 ArgVTs.push_back(ArgVT);
1912 ArgFlags.push_back(Flags);
1915 // Handle the arguments now that we've gotten them.
1916 SmallVector<unsigned, 4> RegArgs;
1918 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1921 // Issue the call, BLr9 for darwin, BL otherwise.
1922 // TODO: Turn this into the table of arm call ops.
1923 MachineInstrBuilder MIB;
1924 unsigned CallOpc = ARMSelectCallOp(GV);
1925 // Explicitly adding the predicate here.
1927 // Explicitly adding the predicate here.
1928 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1930 .addGlobalAddress(GV, 0, 0);
1932 // Explicitly adding the predicate here.
1933 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1935 .addGlobalAddress(GV, 0, 0));
1937 // Add implicit physical register uses to the call.
1938 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1939 MIB.addReg(RegArgs[i]);
1941 // Finish off the call including any return values.
1942 SmallVector<unsigned, 4> UsedRegs;
1943 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1945 // Set all unused physreg defs as dead.
1946 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1952 bool ARMFastISel::SelectIntCast(const Instruction *I) {
1953 // On ARM, in general, integer casts don't involve legal types; this code
1954 // handles promotable integers. The high bits for a type smaller than
1955 // the register size are assumed to be undefined.
1956 const Type *DestTy = I->getType();
1957 Value *Op = I->getOperand(0);
1958 const Type *SrcTy = Op->getType();
1961 SrcVT = TLI.getValueType(SrcTy, true);
1962 DestVT = TLI.getValueType(DestTy, true);
1964 if (isa<TruncInst>(I)) {
1965 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1967 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1970 unsigned SrcReg = getRegForValue(Op);
1971 if (!SrcReg) return false;
1973 // Because the high bits are undefined, a truncate doesn't generate
1975 UpdateValueMap(I, SrcReg);
1978 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1982 bool isZext = isa<ZExtInst>(I);
1983 bool isBoolZext = false;
1984 if (!SrcVT.isSimple())
1986 switch (SrcVT.getSimpleVT().SimpleTy) {
1987 default: return false;
1990 Opc = isThumb ? ARM::t2UXTHr : ARM::UXTHr;
1992 Opc = isThumb ? ARM::t2SXTHr : ARM::SXTHr;
1996 Opc = isThumb ? ARM::t2UXTBr : ARM::UXTBr;
1998 Opc = isThumb ? ARM::t2SXTBr : ARM::SXTBr;
2002 Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
2009 // FIXME: We could save an instruction in many cases by special-casing
2010 // load instructions.
2011 unsigned SrcReg = getRegForValue(Op);
2012 if (!SrcReg) return false;
2014 unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2015 MachineInstrBuilder MIB;
2016 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
2020 AddOptionalDefs(MIB);
2021 UpdateValueMap(I, DestReg);
2025 // TODO: SoftFP support.
2026 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2028 switch (I->getOpcode()) {
2029 case Instruction::Load:
2030 return SelectLoad(I);
2031 case Instruction::Store:
2032 return SelectStore(I);
2033 case Instruction::Br:
2034 return SelectBranch(I);
2035 case Instruction::ICmp:
2036 case Instruction::FCmp:
2037 return SelectCmp(I);
2038 case Instruction::FPExt:
2039 return SelectFPExt(I);
2040 case Instruction::FPTrunc:
2041 return SelectFPTrunc(I);
2042 case Instruction::SIToFP:
2043 return SelectSIToFP(I);
2044 case Instruction::FPToSI:
2045 return SelectFPToSI(I);
2046 case Instruction::FAdd:
2047 return SelectBinaryOp(I, ISD::FADD);
2048 case Instruction::FSub:
2049 return SelectBinaryOp(I, ISD::FSUB);
2050 case Instruction::FMul:
2051 return SelectBinaryOp(I, ISD::FMUL);
2052 case Instruction::SDiv:
2053 return SelectSDiv(I);
2054 case Instruction::SRem:
2055 return SelectSRem(I);
2056 case Instruction::Call:
2057 return SelectCall(I);
2058 case Instruction::Select:
2059 return SelectSelect(I);
2060 case Instruction::Ret:
2061 return SelectRet(I);
2062 case Instruction::Trunc:
2063 case Instruction::ZExt:
2064 case Instruction::SExt:
2065 return SelectIntCast(I);
2072 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
2073 // Completely untested on non-darwin.
2074 const TargetMachine &TM = funcInfo.MF->getTarget();
2076 // Darwin and thumb1 only for now.
2077 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2078 if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() &&
2079 !DisableARMFastISel)
2080 return new ARMFastISel(funcInfo);