1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "ARMConstantPoolValue.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/Analysis.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/FunctionLoweringInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineConstantPool.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineMemOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/Support/CallSite.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/GetElementPtrTypeIterator.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
51 DisableARMFastISel("disable-arm-fast-isel",
52 cl::desc("Turn off experimental ARM fast-isel support"),
53 cl::init(false), cl::Hidden);
57 class ARMFastISel : public FastISel {
59 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
60 /// make the right decision when generating code for different targets.
61 const ARMSubtarget *Subtarget;
62 const TargetMachine &TM;
63 const TargetInstrInfo &TII;
64 const TargetLowering &TLI;
67 // Convenience variables to avoid some queries.
72 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
74 TM(funcInfo.MF->getTarget()),
75 TII(*TM.getInstrInfo()),
76 TLI(*TM.getTargetLowering()) {
77 Subtarget = &TM.getSubtarget<ARMSubtarget>();
78 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
79 isThumb = AFI->isThumbFunction();
80 Context = &funcInfo.Fn->getContext();
83 // Code from FastISel.cpp.
84 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
85 const TargetRegisterClass *RC);
86 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
87 const TargetRegisterClass *RC,
88 unsigned Op0, bool Op0IsKill);
89 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
90 const TargetRegisterClass *RC,
91 unsigned Op0, bool Op0IsKill,
92 unsigned Op1, bool Op1IsKill);
93 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
94 const TargetRegisterClass *RC,
95 unsigned Op0, bool Op0IsKill,
97 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
98 const TargetRegisterClass *RC,
99 unsigned Op0, bool Op0IsKill,
100 const ConstantFP *FPImm);
101 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
102 const TargetRegisterClass *RC,
104 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
105 const TargetRegisterClass *RC,
106 unsigned Op0, bool Op0IsKill,
107 unsigned Op1, bool Op1IsKill,
109 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
110 unsigned Op0, bool Op0IsKill,
113 // Backend specific FastISel code.
114 virtual bool TargetSelectInstruction(const Instruction *I);
115 virtual unsigned TargetMaterializeConstant(const Constant *C);
116 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
118 #include "ARMGenFastISel.inc"
120 // Instruction selection routines.
122 bool SelectLoad(const Instruction *I);
123 bool SelectStore(const Instruction *I);
124 bool SelectBranch(const Instruction *I);
125 bool SelectCmp(const Instruction *I);
126 bool SelectFPExt(const Instruction *I);
127 bool SelectFPTrunc(const Instruction *I);
128 bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
129 bool SelectSIToFP(const Instruction *I);
130 bool SelectFPToSI(const Instruction *I);
131 bool SelectSDiv(const Instruction *I);
132 bool SelectSRem(const Instruction *I);
133 bool SelectCall(const Instruction *I);
134 bool SelectSelect(const Instruction *I);
135 bool SelectRet(const Instruction *I);
139 bool isTypeLegal(const Type *Ty, EVT &VT);
140 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
141 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Base, int Offset);
142 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Base, int Offset);
143 bool ARMComputeRegOffset(const Value *Obj, unsigned &Base, int &Offset);
144 void ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT);
145 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
146 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
147 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
148 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
149 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
151 // Call handling routines.
153 bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
154 unsigned &ResultReg);
155 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
156 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
157 SmallVectorImpl<unsigned> &ArgRegs,
158 SmallVectorImpl<EVT> &ArgVTs,
159 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
160 SmallVectorImpl<unsigned> &RegArgs,
163 bool FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
164 const Instruction *I, CallingConv::ID CC,
166 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
168 // OptionalDef handling routines.
170 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
171 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
174 } // end anonymous namespace
176 #include "ARMGenCallingConv.inc"
178 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
179 // we don't care about implicit defs here, just places we'll need to add a
180 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
181 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
182 const TargetInstrDesc &TID = MI->getDesc();
183 if (!TID.hasOptionalDef())
186 // Look to see if our OptionalDef is defining CPSR or CCR.
187 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
188 const MachineOperand &MO = MI->getOperand(i);
189 if (!MO.isReg() || !MO.isDef()) continue;
190 if (MO.getReg() == ARM::CPSR)
196 // If the machine is predicable go ahead and add the predicate operands, if
197 // it needs default CC operands add those.
198 const MachineInstrBuilder &
199 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
200 MachineInstr *MI = &*MIB;
202 // Do we use a predicate?
203 if (TII.isPredicable(MI))
206 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
207 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
209 if (DefinesOptionalPredicate(MI, &CPSR)) {
218 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
219 const TargetRegisterClass* RC) {
220 unsigned ResultReg = createResultReg(RC);
221 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
223 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
227 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
228 const TargetRegisterClass *RC,
229 unsigned Op0, bool Op0IsKill) {
230 unsigned ResultReg = createResultReg(RC);
231 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
233 if (II.getNumDefs() >= 1)
234 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
235 .addReg(Op0, Op0IsKill * RegState::Kill));
237 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
238 .addReg(Op0, Op0IsKill * RegState::Kill));
239 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
240 TII.get(TargetOpcode::COPY), ResultReg)
241 .addReg(II.ImplicitDefs[0]));
246 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
247 const TargetRegisterClass *RC,
248 unsigned Op0, bool Op0IsKill,
249 unsigned Op1, bool Op1IsKill) {
250 unsigned ResultReg = createResultReg(RC);
251 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
253 if (II.getNumDefs() >= 1)
254 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
255 .addReg(Op0, Op0IsKill * RegState::Kill)
256 .addReg(Op1, Op1IsKill * RegState::Kill));
258 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
259 .addReg(Op0, Op0IsKill * RegState::Kill)
260 .addReg(Op1, Op1IsKill * RegState::Kill));
261 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
262 TII.get(TargetOpcode::COPY), ResultReg)
263 .addReg(II.ImplicitDefs[0]));
268 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
269 const TargetRegisterClass *RC,
270 unsigned Op0, bool Op0IsKill,
272 unsigned ResultReg = createResultReg(RC);
273 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
275 if (II.getNumDefs() >= 1)
276 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
277 .addReg(Op0, Op0IsKill * RegState::Kill)
280 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
281 .addReg(Op0, Op0IsKill * RegState::Kill)
283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
284 TII.get(TargetOpcode::COPY), ResultReg)
285 .addReg(II.ImplicitDefs[0]));
290 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
291 const TargetRegisterClass *RC,
292 unsigned Op0, bool Op0IsKill,
293 const ConstantFP *FPImm) {
294 unsigned ResultReg = createResultReg(RC);
295 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
297 if (II.getNumDefs() >= 1)
298 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
299 .addReg(Op0, Op0IsKill * RegState::Kill)
302 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
303 .addReg(Op0, Op0IsKill * RegState::Kill)
305 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
306 TII.get(TargetOpcode::COPY), ResultReg)
307 .addReg(II.ImplicitDefs[0]));
312 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
313 const TargetRegisterClass *RC,
314 unsigned Op0, bool Op0IsKill,
315 unsigned Op1, bool Op1IsKill,
317 unsigned ResultReg = createResultReg(RC);
318 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
320 if (II.getNumDefs() >= 1)
321 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
322 .addReg(Op0, Op0IsKill * RegState::Kill)
323 .addReg(Op1, Op1IsKill * RegState::Kill)
326 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
327 .addReg(Op0, Op0IsKill * RegState::Kill)
328 .addReg(Op1, Op1IsKill * RegState::Kill)
330 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
331 TII.get(TargetOpcode::COPY), ResultReg)
332 .addReg(II.ImplicitDefs[0]));
337 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
338 const TargetRegisterClass *RC,
340 unsigned ResultReg = createResultReg(RC);
341 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
343 if (II.getNumDefs() >= 1)
344 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
347 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
349 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
350 TII.get(TargetOpcode::COPY), ResultReg)
351 .addReg(II.ImplicitDefs[0]));
356 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
357 unsigned Op0, bool Op0IsKill,
359 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
360 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
361 "Cannot yet extract from physregs");
362 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
363 DL, TII.get(TargetOpcode::COPY), ResultReg)
364 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
368 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
369 // checks from the various callers.
370 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
371 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
373 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
374 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
375 TII.get(ARM::VMOVRS), MoveReg)
380 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
381 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
383 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
384 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
385 TII.get(ARM::VMOVSR), MoveReg)
390 // For double width floating point we need to materialize two constants
391 // (the high and the low) into integer registers then use a move to get
392 // the combined constant into an FP reg.
393 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
394 const APFloat Val = CFP->getValueAPF();
395 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
397 // This checks to see if we can use VFP3 instructions to materialize
398 // a constant, otherwise we have to go through the constant pool.
399 if (TLI.isFPImmLegal(Val, VT)) {
400 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
401 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
402 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
408 // Require VFP2 for loading fp constants.
409 if (!Subtarget->hasVFP2()) return false;
411 // MachineConstantPool wants an explicit alignment.
412 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
414 // TODO: Figure out if this is correct.
415 Align = TD.getTypeAllocSize(CFP->getType());
417 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
418 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
419 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
421 // The extra reg is for addrmode5.
422 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
424 .addConstantPoolIndex(Idx)
429 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
431 // For now 32-bit only.
432 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
434 // MachineConstantPool wants an explicit alignment.
435 unsigned Align = TD.getPrefTypeAlignment(C->getType());
437 // TODO: Figure out if this is correct.
438 Align = TD.getTypeAllocSize(C->getType());
440 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
441 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
444 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
445 TII.get(ARM::t2LDRpci), DestReg)
446 .addConstantPoolIndex(Idx));
448 // The extra reg and immediate are for addrmode2.
449 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
450 TII.get(ARM::LDRcp), DestReg)
451 .addConstantPoolIndex(Idx)
457 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
458 // For now 32-bit only.
459 if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0;
461 Reloc::Model RelocM = TM.getRelocationModel();
463 // TODO: No external globals for now.
464 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
466 // TODO: Need more magic for ARM PIC.
467 if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
469 // MachineConstantPool wants an explicit alignment.
470 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
472 // TODO: Figure out if this is correct.
473 Align = TD.getTypeAllocSize(GV->getType());
477 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
478 unsigned Id = AFI->createConstPoolEntryUId();
479 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
480 ARMCP::CPValue, PCAdj);
481 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
484 MachineInstrBuilder MIB;
485 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
487 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
488 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
489 .addConstantPoolIndex(Idx);
490 if (RelocM == Reloc::PIC_)
493 // The extra reg and immediate are for addrmode2.
494 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
496 .addConstantPoolIndex(Idx)
497 .addReg(0).addImm(0);
499 AddOptionalDefs(MIB);
503 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
504 EVT VT = TLI.getValueType(C->getType(), true);
506 // Only handle simple types.
507 if (!VT.isSimple()) return 0;
509 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
510 return ARMMaterializeFP(CFP, VT);
511 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
512 return ARMMaterializeGV(GV, VT);
513 else if (isa<ConstantInt>(C))
514 return ARMMaterializeInt(C, VT);
519 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
520 // Don't handle dynamic allocas.
521 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
524 if (!isLoadTypeLegal(AI->getType(), VT)) return false;
526 DenseMap<const AllocaInst*, int>::iterator SI =
527 FuncInfo.StaticAllocaMap.find(AI);
529 // This will get lowered later into the correct offsets and registers
530 // via rewriteXFrameIndex.
531 if (SI != FuncInfo.StaticAllocaMap.end()) {
532 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
533 unsigned ResultReg = createResultReg(RC);
534 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
535 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
536 TII.get(Opc), ResultReg)
537 .addFrameIndex(SI->second)
545 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
546 VT = TLI.getValueType(Ty, true);
548 // Only handle simple types.
549 if (VT == MVT::Other || !VT.isSimple()) return false;
551 // Handle all legal types, i.e. a register that will directly hold this
553 return TLI.isTypeLegal(VT);
556 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
557 if (isTypeLegal(Ty, VT)) return true;
559 // If this is a type than can be sign or zero-extended to a basic operation
560 // go ahead and accept it now.
561 if (VT == MVT::i8 || VT == MVT::i16)
567 // Computes the Reg+Offset to get to an object.
568 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Base,
570 // Some boilerplate from the X86 FastISel.
571 const User *U = NULL;
572 unsigned Opcode = Instruction::UserOp1;
573 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
574 // Don't walk into other basic blocks; it's possible we haven't
575 // visited them yet, so the instructions may not yet be assigned
576 // virtual registers.
577 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
579 Opcode = I->getOpcode();
581 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
582 Opcode = C->getOpcode();
586 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
587 if (Ty->getAddressSpace() > 255)
588 // Fast instruction selection doesn't support the special
595 case Instruction::BitCast: {
596 // Look through bitcasts.
597 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
599 case Instruction::IntToPtr: {
600 // Look past no-op inttoptrs.
601 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
602 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
605 case Instruction::PtrToInt: {
606 // Look past no-op ptrtoints.
607 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
608 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
611 case Instruction::GetElementPtr: {
612 int SavedOffset = Offset;
613 unsigned SavedBase = Base;
614 int TmpOffset = Offset;
616 // Iterate through the GEP folding the constants into offsets where
618 gep_type_iterator GTI = gep_type_begin(U);
619 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
620 i != e; ++i, ++GTI) {
621 const Value *Op = *i;
622 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
623 const StructLayout *SL = TD.getStructLayout(STy);
624 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
625 TmpOffset += SL->getElementOffset(Idx);
627 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
628 SmallVector<const Value *, 4> Worklist;
629 Worklist.push_back(Op);
631 Op = Worklist.pop_back_val();
632 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
633 // Constant-offset addressing.
634 TmpOffset += CI->getSExtValue() * S;
635 } else if (isa<AddOperator>(Op) &&
636 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
637 // An add with a constant operand. Fold the constant.
639 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
640 TmpOffset += CI->getSExtValue() * S;
641 // Add the other operand back to the work list.
642 Worklist.push_back(cast<AddOperator>(Op)->getOperand(0));
644 goto unsupported_gep;
645 } while (!Worklist.empty());
649 // Try to grab the base operand now.
651 if (ARMComputeRegOffset(U->getOperand(0), Base, Offset)) return true;
653 // We failed, restore everything and try the other options.
654 Offset = SavedOffset;
660 case Instruction::Alloca: {
661 const AllocaInst *AI = cast<AllocaInst>(Obj);
662 unsigned Reg = TargetMaterializeAlloca(AI);
664 if (Reg == 0) return false;
671 // Materialize the global variable's address into a reg which can
672 // then be used later to load the variable.
673 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
674 unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
675 if (Tmp == 0) return false;
681 // Try to get this in a register if nothing else has worked.
682 if (Base == 0) Base = getRegForValue(Obj);
686 void ARMFastISel::ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT) {
688 assert(VT.isSimple() && "Non-simple types are invalid here!");
690 bool needsLowering = false;
691 switch (VT.getSimpleVT().SimpleTy) {
693 assert(false && "Unhandled load/store type!");
698 // Integer loads/stores handle 12-bit offsets.
699 needsLowering = ((Offset & 0xfff) != Offset);
703 // Floating point operands handle 8-bit offsets.
704 needsLowering = ((Offset & 0xff) != Offset);
708 // Since the offset is too large for the load/store instruction
709 // get the reg+offset into a register.
711 ARMCC::CondCodes Pred = ARMCC::AL;
712 unsigned PredReg = 0;
714 TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
715 ARM::GPRRegisterClass;
716 unsigned BaseReg = createResultReg(RC);
719 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
720 BaseReg, Base, Offset, Pred, PredReg,
721 static_cast<const ARMBaseInstrInfo&>(TII));
723 assert(AFI->isThumb2Function());
724 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
725 BaseReg, Base, Offset, Pred, PredReg,
726 static_cast<const ARMBaseInstrInfo&>(TII));
733 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
734 unsigned Base, int Offset) {
736 assert(VT.isSimple() && "Non-simple types are invalid here!");
738 TargetRegisterClass *RC;
739 bool isFloat = false;
740 switch (VT.getSimpleVT().SimpleTy) {
742 // This is mostly going to be Neon/vector support.
745 Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
746 RC = ARM::GPRRegisterClass;
749 Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
750 RC = ARM::GPRRegisterClass;
753 Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12;
754 RC = ARM::GPRRegisterClass;
758 RC = TLI.getRegClassFor(VT);
763 RC = TLI.getRegClassFor(VT);
768 ResultReg = createResultReg(RC);
770 ARMSimplifyRegOffset(Base, Offset, VT);
772 // addrmode5 output depends on the selection dag addressing dividing the
773 // offset by 4 that it then later multiplies. Do this here as well.
777 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
778 TII.get(Opc), ResultReg)
779 .addReg(Base).addImm(Offset));
783 bool ARMFastISel::SelectLoad(const Instruction *I) {
784 // Verify we have a legal type before going any further.
786 if (!isLoadTypeLegal(I->getType(), VT))
789 // Our register and offset with innocuous defaults.
793 // See if we can handle this as Reg + Offset
794 if (!ARMComputeRegOffset(I->getOperand(0), Base, Offset))
798 if (!ARMEmitLoad(VT, ResultReg, Base, Offset)) return false;
800 UpdateValueMap(I, ResultReg);
804 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
805 unsigned Base, int Offset) {
807 bool isFloat = false;
808 bool needReg0Op = false;
809 switch (VT.getSimpleVT().SimpleTy) {
810 default: return false;
813 StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
816 StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
820 StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
823 if (!Subtarget->hasVFP2()) return false;
828 if (!Subtarget->hasVFP2()) return false;
834 ARMSimplifyRegOffset(Base, Offset, VT);
836 // addrmode5 output depends on the selection dag addressing dividing the
837 // offset by 4 that it then later multiplies. Do this here as well.
842 // FIXME: The 'needReg0Op' bit goes away once STRH is converted to
843 // not use the mega-addrmode stuff.
845 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
847 .addReg(SrcReg).addReg(Base).addImm(Offset));
849 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
851 .addReg(SrcReg).addReg(Base).addReg(0).addImm(Offset));
856 bool ARMFastISel::SelectStore(const Instruction *I) {
857 Value *Op0 = I->getOperand(0);
860 // Yay type legalization
862 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
865 // Get the value to be stored into a register.
866 SrcReg = getRegForValue(Op0);
870 // Our register and offset with innocuous defaults.
874 // See if we can handle this as Reg + Offset
875 if (!ARMComputeRegOffset(I->getOperand(1), Base, Offset))
878 if (!ARMEmitStore(VT, SrcReg, Base, Offset)) return false;
883 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
885 // Needs two compares...
886 case CmpInst::FCMP_ONE:
887 case CmpInst::FCMP_UEQ:
889 assert(false && "Unhandled CmpInst::Predicate!");
891 case CmpInst::ICMP_EQ:
892 case CmpInst::FCMP_OEQ:
894 case CmpInst::ICMP_SGT:
895 case CmpInst::FCMP_OGT:
897 case CmpInst::ICMP_SGE:
898 case CmpInst::FCMP_OGE:
900 case CmpInst::ICMP_UGT:
901 case CmpInst::FCMP_UGT:
903 case CmpInst::FCMP_OLT:
905 case CmpInst::ICMP_ULE:
906 case CmpInst::FCMP_OLE:
908 case CmpInst::FCMP_ORD:
910 case CmpInst::FCMP_UNO:
912 case CmpInst::FCMP_UGE:
914 case CmpInst::ICMP_SLT:
915 case CmpInst::FCMP_ULT:
917 case CmpInst::ICMP_SLE:
918 case CmpInst::FCMP_ULE:
920 case CmpInst::FCMP_UNE:
921 case CmpInst::ICMP_NE:
923 case CmpInst::ICMP_UGE:
925 case CmpInst::ICMP_ULT:
930 bool ARMFastISel::SelectBranch(const Instruction *I) {
931 const BranchInst *BI = cast<BranchInst>(I);
932 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
933 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
935 // Simple branch support.
937 // If we can, avoid recomputing the compare - redoing it could lead to wonky
939 // TODO: Factor this out.
940 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
941 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
942 const Type *Ty = CI->getOperand(0)->getType();
943 EVT VT = TLI.getValueType(Ty);
944 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
945 if (isFloat && !Subtarget->hasVFP2())
950 switch (VT.getSimpleVT().SimpleTy) {
951 default: return false;
952 // TODO: Verify compares.
954 CmpOpc = ARM::VCMPES;
955 CondReg = ARM::FPSCR;
958 CmpOpc = ARM::VCMPED;
959 CondReg = ARM::FPSCR;
962 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
967 // Get the compare predicate.
968 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
970 // We may not handle every CC for now.
971 if (ARMPred == ARMCC::AL) return false;
973 unsigned Arg1 = getRegForValue(CI->getOperand(0));
974 if (Arg1 == 0) return false;
976 unsigned Arg2 = getRegForValue(CI->getOperand(1));
977 if (Arg2 == 0) return false;
979 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
981 .addReg(Arg1).addReg(Arg2));
983 // For floating point we need to move the result to a comparison register
984 // that we can then use for branches.
986 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
987 TII.get(ARM::FMSTAT)));
989 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
990 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
991 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
992 FastEmitBranch(FBB, DL);
993 FuncInfo.MBB->addSuccessor(TBB);
998 unsigned CmpReg = getRegForValue(BI->getCondition());
999 if (CmpReg == 0) return false;
1001 // Re-set the flags just in case.
1002 unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri;
1003 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1004 .addReg(CmpReg).addImm(1));
1006 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1007 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1008 .addMBB(TBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1009 FastEmitBranch(FBB, DL);
1010 FuncInfo.MBB->addSuccessor(TBB);
1014 bool ARMFastISel::SelectCmp(const Instruction *I) {
1015 const CmpInst *CI = cast<CmpInst>(I);
1018 const Type *Ty = CI->getOperand(0)->getType();
1019 if (!isTypeLegal(Ty, VT))
1022 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1023 if (isFloat && !Subtarget->hasVFP2())
1028 switch (VT.getSimpleVT().SimpleTy) {
1029 default: return false;
1030 // TODO: Verify compares.
1032 CmpOpc = ARM::VCMPES;
1033 CondReg = ARM::FPSCR;
1036 CmpOpc = ARM::VCMPED;
1037 CondReg = ARM::FPSCR;
1040 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1041 CondReg = ARM::CPSR;
1045 // Get the compare predicate.
1046 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1048 // We may not handle every CC for now.
1049 if (ARMPred == ARMCC::AL) return false;
1051 unsigned Arg1 = getRegForValue(CI->getOperand(0));
1052 if (Arg1 == 0) return false;
1054 unsigned Arg2 = getRegForValue(CI->getOperand(1));
1055 if (Arg2 == 0) return false;
1057 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1058 .addReg(Arg1).addReg(Arg2));
1060 // For floating point we need to move the result to a comparison register
1061 // that we can then use for branches.
1063 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1064 TII.get(ARM::FMSTAT)));
1066 // Now set a register based on the comparison. Explicitly set the predicates
1068 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1069 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1070 : ARM::GPRRegisterClass;
1071 unsigned DestReg = createResultReg(RC);
1073 = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1074 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1075 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1076 .addReg(ZeroReg).addImm(1)
1077 .addImm(ARMPred).addReg(CondReg);
1079 UpdateValueMap(I, DestReg);
1083 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1084 // Make sure we have VFP and that we're extending float to double.
1085 if (!Subtarget->hasVFP2()) return false;
1087 Value *V = I->getOperand(0);
1088 if (!I->getType()->isDoubleTy() ||
1089 !V->getType()->isFloatTy()) return false;
1091 unsigned Op = getRegForValue(V);
1092 if (Op == 0) return false;
1094 unsigned Result = createResultReg(ARM::DPRRegisterClass);
1095 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1096 TII.get(ARM::VCVTDS), Result)
1098 UpdateValueMap(I, Result);
1102 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1103 // Make sure we have VFP and that we're truncating double to float.
1104 if (!Subtarget->hasVFP2()) return false;
1106 Value *V = I->getOperand(0);
1107 if (!(I->getType()->isFloatTy() &&
1108 V->getType()->isDoubleTy())) return false;
1110 unsigned Op = getRegForValue(V);
1111 if (Op == 0) return false;
1113 unsigned Result = createResultReg(ARM::SPRRegisterClass);
1114 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1115 TII.get(ARM::VCVTSD), Result)
1117 UpdateValueMap(I, Result);
1121 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1122 // Make sure we have VFP.
1123 if (!Subtarget->hasVFP2()) return false;
1126 const Type *Ty = I->getType();
1127 if (!isTypeLegal(Ty, DstVT))
1130 unsigned Op = getRegForValue(I->getOperand(0));
1131 if (Op == 0) return false;
1133 // The conversion routine works on fp-reg to fp-reg and the operand above
1134 // was an integer, move it to the fp registers if possible.
1135 unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1136 if (FP == 0) return false;
1139 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1140 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1143 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1144 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1147 UpdateValueMap(I, ResultReg);
1151 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1152 // Make sure we have VFP.
1153 if (!Subtarget->hasVFP2()) return false;
1156 const Type *RetTy = I->getType();
1157 if (!isTypeLegal(RetTy, DstVT))
1160 unsigned Op = getRegForValue(I->getOperand(0));
1161 if (Op == 0) return false;
1164 const Type *OpTy = I->getOperand(0)->getType();
1165 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1166 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1169 // f64->s32 or f32->s32 both need an intermediate f32 reg.
1170 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1171 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1175 // This result needs to be in an integer register, but the conversion only
1176 // takes place in fp-regs.
1177 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1178 if (IntReg == 0) return false;
1180 UpdateValueMap(I, IntReg);
1184 bool ARMFastISel::SelectSelect(const Instruction *I) {
1185 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1186 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1189 // Things need to be register sized for register moves.
1190 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
1191 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1193 unsigned CondReg = getRegForValue(I->getOperand(0));
1194 if (CondReg == 0) return false;
1195 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1196 if (Op1Reg == 0) return false;
1197 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1198 if (Op2Reg == 0) return false;
1200 unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1201 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1202 .addReg(CondReg).addImm(1));
1203 unsigned ResultReg = createResultReg(RC);
1204 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1205 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1206 .addReg(Op1Reg).addReg(Op2Reg)
1207 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1208 UpdateValueMap(I, ResultReg);
1212 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1214 const Type *Ty = I->getType();
1215 if (!isTypeLegal(Ty, VT))
1218 // If we have integer div support we should have selected this automagically.
1219 // In case we have a real miss go ahead and return false and we'll pick
1221 if (Subtarget->hasDivide()) return false;
1223 // Otherwise emit a libcall.
1224 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1226 LC = RTLIB::SDIV_I8;
1227 else if (VT == MVT::i16)
1228 LC = RTLIB::SDIV_I16;
1229 else if (VT == MVT::i32)
1230 LC = RTLIB::SDIV_I32;
1231 else if (VT == MVT::i64)
1232 LC = RTLIB::SDIV_I64;
1233 else if (VT == MVT::i128)
1234 LC = RTLIB::SDIV_I128;
1235 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1237 return ARMEmitLibcall(I, LC);
1240 bool ARMFastISel::SelectSRem(const Instruction *I) {
1242 const Type *Ty = I->getType();
1243 if (!isTypeLegal(Ty, VT))
1246 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1248 LC = RTLIB::SREM_I8;
1249 else if (VT == MVT::i16)
1250 LC = RTLIB::SREM_I16;
1251 else if (VT == MVT::i32)
1252 LC = RTLIB::SREM_I32;
1253 else if (VT == MVT::i64)
1254 LC = RTLIB::SREM_I64;
1255 else if (VT == MVT::i128)
1256 LC = RTLIB::SREM_I128;
1257 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1259 return ARMEmitLibcall(I, LC);
1262 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1263 EVT VT = TLI.getValueType(I->getType(), true);
1265 // We can get here in the case when we want to use NEON for our fp
1266 // operations, but can't figure out how to. Just use the vfp instructions
1268 // FIXME: It'd be nice to use NEON instructions.
1269 const Type *Ty = I->getType();
1270 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1271 if (isFloat && !Subtarget->hasVFP2())
1274 unsigned Op1 = getRegForValue(I->getOperand(0));
1275 if (Op1 == 0) return false;
1277 unsigned Op2 = getRegForValue(I->getOperand(1));
1278 if (Op2 == 0) return false;
1281 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
1282 VT.getSimpleVT().SimpleTy == MVT::i64;
1283 switch (ISDOpcode) {
1284 default: return false;
1286 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1289 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1292 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1295 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1296 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1297 TII.get(Opc), ResultReg)
1298 .addReg(Op1).addReg(Op2));
1299 UpdateValueMap(I, ResultReg);
1303 // Call Handling Code
1305 bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src,
1306 EVT SrcVT, unsigned &ResultReg) {
1307 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1308 Src, /*TODO: Kill=*/false);
1317 // This is largely taken directly from CCAssignFnForNode - we don't support
1318 // varargs in FastISel so that part has been removed.
1319 // TODO: We may not support all of this.
1320 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1323 llvm_unreachable("Unsupported calling convention");
1324 case CallingConv::Fast:
1325 // Ignore fastcc. Silence compiler warnings.
1326 (void)RetFastCC_ARM_APCS;
1327 (void)FastCC_ARM_APCS;
1329 case CallingConv::C:
1330 // Use target triple & subtarget features to do actual dispatch.
1331 if (Subtarget->isAAPCS_ABI()) {
1332 if (Subtarget->hasVFP2() &&
1333 FloatABIType == FloatABI::Hard)
1334 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1336 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1338 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1339 case CallingConv::ARM_AAPCS_VFP:
1340 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1341 case CallingConv::ARM_AAPCS:
1342 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1343 case CallingConv::ARM_APCS:
1344 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1348 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1349 SmallVectorImpl<unsigned> &ArgRegs,
1350 SmallVectorImpl<EVT> &ArgVTs,
1351 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1352 SmallVectorImpl<unsigned> &RegArgs,
1354 unsigned &NumBytes) {
1355 SmallVector<CCValAssign, 16> ArgLocs;
1356 CCState CCInfo(CC, false, TM, ArgLocs, *Context);
1357 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1359 // Get a count of how many bytes are to be pushed on the stack.
1360 NumBytes = CCInfo.getNextStackOffset();
1362 // Issue CALLSEQ_START
1363 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1364 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1365 TII.get(AdjStackDown))
1368 // Process the args.
1369 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1370 CCValAssign &VA = ArgLocs[i];
1371 unsigned Arg = ArgRegs[VA.getValNo()];
1372 EVT ArgVT = ArgVTs[VA.getValNo()];
1374 // We don't handle NEON parameters yet.
1375 if (VA.getLocVT().isVector() && VA.getLocVT().getSizeInBits() > 64)
1378 // Handle arg promotion, etc.
1379 switch (VA.getLocInfo()) {
1380 case CCValAssign::Full: break;
1381 case CCValAssign::SExt: {
1382 bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1384 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1386 ArgVT = VA.getLocVT();
1389 case CCValAssign::ZExt: {
1390 bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1392 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1394 ArgVT = VA.getLocVT();
1397 case CCValAssign::AExt: {
1398 bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1401 Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1404 Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1407 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1408 ArgVT = VA.getLocVT();
1411 case CCValAssign::BCvt: {
1412 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(),
1413 VA.getLocVT().getSimpleVT(),
1414 ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false);
1415 assert(BC != 0 && "Failed to emit a bitcast!");
1417 ArgVT = VA.getLocVT();
1420 default: llvm_unreachable("Unknown arg promotion!");
1423 // Now copy/store arg to correct locations.
1424 if (VA.isRegLoc() && !VA.needsCustom()) {
1425 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1428 RegArgs.push_back(VA.getLocReg());
1429 } else if (VA.needsCustom()) {
1430 // TODO: We need custom lowering for vector (v2f64) args.
1431 if (VA.getLocVT() != MVT::f64) return false;
1433 CCValAssign &NextVA = ArgLocs[++i];
1435 // TODO: Only handle register args for now.
1436 if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1438 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1439 TII.get(ARM::VMOVRRD), VA.getLocReg())
1440 .addReg(NextVA.getLocReg(), RegState::Define)
1442 RegArgs.push_back(VA.getLocReg());
1443 RegArgs.push_back(NextVA.getLocReg());
1445 assert(VA.isMemLoc());
1446 // Need to store on the stack.
1447 unsigned Base = ARM::SP;
1448 int Offset = VA.getLocMemOffset();
1450 if (!ARMEmitStore(ArgVT, Arg, Base, Offset)) return false;
1456 bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1457 const Instruction *I, CallingConv::ID CC,
1458 unsigned &NumBytes) {
1459 // Issue CALLSEQ_END
1460 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1461 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1462 TII.get(AdjStackUp))
1463 .addImm(NumBytes).addImm(0));
1465 // Now the return value.
1466 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1467 SmallVector<CCValAssign, 16> RVLocs;
1468 CCState CCInfo(CC, false, TM, RVLocs, *Context);
1469 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1471 // Copy all of the result registers out of their specified physreg.
1472 if (RVLocs.size() == 2 && RetVT.getSimpleVT().SimpleTy == MVT::f64) {
1473 // For this move we copy into two registers and then move into the
1474 // double fp reg we want.
1475 EVT DestVT = RVLocs[0].getValVT();
1476 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1477 unsigned ResultReg = createResultReg(DstRC);
1478 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1479 TII.get(ARM::VMOVDRR), ResultReg)
1480 .addReg(RVLocs[0].getLocReg())
1481 .addReg(RVLocs[1].getLocReg()));
1483 UsedRegs.push_back(RVLocs[0].getLocReg());
1484 UsedRegs.push_back(RVLocs[1].getLocReg());
1486 // Finally update the result.
1487 UpdateValueMap(I, ResultReg);
1489 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1490 EVT CopyVT = RVLocs[0].getValVT();
1491 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1493 unsigned ResultReg = createResultReg(DstRC);
1494 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1495 ResultReg).addReg(RVLocs[0].getLocReg());
1496 UsedRegs.push_back(RVLocs[0].getLocReg());
1498 // Finally update the result.
1499 UpdateValueMap(I, ResultReg);
1506 bool ARMFastISel::SelectRet(const Instruction *I) {
1507 const ReturnInst *Ret = cast<ReturnInst>(I);
1508 const Function &F = *I->getParent()->getParent();
1510 if (!FuncInfo.CanLowerReturn)
1516 CallingConv::ID CC = F.getCallingConv();
1517 if (Ret->getNumOperands() > 0) {
1518 SmallVector<ISD::OutputArg, 4> Outs;
1519 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
1522 // Analyze operands of the call, assigning locations to each operand.
1523 SmallVector<CCValAssign, 16> ValLocs;
1524 CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext());
1525 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
1527 const Value *RV = Ret->getOperand(0);
1528 unsigned Reg = getRegForValue(RV);
1532 // Only handle a single return value for now.
1533 if (ValLocs.size() != 1)
1536 CCValAssign &VA = ValLocs[0];
1538 // Don't bother handling odd stuff for now.
1539 if (VA.getLocInfo() != CCValAssign::Full)
1541 // Only handle register returns for now.
1544 // TODO: For now, don't try to handle cases where getLocInfo()
1545 // says Full but the types don't match.
1546 if (VA.getValVT() != TLI.getValueType(RV->getType()))
1550 unsigned SrcReg = Reg + VA.getValNo();
1551 unsigned DstReg = VA.getLocReg();
1552 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
1553 // Avoid a cross-class copy. This is very unlikely.
1554 if (!SrcRC->contains(DstReg))
1556 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1557 DstReg).addReg(SrcReg);
1559 // Mark the register as live out of the function.
1560 MRI.addLiveOut(VA.getLocReg());
1563 unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET;
1564 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1569 // A quick function that will emit a call for a named libcall in F with the
1570 // vector of passed arguments for the Instruction in I. We can assume that we
1571 // can emit a call for any libcall we can produce. This is an abridged version
1572 // of the full call infrastructure since we won't need to worry about things
1573 // like computed function pointers or strange arguments at call sites.
1574 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1576 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1577 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1579 // Handle *simple* calls for now.
1580 const Type *RetTy = I->getType();
1582 if (RetTy->isVoidTy())
1583 RetVT = MVT::isVoid;
1584 else if (!isTypeLegal(RetTy, RetVT))
1587 // For now we're using BLX etc on the assumption that we have v5t ops.
1588 if (!Subtarget->hasV5TOps()) return false;
1590 // Set up the argument vectors.
1591 SmallVector<Value*, 8> Args;
1592 SmallVector<unsigned, 8> ArgRegs;
1593 SmallVector<EVT, 8> ArgVTs;
1594 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1595 Args.reserve(I->getNumOperands());
1596 ArgRegs.reserve(I->getNumOperands());
1597 ArgVTs.reserve(I->getNumOperands());
1598 ArgFlags.reserve(I->getNumOperands());
1599 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1600 Value *Op = I->getOperand(i);
1601 unsigned Arg = getRegForValue(Op);
1602 if (Arg == 0) return false;
1604 const Type *ArgTy = Op->getType();
1606 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1608 ISD::ArgFlagsTy Flags;
1609 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1610 Flags.setOrigAlign(OriginalAlignment);
1613 ArgRegs.push_back(Arg);
1614 ArgVTs.push_back(ArgVT);
1615 ArgFlags.push_back(Flags);
1618 // Handle the arguments now that we've gotten them.
1619 SmallVector<unsigned, 4> RegArgs;
1621 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1624 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1625 // TODO: Turn this into the table of arm call ops.
1626 MachineInstrBuilder MIB;
1629 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1631 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1632 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1633 .addExternalSymbol(TLI.getLibcallName(Call));
1635 // Add implicit physical register uses to the call.
1636 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1637 MIB.addReg(RegArgs[i]);
1639 // Finish off the call including any return values.
1640 SmallVector<unsigned, 4> UsedRegs;
1641 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1643 // Set all unused physreg defs as dead.
1644 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1649 bool ARMFastISel::SelectCall(const Instruction *I) {
1650 const CallInst *CI = cast<CallInst>(I);
1651 const Value *Callee = CI->getCalledValue();
1653 // Can't handle inline asm or worry about intrinsics yet.
1654 if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1656 // Only handle global variable Callees that are direct calls.
1657 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1658 if (!GV || Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()))
1661 // Check the calling convention.
1662 ImmutableCallSite CS(CI);
1663 CallingConv::ID CC = CS.getCallingConv();
1665 // TODO: Avoid some calling conventions?
1667 // Let SDISel handle vararg functions.
1668 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1669 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1670 if (FTy->isVarArg())
1673 // Handle *simple* calls for now.
1674 const Type *RetTy = I->getType();
1676 if (RetTy->isVoidTy())
1677 RetVT = MVT::isVoid;
1678 else if (!isTypeLegal(RetTy, RetVT))
1681 // For now we're using BLX etc on the assumption that we have v5t ops.
1683 if (!Subtarget->hasV5TOps()) return false;
1685 // Set up the argument vectors.
1686 SmallVector<Value*, 8> Args;
1687 SmallVector<unsigned, 8> ArgRegs;
1688 SmallVector<EVT, 8> ArgVTs;
1689 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1690 Args.reserve(CS.arg_size());
1691 ArgRegs.reserve(CS.arg_size());
1692 ArgVTs.reserve(CS.arg_size());
1693 ArgFlags.reserve(CS.arg_size());
1694 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1696 unsigned Arg = getRegForValue(*i);
1700 ISD::ArgFlagsTy Flags;
1701 unsigned AttrInd = i - CS.arg_begin() + 1;
1702 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1704 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1707 // FIXME: Only handle *easy* calls for now.
1708 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1709 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1710 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1711 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1714 const Type *ArgTy = (*i)->getType();
1716 if (!isTypeLegal(ArgTy, ArgVT))
1718 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1719 Flags.setOrigAlign(OriginalAlignment);
1722 ArgRegs.push_back(Arg);
1723 ArgVTs.push_back(ArgVT);
1724 ArgFlags.push_back(Flags);
1727 // Handle the arguments now that we've gotten them.
1728 SmallVector<unsigned, 4> RegArgs;
1730 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1733 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1734 // TODO: Turn this into the table of arm call ops.
1735 MachineInstrBuilder MIB;
1738 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1740 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1741 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1742 .addGlobalAddress(GV, 0, 0);
1744 // Add implicit physical register uses to the call.
1745 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1746 MIB.addReg(RegArgs[i]);
1748 // Finish off the call including any return values.
1749 SmallVector<unsigned, 4> UsedRegs;
1750 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1752 // Set all unused physreg defs as dead.
1753 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1759 // TODO: SoftFP support.
1760 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1761 // No Thumb-1 for now.
1762 if (isThumb && !AFI->isThumb2Function()) return false;
1764 switch (I->getOpcode()) {
1765 case Instruction::Load:
1766 return SelectLoad(I);
1767 case Instruction::Store:
1768 return SelectStore(I);
1769 case Instruction::Br:
1770 return SelectBranch(I);
1771 case Instruction::ICmp:
1772 case Instruction::FCmp:
1773 return SelectCmp(I);
1774 case Instruction::FPExt:
1775 return SelectFPExt(I);
1776 case Instruction::FPTrunc:
1777 return SelectFPTrunc(I);
1778 case Instruction::SIToFP:
1779 return SelectSIToFP(I);
1780 case Instruction::FPToSI:
1781 return SelectFPToSI(I);
1782 case Instruction::FAdd:
1783 return SelectBinaryOp(I, ISD::FADD);
1784 case Instruction::FSub:
1785 return SelectBinaryOp(I, ISD::FSUB);
1786 case Instruction::FMul:
1787 return SelectBinaryOp(I, ISD::FMUL);
1788 case Instruction::SDiv:
1789 return SelectSDiv(I);
1790 case Instruction::SRem:
1791 return SelectSRem(I);
1792 case Instruction::Call:
1793 return SelectCall(I);
1794 case Instruction::Select:
1795 return SelectSelect(I);
1796 case Instruction::Ret:
1797 return SelectRet(I);
1804 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1805 // Completely untested on non-darwin.
1806 const TargetMachine &TM = funcInfo.MF->getTarget();
1807 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
1808 if (Subtarget->isTargetDarwin() && !DisableARMFastISel)
1809 return new ARMFastISel(funcInfo);