1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "ARMConstantPoolValue.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/Analysis.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/FunctionLoweringInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineConstantPool.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineMemOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/Support/CallSite.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/GetElementPtrTypeIterator.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
51 DisableARMFastISel("disable-arm-fast-isel",
52 cl::desc("Turn off experimental ARM fast-isel support"),
53 cl::init(false), cl::Hidden);
57 class ARMFastISel : public FastISel {
59 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
60 /// make the right decision when generating code for different targets.
61 const ARMSubtarget *Subtarget;
62 const TargetMachine &TM;
63 const TargetInstrInfo &TII;
64 const TargetLowering &TLI;
67 // Convenience variables to avoid some queries.
72 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
74 TM(funcInfo.MF->getTarget()),
75 TII(*TM.getInstrInfo()),
76 TLI(*TM.getTargetLowering()) {
77 Subtarget = &TM.getSubtarget<ARMSubtarget>();
78 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
79 isThumb = AFI->isThumbFunction();
80 Context = &funcInfo.Fn->getContext();
83 // Code from FastISel.cpp.
84 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
85 const TargetRegisterClass *RC);
86 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
87 const TargetRegisterClass *RC,
88 unsigned Op0, bool Op0IsKill);
89 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
90 const TargetRegisterClass *RC,
91 unsigned Op0, bool Op0IsKill,
92 unsigned Op1, bool Op1IsKill);
93 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
94 const TargetRegisterClass *RC,
95 unsigned Op0, bool Op0IsKill,
97 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
98 const TargetRegisterClass *RC,
99 unsigned Op0, bool Op0IsKill,
100 const ConstantFP *FPImm);
101 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
102 const TargetRegisterClass *RC,
104 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
105 const TargetRegisterClass *RC,
106 unsigned Op0, bool Op0IsKill,
107 unsigned Op1, bool Op1IsKill,
109 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
110 unsigned Op0, bool Op0IsKill,
113 // Backend specific FastISel code.
114 virtual bool TargetSelectInstruction(const Instruction *I);
115 virtual unsigned TargetMaterializeConstant(const Constant *C);
116 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
118 #include "ARMGenFastISel.inc"
120 // Instruction selection routines.
122 bool SelectLoad(const Instruction *I);
123 bool SelectStore(const Instruction *I);
124 bool SelectBranch(const Instruction *I);
125 bool SelectCmp(const Instruction *I);
126 bool SelectFPExt(const Instruction *I);
127 bool SelectFPTrunc(const Instruction *I);
128 bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
129 bool SelectSIToFP(const Instruction *I);
130 bool SelectFPToSI(const Instruction *I);
131 bool SelectSDiv(const Instruction *I);
132 bool SelectSRem(const Instruction *I);
133 bool SelectCall(const Instruction *I);
134 bool SelectSelect(const Instruction *I);
135 bool SelectRet(const Instruction *I);
139 bool isTypeLegal(const Type *Ty, MVT &VT);
140 bool isLoadTypeLegal(const Type *Ty, MVT &VT);
141 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Base, int Offset);
142 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Base, int Offset);
143 bool ARMComputeRegOffset(const Value *Obj, unsigned &Base, int &Offset);
144 void ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT);
145 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
146 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
147 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
148 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
149 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
151 // Call handling routines.
153 bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
154 unsigned &ResultReg);
155 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
156 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
157 SmallVectorImpl<unsigned> &ArgRegs,
158 SmallVectorImpl<MVT> &ArgVTs,
159 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
160 SmallVectorImpl<unsigned> &RegArgs,
163 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
164 const Instruction *I, CallingConv::ID CC,
166 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
168 // OptionalDef handling routines.
170 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
171 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
174 } // end anonymous namespace
176 #include "ARMGenCallingConv.inc"
178 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
179 // we don't care about implicit defs here, just places we'll need to add a
180 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
181 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
182 const TargetInstrDesc &TID = MI->getDesc();
183 if (!TID.hasOptionalDef())
186 // Look to see if our OptionalDef is defining CPSR or CCR.
187 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
188 const MachineOperand &MO = MI->getOperand(i);
189 if (!MO.isReg() || !MO.isDef()) continue;
190 if (MO.getReg() == ARM::CPSR)
196 // If the machine is predicable go ahead and add the predicate operands, if
197 // it needs default CC operands add those.
198 // TODO: If we want to support thumb1 then we'll need to deal with optional
199 // CPSR defs that need to be added before the remaining operands. See s_cc_out
200 // for descriptions why.
201 const MachineInstrBuilder &
202 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
203 MachineInstr *MI = &*MIB;
205 // Do we use a predicate?
206 if (TII.isPredicable(MI))
209 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
210 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
212 if (DefinesOptionalPredicate(MI, &CPSR)) {
221 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
222 const TargetRegisterClass* RC) {
223 unsigned ResultReg = createResultReg(RC);
224 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
226 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
230 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
231 const TargetRegisterClass *RC,
232 unsigned Op0, bool Op0IsKill) {
233 unsigned ResultReg = createResultReg(RC);
234 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
236 if (II.getNumDefs() >= 1)
237 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
238 .addReg(Op0, Op0IsKill * RegState::Kill));
240 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
241 .addReg(Op0, Op0IsKill * RegState::Kill));
242 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
243 TII.get(TargetOpcode::COPY), ResultReg)
244 .addReg(II.ImplicitDefs[0]));
249 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
250 const TargetRegisterClass *RC,
251 unsigned Op0, bool Op0IsKill,
252 unsigned Op1, bool Op1IsKill) {
253 unsigned ResultReg = createResultReg(RC);
254 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
256 if (II.getNumDefs() >= 1)
257 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
258 .addReg(Op0, Op0IsKill * RegState::Kill)
259 .addReg(Op1, Op1IsKill * RegState::Kill));
261 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
262 .addReg(Op0, Op0IsKill * RegState::Kill)
263 .addReg(Op1, Op1IsKill * RegState::Kill));
264 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
265 TII.get(TargetOpcode::COPY), ResultReg)
266 .addReg(II.ImplicitDefs[0]));
271 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
272 const TargetRegisterClass *RC,
273 unsigned Op0, bool Op0IsKill,
275 unsigned ResultReg = createResultReg(RC);
276 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
278 if (II.getNumDefs() >= 1)
279 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
280 .addReg(Op0, Op0IsKill * RegState::Kill)
283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
284 .addReg(Op0, Op0IsKill * RegState::Kill)
286 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
287 TII.get(TargetOpcode::COPY), ResultReg)
288 .addReg(II.ImplicitDefs[0]));
293 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
294 const TargetRegisterClass *RC,
295 unsigned Op0, bool Op0IsKill,
296 const ConstantFP *FPImm) {
297 unsigned ResultReg = createResultReg(RC);
298 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
300 if (II.getNumDefs() >= 1)
301 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
302 .addReg(Op0, Op0IsKill * RegState::Kill)
305 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
306 .addReg(Op0, Op0IsKill * RegState::Kill)
308 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
309 TII.get(TargetOpcode::COPY), ResultReg)
310 .addReg(II.ImplicitDefs[0]));
315 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
316 const TargetRegisterClass *RC,
317 unsigned Op0, bool Op0IsKill,
318 unsigned Op1, bool Op1IsKill,
320 unsigned ResultReg = createResultReg(RC);
321 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
323 if (II.getNumDefs() >= 1)
324 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
325 .addReg(Op0, Op0IsKill * RegState::Kill)
326 .addReg(Op1, Op1IsKill * RegState::Kill)
329 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
330 .addReg(Op0, Op0IsKill * RegState::Kill)
331 .addReg(Op1, Op1IsKill * RegState::Kill)
333 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
334 TII.get(TargetOpcode::COPY), ResultReg)
335 .addReg(II.ImplicitDefs[0]));
340 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
341 const TargetRegisterClass *RC,
343 unsigned ResultReg = createResultReg(RC);
344 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
346 if (II.getNumDefs() >= 1)
347 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
350 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
352 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
353 TII.get(TargetOpcode::COPY), ResultReg)
354 .addReg(II.ImplicitDefs[0]));
359 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
360 unsigned Op0, bool Op0IsKill,
362 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
363 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
364 "Cannot yet extract from physregs");
365 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
366 DL, TII.get(TargetOpcode::COPY), ResultReg)
367 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
371 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
372 // checks from the various callers.
373 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
374 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
376 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
377 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
378 TII.get(ARM::VMOVRS), MoveReg)
383 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
384 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
386 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
387 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
388 TII.get(ARM::VMOVSR), MoveReg)
393 // For double width floating point we need to materialize two constants
394 // (the high and the low) into integer registers then use a move to get
395 // the combined constant into an FP reg.
396 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
397 const APFloat Val = CFP->getValueAPF();
398 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
400 // This checks to see if we can use VFP3 instructions to materialize
401 // a constant, otherwise we have to go through the constant pool.
402 if (TLI.isFPImmLegal(Val, VT)) {
403 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
404 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
405 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
411 // Require VFP2 for loading fp constants.
412 if (!Subtarget->hasVFP2()) return false;
414 // MachineConstantPool wants an explicit alignment.
415 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
417 // TODO: Figure out if this is correct.
418 Align = TD.getTypeAllocSize(CFP->getType());
420 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
421 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
422 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
424 // The extra reg is for addrmode5.
425 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
427 .addConstantPoolIndex(Idx)
432 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
434 // For now 32-bit only.
435 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
437 // MachineConstantPool wants an explicit alignment.
438 unsigned Align = TD.getPrefTypeAlignment(C->getType());
440 // TODO: Figure out if this is correct.
441 Align = TD.getTypeAllocSize(C->getType());
443 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
444 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
447 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
448 TII.get(ARM::t2LDRpci), DestReg)
449 .addConstantPoolIndex(Idx));
451 // The extra reg and immediate are for addrmode2.
452 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
453 TII.get(ARM::LDRcp), DestReg)
454 .addConstantPoolIndex(Idx)
460 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
461 // For now 32-bit only.
462 if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0;
464 Reloc::Model RelocM = TM.getRelocationModel();
466 // TODO: No external globals for now.
467 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
469 // TODO: Need more magic for ARM PIC.
470 if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
472 // MachineConstantPool wants an explicit alignment.
473 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
475 // TODO: Figure out if this is correct.
476 Align = TD.getTypeAllocSize(GV->getType());
480 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
481 unsigned Id = AFI->createConstPoolEntryUId();
482 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
483 ARMCP::CPValue, PCAdj);
484 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
487 MachineInstrBuilder MIB;
488 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
490 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
491 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
492 .addConstantPoolIndex(Idx);
493 if (RelocM == Reloc::PIC_)
496 // The extra reg and immediate are for addrmode2.
497 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
499 .addConstantPoolIndex(Idx)
500 .addReg(0).addImm(0);
502 AddOptionalDefs(MIB);
506 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
507 EVT VT = TLI.getValueType(C->getType(), true);
509 // Only handle simple types.
510 if (!VT.isSimple()) return 0;
512 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
513 return ARMMaterializeFP(CFP, VT);
514 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
515 return ARMMaterializeGV(GV, VT);
516 else if (isa<ConstantInt>(C))
517 return ARMMaterializeInt(C, VT);
522 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
523 // Don't handle dynamic allocas.
524 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
527 if (!isLoadTypeLegal(AI->getType(), VT)) return false;
529 DenseMap<const AllocaInst*, int>::iterator SI =
530 FuncInfo.StaticAllocaMap.find(AI);
532 // This will get lowered later into the correct offsets and registers
533 // via rewriteXFrameIndex.
534 if (SI != FuncInfo.StaticAllocaMap.end()) {
535 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
536 unsigned ResultReg = createResultReg(RC);
537 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
538 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
539 TII.get(Opc), ResultReg)
540 .addFrameIndex(SI->second)
548 bool ARMFastISel::isTypeLegal(const Type *Ty, MVT &VT) {
549 EVT evt = TLI.getValueType(Ty, true);
551 // Only handle simple types.
552 if (evt == MVT::Other || !evt.isSimple()) return false;
553 VT = evt.getSimpleVT();
555 // Handle all legal types, i.e. a register that will directly hold this
557 return TLI.isTypeLegal(VT);
560 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, MVT &VT) {
561 if (isTypeLegal(Ty, VT)) return true;
563 // If this is a type than can be sign or zero-extended to a basic operation
564 // go ahead and accept it now.
565 if (VT == MVT::i8 || VT == MVT::i16)
571 // Computes the Reg+Offset to get to an object.
572 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Base,
574 // Some boilerplate from the X86 FastISel.
575 const User *U = NULL;
576 unsigned Opcode = Instruction::UserOp1;
577 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
578 // Don't walk into other basic blocks; it's possible we haven't
579 // visited them yet, so the instructions may not yet be assigned
580 // virtual registers.
581 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
583 Opcode = I->getOpcode();
585 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
586 Opcode = C->getOpcode();
590 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
591 if (Ty->getAddressSpace() > 255)
592 // Fast instruction selection doesn't support the special
599 case Instruction::BitCast: {
600 // Look through bitcasts.
601 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
603 case Instruction::IntToPtr: {
604 // Look past no-op inttoptrs.
605 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
606 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
609 case Instruction::PtrToInt: {
610 // Look past no-op ptrtoints.
611 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
612 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
615 case Instruction::GetElementPtr: {
616 int SavedOffset = Offset;
617 unsigned SavedBase = Base;
618 int TmpOffset = Offset;
620 // Iterate through the GEP folding the constants into offsets where
622 gep_type_iterator GTI = gep_type_begin(U);
623 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
624 i != e; ++i, ++GTI) {
625 const Value *Op = *i;
626 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
627 const StructLayout *SL = TD.getStructLayout(STy);
628 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
629 TmpOffset += SL->getElementOffset(Idx);
631 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
632 SmallVector<const Value *, 4> Worklist;
633 Worklist.push_back(Op);
635 Op = Worklist.pop_back_val();
636 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
637 // Constant-offset addressing.
638 TmpOffset += CI->getSExtValue() * S;
639 } else if (isa<AddOperator>(Op) &&
640 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
641 // An add with a constant operand. Fold the constant.
643 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
644 TmpOffset += CI->getSExtValue() * S;
645 // Add the other operand back to the work list.
646 Worklist.push_back(cast<AddOperator>(Op)->getOperand(0));
648 goto unsupported_gep;
649 } while (!Worklist.empty());
653 // Try to grab the base operand now.
655 if (ARMComputeRegOffset(U->getOperand(0), Base, Offset)) return true;
657 // We failed, restore everything and try the other options.
658 Offset = SavedOffset;
664 case Instruction::Alloca: {
665 const AllocaInst *AI = cast<AllocaInst>(Obj);
666 unsigned Reg = TargetMaterializeAlloca(AI);
668 if (Reg == 0) return false;
675 // Materialize the global variable's address into a reg which can
676 // then be used later to load the variable.
677 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
678 unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
679 if (Tmp == 0) return false;
685 // Try to get this in a register if nothing else has worked.
686 if (Base == 0) Base = getRegForValue(Obj);
690 void ARMFastISel::ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT) {
692 assert(VT.isSimple() && "Non-simple types are invalid here!");
694 bool needsLowering = false;
695 switch (VT.getSimpleVT().SimpleTy) {
697 assert(false && "Unhandled load/store type!");
702 // Integer loads/stores handle 12-bit offsets.
703 needsLowering = ((Offset & 0xfff) != Offset);
707 // Floating point operands handle 8-bit offsets.
708 needsLowering = ((Offset & 0xff) != Offset);
712 // Since the offset is too large for the load/store instruction
713 // get the reg+offset into a register.
715 ARMCC::CondCodes Pred = ARMCC::AL;
716 unsigned PredReg = 0;
718 TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
719 ARM::GPRRegisterClass;
720 unsigned BaseReg = createResultReg(RC);
723 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
724 BaseReg, Base, Offset, Pred, PredReg,
725 static_cast<const ARMBaseInstrInfo&>(TII));
727 assert(AFI->isThumb2Function());
728 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
729 BaseReg, Base, Offset, Pred, PredReg,
730 static_cast<const ARMBaseInstrInfo&>(TII));
737 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
738 unsigned Base, int Offset) {
740 assert(VT.isSimple() && "Non-simple types are invalid here!");
742 TargetRegisterClass *RC;
743 bool isFloat = false;
744 switch (VT.getSimpleVT().SimpleTy) {
746 // This is mostly going to be Neon/vector support.
749 Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
750 RC = ARM::GPRRegisterClass;
753 Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
754 RC = ARM::GPRRegisterClass;
757 Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12;
758 RC = ARM::GPRRegisterClass;
762 RC = TLI.getRegClassFor(VT);
767 RC = TLI.getRegClassFor(VT);
772 ResultReg = createResultReg(RC);
774 ARMSimplifyRegOffset(Base, Offset, VT);
776 // addrmode5 output depends on the selection dag addressing dividing the
777 // offset by 4 that it then later multiplies. Do this here as well.
781 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
782 TII.get(Opc), ResultReg)
783 .addReg(Base).addImm(Offset));
787 bool ARMFastISel::SelectLoad(const Instruction *I) {
788 // Verify we have a legal type before going any further.
790 if (!isLoadTypeLegal(I->getType(), VT))
793 // Our register and offset with innocuous defaults.
797 // See if we can handle this as Reg + Offset
798 if (!ARMComputeRegOffset(I->getOperand(0), Base, Offset))
802 if (!ARMEmitLoad(VT, ResultReg, Base, Offset)) return false;
804 UpdateValueMap(I, ResultReg);
808 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
809 unsigned Base, int Offset) {
811 bool isFloat = false;
812 bool needReg0Op = false;
813 switch (VT.getSimpleVT().SimpleTy) {
814 default: return false;
816 unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass :
817 ARM::GPRRegisterClass);
818 unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
819 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
821 .addReg(SrcReg).addImm(1));
823 } // Fallthrough here.
825 StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
828 StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
832 StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
835 if (!Subtarget->hasVFP2()) return false;
840 if (!Subtarget->hasVFP2()) return false;
846 ARMSimplifyRegOffset(Base, Offset, VT);
848 // addrmode5 output depends on the selection dag addressing dividing the
849 // offset by 4 that it then later multiplies. Do this here as well.
853 // FIXME: The 'needReg0Op' bit goes away once STRH is converted to
854 // not use the mega-addrmode stuff.
856 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
858 .addReg(SrcReg).addReg(Base).addImm(Offset));
860 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
862 .addReg(SrcReg).addReg(Base).addReg(0).addImm(Offset));
867 bool ARMFastISel::SelectStore(const Instruction *I) {
868 Value *Op0 = I->getOperand(0);
871 // Yay type legalization
873 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
876 // Get the value to be stored into a register.
877 SrcReg = getRegForValue(Op0);
881 // Our register and offset with innocuous defaults.
885 // See if we can handle this as Reg + Offset
886 if (!ARMComputeRegOffset(I->getOperand(1), Base, Offset))
889 if (!ARMEmitStore(VT, SrcReg, Base, Offset)) return false;
894 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
896 // Needs two compares...
897 case CmpInst::FCMP_ONE:
898 case CmpInst::FCMP_UEQ:
900 // AL is our "false" for now. The other two need more compares.
902 case CmpInst::ICMP_EQ:
903 case CmpInst::FCMP_OEQ:
905 case CmpInst::ICMP_SGT:
906 case CmpInst::FCMP_OGT:
908 case CmpInst::ICMP_SGE:
909 case CmpInst::FCMP_OGE:
911 case CmpInst::ICMP_UGT:
912 case CmpInst::FCMP_UGT:
914 case CmpInst::FCMP_OLT:
916 case CmpInst::ICMP_ULE:
917 case CmpInst::FCMP_OLE:
919 case CmpInst::FCMP_ORD:
921 case CmpInst::FCMP_UNO:
923 case CmpInst::FCMP_UGE:
925 case CmpInst::ICMP_SLT:
926 case CmpInst::FCMP_ULT:
928 case CmpInst::ICMP_SLE:
929 case CmpInst::FCMP_ULE:
931 case CmpInst::FCMP_UNE:
932 case CmpInst::ICMP_NE:
934 case CmpInst::ICMP_UGE:
936 case CmpInst::ICMP_ULT:
941 bool ARMFastISel::SelectBranch(const Instruction *I) {
942 const BranchInst *BI = cast<BranchInst>(I);
943 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
944 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
946 // Simple branch support.
948 // If we can, avoid recomputing the compare - redoing it could lead to wonky
950 // TODO: Factor this out.
951 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
952 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
954 const Type *Ty = CI->getOperand(0)->getType();
955 if (!isTypeLegal(Ty, VT))
958 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
959 if (isFloat && !Subtarget->hasVFP2())
964 switch (VT.SimpleTy) {
965 default: return false;
966 // TODO: Verify compares.
968 CmpOpc = ARM::VCMPES;
969 CondReg = ARM::FPSCR;
972 CmpOpc = ARM::VCMPED;
973 CondReg = ARM::FPSCR;
976 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
981 // Get the compare predicate.
982 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
984 // We may not handle every CC for now.
985 if (ARMPred == ARMCC::AL) return false;
987 unsigned Arg1 = getRegForValue(CI->getOperand(0));
988 if (Arg1 == 0) return false;
990 unsigned Arg2 = getRegForValue(CI->getOperand(1));
991 if (Arg2 == 0) return false;
993 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
995 .addReg(Arg1).addReg(Arg2));
997 // For floating point we need to move the result to a comparison register
998 // that we can then use for branches.
1000 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1001 TII.get(ARM::FMSTAT)));
1003 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1004 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1005 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1006 FastEmitBranch(FBB, DL);
1007 FuncInfo.MBB->addSuccessor(TBB);
1012 unsigned CmpReg = getRegForValue(BI->getCondition());
1013 if (CmpReg == 0) return false;
1015 // Re-set the flags just in case.
1016 unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri;
1017 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1018 .addReg(CmpReg).addImm(0));
1020 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1021 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1022 .addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
1023 FastEmitBranch(FBB, DL);
1024 FuncInfo.MBB->addSuccessor(TBB);
1028 bool ARMFastISel::SelectCmp(const Instruction *I) {
1029 const CmpInst *CI = cast<CmpInst>(I);
1032 const Type *Ty = CI->getOperand(0)->getType();
1033 if (!isTypeLegal(Ty, VT))
1036 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1037 if (isFloat && !Subtarget->hasVFP2())
1042 switch (VT.SimpleTy) {
1043 default: return false;
1044 // TODO: Verify compares.
1046 CmpOpc = ARM::VCMPES;
1047 CondReg = ARM::FPSCR;
1050 CmpOpc = ARM::VCMPED;
1051 CondReg = ARM::FPSCR;
1054 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1055 CondReg = ARM::CPSR;
1059 // Get the compare predicate.
1060 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1062 // We may not handle every CC for now.
1063 if (ARMPred == ARMCC::AL) return false;
1065 unsigned Arg1 = getRegForValue(CI->getOperand(0));
1066 if (Arg1 == 0) return false;
1068 unsigned Arg2 = getRegForValue(CI->getOperand(1));
1069 if (Arg2 == 0) return false;
1071 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1072 .addReg(Arg1).addReg(Arg2));
1074 // For floating point we need to move the result to a comparison register
1075 // that we can then use for branches.
1077 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1078 TII.get(ARM::FMSTAT)));
1080 // Now set a register based on the comparison. Explicitly set the predicates
1082 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1083 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1084 : ARM::GPRRegisterClass;
1085 unsigned DestReg = createResultReg(RC);
1087 = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1088 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1089 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1090 .addReg(ZeroReg).addImm(1)
1091 .addImm(ARMPred).addReg(CondReg);
1093 UpdateValueMap(I, DestReg);
1097 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1098 // Make sure we have VFP and that we're extending float to double.
1099 if (!Subtarget->hasVFP2()) return false;
1101 Value *V = I->getOperand(0);
1102 if (!I->getType()->isDoubleTy() ||
1103 !V->getType()->isFloatTy()) return false;
1105 unsigned Op = getRegForValue(V);
1106 if (Op == 0) return false;
1108 unsigned Result = createResultReg(ARM::DPRRegisterClass);
1109 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1110 TII.get(ARM::VCVTDS), Result)
1112 UpdateValueMap(I, Result);
1116 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1117 // Make sure we have VFP and that we're truncating double to float.
1118 if (!Subtarget->hasVFP2()) return false;
1120 Value *V = I->getOperand(0);
1121 if (!(I->getType()->isFloatTy() &&
1122 V->getType()->isDoubleTy())) return false;
1124 unsigned Op = getRegForValue(V);
1125 if (Op == 0) return false;
1127 unsigned Result = createResultReg(ARM::SPRRegisterClass);
1128 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1129 TII.get(ARM::VCVTSD), Result)
1131 UpdateValueMap(I, Result);
1135 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1136 // Make sure we have VFP.
1137 if (!Subtarget->hasVFP2()) return false;
1140 const Type *Ty = I->getType();
1141 if (!isTypeLegal(Ty, DstVT))
1144 unsigned Op = getRegForValue(I->getOperand(0));
1145 if (Op == 0) return false;
1147 // The conversion routine works on fp-reg to fp-reg and the operand above
1148 // was an integer, move it to the fp registers if possible.
1149 unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1150 if (FP == 0) return false;
1153 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1154 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1157 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1158 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1161 UpdateValueMap(I, ResultReg);
1165 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1166 // Make sure we have VFP.
1167 if (!Subtarget->hasVFP2()) return false;
1170 const Type *RetTy = I->getType();
1171 if (!isTypeLegal(RetTy, DstVT))
1174 unsigned Op = getRegForValue(I->getOperand(0));
1175 if (Op == 0) return false;
1178 const Type *OpTy = I->getOperand(0)->getType();
1179 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1180 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1183 // f64->s32 or f32->s32 both need an intermediate f32 reg.
1184 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1185 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1189 // This result needs to be in an integer register, but the conversion only
1190 // takes place in fp-regs.
1191 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1192 if (IntReg == 0) return false;
1194 UpdateValueMap(I, IntReg);
1198 bool ARMFastISel::SelectSelect(const Instruction *I) {
1200 if (!isTypeLegal(I->getType(), VT))
1203 // Things need to be register sized for register moves.
1204 if (VT != MVT::i32) return false;
1205 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1207 unsigned CondReg = getRegForValue(I->getOperand(0));
1208 if (CondReg == 0) return false;
1209 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1210 if (Op1Reg == 0) return false;
1211 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1212 if (Op2Reg == 0) return false;
1214 unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1215 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1216 .addReg(CondReg).addImm(1));
1217 unsigned ResultReg = createResultReg(RC);
1218 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1219 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1220 .addReg(Op1Reg).addReg(Op2Reg)
1221 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1222 UpdateValueMap(I, ResultReg);
1226 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1228 const Type *Ty = I->getType();
1229 if (!isTypeLegal(Ty, VT))
1232 // If we have integer div support we should have selected this automagically.
1233 // In case we have a real miss go ahead and return false and we'll pick
1235 if (Subtarget->hasDivide()) return false;
1237 // Otherwise emit a libcall.
1238 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1240 LC = RTLIB::SDIV_I8;
1241 else if (VT == MVT::i16)
1242 LC = RTLIB::SDIV_I16;
1243 else if (VT == MVT::i32)
1244 LC = RTLIB::SDIV_I32;
1245 else if (VT == MVT::i64)
1246 LC = RTLIB::SDIV_I64;
1247 else if (VT == MVT::i128)
1248 LC = RTLIB::SDIV_I128;
1249 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1251 return ARMEmitLibcall(I, LC);
1254 bool ARMFastISel::SelectSRem(const Instruction *I) {
1256 const Type *Ty = I->getType();
1257 if (!isTypeLegal(Ty, VT))
1260 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1262 LC = RTLIB::SREM_I8;
1263 else if (VT == MVT::i16)
1264 LC = RTLIB::SREM_I16;
1265 else if (VT == MVT::i32)
1266 LC = RTLIB::SREM_I32;
1267 else if (VT == MVT::i64)
1268 LC = RTLIB::SREM_I64;
1269 else if (VT == MVT::i128)
1270 LC = RTLIB::SREM_I128;
1271 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1273 return ARMEmitLibcall(I, LC);
1276 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1277 EVT VT = TLI.getValueType(I->getType(), true);
1279 // We can get here in the case when we want to use NEON for our fp
1280 // operations, but can't figure out how to. Just use the vfp instructions
1282 // FIXME: It'd be nice to use NEON instructions.
1283 const Type *Ty = I->getType();
1284 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1285 if (isFloat && !Subtarget->hasVFP2())
1288 unsigned Op1 = getRegForValue(I->getOperand(0));
1289 if (Op1 == 0) return false;
1291 unsigned Op2 = getRegForValue(I->getOperand(1));
1292 if (Op2 == 0) return false;
1295 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
1296 VT.getSimpleVT().SimpleTy == MVT::i64;
1297 switch (ISDOpcode) {
1298 default: return false;
1300 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1303 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1306 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1309 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1310 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1311 TII.get(Opc), ResultReg)
1312 .addReg(Op1).addReg(Op2));
1313 UpdateValueMap(I, ResultReg);
1317 // Call Handling Code
1319 bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src,
1320 EVT SrcVT, unsigned &ResultReg) {
1321 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1322 Src, /*TODO: Kill=*/false);
1331 // This is largely taken directly from CCAssignFnForNode - we don't support
1332 // varargs in FastISel so that part has been removed.
1333 // TODO: We may not support all of this.
1334 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1337 llvm_unreachable("Unsupported calling convention");
1338 case CallingConv::Fast:
1339 // Ignore fastcc. Silence compiler warnings.
1340 (void)RetFastCC_ARM_APCS;
1341 (void)FastCC_ARM_APCS;
1343 case CallingConv::C:
1344 // Use target triple & subtarget features to do actual dispatch.
1345 if (Subtarget->isAAPCS_ABI()) {
1346 if (Subtarget->hasVFP2() &&
1347 FloatABIType == FloatABI::Hard)
1348 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1350 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1352 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1353 case CallingConv::ARM_AAPCS_VFP:
1354 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1355 case CallingConv::ARM_AAPCS:
1356 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1357 case CallingConv::ARM_APCS:
1358 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1362 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1363 SmallVectorImpl<unsigned> &ArgRegs,
1364 SmallVectorImpl<MVT> &ArgVTs,
1365 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1366 SmallVectorImpl<unsigned> &RegArgs,
1368 unsigned &NumBytes) {
1369 SmallVector<CCValAssign, 16> ArgLocs;
1370 CCState CCInfo(CC, false, TM, ArgLocs, *Context);
1371 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1373 // Get a count of how many bytes are to be pushed on the stack.
1374 NumBytes = CCInfo.getNextStackOffset();
1376 // Issue CALLSEQ_START
1377 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1378 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1379 TII.get(AdjStackDown))
1382 // Process the args.
1383 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1384 CCValAssign &VA = ArgLocs[i];
1385 unsigned Arg = ArgRegs[VA.getValNo()];
1386 MVT ArgVT = ArgVTs[VA.getValNo()];
1388 // We don't handle NEON parameters yet.
1389 if (VA.getLocVT().isVector() && VA.getLocVT().getSizeInBits() > 64)
1392 // Handle arg promotion, etc.
1393 switch (VA.getLocInfo()) {
1394 case CCValAssign::Full: break;
1395 case CCValAssign::SExt: {
1396 bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1398 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1400 ArgVT = VA.getLocVT();
1403 case CCValAssign::ZExt: {
1404 bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1406 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1408 ArgVT = VA.getLocVT();
1411 case CCValAssign::AExt: {
1412 bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1415 Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1418 Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1421 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1422 ArgVT = VA.getLocVT();
1425 case CCValAssign::BCvt: {
1426 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BIT_CONVERT, Arg,
1427 /*TODO: Kill=*/false);
1428 assert(BC != 0 && "Failed to emit a bitcast!");
1430 ArgVT = VA.getLocVT();
1433 default: llvm_unreachable("Unknown arg promotion!");
1436 // Now copy/store arg to correct locations.
1437 if (VA.isRegLoc() && !VA.needsCustom()) {
1438 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1441 RegArgs.push_back(VA.getLocReg());
1442 } else if (VA.needsCustom()) {
1443 // TODO: We need custom lowering for vector (v2f64) args.
1444 if (VA.getLocVT() != MVT::f64) return false;
1446 CCValAssign &NextVA = ArgLocs[++i];
1448 // TODO: Only handle register args for now.
1449 if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1451 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1452 TII.get(ARM::VMOVRRD), VA.getLocReg())
1453 .addReg(NextVA.getLocReg(), RegState::Define)
1455 RegArgs.push_back(VA.getLocReg());
1456 RegArgs.push_back(NextVA.getLocReg());
1458 assert(VA.isMemLoc());
1459 // Need to store on the stack.
1460 unsigned Base = ARM::SP;
1461 int Offset = VA.getLocMemOffset();
1463 if (!ARMEmitStore(ArgVT, Arg, Base, Offset)) return false;
1469 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1470 const Instruction *I, CallingConv::ID CC,
1471 unsigned &NumBytes) {
1472 // Issue CALLSEQ_END
1473 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1474 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1475 TII.get(AdjStackUp))
1476 .addImm(NumBytes).addImm(0));
1478 // Now the return value.
1479 if (RetVT != MVT::isVoid) {
1480 SmallVector<CCValAssign, 16> RVLocs;
1481 CCState CCInfo(CC, false, TM, RVLocs, *Context);
1482 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1484 // Copy all of the result registers out of their specified physreg.
1485 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1486 // For this move we copy into two registers and then move into the
1487 // double fp reg we want.
1488 EVT DestVT = RVLocs[0].getValVT();
1489 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1490 unsigned ResultReg = createResultReg(DstRC);
1491 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1492 TII.get(ARM::VMOVDRR), ResultReg)
1493 .addReg(RVLocs[0].getLocReg())
1494 .addReg(RVLocs[1].getLocReg()));
1496 UsedRegs.push_back(RVLocs[0].getLocReg());
1497 UsedRegs.push_back(RVLocs[1].getLocReg());
1499 // Finally update the result.
1500 UpdateValueMap(I, ResultReg);
1502 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1503 EVT CopyVT = RVLocs[0].getValVT();
1504 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1506 unsigned ResultReg = createResultReg(DstRC);
1507 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1508 ResultReg).addReg(RVLocs[0].getLocReg());
1509 UsedRegs.push_back(RVLocs[0].getLocReg());
1511 // Finally update the result.
1512 UpdateValueMap(I, ResultReg);
1519 bool ARMFastISel::SelectRet(const Instruction *I) {
1520 const ReturnInst *Ret = cast<ReturnInst>(I);
1521 const Function &F = *I->getParent()->getParent();
1523 if (!FuncInfo.CanLowerReturn)
1529 CallingConv::ID CC = F.getCallingConv();
1530 if (Ret->getNumOperands() > 0) {
1531 SmallVector<ISD::OutputArg, 4> Outs;
1532 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
1535 // Analyze operands of the call, assigning locations to each operand.
1536 SmallVector<CCValAssign, 16> ValLocs;
1537 CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext());
1538 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
1540 const Value *RV = Ret->getOperand(0);
1541 unsigned Reg = getRegForValue(RV);
1545 // Only handle a single return value for now.
1546 if (ValLocs.size() != 1)
1549 CCValAssign &VA = ValLocs[0];
1551 // Don't bother handling odd stuff for now.
1552 if (VA.getLocInfo() != CCValAssign::Full)
1554 // Only handle register returns for now.
1557 // TODO: For now, don't try to handle cases where getLocInfo()
1558 // says Full but the types don't match.
1559 if (VA.getValVT() != TLI.getValueType(RV->getType()))
1563 unsigned SrcReg = Reg + VA.getValNo();
1564 unsigned DstReg = VA.getLocReg();
1565 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
1566 // Avoid a cross-class copy. This is very unlikely.
1567 if (!SrcRC->contains(DstReg))
1569 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1570 DstReg).addReg(SrcReg);
1572 // Mark the register as live out of the function.
1573 MRI.addLiveOut(VA.getLocReg());
1576 unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET;
1577 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1582 // A quick function that will emit a call for a named libcall in F with the
1583 // vector of passed arguments for the Instruction in I. We can assume that we
1584 // can emit a call for any libcall we can produce. This is an abridged version
1585 // of the full call infrastructure since we won't need to worry about things
1586 // like computed function pointers or strange arguments at call sites.
1587 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1589 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1590 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1592 // Handle *simple* calls for now.
1593 const Type *RetTy = I->getType();
1595 if (RetTy->isVoidTy())
1596 RetVT = MVT::isVoid;
1597 else if (!isTypeLegal(RetTy, RetVT))
1600 // For now we're using BLX etc on the assumption that we have v5t ops.
1601 if (!Subtarget->hasV5TOps()) return false;
1603 // Set up the argument vectors.
1604 SmallVector<Value*, 8> Args;
1605 SmallVector<unsigned, 8> ArgRegs;
1606 SmallVector<MVT, 8> ArgVTs;
1607 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1608 Args.reserve(I->getNumOperands());
1609 ArgRegs.reserve(I->getNumOperands());
1610 ArgVTs.reserve(I->getNumOperands());
1611 ArgFlags.reserve(I->getNumOperands());
1612 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1613 Value *Op = I->getOperand(i);
1614 unsigned Arg = getRegForValue(Op);
1615 if (Arg == 0) return false;
1617 const Type *ArgTy = Op->getType();
1619 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1621 ISD::ArgFlagsTy Flags;
1622 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1623 Flags.setOrigAlign(OriginalAlignment);
1626 ArgRegs.push_back(Arg);
1627 ArgVTs.push_back(ArgVT);
1628 ArgFlags.push_back(Flags);
1631 // Handle the arguments now that we've gotten them.
1632 SmallVector<unsigned, 4> RegArgs;
1634 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1637 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1638 // TODO: Turn this into the table of arm call ops.
1639 MachineInstrBuilder MIB;
1642 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1644 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1645 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1646 .addExternalSymbol(TLI.getLibcallName(Call));
1648 // Add implicit physical register uses to the call.
1649 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1650 MIB.addReg(RegArgs[i]);
1652 // Finish off the call including any return values.
1653 SmallVector<unsigned, 4> UsedRegs;
1654 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1656 // Set all unused physreg defs as dead.
1657 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1662 bool ARMFastISel::SelectCall(const Instruction *I) {
1663 const CallInst *CI = cast<CallInst>(I);
1664 const Value *Callee = CI->getCalledValue();
1666 // Can't handle inline asm or worry about intrinsics yet.
1667 if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1669 // Only handle global variable Callees that are direct calls.
1670 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1671 if (!GV || Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()))
1674 // Check the calling convention.
1675 ImmutableCallSite CS(CI);
1676 CallingConv::ID CC = CS.getCallingConv();
1678 // TODO: Avoid some calling conventions?
1680 // Let SDISel handle vararg functions.
1681 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1682 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1683 if (FTy->isVarArg())
1686 // Handle *simple* calls for now.
1687 const Type *RetTy = I->getType();
1689 if (RetTy->isVoidTy())
1690 RetVT = MVT::isVoid;
1691 else if (!isTypeLegal(RetTy, RetVT))
1694 // For now we're using BLX etc on the assumption that we have v5t ops.
1696 if (!Subtarget->hasV5TOps()) return false;
1698 // Set up the argument vectors.
1699 SmallVector<Value*, 8> Args;
1700 SmallVector<unsigned, 8> ArgRegs;
1701 SmallVector<MVT, 8> ArgVTs;
1702 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1703 Args.reserve(CS.arg_size());
1704 ArgRegs.reserve(CS.arg_size());
1705 ArgVTs.reserve(CS.arg_size());
1706 ArgFlags.reserve(CS.arg_size());
1707 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1709 unsigned Arg = getRegForValue(*i);
1713 ISD::ArgFlagsTy Flags;
1714 unsigned AttrInd = i - CS.arg_begin() + 1;
1715 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1717 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1720 // FIXME: Only handle *easy* calls for now.
1721 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1722 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1723 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1724 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1727 const Type *ArgTy = (*i)->getType();
1729 if (!isTypeLegal(ArgTy, ArgVT))
1731 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1732 Flags.setOrigAlign(OriginalAlignment);
1735 ArgRegs.push_back(Arg);
1736 ArgVTs.push_back(ArgVT);
1737 ArgFlags.push_back(Flags);
1740 // Handle the arguments now that we've gotten them.
1741 SmallVector<unsigned, 4> RegArgs;
1743 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1746 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1747 // TODO: Turn this into the table of arm call ops.
1748 MachineInstrBuilder MIB;
1751 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1753 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1754 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1755 .addGlobalAddress(GV, 0, 0);
1757 // Add implicit physical register uses to the call.
1758 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1759 MIB.addReg(RegArgs[i]);
1761 // Finish off the call including any return values.
1762 SmallVector<unsigned, 4> UsedRegs;
1763 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1765 // Set all unused physreg defs as dead.
1766 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1772 // TODO: SoftFP support.
1773 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1775 switch (I->getOpcode()) {
1776 case Instruction::Load:
1777 return SelectLoad(I);
1778 case Instruction::Store:
1779 return SelectStore(I);
1780 case Instruction::Br:
1781 return SelectBranch(I);
1782 case Instruction::ICmp:
1783 case Instruction::FCmp:
1784 return SelectCmp(I);
1785 case Instruction::FPExt:
1786 return SelectFPExt(I);
1787 case Instruction::FPTrunc:
1788 return SelectFPTrunc(I);
1789 case Instruction::SIToFP:
1790 return SelectSIToFP(I);
1791 case Instruction::FPToSI:
1792 return SelectFPToSI(I);
1793 case Instruction::FAdd:
1794 return SelectBinaryOp(I, ISD::FADD);
1795 case Instruction::FSub:
1796 return SelectBinaryOp(I, ISD::FSUB);
1797 case Instruction::FMul:
1798 return SelectBinaryOp(I, ISD::FMUL);
1799 case Instruction::SDiv:
1800 return SelectSDiv(I);
1801 case Instruction::SRem:
1802 return SelectSRem(I);
1803 case Instruction::Call:
1804 return SelectCall(I);
1805 case Instruction::Select:
1806 return SelectSelect(I);
1807 case Instruction::Ret:
1808 return SelectRet(I);
1815 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1816 // Completely untested on non-darwin.
1817 const TargetMachine &TM = funcInfo.MF->getTarget();
1819 // Darwin and thumb1 only for now.
1820 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
1821 if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() &&
1822 !DisableARMFastISel)
1823 return new ARMFastISel(funcInfo);