1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMRegisterInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/Analysis.h"
27 #include "llvm/CodeGen/FastISel.h"
28 #include "llvm/CodeGen/FunctionLoweringInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineConstantPool.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/Support/CallSite.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/GetElementPtrTypeIterator.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
46 EnableARMFastISel("arm-fast-isel",
47 cl::desc("Turn on experimental ARM fast-isel support"),
48 cl::init(false), cl::Hidden);
52 class ARMFastISel : public FastISel {
54 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
55 /// make the right decision when generating code for different targets.
56 const ARMSubtarget *Subtarget;
57 const TargetMachine &TM;
58 const TargetInstrInfo &TII;
59 const TargetLowering &TLI;
60 const ARMFunctionInfo *AFI;
62 // FIXME: Remove this and replace it with queries.
63 const TargetRegisterClass *FixedRC;
66 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
68 TM(funcInfo.MF->getTarget()),
69 TII(*TM.getInstrInfo()),
70 TLI(*TM.getTargetLowering()) {
71 Subtarget = &TM.getSubtarget<ARMSubtarget>();
72 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
73 FixedRC = ARM::GPRRegisterClass;
76 // Code from FastISel.cpp.
77 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
78 const TargetRegisterClass *RC);
79 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
80 const TargetRegisterClass *RC,
81 unsigned Op0, bool Op0IsKill);
82 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
83 const TargetRegisterClass *RC,
84 unsigned Op0, bool Op0IsKill,
85 unsigned Op1, bool Op1IsKill);
86 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
87 const TargetRegisterClass *RC,
88 unsigned Op0, bool Op0IsKill,
90 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
91 const TargetRegisterClass *RC,
92 unsigned Op0, bool Op0IsKill,
93 const ConstantFP *FPImm);
94 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
95 const TargetRegisterClass *RC,
97 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
98 const TargetRegisterClass *RC,
99 unsigned Op0, bool Op0IsKill,
100 unsigned Op1, bool Op1IsKill,
102 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
103 unsigned Op0, bool Op0IsKill,
106 // Backend specific FastISel code.
107 virtual bool TargetSelectInstruction(const Instruction *I);
109 #include "ARMGenFastISel.inc"
111 // Instruction selection routines.
112 virtual bool ARMSelectLoad(const Instruction *I);
116 bool ARMLoadAlloca(const Instruction *I);
117 bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
119 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
120 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
123 } // end anonymous namespace
125 // #include "ARMGenCallingConv.inc"
127 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
128 // we don't care about implicit defs here, just places we'll need to add a
129 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
130 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
131 const TargetInstrDesc &TID = MI->getDesc();
132 if (!TID.hasOptionalDef())
135 // Look to see if our OptionalDef is defining CPSR or CCR.
136 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
137 const MachineOperand &MO = MI->getOperand(i);
138 if (!MO.isReg() || !MO.isDef()) continue;
139 if (MO.getReg() == ARM::CPSR)
145 // If the machine is predicable go ahead and add the predicate operands, if
146 // it needs default CC operands add those.
147 const MachineInstrBuilder &
148 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
149 MachineInstr *MI = &*MIB;
151 // Do we use a predicate?
152 if (TII.isPredicable(MI))
155 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
156 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
158 if (DefinesOptionalPredicate(MI, &CPSR)) {
167 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
168 const TargetRegisterClass* RC) {
169 unsigned ResultReg = createResultReg(RC);
170 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
172 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
176 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
177 const TargetRegisterClass *RC,
178 unsigned Op0, bool Op0IsKill) {
179 unsigned ResultReg = createResultReg(RC);
180 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
182 if (II.getNumDefs() >= 1)
183 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
184 .addReg(Op0, Op0IsKill * RegState::Kill));
186 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
187 .addReg(Op0, Op0IsKill * RegState::Kill));
188 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
189 TII.get(TargetOpcode::COPY), ResultReg)
190 .addReg(II.ImplicitDefs[0]));
195 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
196 const TargetRegisterClass *RC,
197 unsigned Op0, bool Op0IsKill,
198 unsigned Op1, bool Op1IsKill) {
199 unsigned ResultReg = createResultReg(RC);
200 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
202 if (II.getNumDefs() >= 1)
203 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
204 .addReg(Op0, Op0IsKill * RegState::Kill)
205 .addReg(Op1, Op1IsKill * RegState::Kill));
207 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
208 .addReg(Op0, Op0IsKill * RegState::Kill)
209 .addReg(Op1, Op1IsKill * RegState::Kill));
210 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
211 TII.get(TargetOpcode::COPY), ResultReg)
212 .addReg(II.ImplicitDefs[0]));
217 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
218 const TargetRegisterClass *RC,
219 unsigned Op0, bool Op0IsKill,
221 unsigned ResultReg = createResultReg(RC);
222 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
224 if (II.getNumDefs() >= 1)
225 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
226 .addReg(Op0, Op0IsKill * RegState::Kill)
229 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
230 .addReg(Op0, Op0IsKill * RegState::Kill)
232 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
233 TII.get(TargetOpcode::COPY), ResultReg)
234 .addReg(II.ImplicitDefs[0]));
239 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
240 const TargetRegisterClass *RC,
241 unsigned Op0, bool Op0IsKill,
242 const ConstantFP *FPImm) {
243 unsigned ResultReg = createResultReg(RC);
244 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
246 if (II.getNumDefs() >= 1)
247 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
248 .addReg(Op0, Op0IsKill * RegState::Kill)
251 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
252 .addReg(Op0, Op0IsKill * RegState::Kill)
254 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
255 TII.get(TargetOpcode::COPY), ResultReg)
256 .addReg(II.ImplicitDefs[0]));
261 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
262 const TargetRegisterClass *RC,
263 unsigned Op0, bool Op0IsKill,
264 unsigned Op1, bool Op1IsKill,
266 unsigned ResultReg = createResultReg(RC);
267 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
269 if (II.getNumDefs() >= 1)
270 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
271 .addReg(Op0, Op0IsKill * RegState::Kill)
272 .addReg(Op1, Op1IsKill * RegState::Kill)
275 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
276 .addReg(Op0, Op0IsKill * RegState::Kill)
277 .addReg(Op1, Op1IsKill * RegState::Kill)
279 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
280 TII.get(TargetOpcode::COPY), ResultReg)
281 .addReg(II.ImplicitDefs[0]));
286 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
287 const TargetRegisterClass *RC,
289 unsigned ResultReg = createResultReg(RC);
290 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
292 if (II.getNumDefs() >= 1)
293 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
296 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
298 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
299 TII.get(TargetOpcode::COPY), ResultReg)
300 .addReg(II.ImplicitDefs[0]));
305 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
306 unsigned Op0, bool Op0IsKill,
308 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
309 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
310 "Cannot yet extract from physregs");
311 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
312 DL, TII.get(TargetOpcode::COPY), ResultReg)
313 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
317 // Computes the Reg+Offset to get to an object.
318 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
320 // Some boilerplate from the X86 FastISel.
321 const User *U = NULL;
322 unsigned Opcode = Instruction::UserOp1;
323 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
324 // Don't walk into other basic blocks; it's possible we haven't
325 // visited them yet, so the instructions may not yet be assigned
326 // virtual registers.
327 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
330 Opcode = I->getOpcode();
332 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
333 Opcode = C->getOpcode();
337 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
338 if (Ty->getAddressSpace() > 255)
339 // Fast instruction selection doesn't support the special
345 //errs() << "Failing Opcode is: " << *Op1 << "\n";
347 case Instruction::Alloca: {
348 assert(false && "Alloca should have been handled earlier!");
353 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
354 //errs() << "Failing GV is: " << GV << "\n";
359 // Try to get this in a register if nothing else has worked.
360 Reg = getRegForValue(Obj);
364 bool ARMFastISel::ARMLoadAlloca(const Instruction *I) {
365 Value *Op0 = I->getOperand(0);
367 // Verify it's an alloca.
368 const Instruction *Inst = dyn_cast<Instruction>(Op0);
369 if (!Inst || Inst->getOpcode() != Instruction::Alloca) return false;
371 const AllocaInst *AI = cast<AllocaInst>(Op0);
372 DenseMap<const AllocaInst*, int>::iterator SI =
373 FuncInfo.StaticAllocaMap.find(AI);
375 if (SI != FuncInfo.StaticAllocaMap.end()) {
376 unsigned ResultReg = createResultReg(FixedRC);
377 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
378 ResultReg, SI->second, FixedRC,
379 TM.getRegisterInfo());
380 UpdateValueMap(I, ResultReg);
387 bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
388 // Our register and offset with innocuous defaults.
392 // TODO: Think about using loadRegFromStackSlot() here when we can.
393 if (ARMLoadAlloca(I))
396 // See if we can handle this as Reg + Offset
397 if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
400 // Since the offset may be too large for the load instruction
401 // get the reg+offset into a register.
402 // TODO: Optimize this somewhat.
403 ARMCC::CondCodes Pred = ARMCC::AL;
404 unsigned PredReg = 0;
406 if (!AFI->isThumbFunction())
407 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
408 Reg, Reg, Offset, Pred, PredReg,
409 static_cast<const ARMBaseInstrInfo&>(TII));
411 assert(AFI->isThumb2Function());
412 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
413 Reg, Reg, Offset, Pred, PredReg,
414 static_cast<const ARMBaseInstrInfo&>(TII));
417 // FIXME: There is more than one register class in the world...
418 // TODO: Verify the additions above work, otherwise we'll need to add the
419 // offset instead of 0 and do all sorts of operand munging.
420 unsigned ResultReg = createResultReg(FixedRC);
421 unsigned Opc = AFI->isThumb2Function() ? ARM::tLDR : ARM::LDR;
422 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
423 TII.get(Opc), ResultReg)
424 .addReg(Reg).addReg(0).addImm(0));
425 UpdateValueMap(I, ResultReg);
430 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
431 // No Thumb-1 for now.
432 if (AFI->isThumbFunction() && !AFI->isThumb2Function()) return false;
434 switch (I->getOpcode()) {
435 case Instruction::Load:
436 return ARMSelectLoad(I);
443 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
444 if (EnableARMFastISel) return new ARMFastISel(funcInfo);