1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMSubtarget.h"
21 #include "ARMConstantPoolValue.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/Operator.h"
30 #include "llvm/CodeGen/Analysis.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/FunctionLoweringInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineConstantPool.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineMemOperand.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/Support/CallSite.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/GetElementPtrTypeIterator.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
50 extern cl::opt<bool> EnableARMLongCalls;
54 // All possible address modes, plus some.
55 typedef struct Address {
68 // Innocuous defaults for our address.
70 : BaseType(RegBase), Offset(0) {
75 class ARMFastISel : public FastISel {
77 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
78 /// make the right decision when generating code for different targets.
79 const ARMSubtarget *Subtarget;
80 const TargetMachine &TM;
81 const TargetInstrInfo &TII;
82 const TargetLowering &TLI;
85 // Convenience variables to avoid some queries.
90 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
91 const TargetLibraryInfo *libInfo)
92 : FastISel(funcInfo, libInfo),
93 TM(funcInfo.MF->getTarget()),
94 TII(*TM.getInstrInfo()),
95 TLI(*TM.getTargetLowering()) {
96 Subtarget = &TM.getSubtarget<ARMSubtarget>();
97 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
98 isThumb2 = AFI->isThumbFunction();
99 Context = &funcInfo.Fn->getContext();
102 // Code from FastISel.cpp.
103 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
104 const TargetRegisterClass *RC);
105 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
106 const TargetRegisterClass *RC,
107 unsigned Op0, bool Op0IsKill);
108 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
109 const TargetRegisterClass *RC,
110 unsigned Op0, bool Op0IsKill,
111 unsigned Op1, bool Op1IsKill);
112 virtual unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
113 const TargetRegisterClass *RC,
114 unsigned Op0, bool Op0IsKill,
115 unsigned Op1, bool Op1IsKill,
116 unsigned Op2, bool Op2IsKill);
117 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
118 const TargetRegisterClass *RC,
119 unsigned Op0, bool Op0IsKill,
121 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
122 const TargetRegisterClass *RC,
123 unsigned Op0, bool Op0IsKill,
124 const ConstantFP *FPImm);
125 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
126 const TargetRegisterClass *RC,
127 unsigned Op0, bool Op0IsKill,
128 unsigned Op1, bool Op1IsKill,
130 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
131 const TargetRegisterClass *RC,
133 virtual unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
134 const TargetRegisterClass *RC,
135 uint64_t Imm1, uint64_t Imm2);
137 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
138 unsigned Op0, bool Op0IsKill,
141 // Backend specific FastISel code.
142 virtual bool TargetSelectInstruction(const Instruction *I);
143 virtual unsigned TargetMaterializeConstant(const Constant *C);
144 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
145 virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
148 #include "ARMGenFastISel.inc"
150 // Instruction selection routines.
152 bool SelectLoad(const Instruction *I);
153 bool SelectStore(const Instruction *I);
154 bool SelectBranch(const Instruction *I);
155 bool SelectIndirectBr(const Instruction *I);
156 bool SelectCmp(const Instruction *I);
157 bool SelectFPExt(const Instruction *I);
158 bool SelectFPTrunc(const Instruction *I);
159 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
160 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
161 bool SelectIToFP(const Instruction *I, bool isSigned);
162 bool SelectFPToI(const Instruction *I, bool isSigned);
163 bool SelectDiv(const Instruction *I, bool isSigned);
164 bool SelectRem(const Instruction *I, bool isSigned);
165 bool SelectCall(const Instruction *I, const char *IntrMemName);
166 bool SelectIntrinsicCall(const IntrinsicInst &I);
167 bool SelectSelect(const Instruction *I);
168 bool SelectRet(const Instruction *I);
169 bool SelectTrunc(const Instruction *I);
170 bool SelectIntExt(const Instruction *I);
171 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
175 bool isTypeLegal(Type *Ty, MVT &VT);
176 bool isLoadTypeLegal(Type *Ty, MVT &VT);
177 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
179 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
180 unsigned Alignment = 0, bool isZExt = true,
181 bool allocReg = true);
182 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
183 unsigned Alignment = 0);
184 bool ARMComputeAddress(const Value *Obj, Address &Addr);
185 void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
186 bool ARMIsMemCpySmall(uint64_t Len);
187 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len);
188 unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
189 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
190 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
191 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
192 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
193 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
194 unsigned ARMSelectCallOp(bool UseReg);
196 // Call handling routines.
198 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
201 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
202 SmallVectorImpl<unsigned> &ArgRegs,
203 SmallVectorImpl<MVT> &ArgVTs,
204 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
205 SmallVectorImpl<unsigned> &RegArgs,
209 unsigned getLibcallReg(const Twine &Name);
210 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
211 const Instruction *I, CallingConv::ID CC,
212 unsigned &NumBytes, bool isVarArg);
213 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
215 // OptionalDef handling routines.
217 bool isARMNEONPred(const MachineInstr *MI);
218 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
219 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
220 void AddLoadStoreOperands(EVT VT, Address &Addr,
221 const MachineInstrBuilder &MIB,
222 unsigned Flags, bool useAM3);
225 } // end anonymous namespace
227 #include "ARMGenCallingConv.inc"
229 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
230 // we don't care about implicit defs here, just places we'll need to add a
231 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
232 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
233 if (!MI->hasOptionalDef())
236 // Look to see if our OptionalDef is defining CPSR or CCR.
237 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
238 const MachineOperand &MO = MI->getOperand(i);
239 if (!MO.isReg() || !MO.isDef()) continue;
240 if (MO.getReg() == ARM::CPSR)
246 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
247 const MCInstrDesc &MCID = MI->getDesc();
249 // If we're a thumb2 or not NEON function we were handled via isPredicable.
250 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
251 AFI->isThumb2Function())
254 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
255 if (MCID.OpInfo[i].isPredicate())
261 // If the machine is predicable go ahead and add the predicate operands, if
262 // it needs default CC operands add those.
263 // TODO: If we want to support thumb1 then we'll need to deal with optional
264 // CPSR defs that need to be added before the remaining operands. See s_cc_out
265 // for descriptions why.
266 const MachineInstrBuilder &
267 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
268 MachineInstr *MI = &*MIB;
270 // Do we use a predicate? or...
271 // Are we NEON in ARM mode and have a predicate operand? If so, I know
272 // we're not predicable but add it anyways.
273 if (TII.isPredicable(MI) || isARMNEONPred(MI))
276 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
277 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
279 if (DefinesOptionalPredicate(MI, &CPSR)) {
288 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
289 const TargetRegisterClass* RC) {
290 unsigned ResultReg = createResultReg(RC);
291 const MCInstrDesc &II = TII.get(MachineInstOpcode);
293 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
297 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
298 const TargetRegisterClass *RC,
299 unsigned Op0, bool Op0IsKill) {
300 unsigned ResultReg = createResultReg(RC);
301 const MCInstrDesc &II = TII.get(MachineInstOpcode);
303 if (II.getNumDefs() >= 1) {
304 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
305 .addReg(Op0, Op0IsKill * RegState::Kill));
307 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
308 .addReg(Op0, Op0IsKill * RegState::Kill));
309 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
310 TII.get(TargetOpcode::COPY), ResultReg)
311 .addReg(II.ImplicitDefs[0]));
316 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
317 const TargetRegisterClass *RC,
318 unsigned Op0, bool Op0IsKill,
319 unsigned Op1, bool Op1IsKill) {
320 unsigned ResultReg = createResultReg(RC);
321 const MCInstrDesc &II = TII.get(MachineInstOpcode);
323 if (II.getNumDefs() >= 1) {
324 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
325 .addReg(Op0, Op0IsKill * RegState::Kill)
326 .addReg(Op1, Op1IsKill * RegState::Kill));
328 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
329 .addReg(Op0, Op0IsKill * RegState::Kill)
330 .addReg(Op1, Op1IsKill * RegState::Kill));
331 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
332 TII.get(TargetOpcode::COPY), ResultReg)
333 .addReg(II.ImplicitDefs[0]));
338 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
339 const TargetRegisterClass *RC,
340 unsigned Op0, bool Op0IsKill,
341 unsigned Op1, bool Op1IsKill,
342 unsigned Op2, bool Op2IsKill) {
343 unsigned ResultReg = createResultReg(RC);
344 const MCInstrDesc &II = TII.get(MachineInstOpcode);
346 if (II.getNumDefs() >= 1) {
347 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
348 .addReg(Op0, Op0IsKill * RegState::Kill)
349 .addReg(Op1, Op1IsKill * RegState::Kill)
350 .addReg(Op2, Op2IsKill * RegState::Kill));
352 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
353 .addReg(Op0, Op0IsKill * RegState::Kill)
354 .addReg(Op1, Op1IsKill * RegState::Kill)
355 .addReg(Op2, Op2IsKill * RegState::Kill));
356 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
357 TII.get(TargetOpcode::COPY), ResultReg)
358 .addReg(II.ImplicitDefs[0]));
363 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
364 const TargetRegisterClass *RC,
365 unsigned Op0, bool Op0IsKill,
367 unsigned ResultReg = createResultReg(RC);
368 const MCInstrDesc &II = TII.get(MachineInstOpcode);
370 if (II.getNumDefs() >= 1) {
371 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
372 .addReg(Op0, Op0IsKill * RegState::Kill)
375 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
376 .addReg(Op0, Op0IsKill * RegState::Kill)
378 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
379 TII.get(TargetOpcode::COPY), ResultReg)
380 .addReg(II.ImplicitDefs[0]));
385 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
386 const TargetRegisterClass *RC,
387 unsigned Op0, bool Op0IsKill,
388 const ConstantFP *FPImm) {
389 unsigned ResultReg = createResultReg(RC);
390 const MCInstrDesc &II = TII.get(MachineInstOpcode);
392 if (II.getNumDefs() >= 1) {
393 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
394 .addReg(Op0, Op0IsKill * RegState::Kill)
397 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
398 .addReg(Op0, Op0IsKill * RegState::Kill)
400 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
401 TII.get(TargetOpcode::COPY), ResultReg)
402 .addReg(II.ImplicitDefs[0]));
407 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
408 const TargetRegisterClass *RC,
409 unsigned Op0, bool Op0IsKill,
410 unsigned Op1, bool Op1IsKill,
412 unsigned ResultReg = createResultReg(RC);
413 const MCInstrDesc &II = TII.get(MachineInstOpcode);
415 if (II.getNumDefs() >= 1) {
416 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
417 .addReg(Op0, Op0IsKill * RegState::Kill)
418 .addReg(Op1, Op1IsKill * RegState::Kill)
421 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
422 .addReg(Op0, Op0IsKill * RegState::Kill)
423 .addReg(Op1, Op1IsKill * RegState::Kill)
425 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
426 TII.get(TargetOpcode::COPY), ResultReg)
427 .addReg(II.ImplicitDefs[0]));
432 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
433 const TargetRegisterClass *RC,
435 unsigned ResultReg = createResultReg(RC);
436 const MCInstrDesc &II = TII.get(MachineInstOpcode);
438 if (II.getNumDefs() >= 1) {
439 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
442 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
444 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
445 TII.get(TargetOpcode::COPY), ResultReg)
446 .addReg(II.ImplicitDefs[0]));
451 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
452 const TargetRegisterClass *RC,
453 uint64_t Imm1, uint64_t Imm2) {
454 unsigned ResultReg = createResultReg(RC);
455 const MCInstrDesc &II = TII.get(MachineInstOpcode);
457 if (II.getNumDefs() >= 1) {
458 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
459 .addImm(Imm1).addImm(Imm2));
461 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
462 .addImm(Imm1).addImm(Imm2));
463 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
464 TII.get(TargetOpcode::COPY),
466 .addReg(II.ImplicitDefs[0]));
471 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
472 unsigned Op0, bool Op0IsKill,
474 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
475 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
476 "Cannot yet extract from physregs");
478 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
479 DL, TII.get(TargetOpcode::COPY), ResultReg)
480 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
484 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
485 // checks from the various callers.
486 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
487 if (VT == MVT::f64) return 0;
489 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
490 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
491 TII.get(ARM::VMOVSR), MoveReg)
496 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
497 if (VT == MVT::i64) return 0;
499 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
500 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
501 TII.get(ARM::VMOVRS), MoveReg)
506 // For double width floating point we need to materialize two constants
507 // (the high and the low) into integer registers then use a move to get
508 // the combined constant into an FP reg.
509 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
510 const APFloat Val = CFP->getValueAPF();
511 bool is64bit = VT == MVT::f64;
513 // This checks to see if we can use VFP3 instructions to materialize
514 // a constant, otherwise we have to go through the constant pool.
515 if (TLI.isFPImmLegal(Val, VT)) {
519 Imm = ARM_AM::getFP64Imm(Val);
522 Imm = ARM_AM::getFP32Imm(Val);
525 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
526 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
532 // Require VFP2 for loading fp constants.
533 if (!Subtarget->hasVFP2()) return false;
535 // MachineConstantPool wants an explicit alignment.
536 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
538 // TODO: Figure out if this is correct.
539 Align = TD.getTypeAllocSize(CFP->getType());
541 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
542 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
543 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
545 // The extra reg is for addrmode5.
546 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
548 .addConstantPoolIndex(Idx)
553 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
555 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
558 // If we can do this in a single instruction without a constant pool entry
560 const ConstantInt *CI = cast<ConstantInt>(C);
561 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
562 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
563 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
564 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
565 TII.get(Opc), ImmReg)
566 .addImm(CI->getZExtValue()));
570 // Use MVN to emit negative constants.
571 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
572 unsigned Imm = (unsigned)~(CI->getSExtValue());
573 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
574 (ARM_AM::getSOImmVal(Imm) != -1);
576 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
577 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
578 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
579 TII.get(Opc), ImmReg)
585 // Load from constant pool. For now 32-bit only.
589 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
591 // MachineConstantPool wants an explicit alignment.
592 unsigned Align = TD.getPrefTypeAlignment(C->getType());
594 // TODO: Figure out if this is correct.
595 Align = TD.getTypeAllocSize(C->getType());
597 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
600 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
601 TII.get(ARM::t2LDRpci), DestReg)
602 .addConstantPoolIndex(Idx));
604 // The extra immediate is for addrmode2.
605 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
606 TII.get(ARM::LDRcp), DestReg)
607 .addConstantPoolIndex(Idx)
613 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
614 // For now 32-bit only.
615 if (VT != MVT::i32) return 0;
617 Reloc::Model RelocM = TM.getRelocationModel();
619 // TODO: Need more magic for ARM PIC.
620 if (!isThumb2 && (RelocM == Reloc::PIC_)) return 0;
622 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
624 // Use movw+movt when possible, it avoids constant pool entries.
625 // Darwin targets don't support movt with Reloc::Static, see
626 // ARMTargetLowering::LowerGlobalAddressDarwin. Other targets only support
627 // static movt relocations.
628 if (Subtarget->useMovt() &&
629 Subtarget->isTargetDarwin() == (RelocM != Reloc::Static)) {
633 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
635 case Reloc::DynamicNoPIC:
636 Opc = isThumb2 ? ARM::t2MOV_ga_dyn : ARM::MOV_ga_dyn;
639 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
642 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
643 DestReg).addGlobalAddress(GV));
645 // MachineConstantPool wants an explicit alignment.
646 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
648 // TODO: Figure out if this is correct.
649 Align = TD.getTypeAllocSize(GV->getType());
653 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
654 (Subtarget->isThumb() ? 4 : 8);
655 unsigned Id = AFI->createPICLabelUId();
656 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
659 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
662 MachineInstrBuilder MIB;
664 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
665 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
666 .addConstantPoolIndex(Idx);
667 if (RelocM == Reloc::PIC_)
670 // The extra immediate is for addrmode2.
671 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
673 .addConstantPoolIndex(Idx)
676 AddOptionalDefs(MIB);
679 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
680 MachineInstrBuilder MIB;
681 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
683 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
684 TII.get(ARM::t2LDRi12), NewDestReg)
688 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
692 DestReg = NewDestReg;
693 AddOptionalDefs(MIB);
699 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
700 EVT VT = TLI.getValueType(C->getType(), true);
702 // Only handle simple types.
703 if (!VT.isSimple()) return 0;
705 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
706 return ARMMaterializeFP(CFP, VT);
707 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
708 return ARMMaterializeGV(GV, VT);
709 else if (isa<ConstantInt>(C))
710 return ARMMaterializeInt(C, VT);
715 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
717 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
718 // Don't handle dynamic allocas.
719 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
722 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
724 DenseMap<const AllocaInst*, int>::iterator SI =
725 FuncInfo.StaticAllocaMap.find(AI);
727 // This will get lowered later into the correct offsets and registers
728 // via rewriteXFrameIndex.
729 if (SI != FuncInfo.StaticAllocaMap.end()) {
730 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
731 unsigned ResultReg = createResultReg(RC);
732 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
733 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
734 TII.get(Opc), ResultReg)
735 .addFrameIndex(SI->second)
743 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
744 EVT evt = TLI.getValueType(Ty, true);
746 // Only handle simple types.
747 if (evt == MVT::Other || !evt.isSimple()) return false;
748 VT = evt.getSimpleVT();
750 // Handle all legal types, i.e. a register that will directly hold this
752 return TLI.isTypeLegal(VT);
755 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
756 if (isTypeLegal(Ty, VT)) return true;
758 // If this is a type than can be sign or zero-extended to a basic operation
759 // go ahead and accept it now.
760 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
766 // Computes the address to get to an object.
767 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
768 // Some boilerplate from the X86 FastISel.
769 const User *U = NULL;
770 unsigned Opcode = Instruction::UserOp1;
771 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
772 // Don't walk into other basic blocks unless the object is an alloca from
773 // another block, otherwise it may not have a virtual register assigned.
774 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
775 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
776 Opcode = I->getOpcode();
779 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
780 Opcode = C->getOpcode();
784 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
785 if (Ty->getAddressSpace() > 255)
786 // Fast instruction selection doesn't support the special
793 case Instruction::BitCast: {
794 // Look through bitcasts.
795 return ARMComputeAddress(U->getOperand(0), Addr);
797 case Instruction::IntToPtr: {
798 // Look past no-op inttoptrs.
799 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
800 return ARMComputeAddress(U->getOperand(0), Addr);
803 case Instruction::PtrToInt: {
804 // Look past no-op ptrtoints.
805 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
806 return ARMComputeAddress(U->getOperand(0), Addr);
809 case Instruction::GetElementPtr: {
810 Address SavedAddr = Addr;
811 int TmpOffset = Addr.Offset;
813 // Iterate through the GEP folding the constants into offsets where
815 gep_type_iterator GTI = gep_type_begin(U);
816 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
817 i != e; ++i, ++GTI) {
818 const Value *Op = *i;
819 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
820 const StructLayout *SL = TD.getStructLayout(STy);
821 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
822 TmpOffset += SL->getElementOffset(Idx);
824 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
826 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
827 // Constant-offset addressing.
828 TmpOffset += CI->getSExtValue() * S;
831 if (isa<AddOperator>(Op) &&
832 (!isa<Instruction>(Op) ||
833 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
835 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
836 // An add (in the same block) with a constant operand. Fold the
839 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
840 TmpOffset += CI->getSExtValue() * S;
841 // Iterate on the other operand.
842 Op = cast<AddOperator>(Op)->getOperand(0);
846 goto unsupported_gep;
851 // Try to grab the base operand now.
852 Addr.Offset = TmpOffset;
853 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
855 // We failed, restore everything and try the other options.
861 case Instruction::Alloca: {
862 const AllocaInst *AI = cast<AllocaInst>(Obj);
863 DenseMap<const AllocaInst*, int>::iterator SI =
864 FuncInfo.StaticAllocaMap.find(AI);
865 if (SI != FuncInfo.StaticAllocaMap.end()) {
866 Addr.BaseType = Address::FrameIndexBase;
867 Addr.Base.FI = SI->second;
874 // Try to get this in a register if nothing else has worked.
875 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
876 return Addr.Base.Reg != 0;
879 void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) {
881 assert(VT.isSimple() && "Non-simple types are invalid here!");
883 bool needsLowering = false;
884 switch (VT.getSimpleVT().SimpleTy) {
885 default: llvm_unreachable("Unhandled load/store type!");
891 // Integer loads/stores handle 12-bit offsets.
892 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
893 // Handle negative offsets.
894 if (needsLowering && isThumb2)
895 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
898 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
899 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
904 // Floating point operands handle 8-bit offsets.
905 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
909 // If this is a stack pointer and the offset needs to be simplified then
910 // put the alloca address into a register, set the base type back to
911 // register and continue. This should almost never happen.
912 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
913 const TargetRegisterClass *RC = isThumb2 ?
914 (const TargetRegisterClass*)&ARM::tGPRRegClass :
915 (const TargetRegisterClass*)&ARM::GPRRegClass;
916 unsigned ResultReg = createResultReg(RC);
917 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
918 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
919 TII.get(Opc), ResultReg)
920 .addFrameIndex(Addr.Base.FI)
922 Addr.Base.Reg = ResultReg;
923 Addr.BaseType = Address::RegBase;
926 // Since the offset is too large for the load/store instruction
927 // get the reg+offset into a register.
929 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
930 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
935 void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
936 const MachineInstrBuilder &MIB,
937 unsigned Flags, bool useAM3) {
938 // addrmode5 output depends on the selection dag addressing dividing the
939 // offset by 4 that it then later multiplies. Do this here as well.
940 if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
941 VT.getSimpleVT().SimpleTy == MVT::f64)
944 // Frame base works a bit differently. Handle it separately.
945 if (Addr.BaseType == Address::FrameIndexBase) {
946 int FI = Addr.Base.FI;
947 int Offset = Addr.Offset;
948 MachineMemOperand *MMO =
949 FuncInfo.MF->getMachineMemOperand(
950 MachinePointerInfo::getFixedStack(FI, Offset),
952 MFI.getObjectSize(FI),
953 MFI.getObjectAlignment(FI));
954 // Now add the rest of the operands.
955 MIB.addFrameIndex(FI);
957 // ARM halfword load/stores and signed byte loads need an additional
960 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
964 MIB.addImm(Addr.Offset);
966 MIB.addMemOperand(MMO);
968 // Now add the rest of the operands.
969 MIB.addReg(Addr.Base.Reg);
971 // ARM halfword load/stores and signed byte loads need an additional
974 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
978 MIB.addImm(Addr.Offset);
981 AddOptionalDefs(MIB);
984 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
985 unsigned Alignment, bool isZExt, bool allocReg) {
986 assert(VT.isSimple() && "Non-simple types are invalid here!");
989 bool needVMOV = false;
990 const TargetRegisterClass *RC;
991 switch (VT.getSimpleVT().SimpleTy) {
992 // This is mostly going to be Neon/vector support.
993 default: return false;
997 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
998 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
1000 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
1009 RC = &ARM::GPRRegClass;
1013 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1014 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
1016 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1018 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1021 RC = &ARM::GPRRegClass;
1025 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1028 Opc = ARM::t2LDRi12;
1032 RC = &ARM::GPRRegClass;
1035 if (!Subtarget->hasVFP2()) return false;
1036 // Unaligned loads need special handling. Floats require word-alignment.
1037 if (Alignment && Alignment < 4) {
1040 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1041 RC = &ARM::GPRRegClass;
1044 RC = TLI.getRegClassFor(VT);
1048 if (!Subtarget->hasVFP2()) return false;
1049 // FIXME: Unaligned loads need special handling. Doublewords require
1051 if (Alignment && Alignment < 4)
1055 RC = TLI.getRegClassFor(VT);
1058 // Simplify this down to something we can handle.
1059 ARMSimplifyAddress(Addr, VT, useAM3);
1061 // Create the base instruction, then add the operands.
1063 ResultReg = createResultReg(RC);
1064 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1065 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1066 TII.get(Opc), ResultReg);
1067 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1069 // If we had an unaligned load of a float we've converted it to an regular
1070 // load. Now we must move from the GRP to the FP register.
1072 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1073 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1074 TII.get(ARM::VMOVSR), MoveReg)
1075 .addReg(ResultReg));
1076 ResultReg = MoveReg;
1081 bool ARMFastISel::SelectLoad(const Instruction *I) {
1082 // Atomic loads need special handling.
1083 if (cast<LoadInst>(I)->isAtomic())
1086 // Verify we have a legal type before going any further.
1088 if (!isLoadTypeLegal(I->getType(), VT))
1091 // See if we can handle this address.
1093 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1096 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1098 UpdateValueMap(I, ResultReg);
1102 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
1103 unsigned Alignment) {
1105 bool useAM3 = false;
1106 switch (VT.getSimpleVT().SimpleTy) {
1107 // This is mostly going to be Neon/vector support.
1108 default: return false;
1110 unsigned Res = createResultReg(isThumb2 ?
1111 (const TargetRegisterClass*)&ARM::tGPRRegClass :
1112 (const TargetRegisterClass*)&ARM::GPRRegClass);
1113 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1114 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1116 .addReg(SrcReg).addImm(1));
1118 } // Fallthrough here.
1121 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1122 StrOpc = ARM::t2STRBi8;
1124 StrOpc = ARM::t2STRBi12;
1126 StrOpc = ARM::STRBi12;
1131 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1132 StrOpc = ARM::t2STRHi8;
1134 StrOpc = ARM::t2STRHi12;
1142 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1143 StrOpc = ARM::t2STRi8;
1145 StrOpc = ARM::t2STRi12;
1147 StrOpc = ARM::STRi12;
1151 if (!Subtarget->hasVFP2()) return false;
1152 // Unaligned stores need special handling. Floats require word-alignment.
1153 if (Alignment && Alignment < 4) {
1154 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1155 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1156 TII.get(ARM::VMOVRS), MoveReg)
1160 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1162 StrOpc = ARM::VSTRS;
1166 if (!Subtarget->hasVFP2()) return false;
1167 // FIXME: Unaligned stores need special handling. Doublewords require
1169 if (Alignment && Alignment < 4)
1172 StrOpc = ARM::VSTRD;
1175 // Simplify this down to something we can handle.
1176 ARMSimplifyAddress(Addr, VT, useAM3);
1178 // Create the base instruction, then add the operands.
1179 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1182 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1186 bool ARMFastISel::SelectStore(const Instruction *I) {
1187 Value *Op0 = I->getOperand(0);
1188 unsigned SrcReg = 0;
1190 // Atomic stores need special handling.
1191 if (cast<StoreInst>(I)->isAtomic())
1194 // Verify we have a legal type before going any further.
1196 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1199 // Get the value to be stored into a register.
1200 SrcReg = getRegForValue(Op0);
1201 if (SrcReg == 0) return false;
1203 // See if we can handle this address.
1205 if (!ARMComputeAddress(I->getOperand(1), Addr))
1208 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1213 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1215 // Needs two compares...
1216 case CmpInst::FCMP_ONE:
1217 case CmpInst::FCMP_UEQ:
1219 // AL is our "false" for now. The other two need more compares.
1221 case CmpInst::ICMP_EQ:
1222 case CmpInst::FCMP_OEQ:
1224 case CmpInst::ICMP_SGT:
1225 case CmpInst::FCMP_OGT:
1227 case CmpInst::ICMP_SGE:
1228 case CmpInst::FCMP_OGE:
1230 case CmpInst::ICMP_UGT:
1231 case CmpInst::FCMP_UGT:
1233 case CmpInst::FCMP_OLT:
1235 case CmpInst::ICMP_ULE:
1236 case CmpInst::FCMP_OLE:
1238 case CmpInst::FCMP_ORD:
1240 case CmpInst::FCMP_UNO:
1242 case CmpInst::FCMP_UGE:
1244 case CmpInst::ICMP_SLT:
1245 case CmpInst::FCMP_ULT:
1247 case CmpInst::ICMP_SLE:
1248 case CmpInst::FCMP_ULE:
1250 case CmpInst::FCMP_UNE:
1251 case CmpInst::ICMP_NE:
1253 case CmpInst::ICMP_UGE:
1255 case CmpInst::ICMP_ULT:
1260 bool ARMFastISel::SelectBranch(const Instruction *I) {
1261 const BranchInst *BI = cast<BranchInst>(I);
1262 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1263 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1265 // Simple branch support.
1267 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1269 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1270 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1272 // Get the compare predicate.
1273 // Try to take advantage of fallthrough opportunities.
1274 CmpInst::Predicate Predicate = CI->getPredicate();
1275 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1276 std::swap(TBB, FBB);
1277 Predicate = CmpInst::getInversePredicate(Predicate);
1280 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1282 // We may not handle every CC for now.
1283 if (ARMPred == ARMCC::AL) return false;
1285 // Emit the compare.
1286 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1289 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1290 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1291 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1292 FastEmitBranch(FBB, DL);
1293 FuncInfo.MBB->addSuccessor(TBB);
1296 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1298 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1299 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1300 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1301 unsigned OpReg = getRegForValue(TI->getOperand(0));
1302 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1304 .addReg(OpReg).addImm(1));
1306 unsigned CCMode = ARMCC::NE;
1307 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1308 std::swap(TBB, FBB);
1312 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1313 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1314 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1316 FastEmitBranch(FBB, DL);
1317 FuncInfo.MBB->addSuccessor(TBB);
1320 } else if (const ConstantInt *CI =
1321 dyn_cast<ConstantInt>(BI->getCondition())) {
1322 uint64_t Imm = CI->getZExtValue();
1323 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1324 FastEmitBranch(Target, DL);
1328 unsigned CmpReg = getRegForValue(BI->getCondition());
1329 if (CmpReg == 0) return false;
1331 // We've been divorced from our compare! Our block was split, and
1332 // now our compare lives in a predecessor block. We musn't
1333 // re-compare here, as the children of the compare aren't guaranteed
1334 // live across the block boundary (we *could* check for this).
1335 // Regardless, the compare has been done in the predecessor block,
1336 // and it left a value for us in a virtual register. Ergo, we test
1337 // the one-bit value left in the virtual register.
1338 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1339 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1340 .addReg(CmpReg).addImm(1));
1342 unsigned CCMode = ARMCC::NE;
1343 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1344 std::swap(TBB, FBB);
1348 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1349 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1350 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1351 FastEmitBranch(FBB, DL);
1352 FuncInfo.MBB->addSuccessor(TBB);
1356 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1357 unsigned AddrReg = getRegForValue(I->getOperand(0));
1358 if (AddrReg == 0) return false;
1360 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1361 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
1366 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1368 Type *Ty = Src1Value->getType();
1369 EVT SrcVT = TLI.getValueType(Ty, true);
1370 if (!SrcVT.isSimple()) return false;
1372 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1373 if (isFloat && !Subtarget->hasVFP2())
1376 // Check to see if the 2nd operand is a constant that we can encode directly
1379 bool UseImm = false;
1380 bool isNegativeImm = false;
1381 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1382 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1383 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1384 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1386 const APInt &CIVal = ConstInt->getValue();
1387 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1388 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1389 // then a cmn, because there is no way to represent 2147483648 as a
1390 // signed 32-bit int.
1391 if (Imm < 0 && Imm != (int)0x80000000) {
1392 isNegativeImm = true;
1395 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1396 (ARM_AM::getSOImmVal(Imm) != -1);
1398 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1399 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1400 if (ConstFP->isZero() && !ConstFP->isNegative())
1406 bool needsExt = false;
1407 switch (SrcVT.getSimpleVT().SimpleTy) {
1408 default: return false;
1409 // TODO: Verify compares.
1412 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1416 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1422 // Intentional fall-through.
1426 CmpOpc = ARM::t2CMPrr;
1428 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1431 CmpOpc = ARM::CMPrr;
1433 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1438 unsigned SrcReg1 = getRegForValue(Src1Value);
1439 if (SrcReg1 == 0) return false;
1441 unsigned SrcReg2 = 0;
1443 SrcReg2 = getRegForValue(Src2Value);
1444 if (SrcReg2 == 0) return false;
1447 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1449 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1450 if (SrcReg1 == 0) return false;
1452 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1453 if (SrcReg2 == 0) return false;
1458 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1460 .addReg(SrcReg1).addReg(SrcReg2));
1462 MachineInstrBuilder MIB;
1463 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1466 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1469 AddOptionalDefs(MIB);
1472 // For floating point we need to move the result to a comparison register
1473 // that we can then use for branches.
1474 if (Ty->isFloatTy() || Ty->isDoubleTy())
1475 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1476 TII.get(ARM::FMSTAT)));
1480 bool ARMFastISel::SelectCmp(const Instruction *I) {
1481 const CmpInst *CI = cast<CmpInst>(I);
1483 // Get the compare predicate.
1484 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1486 // We may not handle every CC for now.
1487 if (ARMPred == ARMCC::AL) return false;
1489 // Emit the compare.
1490 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1493 // Now set a register based on the comparison. Explicitly set the predicates
1495 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1496 const TargetRegisterClass *RC = isThumb2 ?
1497 (const TargetRegisterClass*)&ARM::rGPRRegClass :
1498 (const TargetRegisterClass*)&ARM::GPRRegClass;
1499 unsigned DestReg = createResultReg(RC);
1500 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1501 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1502 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1503 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1504 .addReg(ZeroReg).addImm(1)
1505 .addImm(ARMPred).addReg(ARM::CPSR);
1507 UpdateValueMap(I, DestReg);
1511 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1512 // Make sure we have VFP and that we're extending float to double.
1513 if (!Subtarget->hasVFP2()) return false;
1515 Value *V = I->getOperand(0);
1516 if (!I->getType()->isDoubleTy() ||
1517 !V->getType()->isFloatTy()) return false;
1519 unsigned Op = getRegForValue(V);
1520 if (Op == 0) return false;
1522 unsigned Result = createResultReg(&ARM::DPRRegClass);
1523 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1524 TII.get(ARM::VCVTDS), Result)
1526 UpdateValueMap(I, Result);
1530 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1531 // Make sure we have VFP and that we're truncating double to float.
1532 if (!Subtarget->hasVFP2()) return false;
1534 Value *V = I->getOperand(0);
1535 if (!(I->getType()->isFloatTy() &&
1536 V->getType()->isDoubleTy())) return false;
1538 unsigned Op = getRegForValue(V);
1539 if (Op == 0) return false;
1541 unsigned Result = createResultReg(&ARM::SPRRegClass);
1542 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1543 TII.get(ARM::VCVTSD), Result)
1545 UpdateValueMap(I, Result);
1549 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1550 // Make sure we have VFP.
1551 if (!Subtarget->hasVFP2()) return false;
1554 Type *Ty = I->getType();
1555 if (!isTypeLegal(Ty, DstVT))
1558 Value *Src = I->getOperand(0);
1559 EVT SrcVT = TLI.getValueType(Src->getType(), true);
1560 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1563 unsigned SrcReg = getRegForValue(Src);
1564 if (SrcReg == 0) return false;
1566 // Handle sign-extension.
1567 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1568 EVT DestVT = MVT::i32;
1569 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT,
1570 /*isZExt*/!isSigned);
1571 if (SrcReg == 0) return false;
1574 // The conversion routine works on fp-reg to fp-reg and the operand above
1575 // was an integer, move it to the fp registers if possible.
1576 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1577 if (FP == 0) return false;
1580 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1581 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1584 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1585 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1588 UpdateValueMap(I, ResultReg);
1592 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1593 // Make sure we have VFP.
1594 if (!Subtarget->hasVFP2()) return false;
1597 Type *RetTy = I->getType();
1598 if (!isTypeLegal(RetTy, DstVT))
1601 unsigned Op = getRegForValue(I->getOperand(0));
1602 if (Op == 0) return false;
1605 Type *OpTy = I->getOperand(0)->getType();
1606 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1607 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1610 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1611 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1612 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1616 // This result needs to be in an integer register, but the conversion only
1617 // takes place in fp-regs.
1618 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1619 if (IntReg == 0) return false;
1621 UpdateValueMap(I, IntReg);
1625 bool ARMFastISel::SelectSelect(const Instruction *I) {
1627 if (!isTypeLegal(I->getType(), VT))
1630 // Things need to be register sized for register moves.
1631 if (VT != MVT::i32) return false;
1632 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1634 unsigned CondReg = getRegForValue(I->getOperand(0));
1635 if (CondReg == 0) return false;
1636 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1637 if (Op1Reg == 0) return false;
1639 // Check to see if we can use an immediate in the conditional move.
1641 bool UseImm = false;
1642 bool isNegativeImm = false;
1643 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1644 assert (VT == MVT::i32 && "Expecting an i32.");
1645 Imm = (int)ConstInt->getValue().getZExtValue();
1647 isNegativeImm = true;
1650 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1651 (ARM_AM::getSOImmVal(Imm) != -1);
1654 unsigned Op2Reg = 0;
1656 Op2Reg = getRegForValue(I->getOperand(2));
1657 if (Op2Reg == 0) return false;
1660 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1661 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1662 .addReg(CondReg).addImm(0));
1666 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1668 if (!isNegativeImm) {
1669 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1671 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1674 unsigned ResultReg = createResultReg(RC);
1676 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1677 .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1679 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1680 .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1681 UpdateValueMap(I, ResultReg);
1685 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1687 Type *Ty = I->getType();
1688 if (!isTypeLegal(Ty, VT))
1691 // If we have integer div support we should have selected this automagically.
1692 // In case we have a real miss go ahead and return false and we'll pick
1694 if (Subtarget->hasDivide()) return false;
1696 // Otherwise emit a libcall.
1697 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1699 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1700 else if (VT == MVT::i16)
1701 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1702 else if (VT == MVT::i32)
1703 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1704 else if (VT == MVT::i64)
1705 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1706 else if (VT == MVT::i128)
1707 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1708 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1710 return ARMEmitLibcall(I, LC);
1713 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1715 Type *Ty = I->getType();
1716 if (!isTypeLegal(Ty, VT))
1719 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1721 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1722 else if (VT == MVT::i16)
1723 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1724 else if (VT == MVT::i32)
1725 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1726 else if (VT == MVT::i64)
1727 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1728 else if (VT == MVT::i128)
1729 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1730 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1732 return ARMEmitLibcall(I, LC);
1735 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1736 EVT DestVT = TLI.getValueType(I->getType(), true);
1738 // We can get here in the case when we have a binary operation on a non-legal
1739 // type and the target independent selector doesn't know how to handle it.
1740 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1744 switch (ISDOpcode) {
1745 default: return false;
1747 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1750 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1753 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1757 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1758 if (SrcReg1 == 0) return false;
1760 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1761 // in the instruction, rather then materializing the value in a register.
1762 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1763 if (SrcReg2 == 0) return false;
1765 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1766 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1767 TII.get(Opc), ResultReg)
1768 .addReg(SrcReg1).addReg(SrcReg2));
1769 UpdateValueMap(I, ResultReg);
1773 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1774 EVT VT = TLI.getValueType(I->getType(), true);
1776 // We can get here in the case when we want to use NEON for our fp
1777 // operations, but can't figure out how to. Just use the vfp instructions
1779 // FIXME: It'd be nice to use NEON instructions.
1780 Type *Ty = I->getType();
1781 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1782 if (isFloat && !Subtarget->hasVFP2())
1786 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1787 switch (ISDOpcode) {
1788 default: return false;
1790 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1793 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1796 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1799 unsigned Op1 = getRegForValue(I->getOperand(0));
1800 if (Op1 == 0) return false;
1802 unsigned Op2 = getRegForValue(I->getOperand(1));
1803 if (Op2 == 0) return false;
1805 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1806 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1807 TII.get(Opc), ResultReg)
1808 .addReg(Op1).addReg(Op2));
1809 UpdateValueMap(I, ResultReg);
1813 // Call Handling Code
1815 // This is largely taken directly from CCAssignFnForNode
1816 // TODO: We may not support all of this.
1817 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1822 llvm_unreachable("Unsupported calling convention");
1823 case CallingConv::Fast:
1824 if (Subtarget->hasVFP2() && !isVarArg) {
1825 if (!Subtarget->isAAPCS_ABI())
1826 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1827 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1828 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1831 case CallingConv::C:
1832 // Use target triple & subtarget features to do actual dispatch.
1833 if (Subtarget->isAAPCS_ABI()) {
1834 if (Subtarget->hasVFP2() &&
1835 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1836 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1838 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1840 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1841 case CallingConv::ARM_AAPCS_VFP:
1843 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1844 // Fall through to soft float variant, variadic functions don't
1845 // use hard floating point ABI.
1846 case CallingConv::ARM_AAPCS:
1847 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1848 case CallingConv::ARM_APCS:
1849 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1850 case CallingConv::GHC:
1852 llvm_unreachable("Can't return in GHC call convention");
1854 return CC_ARM_APCS_GHC;
1858 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1859 SmallVectorImpl<unsigned> &ArgRegs,
1860 SmallVectorImpl<MVT> &ArgVTs,
1861 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1862 SmallVectorImpl<unsigned> &RegArgs,
1866 SmallVector<CCValAssign, 16> ArgLocs;
1867 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1868 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1869 CCAssignFnForCall(CC, false, isVarArg));
1871 // Check that we can handle all of the arguments. If we can't, then bail out
1872 // now before we add code to the MBB.
1873 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1874 CCValAssign &VA = ArgLocs[i];
1875 MVT ArgVT = ArgVTs[VA.getValNo()];
1877 // We don't handle NEON/vector parameters yet.
1878 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1881 // Now copy/store arg to correct locations.
1882 if (VA.isRegLoc() && !VA.needsCustom()) {
1884 } else if (VA.needsCustom()) {
1885 // TODO: We need custom lowering for vector (v2f64) args.
1886 if (VA.getLocVT() != MVT::f64 ||
1887 // TODO: Only handle register args for now.
1888 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1891 switch (static_cast<EVT>(ArgVT).getSimpleVT().SimpleTy) {
1900 if (!Subtarget->hasVFP2())
1904 if (!Subtarget->hasVFP2())
1911 // At the point, we are able to handle the call's arguments in fast isel.
1913 // Get a count of how many bytes are to be pushed on the stack.
1914 NumBytes = CCInfo.getNextStackOffset();
1916 // Issue CALLSEQ_START
1917 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1918 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1919 TII.get(AdjStackDown))
1922 // Process the args.
1923 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1924 CCValAssign &VA = ArgLocs[i];
1925 unsigned Arg = ArgRegs[VA.getValNo()];
1926 MVT ArgVT = ArgVTs[VA.getValNo()];
1928 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1929 "We don't handle NEON/vector parameters yet.");
1931 // Handle arg promotion, etc.
1932 switch (VA.getLocInfo()) {
1933 case CCValAssign::Full: break;
1934 case CCValAssign::SExt: {
1935 MVT DestVT = VA.getLocVT();
1936 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1937 assert (Arg != 0 && "Failed to emit a sext");
1941 case CCValAssign::AExt:
1942 // Intentional fall-through. Handle AExt and ZExt.
1943 case CCValAssign::ZExt: {
1944 MVT DestVT = VA.getLocVT();
1945 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1946 assert (Arg != 0 && "Failed to emit a sext");
1950 case CCValAssign::BCvt: {
1951 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1952 /*TODO: Kill=*/false);
1953 assert(BC != 0 && "Failed to emit a bitcast!");
1955 ArgVT = VA.getLocVT();
1958 default: llvm_unreachable("Unknown arg promotion!");
1961 // Now copy/store arg to correct locations.
1962 if (VA.isRegLoc() && !VA.needsCustom()) {
1963 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1966 RegArgs.push_back(VA.getLocReg());
1967 } else if (VA.needsCustom()) {
1968 // TODO: We need custom lowering for vector (v2f64) args.
1969 assert(VA.getLocVT() == MVT::f64 &&
1970 "Custom lowering for v2f64 args not available");
1972 CCValAssign &NextVA = ArgLocs[++i];
1974 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
1975 "We only handle register args!");
1977 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1978 TII.get(ARM::VMOVRRD), VA.getLocReg())
1979 .addReg(NextVA.getLocReg(), RegState::Define)
1981 RegArgs.push_back(VA.getLocReg());
1982 RegArgs.push_back(NextVA.getLocReg());
1984 assert(VA.isMemLoc());
1985 // Need to store on the stack.
1987 Addr.BaseType = Address::RegBase;
1988 Addr.Base.Reg = ARM::SP;
1989 Addr.Offset = VA.getLocMemOffset();
1991 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
1992 assert(EmitRet && "Could not emit a store for argument!");
1999 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2000 const Instruction *I, CallingConv::ID CC,
2001 unsigned &NumBytes, bool isVarArg) {
2002 // Issue CALLSEQ_END
2003 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2004 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2005 TII.get(AdjStackUp))
2006 .addImm(NumBytes).addImm(0));
2008 // Now the return value.
2009 if (RetVT != MVT::isVoid) {
2010 SmallVector<CCValAssign, 16> RVLocs;
2011 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2012 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2014 // Copy all of the result registers out of their specified physreg.
2015 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2016 // For this move we copy into two registers and then move into the
2017 // double fp reg we want.
2018 EVT DestVT = RVLocs[0].getValVT();
2019 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2020 unsigned ResultReg = createResultReg(DstRC);
2021 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2022 TII.get(ARM::VMOVDRR), ResultReg)
2023 .addReg(RVLocs[0].getLocReg())
2024 .addReg(RVLocs[1].getLocReg()));
2026 UsedRegs.push_back(RVLocs[0].getLocReg());
2027 UsedRegs.push_back(RVLocs[1].getLocReg());
2029 // Finally update the result.
2030 UpdateValueMap(I, ResultReg);
2032 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2033 EVT CopyVT = RVLocs[0].getValVT();
2035 // Special handling for extended integers.
2036 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2039 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2041 unsigned ResultReg = createResultReg(DstRC);
2042 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2043 ResultReg).addReg(RVLocs[0].getLocReg());
2044 UsedRegs.push_back(RVLocs[0].getLocReg());
2046 // Finally update the result.
2047 UpdateValueMap(I, ResultReg);
2054 bool ARMFastISel::SelectRet(const Instruction *I) {
2055 const ReturnInst *Ret = cast<ReturnInst>(I);
2056 const Function &F = *I->getParent()->getParent();
2058 if (!FuncInfo.CanLowerReturn)
2061 CallingConv::ID CC = F.getCallingConv();
2062 if (Ret->getNumOperands() > 0) {
2063 SmallVector<ISD::OutputArg, 4> Outs;
2064 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
2067 // Analyze operands of the call, assigning locations to each operand.
2068 SmallVector<CCValAssign, 16> ValLocs;
2069 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
2070 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2073 const Value *RV = Ret->getOperand(0);
2074 unsigned Reg = getRegForValue(RV);
2078 // Only handle a single return value for now.
2079 if (ValLocs.size() != 1)
2082 CCValAssign &VA = ValLocs[0];
2084 // Don't bother handling odd stuff for now.
2085 if (VA.getLocInfo() != CCValAssign::Full)
2087 // Only handle register returns for now.
2091 unsigned SrcReg = Reg + VA.getValNo();
2092 EVT RVVT = TLI.getValueType(RV->getType());
2093 EVT DestVT = VA.getValVT();
2094 // Special handling for extended integers.
2095 if (RVVT != DestVT) {
2096 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2099 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2101 // Perform extension if flagged as either zext or sext. Otherwise, do
2103 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2104 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2105 if (SrcReg == 0) return false;
2110 unsigned DstReg = VA.getLocReg();
2111 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2112 // Avoid a cross-class copy. This is very unlikely.
2113 if (!SrcRC->contains(DstReg))
2115 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2116 DstReg).addReg(SrcReg);
2118 // Mark the register as live out of the function.
2119 MRI.addLiveOut(VA.getLocReg());
2122 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2123 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2128 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2130 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2132 return isThumb2 ? ARM::tBL : ARM::BL;
2135 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2136 GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false,
2137 GlobalValue::ExternalLinkage, 0, Name);
2138 return ARMMaterializeGV(GV, TLI.getValueType(GV->getType()));
2141 // A quick function that will emit a call for a named libcall in F with the
2142 // vector of passed arguments for the Instruction in I. We can assume that we
2143 // can emit a call for any libcall we can produce. This is an abridged version
2144 // of the full call infrastructure since we won't need to worry about things
2145 // like computed function pointers or strange arguments at call sites.
2146 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2148 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2149 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2151 // Handle *simple* calls for now.
2152 Type *RetTy = I->getType();
2154 if (RetTy->isVoidTy())
2155 RetVT = MVT::isVoid;
2156 else if (!isTypeLegal(RetTy, RetVT))
2159 // Can't handle non-double multi-reg retvals.
2160 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2161 SmallVector<CCValAssign, 16> RVLocs;
2162 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
2163 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2164 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2168 // Set up the argument vectors.
2169 SmallVector<Value*, 8> Args;
2170 SmallVector<unsigned, 8> ArgRegs;
2171 SmallVector<MVT, 8> ArgVTs;
2172 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2173 Args.reserve(I->getNumOperands());
2174 ArgRegs.reserve(I->getNumOperands());
2175 ArgVTs.reserve(I->getNumOperands());
2176 ArgFlags.reserve(I->getNumOperands());
2177 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2178 Value *Op = I->getOperand(i);
2179 unsigned Arg = getRegForValue(Op);
2180 if (Arg == 0) return false;
2182 Type *ArgTy = Op->getType();
2184 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2186 ISD::ArgFlagsTy Flags;
2187 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2188 Flags.setOrigAlign(OriginalAlignment);
2191 ArgRegs.push_back(Arg);
2192 ArgVTs.push_back(ArgVT);
2193 ArgFlags.push_back(Flags);
2196 // Handle the arguments now that we've gotten them.
2197 SmallVector<unsigned, 4> RegArgs;
2199 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2200 RegArgs, CC, NumBytes, false))
2203 unsigned CalleeReg = 0;
2204 if (EnableARMLongCalls) {
2205 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2206 if (CalleeReg == 0) return false;
2210 unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
2211 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2212 DL, TII.get(CallOpc));
2214 // Explicitly adding the predicate here.
2215 AddDefaultPred(MIB);
2216 if (EnableARMLongCalls)
2217 MIB.addReg(CalleeReg);
2219 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2221 if (EnableARMLongCalls)
2222 MIB.addReg(CalleeReg);
2224 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2226 // Explicitly adding the predicate here.
2227 AddDefaultPred(MIB);
2229 // Add implicit physical register uses to the call.
2230 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2231 MIB.addReg(RegArgs[i]);
2233 // Add a register mask with the call-preserved registers.
2234 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2235 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2237 // Finish off the call including any return values.
2238 SmallVector<unsigned, 4> UsedRegs;
2239 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2241 // Set all unused physreg defs as dead.
2242 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2247 bool ARMFastISel::SelectCall(const Instruction *I,
2248 const char *IntrMemName = 0) {
2249 const CallInst *CI = cast<CallInst>(I);
2250 const Value *Callee = CI->getCalledValue();
2252 // Can't handle inline asm.
2253 if (isa<InlineAsm>(Callee)) return false;
2255 // Check the calling convention.
2256 ImmutableCallSite CS(CI);
2257 CallingConv::ID CC = CS.getCallingConv();
2259 // TODO: Avoid some calling conventions?
2261 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2262 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2263 bool isVarArg = FTy->isVarArg();
2265 // Handle *simple* calls for now.
2266 Type *RetTy = I->getType();
2268 if (RetTy->isVoidTy())
2269 RetVT = MVT::isVoid;
2270 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2271 RetVT != MVT::i8 && RetVT != MVT::i1)
2274 // Can't handle non-double multi-reg retvals.
2275 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2276 RetVT != MVT::i16 && RetVT != MVT::i32) {
2277 SmallVector<CCValAssign, 16> RVLocs;
2278 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2279 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2280 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2284 // Set up the argument vectors.
2285 SmallVector<Value*, 8> Args;
2286 SmallVector<unsigned, 8> ArgRegs;
2287 SmallVector<MVT, 8> ArgVTs;
2288 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2289 unsigned arg_size = CS.arg_size();
2290 Args.reserve(arg_size);
2291 ArgRegs.reserve(arg_size);
2292 ArgVTs.reserve(arg_size);
2293 ArgFlags.reserve(arg_size);
2294 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2296 // If we're lowering a memory intrinsic instead of a regular call, skip the
2297 // last two arguments, which shouldn't be passed to the underlying function.
2298 if (IntrMemName && e-i <= 2)
2301 ISD::ArgFlagsTy Flags;
2302 unsigned AttrInd = i - CS.arg_begin() + 1;
2303 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2305 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2308 // FIXME: Only handle *easy* calls for now.
2309 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2310 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2311 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2312 CS.paramHasAttr(AttrInd, Attribute::ByVal))
2315 Type *ArgTy = (*i)->getType();
2317 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2321 unsigned Arg = getRegForValue(*i);
2325 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2326 Flags.setOrigAlign(OriginalAlignment);
2329 ArgRegs.push_back(Arg);
2330 ArgVTs.push_back(ArgVT);
2331 ArgFlags.push_back(Flags);
2334 // Handle the arguments now that we've gotten them.
2335 SmallVector<unsigned, 4> RegArgs;
2337 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2338 RegArgs, CC, NumBytes, isVarArg))
2341 bool UseReg = false;
2342 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2343 if (!GV || EnableARMLongCalls) UseReg = true;
2345 unsigned CalleeReg = 0;
2348 CalleeReg = getLibcallReg(IntrMemName);
2350 CalleeReg = getRegForValue(Callee);
2352 if (CalleeReg == 0) return false;
2356 unsigned CallOpc = ARMSelectCallOp(UseReg);
2357 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2358 DL, TII.get(CallOpc));
2360 // Explicitly adding the predicate here.
2361 AddDefaultPred(MIB);
2363 MIB.addReg(CalleeReg);
2364 else if (!IntrMemName)
2365 MIB.addGlobalAddress(GV, 0, 0);
2367 MIB.addExternalSymbol(IntrMemName, 0);
2370 MIB.addReg(CalleeReg);
2371 else if (!IntrMemName)
2372 MIB.addGlobalAddress(GV, 0, 0);
2374 MIB.addExternalSymbol(IntrMemName, 0);
2376 // Explicitly adding the predicate here.
2377 AddDefaultPred(MIB);
2380 // Add implicit physical register uses to the call.
2381 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2382 MIB.addReg(RegArgs[i]);
2384 // Add a register mask with the call-preserved registers.
2385 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2386 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2388 // Finish off the call including any return values.
2389 SmallVector<unsigned, 4> UsedRegs;
2390 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2393 // Set all unused physreg defs as dead.
2394 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2399 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2403 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2405 // Make sure we don't bloat code by inlining very large memcpy's.
2406 if (!ARMIsMemCpySmall(Len))
2409 // We don't care about alignment here since we just emit integer accesses.
2423 RV = ARMEmitLoad(VT, ResultReg, Src);
2424 assert (RV == true && "Should be able to handle this load.");
2425 RV = ARMEmitStore(VT, ResultReg, Dest);
2426 assert (RV == true && "Should be able to handle this store.");
2429 unsigned Size = VT.getSizeInBits()/8;
2431 Dest.Offset += Size;
2438 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2439 // FIXME: Handle more intrinsics.
2440 switch (I.getIntrinsicID()) {
2441 default: return false;
2442 case Intrinsic::frameaddress: {
2443 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2444 MFI->setFrameAddressIsTaken(true);
2447 const TargetRegisterClass *RC;
2449 LdrOpc = ARM::t2LDRi12;
2450 RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2452 LdrOpc = ARM::LDRi12;
2453 RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2456 const ARMBaseRegisterInfo *RegInfo =
2457 static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
2458 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2459 unsigned SrcReg = FramePtr;
2461 // Recursively load frame address
2467 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2469 DestReg = createResultReg(RC);
2470 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2471 TII.get(LdrOpc), DestReg)
2472 .addReg(SrcReg).addImm(0));
2475 UpdateValueMap(&I, SrcReg);
2478 case Intrinsic::memcpy:
2479 case Intrinsic::memmove: {
2480 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2481 // Don't handle volatile.
2482 if (MTI.isVolatile())
2485 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2486 // we would emit dead code because we don't currently handle memmoves.
2487 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2488 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2489 // Small memcpy's are common enough that we want to do them without a call
2491 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2492 if (ARMIsMemCpySmall(Len)) {
2494 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2495 !ARMComputeAddress(MTI.getRawSource(), Src))
2497 if (ARMTryEmitSmallMemCpy(Dest, Src, Len))
2502 if (!MTI.getLength()->getType()->isIntegerTy(32))
2505 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2508 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2509 return SelectCall(&I, IntrMemName);
2511 case Intrinsic::memset: {
2512 const MemSetInst &MSI = cast<MemSetInst>(I);
2513 // Don't handle volatile.
2514 if (MSI.isVolatile())
2517 if (!MSI.getLength()->getType()->isIntegerTy(32))
2520 if (MSI.getDestAddressSpace() > 255)
2523 return SelectCall(&I, "memset");
2525 case Intrinsic::trap: {
2526 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::TRAP));
2532 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2533 // The high bits for a type smaller than the register size are assumed to be
2535 Value *Op = I->getOperand(0);
2538 SrcVT = TLI.getValueType(Op->getType(), true);
2539 DestVT = TLI.getValueType(I->getType(), true);
2541 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2543 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2546 unsigned SrcReg = getRegForValue(Op);
2547 if (!SrcReg) return false;
2549 // Because the high bits are undefined, a truncate doesn't generate
2551 UpdateValueMap(I, SrcReg);
2555 unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
2557 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2561 bool isBoolZext = false;
2562 if (!SrcVT.isSimple()) return 0;
2563 switch (SrcVT.getSimpleVT().SimpleTy) {
2566 if (!Subtarget->hasV6Ops()) return 0;
2568 Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
2570 Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
2573 if (!Subtarget->hasV6Ops()) return 0;
2575 Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
2577 Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
2581 Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
2588 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2589 MachineInstrBuilder MIB;
2590 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
2596 AddOptionalDefs(MIB);
2600 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2601 // On ARM, in general, integer casts don't involve legal types; this code
2602 // handles promotable integers.
2603 Type *DestTy = I->getType();
2604 Value *Src = I->getOperand(0);
2605 Type *SrcTy = Src->getType();
2608 SrcVT = TLI.getValueType(SrcTy, true);
2609 DestVT = TLI.getValueType(DestTy, true);
2611 bool isZExt = isa<ZExtInst>(I);
2612 unsigned SrcReg = getRegForValue(Src);
2613 if (!SrcReg) return false;
2615 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2616 if (ResultReg == 0) return false;
2617 UpdateValueMap(I, ResultReg);
2621 bool ARMFastISel::SelectShift(const Instruction *I,
2622 ARM_AM::ShiftOpc ShiftTy) {
2623 // We handle thumb2 mode by target independent selector
2624 // or SelectionDAG ISel.
2628 // Only handle i32 now.
2629 EVT DestVT = TLI.getValueType(I->getType(), true);
2630 if (DestVT != MVT::i32)
2633 unsigned Opc = ARM::MOVsr;
2635 Value *Src2Value = I->getOperand(1);
2636 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2637 ShiftImm = CI->getZExtValue();
2639 // Fall back to selection DAG isel if the shift amount
2640 // is zero or greater than the width of the value type.
2641 if (ShiftImm == 0 || ShiftImm >=32)
2647 Value *Src1Value = I->getOperand(0);
2648 unsigned Reg1 = getRegForValue(Src1Value);
2649 if (Reg1 == 0) return false;
2652 if (Opc == ARM::MOVsr) {
2653 Reg2 = getRegForValue(Src2Value);
2654 if (Reg2 == 0) return false;
2657 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2658 if(ResultReg == 0) return false;
2660 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2661 TII.get(Opc), ResultReg)
2664 if (Opc == ARM::MOVsi)
2665 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2666 else if (Opc == ARM::MOVsr) {
2668 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2671 AddOptionalDefs(MIB);
2672 UpdateValueMap(I, ResultReg);
2676 // TODO: SoftFP support.
2677 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2679 switch (I->getOpcode()) {
2680 case Instruction::Load:
2681 return SelectLoad(I);
2682 case Instruction::Store:
2683 return SelectStore(I);
2684 case Instruction::Br:
2685 return SelectBranch(I);
2686 case Instruction::IndirectBr:
2687 return SelectIndirectBr(I);
2688 case Instruction::ICmp:
2689 case Instruction::FCmp:
2690 return SelectCmp(I);
2691 case Instruction::FPExt:
2692 return SelectFPExt(I);
2693 case Instruction::FPTrunc:
2694 return SelectFPTrunc(I);
2695 case Instruction::SIToFP:
2696 return SelectIToFP(I, /*isSigned*/ true);
2697 case Instruction::UIToFP:
2698 return SelectIToFP(I, /*isSigned*/ false);
2699 case Instruction::FPToSI:
2700 return SelectFPToI(I, /*isSigned*/ true);
2701 case Instruction::FPToUI:
2702 return SelectFPToI(I, /*isSigned*/ false);
2703 case Instruction::Add:
2704 return SelectBinaryIntOp(I, ISD::ADD);
2705 case Instruction::Or:
2706 return SelectBinaryIntOp(I, ISD::OR);
2707 case Instruction::Sub:
2708 return SelectBinaryIntOp(I, ISD::SUB);
2709 case Instruction::FAdd:
2710 return SelectBinaryFPOp(I, ISD::FADD);
2711 case Instruction::FSub:
2712 return SelectBinaryFPOp(I, ISD::FSUB);
2713 case Instruction::FMul:
2714 return SelectBinaryFPOp(I, ISD::FMUL);
2715 case Instruction::SDiv:
2716 return SelectDiv(I, /*isSigned*/ true);
2717 case Instruction::UDiv:
2718 return SelectDiv(I, /*isSigned*/ false);
2719 case Instruction::SRem:
2720 return SelectRem(I, /*isSigned*/ true);
2721 case Instruction::URem:
2722 return SelectRem(I, /*isSigned*/ false);
2723 case Instruction::Call:
2724 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2725 return SelectIntrinsicCall(*II);
2726 return SelectCall(I);
2727 case Instruction::Select:
2728 return SelectSelect(I);
2729 case Instruction::Ret:
2730 return SelectRet(I);
2731 case Instruction::Trunc:
2732 return SelectTrunc(I);
2733 case Instruction::ZExt:
2734 case Instruction::SExt:
2735 return SelectIntExt(I);
2736 case Instruction::Shl:
2737 return SelectShift(I, ARM_AM::lsl);
2738 case Instruction::LShr:
2739 return SelectShift(I, ARM_AM::lsr);
2740 case Instruction::AShr:
2741 return SelectShift(I, ARM_AM::asr);
2747 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
2748 /// vreg is being provided by the specified load instruction. If possible,
2749 /// try to fold the load as an operand to the instruction, returning true if
2751 bool ARMFastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
2752 const LoadInst *LI) {
2753 // Verify we have a legal type before going any further.
2755 if (!isLoadTypeLegal(LI->getType(), VT))
2758 // Combine load followed by zero- or sign-extend.
2759 // ldrb r1, [r0] ldrb r1, [r0]
2761 // mov r3, r2 mov r3, r1
2763 switch(MI->getOpcode()) {
2764 default: return false;
2782 // See if we can handle this address.
2784 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2786 unsigned ResultReg = MI->getOperand(0).getReg();
2787 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2789 MI->eraseFromParent();
2794 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
2795 const TargetLibraryInfo *libInfo) {
2796 // Completely untested on non-iOS.
2797 const TargetMachine &TM = funcInfo.MF->getTarget();
2799 // Darwin and thumb1 only for now.
2800 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2801 if (Subtarget->isTargetIOS() && !Subtarget->isThumb1Only())
2802 return new ARMFastISel(funcInfo, libInfo);