1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "ARMConstantPoolValue.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/Analysis.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/FunctionLoweringInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineConstantPool.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/Support/CallSite.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/GetElementPtrTypeIterator.h"
41 #include "llvm/Target/TargetData.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
49 EnableARMFastISel("arm-fast-isel",
50 cl::desc("Turn on experimental ARM fast-isel support"),
51 cl::init(false), cl::Hidden);
55 class ARMFastISel : public FastISel {
57 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
58 /// make the right decision when generating code for different targets.
59 const ARMSubtarget *Subtarget;
60 const TargetMachine &TM;
61 const TargetInstrInfo &TII;
62 const TargetLowering &TLI;
65 // Convenience variables to avoid some queries.
70 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
72 TM(funcInfo.MF->getTarget()),
73 TII(*TM.getInstrInfo()),
74 TLI(*TM.getTargetLowering()) {
75 Subtarget = &TM.getSubtarget<ARMSubtarget>();
76 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
77 isThumb = AFI->isThumbFunction();
78 Context = &funcInfo.Fn->getContext();
81 // Code from FastISel.cpp.
82 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
83 const TargetRegisterClass *RC);
84 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
85 const TargetRegisterClass *RC,
86 unsigned Op0, bool Op0IsKill);
87 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
88 const TargetRegisterClass *RC,
89 unsigned Op0, bool Op0IsKill,
90 unsigned Op1, bool Op1IsKill);
91 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
92 const TargetRegisterClass *RC,
93 unsigned Op0, bool Op0IsKill,
95 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
96 const TargetRegisterClass *RC,
97 unsigned Op0, bool Op0IsKill,
98 const ConstantFP *FPImm);
99 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
100 const TargetRegisterClass *RC,
102 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
103 const TargetRegisterClass *RC,
104 unsigned Op0, bool Op0IsKill,
105 unsigned Op1, bool Op1IsKill,
107 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
108 unsigned Op0, bool Op0IsKill,
111 // Backend specific FastISel code.
112 virtual bool TargetSelectInstruction(const Instruction *I);
113 virtual unsigned TargetMaterializeConstant(const Constant *C);
114 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
116 #include "ARMGenFastISel.inc"
118 // Instruction selection routines.
120 virtual bool SelectLoad(const Instruction *I);
121 virtual bool SelectStore(const Instruction *I);
122 virtual bool SelectBranch(const Instruction *I);
123 virtual bool SelectCmp(const Instruction *I);
124 virtual bool SelectFPExt(const Instruction *I);
125 virtual bool SelectFPTrunc(const Instruction *I);
126 virtual bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
127 virtual bool SelectSIToFP(const Instruction *I);
128 virtual bool SelectFPToSI(const Instruction *I);
129 virtual bool SelectSDiv(const Instruction *I);
130 virtual bool SelectCall(const Instruction *I);
131 virtual bool SelectSelect(const Instruction *I);
135 bool isTypeLegal(const Type *Ty, EVT &VT);
136 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
137 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
138 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
139 bool ARMLoadAlloca(const Instruction *I, EVT VT);
140 bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
141 bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
142 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
143 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
144 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
145 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
146 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
148 // Call handling routines.
150 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
151 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
152 SmallVectorImpl<unsigned> &ArgRegs,
153 SmallVectorImpl<EVT> &ArgVTs,
154 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
155 SmallVectorImpl<unsigned> &RegArgs,
158 bool FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
159 const Instruction *I, CallingConv::ID CC,
161 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
163 // OptionalDef handling routines.
165 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
166 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
169 } // end anonymous namespace
171 #include "ARMGenCallingConv.inc"
173 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
174 // we don't care about implicit defs here, just places we'll need to add a
175 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
176 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
177 const TargetInstrDesc &TID = MI->getDesc();
178 if (!TID.hasOptionalDef())
181 // Look to see if our OptionalDef is defining CPSR or CCR.
182 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
183 const MachineOperand &MO = MI->getOperand(i);
184 if (!MO.isReg() || !MO.isDef()) continue;
185 if (MO.getReg() == ARM::CPSR)
191 // If the machine is predicable go ahead and add the predicate operands, if
192 // it needs default CC operands add those.
193 const MachineInstrBuilder &
194 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
195 MachineInstr *MI = &*MIB;
197 // Do we use a predicate?
198 if (TII.isPredicable(MI))
201 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
202 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
204 if (DefinesOptionalPredicate(MI, &CPSR)) {
213 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
214 const TargetRegisterClass* RC) {
215 unsigned ResultReg = createResultReg(RC);
216 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
218 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
222 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
223 const TargetRegisterClass *RC,
224 unsigned Op0, bool Op0IsKill) {
225 unsigned ResultReg = createResultReg(RC);
226 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
228 if (II.getNumDefs() >= 1)
229 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
230 .addReg(Op0, Op0IsKill * RegState::Kill));
232 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
233 .addReg(Op0, Op0IsKill * RegState::Kill));
234 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
235 TII.get(TargetOpcode::COPY), ResultReg)
236 .addReg(II.ImplicitDefs[0]));
241 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
242 const TargetRegisterClass *RC,
243 unsigned Op0, bool Op0IsKill,
244 unsigned Op1, bool Op1IsKill) {
245 unsigned ResultReg = createResultReg(RC);
246 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
248 if (II.getNumDefs() >= 1)
249 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
250 .addReg(Op0, Op0IsKill * RegState::Kill)
251 .addReg(Op1, Op1IsKill * RegState::Kill));
253 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
254 .addReg(Op0, Op0IsKill * RegState::Kill)
255 .addReg(Op1, Op1IsKill * RegState::Kill));
256 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
257 TII.get(TargetOpcode::COPY), ResultReg)
258 .addReg(II.ImplicitDefs[0]));
263 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
264 const TargetRegisterClass *RC,
265 unsigned Op0, bool Op0IsKill,
267 unsigned ResultReg = createResultReg(RC);
268 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
270 if (II.getNumDefs() >= 1)
271 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
272 .addReg(Op0, Op0IsKill * RegState::Kill)
275 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
276 .addReg(Op0, Op0IsKill * RegState::Kill)
278 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
279 TII.get(TargetOpcode::COPY), ResultReg)
280 .addReg(II.ImplicitDefs[0]));
285 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
286 const TargetRegisterClass *RC,
287 unsigned Op0, bool Op0IsKill,
288 const ConstantFP *FPImm) {
289 unsigned ResultReg = createResultReg(RC);
290 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
292 if (II.getNumDefs() >= 1)
293 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
294 .addReg(Op0, Op0IsKill * RegState::Kill)
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
298 .addReg(Op0, Op0IsKill * RegState::Kill)
300 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
301 TII.get(TargetOpcode::COPY), ResultReg)
302 .addReg(II.ImplicitDefs[0]));
307 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
308 const TargetRegisterClass *RC,
309 unsigned Op0, bool Op0IsKill,
310 unsigned Op1, bool Op1IsKill,
312 unsigned ResultReg = createResultReg(RC);
313 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
315 if (II.getNumDefs() >= 1)
316 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
317 .addReg(Op0, Op0IsKill * RegState::Kill)
318 .addReg(Op1, Op1IsKill * RegState::Kill)
321 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
322 .addReg(Op0, Op0IsKill * RegState::Kill)
323 .addReg(Op1, Op1IsKill * RegState::Kill)
325 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
326 TII.get(TargetOpcode::COPY), ResultReg)
327 .addReg(II.ImplicitDefs[0]));
332 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
333 const TargetRegisterClass *RC,
335 unsigned ResultReg = createResultReg(RC);
336 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
338 if (II.getNumDefs() >= 1)
339 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
342 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
344 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
345 TII.get(TargetOpcode::COPY), ResultReg)
346 .addReg(II.ImplicitDefs[0]));
351 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
352 unsigned Op0, bool Op0IsKill,
354 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
355 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
356 "Cannot yet extract from physregs");
357 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
358 DL, TII.get(TargetOpcode::COPY), ResultReg)
359 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
363 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
364 // checks from the various callers.
365 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
366 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
368 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
369 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
370 TII.get(ARM::VMOVRS), MoveReg)
375 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
376 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
378 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
379 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
380 TII.get(ARM::VMOVSR), MoveReg)
385 // For double width floating point we need to materialize two constants
386 // (the high and the low) into integer registers then use a move to get
387 // the combined constant into an FP reg.
388 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
389 const APFloat Val = CFP->getValueAPF();
390 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
392 // This checks to see if we can use VFP3 instructions to materialize
393 // a constant, otherwise we have to go through the constant pool.
394 if (TLI.isFPImmLegal(Val, VT)) {
395 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
396 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
397 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
403 // Require VFP2 for loading fp constants.
404 if (!Subtarget->hasVFP2()) return false;
406 // MachineConstantPool wants an explicit alignment.
407 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
409 // TODO: Figure out if this is correct.
410 Align = TD.getTypeAllocSize(CFP->getType());
412 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
413 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
414 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
416 // The extra reg is for addrmode5.
417 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
419 .addConstantPoolIndex(Idx)
424 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
426 // For now 32-bit only.
427 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
429 // MachineConstantPool wants an explicit alignment.
430 unsigned Align = TD.getPrefTypeAlignment(C->getType());
432 // TODO: Figure out if this is correct.
433 Align = TD.getTypeAllocSize(C->getType());
435 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
436 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
439 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
440 TII.get(ARM::t2LDRpci), DestReg)
441 .addConstantPoolIndex(Idx));
443 // The extra reg and immediate are for addrmode2.
444 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
445 TII.get(ARM::LDRcp), DestReg)
446 .addConstantPoolIndex(Idx)
447 .addReg(0).addImm(0));
452 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
453 // For now 32-bit only.
454 if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0;
456 Reloc::Model RelocM = TM.getRelocationModel();
458 // TODO: No external globals for now.
459 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
461 // TODO: Need more magic for ARM PIC.
462 if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
464 // MachineConstantPool wants an explicit alignment.
465 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
467 // TODO: Figure out if this is correct.
468 Align = TD.getTypeAllocSize(GV->getType());
472 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
473 unsigned Id = AFI->createConstPoolEntryUId();
474 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
475 ARMCP::CPValue, PCAdj);
476 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
479 MachineInstrBuilder MIB;
480 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
482 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
483 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
484 .addConstantPoolIndex(Idx);
485 if (RelocM == Reloc::PIC_)
488 // The extra reg and immediate are for addrmode2.
489 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
491 .addConstantPoolIndex(Idx)
492 .addReg(0).addImm(0);
494 AddOptionalDefs(MIB);
498 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
499 EVT VT = TLI.getValueType(C->getType(), true);
501 // Only handle simple types.
502 if (!VT.isSimple()) return 0;
504 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
505 return ARMMaterializeFP(CFP, VT);
506 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
507 return ARMMaterializeGV(GV, VT);
508 else if (isa<ConstantInt>(C))
509 return ARMMaterializeInt(C, VT);
514 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
515 // Don't handle dynamic allocas.
516 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
519 if (!isTypeLegal(AI->getType(), VT)) return false;
521 DenseMap<const AllocaInst*, int>::iterator SI =
522 FuncInfo.StaticAllocaMap.find(AI);
524 // This will get lowered later into the correct offsets and registers
525 // via rewriteXFrameIndex.
526 if (SI != FuncInfo.StaticAllocaMap.end()) {
527 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
528 unsigned ResultReg = createResultReg(RC);
529 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
530 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
531 TII.get(Opc), ResultReg)
532 .addFrameIndex(SI->second)
540 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
541 VT = TLI.getValueType(Ty, true);
543 // Only handle simple types.
544 if (VT == MVT::Other || !VT.isSimple()) return false;
546 // Handle all legal types, i.e. a register that will directly hold this
548 return TLI.isTypeLegal(VT);
551 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
552 if (isTypeLegal(Ty, VT)) return true;
554 // If this is a type than can be sign or zero-extended to a basic operation
555 // go ahead and accept it now.
556 if (VT == MVT::i8 || VT == MVT::i16)
562 // Computes the Reg+Offset to get to an object.
563 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
565 // Some boilerplate from the X86 FastISel.
566 const User *U = NULL;
567 unsigned Opcode = Instruction::UserOp1;
568 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
569 // Don't walk into other basic blocks; it's possible we haven't
570 // visited them yet, so the instructions may not yet be assigned
571 // virtual registers.
572 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
574 Opcode = I->getOpcode();
576 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
577 Opcode = C->getOpcode();
581 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
582 if (Ty->getAddressSpace() > 255)
583 // Fast instruction selection doesn't support the special
590 case Instruction::Alloca: {
591 assert(false && "Alloca should have been handled earlier!");
596 // FIXME: Handle global variables.
597 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
602 // Try to get this in a register if nothing else has worked.
603 Reg = getRegForValue(Obj);
604 if (Reg == 0) return false;
606 // Since the offset may be too large for the load instruction
607 // get the reg+offset into a register.
608 // TODO: Verify the additions work, otherwise we'll need to add the
609 // offset instead of 0 to the instructions and do all sorts of operand
611 // TODO: Optimize this somewhat.
613 ARMCC::CondCodes Pred = ARMCC::AL;
614 unsigned PredReg = 0;
617 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
618 Reg, Reg, Offset, Pred, PredReg,
619 static_cast<const ARMBaseInstrInfo&>(TII));
621 assert(AFI->isThumb2Function());
622 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
623 Reg, Reg, Offset, Pred, PredReg,
624 static_cast<const ARMBaseInstrInfo&>(TII));
630 bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
631 Value *Op0 = I->getOperand(0);
633 // Promote load/store types.
634 if (VT == MVT::i8 || VT == MVT::i16) VT = MVT::i32;
636 // Verify it's an alloca.
637 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
638 DenseMap<const AllocaInst*, int>::iterator SI =
639 FuncInfo.StaticAllocaMap.find(AI);
641 if (SI != FuncInfo.StaticAllocaMap.end()) {
642 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
643 unsigned ResultReg = createResultReg(RC);
644 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
645 ResultReg, SI->second, RC,
646 TM.getRegisterInfo());
647 UpdateValueMap(I, ResultReg);
654 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
655 unsigned Reg, int Offset) {
657 assert(VT.isSimple() && "Non-simple types are invalid here!");
659 TargetRegisterClass *RC;
660 bool isFloat = false;
661 switch (VT.getSimpleVT().SimpleTy) {
663 // This is mostly going to be Neon/vector support.
666 Opc = isThumb ? ARM::t2LDRHi8 : ARM::LDRH;
667 RC = ARM::GPRRegisterClass;
671 Opc = isThumb ? ARM::t2LDRBi8 : ARM::LDRB;
672 RC = ARM::GPRRegisterClass;
676 Opc = isThumb ? ARM::t2LDRi8 : ARM::LDR;
677 RC = ARM::GPRRegisterClass;
681 RC = TLI.getRegClassFor(VT);
686 RC = TLI.getRegClassFor(VT);
691 ResultReg = createResultReg(RC);
693 // For now with the additions above the offset should be zero - thus we
694 // can always fit into an i8.
695 assert(Offset == 0 && "Offset not zero!");
697 // The thumb and floating point instructions both take 2 operands, ARM takes
699 if (isFloat || isThumb)
700 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
701 TII.get(Opc), ResultReg)
702 .addReg(Reg).addImm(Offset));
704 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
705 TII.get(Opc), ResultReg)
706 .addReg(Reg).addReg(0).addImm(Offset));
710 bool ARMFastISel::SelectLoad(const Instruction *I) {
711 // Verify we have a legal type before going any further.
713 if (!isLoadTypeLegal(I->getType(), VT))
716 // If we're an alloca we know we have a frame index and can emit the load
717 // directly in short order.
718 if (ARMLoadAlloca(I, VT))
721 // Our register and offset with innocuous defaults.
725 // See if we can handle this as Reg + Offset
726 if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
730 if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
732 UpdateValueMap(I, ResultReg);
736 bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
737 Value *Op1 = I->getOperand(1);
739 // Promote load/store types.
740 if (VT == MVT::i8 || VT == MVT::i16) VT = MVT::i32;
742 // Verify it's an alloca.
743 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
744 DenseMap<const AllocaInst*, int>::iterator SI =
745 FuncInfo.StaticAllocaMap.find(AI);
747 if (SI != FuncInfo.StaticAllocaMap.end()) {
748 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
749 assert(SrcReg != 0 && "Nothing to store!");
750 TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
751 SrcReg, true /*isKill*/, SI->second, RC,
752 TM.getRegisterInfo());
759 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
760 unsigned DstReg, int Offset) {
762 bool isFloat = false;
763 switch (VT.getSimpleVT().SimpleTy) {
764 default: return false;
766 case MVT::i8: StrOpc = isThumb ? ARM::t2STRBi8 : ARM::STRB; break;
767 case MVT::i16: StrOpc = isThumb ? ARM::t2STRHi8 : ARM::STRH; break;
768 case MVT::i32: StrOpc = isThumb ? ARM::t2STRi8 : ARM::STR; break;
770 if (!Subtarget->hasVFP2()) return false;
775 if (!Subtarget->hasVFP2()) return false;
781 // The thumb addressing mode has operands swapped from the arm addressing
782 // mode, the floating point one only has two operands.
783 if (isFloat || isThumb)
784 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
786 .addReg(SrcReg).addReg(DstReg).addImm(Offset));
788 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
790 .addReg(SrcReg).addReg(DstReg).addReg(0).addImm(Offset));
795 bool ARMFastISel::SelectStore(const Instruction *I) {
796 Value *Op0 = I->getOperand(0);
799 // Yay type legalization
801 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
804 // Get the value to be stored into a register.
805 SrcReg = getRegForValue(Op0);
809 // If we're an alloca we know we have a frame index and can emit the store
811 if (ARMStoreAlloca(I, SrcReg, VT))
814 // Our register and offset with innocuous defaults.
818 // See if we can handle this as Reg + Offset
819 if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
822 if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
827 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
829 // Needs two compares...
830 case CmpInst::FCMP_ONE:
831 case CmpInst::FCMP_UEQ:
833 assert(false && "Unhandled CmpInst::Predicate!");
835 case CmpInst::ICMP_EQ:
836 case CmpInst::FCMP_OEQ:
838 case CmpInst::ICMP_SGT:
839 case CmpInst::FCMP_OGT:
841 case CmpInst::ICMP_SGE:
842 case CmpInst::FCMP_OGE:
844 case CmpInst::ICMP_UGT:
845 case CmpInst::FCMP_UGT:
847 case CmpInst::FCMP_OLT:
849 case CmpInst::ICMP_ULE:
850 case CmpInst::FCMP_OLE:
852 case CmpInst::FCMP_ORD:
854 case CmpInst::FCMP_UNO:
856 case CmpInst::FCMP_UGE:
858 case CmpInst::ICMP_SLT:
859 case CmpInst::FCMP_ULT:
861 case CmpInst::ICMP_SLE:
862 case CmpInst::FCMP_ULE:
864 case CmpInst::FCMP_UNE:
865 case CmpInst::ICMP_NE:
867 case CmpInst::ICMP_UGE:
869 case CmpInst::ICMP_ULT:
874 bool ARMFastISel::SelectBranch(const Instruction *I) {
875 const BranchInst *BI = cast<BranchInst>(I);
876 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
877 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
879 // Simple branch support.
880 // TODO: Try to avoid the re-computation in some places.
881 unsigned CondReg = getRegForValue(BI->getCondition());
882 if (CondReg == 0) return false;
884 // Re-set the flags just in case.
885 unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri;
886 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
887 .addReg(CondReg).addImm(1));
889 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
890 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
891 .addMBB(TBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
892 FastEmitBranch(FBB, DL);
893 FuncInfo.MBB->addSuccessor(TBB);
897 bool ARMFastISel::SelectCmp(const Instruction *I) {
898 const CmpInst *CI = cast<CmpInst>(I);
901 const Type *Ty = CI->getOperand(0)->getType();
902 if (!isTypeLegal(Ty, VT))
905 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
906 if (isFloat && !Subtarget->hasVFP2())
911 switch (VT.getSimpleVT().SimpleTy) {
912 default: return false;
913 // TODO: Verify compares.
915 CmpOpc = ARM::VCMPES;
916 CondReg = ARM::FPSCR;
919 CmpOpc = ARM::VCMPED;
920 CondReg = ARM::FPSCR;
923 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
928 // Get the compare predicate.
929 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
931 // We may not handle every CC for now.
932 if (ARMPred == ARMCC::AL) return false;
934 unsigned Arg1 = getRegForValue(CI->getOperand(0));
935 if (Arg1 == 0) return false;
937 unsigned Arg2 = getRegForValue(CI->getOperand(1));
938 if (Arg2 == 0) return false;
940 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
941 .addReg(Arg1).addReg(Arg2));
943 // For floating point we need to move the result to a comparison register
944 // that we can then use for branches.
946 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
947 TII.get(ARM::FMSTAT)));
949 // Now set a register based on the comparison. Explicitly set the predicates
951 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
952 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
953 : ARM::GPRRegisterClass;
954 unsigned DestReg = createResultReg(RC);
956 = ConstantInt::get(Type::getInt32Ty(*Context), 0);
957 unsigned ZeroReg = TargetMaterializeConstant(Zero);
958 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
959 .addReg(ZeroReg).addImm(1)
960 .addImm(ARMPred).addReg(CondReg);
962 UpdateValueMap(I, DestReg);
966 bool ARMFastISel::SelectFPExt(const Instruction *I) {
967 // Make sure we have VFP and that we're extending float to double.
968 if (!Subtarget->hasVFP2()) return false;
970 Value *V = I->getOperand(0);
971 if (!I->getType()->isDoubleTy() ||
972 !V->getType()->isFloatTy()) return false;
974 unsigned Op = getRegForValue(V);
975 if (Op == 0) return false;
977 unsigned Result = createResultReg(ARM::DPRRegisterClass);
978 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
979 TII.get(ARM::VCVTDS), Result)
981 UpdateValueMap(I, Result);
985 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
986 // Make sure we have VFP and that we're truncating double to float.
987 if (!Subtarget->hasVFP2()) return false;
989 Value *V = I->getOperand(0);
990 if (!(I->getType()->isFloatTy() &&
991 V->getType()->isDoubleTy())) return false;
993 unsigned Op = getRegForValue(V);
994 if (Op == 0) return false;
996 unsigned Result = createResultReg(ARM::SPRRegisterClass);
997 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
998 TII.get(ARM::VCVTSD), Result)
1000 UpdateValueMap(I, Result);
1004 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1005 // Make sure we have VFP.
1006 if (!Subtarget->hasVFP2()) return false;
1009 const Type *Ty = I->getType();
1010 if (!isTypeLegal(Ty, DstVT))
1013 unsigned Op = getRegForValue(I->getOperand(0));
1014 if (Op == 0) return false;
1016 // The conversion routine works on fp-reg to fp-reg and the operand above
1017 // was an integer, move it to the fp registers if possible.
1018 unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1019 if (FP == 0) return false;
1022 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1023 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1026 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1027 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1030 UpdateValueMap(I, ResultReg);
1034 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1035 // Make sure we have VFP.
1036 if (!Subtarget->hasVFP2()) return false;
1039 const Type *RetTy = I->getType();
1040 if (!isTypeLegal(RetTy, DstVT))
1043 unsigned Op = getRegForValue(I->getOperand(0));
1044 if (Op == 0) return false;
1047 const Type *OpTy = I->getOperand(0)->getType();
1048 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1049 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1052 // f64->s32 or f32->s32 both need an intermediate f32 reg.
1053 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1054 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1058 // This result needs to be in an integer register, but the conversion only
1059 // takes place in fp-regs.
1060 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1061 if (IntReg == 0) return false;
1063 UpdateValueMap(I, IntReg);
1067 bool ARMFastISel::SelectSelect(const Instruction *I) {
1068 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1069 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1072 // Things need to be register sized for register moves.
1073 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
1074 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1076 unsigned CondReg = getRegForValue(I->getOperand(0));
1077 if (CondReg == 0) return false;
1078 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1079 if (Op1Reg == 0) return false;
1080 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1081 if (Op2Reg == 0) return false;
1083 unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1084 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1085 .addReg(CondReg).addImm(1));
1086 unsigned ResultReg = createResultReg(RC);
1087 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1088 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1089 .addReg(Op1Reg).addReg(Op2Reg)
1090 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1091 UpdateValueMap(I, ResultReg);
1095 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1097 const Type *Ty = I->getType();
1098 if (!isTypeLegal(Ty, VT))
1101 // If we have integer div support we should have selected this automagically.
1102 // In case we have a real miss go ahead and return false and we'll pick
1104 if (Subtarget->hasDivide()) return false;
1106 // Otherwise emit a libcall.
1107 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1109 LC = RTLIB::SDIV_I16;
1110 else if (VT == MVT::i32)
1111 LC = RTLIB::SDIV_I32;
1112 else if (VT == MVT::i64)
1113 LC = RTLIB::SDIV_I64;
1114 else if (VT == MVT::i128)
1115 LC = RTLIB::SDIV_I128;
1116 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1118 return ARMEmitLibcall(I, LC);
1121 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1122 EVT VT = TLI.getValueType(I->getType(), true);
1124 // We can get here in the case when we want to use NEON for our fp
1125 // operations, but can't figure out how to. Just use the vfp instructions
1127 // FIXME: It'd be nice to use NEON instructions.
1128 const Type *Ty = I->getType();
1129 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1130 if (isFloat && !Subtarget->hasVFP2())
1133 unsigned Op1 = getRegForValue(I->getOperand(0));
1134 if (Op1 == 0) return false;
1136 unsigned Op2 = getRegForValue(I->getOperand(1));
1137 if (Op2 == 0) return false;
1140 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
1141 VT.getSimpleVT().SimpleTy == MVT::i64;
1142 switch (ISDOpcode) {
1143 default: return false;
1145 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1148 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1151 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1154 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1155 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1156 TII.get(Opc), ResultReg)
1157 .addReg(Op1).addReg(Op2));
1158 UpdateValueMap(I, ResultReg);
1162 // Call Handling Code
1164 // This is largely taken directly from CCAssignFnForNode - we don't support
1165 // varargs in FastISel so that part has been removed.
1166 // TODO: We may not support all of this.
1167 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1170 llvm_unreachable("Unsupported calling convention");
1171 case CallingConv::C:
1172 case CallingConv::Fast:
1173 // Use target triple & subtarget features to do actual dispatch.
1174 if (Subtarget->isAAPCS_ABI()) {
1175 if (Subtarget->hasVFP2() &&
1176 FloatABIType == FloatABI::Hard)
1177 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1179 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1181 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1182 case CallingConv::ARM_AAPCS_VFP:
1183 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1184 case CallingConv::ARM_AAPCS:
1185 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1186 case CallingConv::ARM_APCS:
1187 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1191 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1192 SmallVectorImpl<unsigned> &ArgRegs,
1193 SmallVectorImpl<EVT> &ArgVTs,
1194 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1195 SmallVectorImpl<unsigned> &RegArgs,
1197 unsigned &NumBytes) {
1198 SmallVector<CCValAssign, 16> ArgLocs;
1199 CCState CCInfo(CC, false, TM, ArgLocs, *Context);
1200 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1202 // Get a count of how many bytes are to be pushed on the stack.
1203 NumBytes = CCInfo.getNextStackOffset();
1205 // Issue CALLSEQ_START
1206 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1207 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
1210 // Process the args.
1211 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1212 CCValAssign &VA = ArgLocs[i];
1213 unsigned Arg = ArgRegs[VA.getValNo()];
1214 EVT ArgVT = ArgVTs[VA.getValNo()];
1216 // Handle arg promotion, etc.
1217 switch (VA.getLocInfo()) {
1218 case CCValAssign::Full: break;
1220 // TODO: Handle arg promotion.
1224 // Now copy/store arg to correct locations.
1225 if (VA.isRegLoc()) {
1226 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1229 RegArgs.push_back(VA.getLocReg());
1239 bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1240 const Instruction *I, CallingConv::ID CC,
1241 unsigned &NumBytes) {
1242 // Issue CALLSEQ_END
1243 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1244 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
1245 .addImm(NumBytes).addImm(0);
1247 // Now the return value.
1248 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1249 SmallVector<CCValAssign, 16> RVLocs;
1250 CCState CCInfo(CC, false, TM, RVLocs, *Context);
1251 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1253 // Copy all of the result registers out of their specified physreg.
1254 if (RVLocs.size() == 2 && RetVT.getSimpleVT().SimpleTy == MVT::f64) {
1255 // For this move we copy into two registers and then move into the
1256 // double fp reg we want.
1257 // TODO: Are the copies necessary?
1258 TargetRegisterClass *CopyRC = TLI.getRegClassFor(MVT::i32);
1259 unsigned Copy1 = createResultReg(CopyRC);
1260 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1261 Copy1).addReg(RVLocs[0].getLocReg());
1262 UsedRegs.push_back(RVLocs[0].getLocReg());
1264 unsigned Copy2 = createResultReg(CopyRC);
1265 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1266 Copy2).addReg(RVLocs[1].getLocReg());
1267 UsedRegs.push_back(RVLocs[1].getLocReg());
1269 EVT DestVT = RVLocs[0].getValVT();
1270 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1271 unsigned ResultReg = createResultReg(DstRC);
1272 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1273 TII.get(ARM::VMOVDRR), ResultReg)
1274 .addReg(Copy1).addReg(Copy2));
1276 // Finally update the result.
1277 UpdateValueMap(I, ResultReg);
1279 assert(RVLocs.size() == 1 && "Can't handle non-double multi-reg retvals!");
1280 EVT CopyVT = RVLocs[0].getValVT();
1281 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1283 unsigned ResultReg = createResultReg(DstRC);
1284 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1285 ResultReg).addReg(RVLocs[0].getLocReg());
1286 UsedRegs.push_back(RVLocs[0].getLocReg());
1288 // Finally update the result.
1289 UpdateValueMap(I, ResultReg);
1296 // A quick function that will emit a call for a named libcall in F with the
1297 // vector of passed arguments for the Instruction in I. We can assume that we
1298 // can emit a call for any libcall we can produce. This is an abridged version
1299 // of the full call infrastructure since we won't need to worry about things
1300 // like computed function pointers or strange arguments at call sites.
1301 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1303 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1304 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1306 // Handle *simple* calls for now.
1307 const Type *RetTy = I->getType();
1309 if (RetTy->isVoidTy())
1310 RetVT = MVT::isVoid;
1311 else if (!isTypeLegal(RetTy, RetVT))
1314 // For now we're using BLX etc on the assumption that we have v5t ops.
1315 if (!Subtarget->hasV5TOps()) return false;
1317 // Set up the argument vectors.
1318 SmallVector<Value*, 8> Args;
1319 SmallVector<unsigned, 8> ArgRegs;
1320 SmallVector<EVT, 8> ArgVTs;
1321 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1322 Args.reserve(I->getNumOperands());
1323 ArgRegs.reserve(I->getNumOperands());
1324 ArgVTs.reserve(I->getNumOperands());
1325 ArgFlags.reserve(I->getNumOperands());
1326 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1327 Value *Op = I->getOperand(i);
1328 unsigned Arg = getRegForValue(Op);
1329 if (Arg == 0) return false;
1331 const Type *ArgTy = Op->getType();
1333 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1335 ISD::ArgFlagsTy Flags;
1336 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1337 Flags.setOrigAlign(OriginalAlignment);
1340 ArgRegs.push_back(Arg);
1341 ArgVTs.push_back(ArgVT);
1342 ArgFlags.push_back(Flags);
1345 // Handle the arguments now that we've gotten them.
1346 SmallVector<unsigned, 4> RegArgs;
1348 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1351 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1352 // TODO: Turn this into the table of arm call ops.
1353 MachineInstrBuilder MIB;
1356 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1358 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1359 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1360 .addExternalSymbol(TLI.getLibcallName(Call));
1362 // Add implicit physical register uses to the call.
1363 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1364 MIB.addReg(RegArgs[i]);
1366 // Finish off the call including any return values.
1367 SmallVector<unsigned, 4> UsedRegs;
1368 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1370 // Set all unused physreg defs as dead.
1371 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1376 bool ARMFastISel::SelectCall(const Instruction *I) {
1377 const CallInst *CI = cast<CallInst>(I);
1378 const Value *Callee = CI->getCalledValue();
1380 // Can't handle inline asm or worry about intrinsics yet.
1381 if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1383 // Only handle global variable Callees that are direct calls.
1384 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1385 if (!GV || Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()))
1388 // Check the calling convention.
1389 ImmutableCallSite CS(CI);
1390 CallingConv::ID CC = CS.getCallingConv();
1391 // TODO: Avoid some calling conventions?
1392 if (CC != CallingConv::C) {
1393 // errs() << "Can't handle calling convention: " << CC << "\n";
1397 // Let SDISel handle vararg functions.
1398 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1399 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1400 if (FTy->isVarArg())
1403 // Handle *simple* calls for now.
1404 const Type *RetTy = I->getType();
1406 if (RetTy->isVoidTy())
1407 RetVT = MVT::isVoid;
1408 else if (!isTypeLegal(RetTy, RetVT))
1411 // For now we're using BLX etc on the assumption that we have v5t ops.
1413 if (!Subtarget->hasV5TOps()) return false;
1415 // Set up the argument vectors.
1416 SmallVector<Value*, 8> Args;
1417 SmallVector<unsigned, 8> ArgRegs;
1418 SmallVector<EVT, 8> ArgVTs;
1419 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1420 Args.reserve(CS.arg_size());
1421 ArgRegs.reserve(CS.arg_size());
1422 ArgVTs.reserve(CS.arg_size());
1423 ArgFlags.reserve(CS.arg_size());
1424 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1426 unsigned Arg = getRegForValue(*i);
1430 ISD::ArgFlagsTy Flags;
1431 unsigned AttrInd = i - CS.arg_begin() + 1;
1432 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1434 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1437 // FIXME: Only handle *easy* calls for now.
1438 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1439 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1440 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1441 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1444 const Type *ArgTy = (*i)->getType();
1446 if (!isTypeLegal(ArgTy, ArgVT))
1448 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1449 Flags.setOrigAlign(OriginalAlignment);
1452 ArgRegs.push_back(Arg);
1453 ArgVTs.push_back(ArgVT);
1454 ArgFlags.push_back(Flags);
1457 // Handle the arguments now that we've gotten them.
1458 SmallVector<unsigned, 4> RegArgs;
1460 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1463 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1464 // TODO: Turn this into the table of arm call ops.
1465 MachineInstrBuilder MIB;
1468 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1470 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1471 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1472 .addGlobalAddress(GV, 0, 0);
1474 // Add implicit physical register uses to the call.
1475 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1476 MIB.addReg(RegArgs[i]);
1478 // Finish off the call including any return values.
1479 SmallVector<unsigned, 4> UsedRegs;
1480 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1482 // Set all unused physreg defs as dead.
1483 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1489 // TODO: SoftFP support.
1490 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1491 // No Thumb-1 for now.
1492 if (isThumb && !AFI->isThumb2Function()) return false;
1494 switch (I->getOpcode()) {
1495 case Instruction::Load:
1496 return SelectLoad(I);
1497 case Instruction::Store:
1498 return SelectStore(I);
1499 case Instruction::Br:
1500 return SelectBranch(I);
1501 case Instruction::ICmp:
1502 case Instruction::FCmp:
1503 return SelectCmp(I);
1504 case Instruction::FPExt:
1505 return SelectFPExt(I);
1506 case Instruction::FPTrunc:
1507 return SelectFPTrunc(I);
1508 case Instruction::SIToFP:
1509 return SelectSIToFP(I);
1510 case Instruction::FPToSI:
1511 return SelectFPToSI(I);
1512 case Instruction::FAdd:
1513 return SelectBinaryOp(I, ISD::FADD);
1514 case Instruction::FSub:
1515 return SelectBinaryOp(I, ISD::FSUB);
1516 case Instruction::FMul:
1517 return SelectBinaryOp(I, ISD::FMUL);
1518 case Instruction::SDiv:
1519 return SelectSDiv(I);
1520 case Instruction::Call:
1521 return SelectCall(I);
1522 case Instruction::Select:
1523 return SelectSelect(I);
1530 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1531 if (EnableARMFastISel) return new ARMFastISel(funcInfo);