1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/Module.h"
28 #include "llvm/CodeGen/Analysis.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/FunctionLoweringInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineConstantPool.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/Support/CallSite.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/GetElementPtrTypeIterator.h"
40 #include "llvm/Target/TargetData.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
48 EnableARMFastISel("arm-fast-isel",
49 cl::desc("Turn on experimental ARM fast-isel support"),
50 cl::init(false), cl::Hidden);
54 class ARMFastISel : public FastISel {
56 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
57 /// make the right decision when generating code for different targets.
58 const ARMSubtarget *Subtarget;
59 const TargetMachine &TM;
60 const TargetInstrInfo &TII;
61 const TargetLowering &TLI;
62 const ARMFunctionInfo *AFI;
64 // Convenience variable to avoid checking all the time.
68 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
70 TM(funcInfo.MF->getTarget()),
71 TII(*TM.getInstrInfo()),
72 TLI(*TM.getTargetLowering()) {
73 Subtarget = &TM.getSubtarget<ARMSubtarget>();
74 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
75 isThumb = AFI->isThumbFunction();
78 // Code from FastISel.cpp.
79 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
80 const TargetRegisterClass *RC);
81 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
82 const TargetRegisterClass *RC,
83 unsigned Op0, bool Op0IsKill);
84 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
85 const TargetRegisterClass *RC,
86 unsigned Op0, bool Op0IsKill,
87 unsigned Op1, bool Op1IsKill);
88 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
89 const TargetRegisterClass *RC,
90 unsigned Op0, bool Op0IsKill,
92 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
93 const TargetRegisterClass *RC,
94 unsigned Op0, bool Op0IsKill,
95 const ConstantFP *FPImm);
96 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
97 const TargetRegisterClass *RC,
99 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
100 const TargetRegisterClass *RC,
101 unsigned Op0, bool Op0IsKill,
102 unsigned Op1, bool Op1IsKill,
104 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
105 unsigned Op0, bool Op0IsKill,
108 // Backend specific FastISel code.
109 virtual bool TargetSelectInstruction(const Instruction *I);
110 virtual unsigned TargetMaterializeConstant(const Constant *C);
112 #include "ARMGenFastISel.inc"
114 // Instruction selection routines.
116 virtual bool SelectLoad(const Instruction *I);
117 virtual bool SelectStore(const Instruction *I);
118 virtual bool SelectBranch(const Instruction *I);
119 virtual bool SelectCmp(const Instruction *I);
120 virtual bool SelectFPExt(const Instruction *I);
121 virtual bool SelectFPTrunc(const Instruction *I);
122 virtual bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
123 virtual bool SelectSIToFP(const Instruction *I);
124 virtual bool SelectFPToSI(const Instruction *I);
125 virtual bool SelectSDiv(const Instruction *I);
129 bool isTypeLegal(const Type *Ty, EVT &VT);
130 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
131 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
132 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
133 bool ARMLoadAlloca(const Instruction *I, EVT VT);
134 bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
135 bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
136 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
137 unsigned ARMMaterializeInt(const Constant *C);
138 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
139 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
141 // Call handling routines.
143 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
144 bool ARMEmitLibcall(const Instruction *I, Function *F);
146 // OptionalDef handling routines.
148 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
149 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
152 } // end anonymous namespace
154 #include "ARMGenCallingConv.inc"
156 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
157 // we don't care about implicit defs here, just places we'll need to add a
158 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
159 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
160 const TargetInstrDesc &TID = MI->getDesc();
161 if (!TID.hasOptionalDef())
164 // Look to see if our OptionalDef is defining CPSR or CCR.
165 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
166 const MachineOperand &MO = MI->getOperand(i);
167 if (!MO.isReg() || !MO.isDef()) continue;
168 if (MO.getReg() == ARM::CPSR)
174 // If the machine is predicable go ahead and add the predicate operands, if
175 // it needs default CC operands add those.
176 const MachineInstrBuilder &
177 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
178 MachineInstr *MI = &*MIB;
180 // Do we use a predicate?
181 if (TII.isPredicable(MI))
184 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
185 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
187 if (DefinesOptionalPredicate(MI, &CPSR)) {
196 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
197 const TargetRegisterClass* RC) {
198 unsigned ResultReg = createResultReg(RC);
199 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
201 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
205 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
206 const TargetRegisterClass *RC,
207 unsigned Op0, bool Op0IsKill) {
208 unsigned ResultReg = createResultReg(RC);
209 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
211 if (II.getNumDefs() >= 1)
212 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
213 .addReg(Op0, Op0IsKill * RegState::Kill));
215 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
216 .addReg(Op0, Op0IsKill * RegState::Kill));
217 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
218 TII.get(TargetOpcode::COPY), ResultReg)
219 .addReg(II.ImplicitDefs[0]));
224 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
225 const TargetRegisterClass *RC,
226 unsigned Op0, bool Op0IsKill,
227 unsigned Op1, bool Op1IsKill) {
228 unsigned ResultReg = createResultReg(RC);
229 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
231 if (II.getNumDefs() >= 1)
232 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
233 .addReg(Op0, Op0IsKill * RegState::Kill)
234 .addReg(Op1, Op1IsKill * RegState::Kill));
236 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
237 .addReg(Op0, Op0IsKill * RegState::Kill)
238 .addReg(Op1, Op1IsKill * RegState::Kill));
239 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
240 TII.get(TargetOpcode::COPY), ResultReg)
241 .addReg(II.ImplicitDefs[0]));
246 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
247 const TargetRegisterClass *RC,
248 unsigned Op0, bool Op0IsKill,
250 unsigned ResultReg = createResultReg(RC);
251 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
253 if (II.getNumDefs() >= 1)
254 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
255 .addReg(Op0, Op0IsKill * RegState::Kill)
258 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
259 .addReg(Op0, Op0IsKill * RegState::Kill)
261 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
262 TII.get(TargetOpcode::COPY), ResultReg)
263 .addReg(II.ImplicitDefs[0]));
268 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
269 const TargetRegisterClass *RC,
270 unsigned Op0, bool Op0IsKill,
271 const ConstantFP *FPImm) {
272 unsigned ResultReg = createResultReg(RC);
273 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
275 if (II.getNumDefs() >= 1)
276 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
277 .addReg(Op0, Op0IsKill * RegState::Kill)
280 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
281 .addReg(Op0, Op0IsKill * RegState::Kill)
283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
284 TII.get(TargetOpcode::COPY), ResultReg)
285 .addReg(II.ImplicitDefs[0]));
290 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
291 const TargetRegisterClass *RC,
292 unsigned Op0, bool Op0IsKill,
293 unsigned Op1, bool Op1IsKill,
295 unsigned ResultReg = createResultReg(RC);
296 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
298 if (II.getNumDefs() >= 1)
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
300 .addReg(Op0, Op0IsKill * RegState::Kill)
301 .addReg(Op1, Op1IsKill * RegState::Kill)
304 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
305 .addReg(Op0, Op0IsKill * RegState::Kill)
306 .addReg(Op1, Op1IsKill * RegState::Kill)
308 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
309 TII.get(TargetOpcode::COPY), ResultReg)
310 .addReg(II.ImplicitDefs[0]));
315 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
316 const TargetRegisterClass *RC,
318 unsigned ResultReg = createResultReg(RC);
319 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
321 if (II.getNumDefs() >= 1)
322 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
325 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
327 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
328 TII.get(TargetOpcode::COPY), ResultReg)
329 .addReg(II.ImplicitDefs[0]));
334 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
335 unsigned Op0, bool Op0IsKill,
337 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
338 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
339 "Cannot yet extract from physregs");
340 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
341 DL, TII.get(TargetOpcode::COPY), ResultReg)
342 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
346 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
347 // checks from the various callers.
348 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
349 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
351 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
352 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
353 TII.get(ARM::VMOVRS), MoveReg)
358 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
359 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
361 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
362 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
363 TII.get(ARM::VMOVSR), MoveReg)
368 // For double width floating point we need to materialize two constants
369 // (the high and the low) into integer registers then use a move to get
370 // the combined constant into an FP reg.
371 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
372 const APFloat Val = CFP->getValueAPF();
373 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
375 // This checks to see if we can use VFP3 instructions to materialize
376 // a constant, otherwise we have to go through the constant pool.
377 if (TLI.isFPImmLegal(Val, VT)) {
378 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
379 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
380 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
386 // Require VFP2 for loading fp constants.
387 if (!Subtarget->hasVFP2()) return false;
389 // MachineConstantPool wants an explicit alignment.
390 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
392 // TODO: Figure out if this is correct.
393 Align = TD.getTypeAllocSize(CFP->getType());
395 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
396 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
397 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
399 // The extra reg is for addrmode5.
400 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
401 .addReg(DestReg).addConstantPoolIndex(Idx)
406 // TODO: Verify 64-bit.
407 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) {
408 // MachineConstantPool wants an explicit alignment.
409 unsigned Align = TD.getPrefTypeAlignment(C->getType());
411 // TODO: Figure out if this is correct.
412 Align = TD.getTypeAllocSize(C->getType());
414 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
415 unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
418 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
419 TII.get(ARM::t2LDRpci))
420 .addReg(DestReg).addConstantPoolIndex(Idx));
422 // The extra reg and immediate are for addrmode2.
423 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
425 .addReg(DestReg).addConstantPoolIndex(Idx)
426 .addReg(0).addImm(0));
431 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
432 EVT VT = TLI.getValueType(C->getType(), true);
434 // Only handle simple types.
435 if (!VT.isSimple()) return 0;
437 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
438 return ARMMaterializeFP(CFP, VT);
439 return ARMMaterializeInt(C);
442 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
443 VT = TLI.getValueType(Ty, true);
445 // Only handle simple types.
446 if (VT == MVT::Other || !VT.isSimple()) return false;
448 // Handle all legal types, i.e. a register that will directly hold this
450 return TLI.isTypeLegal(VT);
453 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
454 if (isTypeLegal(Ty, VT)) return true;
456 // If this is a type than can be sign or zero-extended to a basic operation
457 // go ahead and accept it now.
458 if (VT == MVT::i8 || VT == MVT::i16)
464 // Computes the Reg+Offset to get to an object.
465 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
467 // Some boilerplate from the X86 FastISel.
468 const User *U = NULL;
469 unsigned Opcode = Instruction::UserOp1;
470 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
471 // Don't walk into other basic blocks; it's possible we haven't
472 // visited them yet, so the instructions may not yet be assigned
473 // virtual registers.
474 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
476 Opcode = I->getOpcode();
478 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
479 Opcode = C->getOpcode();
483 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
484 if (Ty->getAddressSpace() > 255)
485 // Fast instruction selection doesn't support the special
492 case Instruction::Alloca: {
493 assert(false && "Alloca should have been handled earlier!");
498 // FIXME: Handle global variables.
499 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
504 // Try to get this in a register if nothing else has worked.
505 Reg = getRegForValue(Obj);
506 if (Reg == 0) return false;
508 // Since the offset may be too large for the load instruction
509 // get the reg+offset into a register.
510 // TODO: Verify the additions work, otherwise we'll need to add the
511 // offset instead of 0 to the instructions and do all sorts of operand
513 // TODO: Optimize this somewhat.
515 ARMCC::CondCodes Pred = ARMCC::AL;
516 unsigned PredReg = 0;
519 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
520 Reg, Reg, Offset, Pred, PredReg,
521 static_cast<const ARMBaseInstrInfo&>(TII));
523 assert(AFI->isThumb2Function());
524 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
525 Reg, Reg, Offset, Pred, PredReg,
526 static_cast<const ARMBaseInstrInfo&>(TII));
532 bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
533 Value *Op0 = I->getOperand(0);
535 // Verify it's an alloca.
536 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
537 DenseMap<const AllocaInst*, int>::iterator SI =
538 FuncInfo.StaticAllocaMap.find(AI);
540 if (SI != FuncInfo.StaticAllocaMap.end()) {
541 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
542 unsigned ResultReg = createResultReg(RC);
543 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
544 ResultReg, SI->second, RC,
545 TM.getRegisterInfo());
546 UpdateValueMap(I, ResultReg);
553 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
554 unsigned Reg, int Offset) {
556 assert(VT.isSimple() && "Non-simple types are invalid here!");
558 bool isFloat = false;
559 switch (VT.getSimpleVT().SimpleTy) {
561 assert(false && "Trying to emit for an unhandled type!");
564 Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
568 Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
572 Opc = isThumb ? ARM::tLDR : ARM::LDR;
584 ResultReg = createResultReg(TLI.getRegClassFor(VT));
586 // TODO: Fix the Addressing modes so that these can share some code.
587 // Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
588 // The thumb addressing mode has operands swapped from the arm addressing
589 // mode, the floating point one only has two operands.
591 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
592 TII.get(Opc), ResultReg)
593 .addReg(Reg).addImm(Offset));
595 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
596 TII.get(Opc), ResultReg)
597 .addReg(Reg).addImm(Offset).addReg(0));
599 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
600 TII.get(Opc), ResultReg)
601 .addReg(Reg).addReg(0).addImm(Offset));
605 bool ARMFastISel::SelectLoad(const Instruction *I) {
606 // Verify we have a legal type before going any further.
608 if (!isLoadTypeLegal(I->getType(), VT))
611 // If we're an alloca we know we have a frame index and can emit the load
612 // directly in short order.
613 if (ARMLoadAlloca(I, VT))
616 // Our register and offset with innocuous defaults.
620 // See if we can handle this as Reg + Offset
621 if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
625 if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
627 UpdateValueMap(I, ResultReg);
631 bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
632 Value *Op1 = I->getOperand(1);
634 // Verify it's an alloca.
635 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
636 DenseMap<const AllocaInst*, int>::iterator SI =
637 FuncInfo.StaticAllocaMap.find(AI);
639 if (SI != FuncInfo.StaticAllocaMap.end()) {
640 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
641 assert(SrcReg != 0 && "Nothing to store!");
642 TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
643 SrcReg, true /*isKill*/, SI->second, RC,
644 TM.getRegisterInfo());
651 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
652 unsigned DstReg, int Offset) {
654 bool isFloat = false;
655 switch (VT.getSimpleVT().SimpleTy) {
656 default: return false;
658 case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break;
659 case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break;
660 case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break;
662 if (!Subtarget->hasVFP2()) return false;
667 if (!Subtarget->hasVFP2()) return false;
673 // The thumb addressing mode has operands swapped from the arm addressing
674 // mode, the floating point one only has two operands.
676 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
677 TII.get(StrOpc), SrcReg)
678 .addReg(DstReg).addImm(Offset));
680 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
681 TII.get(StrOpc), SrcReg)
682 .addReg(DstReg).addImm(Offset).addReg(0));
685 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
686 TII.get(StrOpc), SrcReg)
687 .addReg(DstReg).addReg(0).addImm(Offset));
692 bool ARMFastISel::SelectStore(const Instruction *I) {
693 Value *Op0 = I->getOperand(0);
696 // Yay type legalization
698 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
701 // Get the value to be stored into a register.
702 SrcReg = getRegForValue(Op0);
706 // If we're an alloca we know we have a frame index and can emit the store
708 if (ARMStoreAlloca(I, SrcReg, VT))
711 // Our register and offset with innocuous defaults.
715 // See if we can handle this as Reg + Offset
716 if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
719 if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
724 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
726 // Needs two compares...
727 case CmpInst::FCMP_ONE:
728 case CmpInst::FCMP_UEQ:
730 assert(false && "Unhandled CmpInst::Predicate!");
732 case CmpInst::ICMP_EQ:
733 case CmpInst::FCMP_OEQ:
735 case CmpInst::ICMP_SGT:
736 case CmpInst::FCMP_OGT:
738 case CmpInst::ICMP_SGE:
739 case CmpInst::FCMP_OGE:
741 case CmpInst::ICMP_UGT:
742 case CmpInst::FCMP_UGT:
744 case CmpInst::FCMP_OLT:
746 case CmpInst::ICMP_ULE:
747 case CmpInst::FCMP_OLE:
749 case CmpInst::FCMP_ORD:
751 case CmpInst::FCMP_UNO:
753 case CmpInst::FCMP_UGE:
755 case CmpInst::ICMP_SLT:
756 case CmpInst::FCMP_ULT:
758 case CmpInst::ICMP_SLE:
759 case CmpInst::FCMP_ULE:
761 case CmpInst::FCMP_UNE:
762 case CmpInst::ICMP_NE:
764 case CmpInst::ICMP_UGE:
766 case CmpInst::ICMP_ULT:
771 bool ARMFastISel::SelectBranch(const Instruction *I) {
772 const BranchInst *BI = cast<BranchInst>(I);
773 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
774 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
776 // Simple branch support.
777 // TODO: Hopefully we've already handled the condition since we won't
778 // have left an update in the value map. See the TODO below in SelectCMP.
779 Value *Cond = BI->getCondition();
780 unsigned CondReg = getRegForValue(Cond);
781 if (CondReg == 0) return false;
783 ARMCC::CondCodes ARMPred = ARMCC::NE;
784 CmpInst *CI = dyn_cast<CmpInst>(Cond);
785 if (!CI) return false;
787 // Get the compare predicate.
788 ARMPred = getComparePred(CI->getPredicate());
790 // We may not handle every CC for now.
791 if (ARMPred == ARMCC::AL) return false;
793 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
794 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
795 .addMBB(TBB).addImm(ARMPred).addReg(CondReg);
796 FastEmitBranch(FBB, DL);
797 FuncInfo.MBB->addSuccessor(TBB);
801 bool ARMFastISel::SelectCmp(const Instruction *I) {
802 const CmpInst *CI = cast<CmpInst>(I);
805 const Type *Ty = CI->getOperand(0)->getType();
806 if (!isTypeLegal(Ty, VT))
809 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
810 if (isFloat && !Subtarget->hasVFP2())
815 switch (VT.getSimpleVT().SimpleTy) {
816 default: return false;
817 // TODO: Verify compares.
819 CmpOpc = ARM::VCMPES;
820 DestReg = ARM::FPSCR;
823 CmpOpc = ARM::VCMPED;
824 DestReg = ARM::FPSCR;
827 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
832 unsigned Arg1 = getRegForValue(CI->getOperand(0));
833 if (Arg1 == 0) return false;
835 unsigned Arg2 = getRegForValue(CI->getOperand(1));
836 if (Arg2 == 0) return false;
838 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
839 .addReg(Arg1).addReg(Arg2));
841 // For floating point we need to move the result to a comparison register
842 // that we can then use for branches.
844 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
845 TII.get(ARM::FMSTAT)));
847 // Update the value to the implicit def reg.
848 UpdateValueMap(I, DestReg);
852 bool ARMFastISel::SelectFPExt(const Instruction *I) {
853 // Make sure we have VFP and that we're extending float to double.
854 if (!Subtarget->hasVFP2()) return false;
856 Value *V = I->getOperand(0);
857 if (!I->getType()->isDoubleTy() ||
858 !V->getType()->isFloatTy()) return false;
860 unsigned Op = getRegForValue(V);
861 if (Op == 0) return false;
863 unsigned Result = createResultReg(ARM::DPRRegisterClass);
864 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
865 TII.get(ARM::VCVTDS), Result)
867 UpdateValueMap(I, Result);
871 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
872 // Make sure we have VFP and that we're truncating double to float.
873 if (!Subtarget->hasVFP2()) return false;
875 Value *V = I->getOperand(0);
876 if (!I->getType()->isFloatTy() ||
877 !V->getType()->isDoubleTy()) return false;
879 unsigned Op = getRegForValue(V);
880 if (Op == 0) return false;
882 unsigned Result = createResultReg(ARM::SPRRegisterClass);
883 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
884 TII.get(ARM::VCVTSD), Result)
886 UpdateValueMap(I, Result);
890 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
891 // Make sure we have VFP.
892 if (!Subtarget->hasVFP2()) return false;
895 const Type *Ty = I->getType();
896 if (!isTypeLegal(Ty, DstVT))
899 unsigned Op = getRegForValue(I->getOperand(0));
900 if (Op == 0) return false;
902 // The conversion routine works on fp-reg to fp-reg and the operand above
903 // was an integer, move it to the fp registers if possible.
904 unsigned FP = ARMMoveToFPReg(DstVT, Op);
905 if (FP == 0) return false;
908 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
909 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
912 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
913 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
916 UpdateValueMap(I, ResultReg);
920 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
921 // Make sure we have VFP.
922 if (!Subtarget->hasVFP2()) return false;
925 const Type *RetTy = I->getType();
926 if (!isTypeLegal(RetTy, DstVT))
929 unsigned Op = getRegForValue(I->getOperand(0));
930 if (Op == 0) return false;
933 const Type *OpTy = I->getOperand(0)->getType();
934 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
935 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
937 EVT OpVT = TLI.getValueType(OpTy, true);
939 unsigned ResultReg = createResultReg(TLI.getRegClassFor(OpVT));
940 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
944 // This result needs to be in an integer register, but the conversion only
945 // takes place in fp-regs.
946 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
947 if (IntReg == 0) return false;
949 UpdateValueMap(I, IntReg);
953 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
954 EVT VT = TLI.getValueType(I->getType(), true);
956 // We can get here in the case when we want to use NEON for our fp
957 // operations, but can't figure out how to. Just use the vfp instructions
959 // FIXME: It'd be nice to use NEON instructions.
960 const Type *Ty = I->getType();
961 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
962 if (isFloat && !Subtarget->hasVFP2())
965 unsigned Op1 = getRegForValue(I->getOperand(0));
966 if (Op1 == 0) return false;
968 unsigned Op2 = getRegForValue(I->getOperand(1));
969 if (Op2 == 0) return false;
972 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
973 VT.getSimpleVT().SimpleTy == MVT::i64;
975 default: return false;
977 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
980 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
983 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
986 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
987 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
988 TII.get(Opc), ResultReg)
989 .addReg(Op1).addReg(Op2));
990 UpdateValueMap(I, ResultReg);
994 // Call Handling Code
996 // This is largely taken directly from CCAssignFnForNode - we don't support
997 // varargs in FastISel so that part has been removed.
998 // TODO: We may not support all of this.
999 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1002 llvm_unreachable("Unsupported calling convention");
1003 case CallingConv::C:
1004 case CallingConv::Fast:
1005 // Use target triple & subtarget features to do actual dispatch.
1006 if (Subtarget->isAAPCS_ABI()) {
1007 if (Subtarget->hasVFP2() &&
1008 FloatABIType == FloatABI::Hard)
1009 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1011 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1013 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1014 case CallingConv::ARM_AAPCS_VFP:
1015 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1016 case CallingConv::ARM_AAPCS:
1017 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1018 case CallingConv::ARM_APCS:
1019 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1023 // A quick function that will emit a call for a named libcall in F with the
1024 // vector of passed arguments for the Instruction in I. We can assume that we
1025 // can emit a call for any libcall we can produce. This is an abridged version
1026 // of the full call infrastructure since we won't need to worry about things
1027 // like computed function pointers or strange arguments at call sites.
1028 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1030 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, Function *F) {
1031 CallingConv::ID CC = F->getCallingConv();
1033 // Handle *simple* calls for now.
1034 const Type *RetTy = F->getReturnType();
1036 if (RetTy->isVoidTy())
1037 RetVT = MVT::isVoid;
1038 else if (!isTypeLegal(RetTy, RetVT))
1041 assert(!F->isVarArg() && "Vararg libcall?!");
1043 // Abridged from the X86 FastISel call selection mechanism
1044 SmallVector<Value*, 8> Args;
1045 SmallVector<unsigned, 8> ArgRegs;
1046 SmallVector<EVT, 8> ArgVTs;
1047 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1048 Args.reserve(I->getNumOperands());
1049 ArgRegs.reserve(I->getNumOperands());
1050 ArgVTs.reserve(I->getNumOperands());
1051 ArgFlags.reserve(I->getNumOperands());
1052 for (unsigned i = 0; i < Args.size(); ++i) {
1053 Value *Op = I->getOperand(i);
1054 unsigned Arg = getRegForValue(Op);
1055 if (Arg == 0) return false;
1057 const Type *ArgTy = Op->getType();
1059 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1061 ISD::ArgFlagsTy Flags;
1062 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1063 Flags.setOrigAlign(OriginalAlignment);
1066 ArgRegs.push_back(Arg);
1067 ArgVTs.push_back(ArgVT);
1068 ArgFlags.push_back(Flags);
1071 SmallVector<CCValAssign, 16> ArgLocs;
1072 CCState CCInfo(CC, false, TM, ArgLocs, F->getContext());
1073 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1075 // Process the args.
1076 SmallVector<unsigned, 4> RegArgs;
1077 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1078 CCValAssign &VA = ArgLocs[i];
1079 unsigned Arg = ArgRegs[VA.getValNo()];
1080 EVT ArgVT = ArgVTs[VA.getValNo()];
1082 // Should we ever have to promote?
1083 switch (VA.getLocInfo()) {
1084 case CCValAssign::Full: break;
1086 assert(false && "Handle arg promotion for libcalls?");
1090 // Now copy/store arg to correct locations.
1091 if (VA.isRegLoc()) {
1092 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1093 VA.getLocReg()).addReg(Arg);
1094 RegArgs.push_back(VA.getLocReg());
1101 // Issue the call, BLr9 for darwin, BL otherwise.
1102 MachineInstrBuilder MIB;
1105 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLr9 : ARM::tBL;
1107 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1108 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1109 .addGlobalAddress(F, 0, 0);
1111 // Add implicit physical register uses to the call.
1112 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1113 MIB.addReg(RegArgs[i]);
1115 // Now the return value.
1116 SmallVector<unsigned, 4> UsedRegs;
1117 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1118 SmallVector<CCValAssign, 16> RVLocs;
1119 CCState CCInfo(CC, false, TM, RVLocs, F->getContext());
1120 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1122 // Copy all of the result registers out of their specified physreg.
1123 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1124 EVT CopyVT = RVLocs[0].getValVT();
1125 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1127 unsigned ResultReg = createResultReg(DstRC);
1128 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1129 ResultReg).addReg(RVLocs[0].getLocReg());
1130 UsedRegs.push_back(RVLocs[0].getLocReg());
1132 // Finally update the result.
1133 UpdateValueMap(I, ResultReg);
1136 // Set all unused physreg defs as dead.
1137 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1142 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1144 const Type *Ty = I->getType();
1145 if (!isTypeLegal(Ty, VT))
1148 // If we have integer div support we should have gotten already, emit a
1150 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1152 LC = RTLIB::SDIV_I16;
1153 else if (VT == MVT::i32)
1154 LC = RTLIB::SDIV_I32;
1155 else if (VT == MVT::i64)
1156 LC = RTLIB::SDIV_I64;
1157 else if (VT == MVT::i128)
1158 LC = RTLIB::SDIV_I128;
1159 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1161 // Binary operand with all the same type.
1162 std::vector<const Type*> ArgTys;
1163 ArgTys.push_back(Ty);
1164 ArgTys.push_back(Ty);
1165 const FunctionType *FTy = FunctionType::get(Ty, ArgTys, false);
1166 Function *F = Function::Create(FTy, GlobalValue::ExternalLinkage,
1167 TLI.getLibcallName(LC));
1168 if (Subtarget->isAAPCS_ABI())
1169 F->setCallingConv(CallingConv::ARM_AAPCS);
1171 F->setCallingConv(I->getParent()->getParent()->getCallingConv());
1173 return ARMEmitLibcall(I, F);
1176 // TODO: SoftFP support.
1177 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1178 // No Thumb-1 for now.
1179 if (isThumb && !AFI->isThumb2Function()) return false;
1181 switch (I->getOpcode()) {
1182 case Instruction::Load:
1183 return SelectLoad(I);
1184 case Instruction::Store:
1185 return SelectStore(I);
1186 case Instruction::Br:
1187 return SelectBranch(I);
1188 case Instruction::ICmp:
1189 case Instruction::FCmp:
1190 return SelectCmp(I);
1191 case Instruction::FPExt:
1192 return SelectFPExt(I);
1193 case Instruction::FPTrunc:
1194 return SelectFPTrunc(I);
1195 case Instruction::SIToFP:
1196 return SelectSIToFP(I);
1197 case Instruction::FPToSI:
1198 return SelectFPToSI(I);
1199 case Instruction::FAdd:
1200 return SelectBinaryOp(I, ISD::FADD);
1201 case Instruction::FSub:
1202 return SelectBinaryOp(I, ISD::FSUB);
1203 case Instruction::FMul:
1204 return SelectBinaryOp(I, ISD::FMUL);
1205 case Instruction::SDiv:
1206 return SelectSDiv(I);
1213 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1214 if (EnableARMFastISel) return new ARMFastISel(funcInfo);