1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "ARMConstantPoolValue.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/IntrinsicInst.h"
29 #include "llvm/Module.h"
30 #include "llvm/Operator.h"
31 #include "llvm/CodeGen/Analysis.h"
32 #include "llvm/CodeGen/FastISel.h"
33 #include "llvm/CodeGen/FunctionLoweringInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineConstantPool.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineMemOperand.h"
39 #include "llvm/CodeGen/MachineRegisterInfo.h"
40 #include "llvm/CodeGen/PseudoSourceValue.h"
41 #include "llvm/Support/CallSite.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/GetElementPtrTypeIterator.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
53 DisableARMFastISel("disable-arm-fast-isel",
54 cl::desc("Turn off experimental ARM fast-isel support"),
55 cl::init(false), cl::Hidden);
57 extern cl::opt<bool> EnableARMLongCalls;
61 // All possible address modes, plus some.
62 typedef struct Address {
75 // Innocuous defaults for our address.
77 : BaseType(RegBase), Offset(0) {
82 class ARMFastISel : public FastISel {
84 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
85 /// make the right decision when generating code for different targets.
86 const ARMSubtarget *Subtarget;
87 const TargetMachine &TM;
88 const TargetInstrInfo &TII;
89 const TargetLowering &TLI;
92 // Convenience variables to avoid some queries.
97 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
99 TM(funcInfo.MF->getTarget()),
100 TII(*TM.getInstrInfo()),
101 TLI(*TM.getTargetLowering()) {
102 Subtarget = &TM.getSubtarget<ARMSubtarget>();
103 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
104 isThumb = AFI->isThumbFunction();
105 Context = &funcInfo.Fn->getContext();
108 // Code from FastISel.cpp.
109 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
110 const TargetRegisterClass *RC);
111 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
112 const TargetRegisterClass *RC,
113 unsigned Op0, bool Op0IsKill);
114 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
115 const TargetRegisterClass *RC,
116 unsigned Op0, bool Op0IsKill,
117 unsigned Op1, bool Op1IsKill);
118 virtual unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill,
121 unsigned Op1, bool Op1IsKill,
122 unsigned Op2, bool Op2IsKill);
123 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
124 const TargetRegisterClass *RC,
125 unsigned Op0, bool Op0IsKill,
127 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
128 const TargetRegisterClass *RC,
129 unsigned Op0, bool Op0IsKill,
130 const ConstantFP *FPImm);
131 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
132 const TargetRegisterClass *RC,
133 unsigned Op0, bool Op0IsKill,
134 unsigned Op1, bool Op1IsKill,
136 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
137 const TargetRegisterClass *RC,
139 virtual unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
140 const TargetRegisterClass *RC,
141 uint64_t Imm1, uint64_t Imm2);
143 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
144 unsigned Op0, bool Op0IsKill,
147 // Backend specific FastISel code.
148 virtual bool TargetSelectInstruction(const Instruction *I);
149 virtual unsigned TargetMaterializeConstant(const Constant *C);
150 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
152 #include "ARMGenFastISel.inc"
154 // Instruction selection routines.
156 bool SelectLoad(const Instruction *I);
157 bool SelectStore(const Instruction *I);
158 bool SelectBranch(const Instruction *I);
159 bool SelectCmp(const Instruction *I);
160 bool SelectFPExt(const Instruction *I);
161 bool SelectFPTrunc(const Instruction *I);
162 bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
163 bool SelectSIToFP(const Instruction *I);
164 bool SelectFPToSI(const Instruction *I);
165 bool SelectSDiv(const Instruction *I);
166 bool SelectSRem(const Instruction *I);
167 bool SelectCall(const Instruction *I);
168 bool SelectSelect(const Instruction *I);
169 bool SelectRet(const Instruction *I);
170 bool SelectIntCast(const Instruction *I);
174 bool isTypeLegal(Type *Ty, MVT &VT);
175 bool isLoadTypeLegal(Type *Ty, MVT &VT);
176 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
177 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
178 bool ARMComputeAddress(const Value *Obj, Address &Addr);
179 void ARMSimplifyAddress(Address &Addr, EVT VT);
180 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
181 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
182 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
183 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
184 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
185 unsigned ARMSelectCallOp(const GlobalValue *GV);
187 // Call handling routines.
189 bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
190 unsigned &ResultReg);
191 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
192 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
193 SmallVectorImpl<unsigned> &ArgRegs,
194 SmallVectorImpl<MVT> &ArgVTs,
195 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
196 SmallVectorImpl<unsigned> &RegArgs,
199 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
200 const Instruction *I, CallingConv::ID CC,
202 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
204 // OptionalDef handling routines.
206 bool isARMNEONPred(const MachineInstr *MI);
207 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
208 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
209 void AddLoadStoreOperands(EVT VT, Address &Addr,
210 const MachineInstrBuilder &MIB,
214 } // end anonymous namespace
216 #include "ARMGenCallingConv.inc"
218 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
219 // we don't care about implicit defs here, just places we'll need to add a
220 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
221 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
222 const MCInstrDesc &MCID = MI->getDesc();
223 if (!MCID.hasOptionalDef())
226 // Look to see if our OptionalDef is defining CPSR or CCR.
227 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
228 const MachineOperand &MO = MI->getOperand(i);
229 if (!MO.isReg() || !MO.isDef()) continue;
230 if (MO.getReg() == ARM::CPSR)
236 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
237 const MCInstrDesc &MCID = MI->getDesc();
239 // If we're a thumb2 or not NEON function we were handled via isPredicable.
240 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
241 AFI->isThumb2Function())
244 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
245 if (MCID.OpInfo[i].isPredicate())
251 // If the machine is predicable go ahead and add the predicate operands, if
252 // it needs default CC operands add those.
253 // TODO: If we want to support thumb1 then we'll need to deal with optional
254 // CPSR defs that need to be added before the remaining operands. See s_cc_out
255 // for descriptions why.
256 const MachineInstrBuilder &
257 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
258 MachineInstr *MI = &*MIB;
260 // Do we use a predicate? or...
261 // Are we NEON in ARM mode and have a predicate operand? If so, I know
262 // we're not predicable but add it anyways.
263 if (TII.isPredicable(MI) || isARMNEONPred(MI))
266 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
267 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
269 if (DefinesOptionalPredicate(MI, &CPSR)) {
278 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
279 const TargetRegisterClass* RC) {
280 unsigned ResultReg = createResultReg(RC);
281 const MCInstrDesc &II = TII.get(MachineInstOpcode);
283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
287 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
288 const TargetRegisterClass *RC,
289 unsigned Op0, bool Op0IsKill) {
290 unsigned ResultReg = createResultReg(RC);
291 const MCInstrDesc &II = TII.get(MachineInstOpcode);
293 if (II.getNumDefs() >= 1)
294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
295 .addReg(Op0, Op0IsKill * RegState::Kill));
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
298 .addReg(Op0, Op0IsKill * RegState::Kill));
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
300 TII.get(TargetOpcode::COPY), ResultReg)
301 .addReg(II.ImplicitDefs[0]));
306 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
307 const TargetRegisterClass *RC,
308 unsigned Op0, bool Op0IsKill,
309 unsigned Op1, bool Op1IsKill) {
310 unsigned ResultReg = createResultReg(RC);
311 const MCInstrDesc &II = TII.get(MachineInstOpcode);
313 if (II.getNumDefs() >= 1)
314 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
315 .addReg(Op0, Op0IsKill * RegState::Kill)
316 .addReg(Op1, Op1IsKill * RegState::Kill));
318 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
319 .addReg(Op0, Op0IsKill * RegState::Kill)
320 .addReg(Op1, Op1IsKill * RegState::Kill));
321 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
322 TII.get(TargetOpcode::COPY), ResultReg)
323 .addReg(II.ImplicitDefs[0]));
328 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
329 const TargetRegisterClass *RC,
330 unsigned Op0, bool Op0IsKill,
331 unsigned Op1, bool Op1IsKill,
332 unsigned Op2, bool Op2IsKill) {
333 unsigned ResultReg = createResultReg(RC);
334 const MCInstrDesc &II = TII.get(MachineInstOpcode);
336 if (II.getNumDefs() >= 1)
337 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
338 .addReg(Op0, Op0IsKill * RegState::Kill)
339 .addReg(Op1, Op1IsKill * RegState::Kill)
340 .addReg(Op2, Op2IsKill * RegState::Kill));
342 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
343 .addReg(Op0, Op0IsKill * RegState::Kill)
344 .addReg(Op1, Op1IsKill * RegState::Kill)
345 .addReg(Op2, Op2IsKill * RegState::Kill));
346 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
347 TII.get(TargetOpcode::COPY), ResultReg)
348 .addReg(II.ImplicitDefs[0]));
353 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
354 const TargetRegisterClass *RC,
355 unsigned Op0, bool Op0IsKill,
357 unsigned ResultReg = createResultReg(RC);
358 const MCInstrDesc &II = TII.get(MachineInstOpcode);
360 if (II.getNumDefs() >= 1)
361 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
362 .addReg(Op0, Op0IsKill * RegState::Kill)
365 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
366 .addReg(Op0, Op0IsKill * RegState::Kill)
368 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
369 TII.get(TargetOpcode::COPY), ResultReg)
370 .addReg(II.ImplicitDefs[0]));
375 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
376 const TargetRegisterClass *RC,
377 unsigned Op0, bool Op0IsKill,
378 const ConstantFP *FPImm) {
379 unsigned ResultReg = createResultReg(RC);
380 const MCInstrDesc &II = TII.get(MachineInstOpcode);
382 if (II.getNumDefs() >= 1)
383 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
384 .addReg(Op0, Op0IsKill * RegState::Kill)
387 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
388 .addReg(Op0, Op0IsKill * RegState::Kill)
390 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
391 TII.get(TargetOpcode::COPY), ResultReg)
392 .addReg(II.ImplicitDefs[0]));
397 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
398 const TargetRegisterClass *RC,
399 unsigned Op0, bool Op0IsKill,
400 unsigned Op1, bool Op1IsKill,
402 unsigned ResultReg = createResultReg(RC);
403 const MCInstrDesc &II = TII.get(MachineInstOpcode);
405 if (II.getNumDefs() >= 1)
406 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
407 .addReg(Op0, Op0IsKill * RegState::Kill)
408 .addReg(Op1, Op1IsKill * RegState::Kill)
411 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
412 .addReg(Op0, Op0IsKill * RegState::Kill)
413 .addReg(Op1, Op1IsKill * RegState::Kill)
415 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
416 TII.get(TargetOpcode::COPY), ResultReg)
417 .addReg(II.ImplicitDefs[0]));
422 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
423 const TargetRegisterClass *RC,
425 unsigned ResultReg = createResultReg(RC);
426 const MCInstrDesc &II = TII.get(MachineInstOpcode);
428 if (II.getNumDefs() >= 1)
429 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
432 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
434 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
435 TII.get(TargetOpcode::COPY), ResultReg)
436 .addReg(II.ImplicitDefs[0]));
441 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
442 const TargetRegisterClass *RC,
443 uint64_t Imm1, uint64_t Imm2) {
444 unsigned ResultReg = createResultReg(RC);
445 const MCInstrDesc &II = TII.get(MachineInstOpcode);
447 if (II.getNumDefs() >= 1)
448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
449 .addImm(Imm1).addImm(Imm2));
451 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
452 .addImm(Imm1).addImm(Imm2));
453 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
454 TII.get(TargetOpcode::COPY),
456 .addReg(II.ImplicitDefs[0]));
461 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
462 unsigned Op0, bool Op0IsKill,
464 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
465 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
466 "Cannot yet extract from physregs");
467 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
468 DL, TII.get(TargetOpcode::COPY), ResultReg)
469 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
473 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
474 // checks from the various callers.
475 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
476 if (VT == MVT::f64) return 0;
478 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
479 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
480 TII.get(ARM::VMOVRS), MoveReg)
485 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
486 if (VT == MVT::i64) return 0;
488 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
489 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
490 TII.get(ARM::VMOVSR), MoveReg)
495 // For double width floating point we need to materialize two constants
496 // (the high and the low) into integer registers then use a move to get
497 // the combined constant into an FP reg.
498 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
499 const APFloat Val = CFP->getValueAPF();
500 bool is64bit = VT == MVT::f64;
502 // This checks to see if we can use VFP3 instructions to materialize
503 // a constant, otherwise we have to go through the constant pool.
504 if (TLI.isFPImmLegal(Val, VT)) {
508 Imm = ARM_AM::getFP64Imm(Val);
511 Imm = ARM_AM::getFP32Imm(Val);
514 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
515 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
521 // Require VFP2 for loading fp constants.
522 if (!Subtarget->hasVFP2()) return false;
524 // MachineConstantPool wants an explicit alignment.
525 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
527 // TODO: Figure out if this is correct.
528 Align = TD.getTypeAllocSize(CFP->getType());
530 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
531 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
532 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
534 // The extra reg is for addrmode5.
535 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
537 .addConstantPoolIndex(Idx)
542 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
544 // For now 32-bit only.
545 if (VT != MVT::i32) return false;
547 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
549 // If we can do this in a single instruction without a constant pool entry
551 const ConstantInt *CI = cast<ConstantInt>(C);
552 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) {
553 unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16;
554 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
555 TII.get(Opc), DestReg)
556 .addImm(CI->getSExtValue()));
560 // MachineConstantPool wants an explicit alignment.
561 unsigned Align = TD.getPrefTypeAlignment(C->getType());
563 // TODO: Figure out if this is correct.
564 Align = TD.getTypeAllocSize(C->getType());
566 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
569 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
570 TII.get(ARM::t2LDRpci), DestReg)
571 .addConstantPoolIndex(Idx));
573 // The extra immediate is for addrmode2.
574 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
575 TII.get(ARM::LDRcp), DestReg)
576 .addConstantPoolIndex(Idx)
582 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
583 // For now 32-bit only.
584 if (VT != MVT::i32) return 0;
586 Reloc::Model RelocM = TM.getRelocationModel();
588 // TODO: Need more magic for ARM PIC.
589 if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
591 // MachineConstantPool wants an explicit alignment.
592 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
594 // TODO: Figure out if this is correct.
595 Align = TD.getTypeAllocSize(GV->getType());
599 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
600 unsigned Id = AFI->createPICLabelUId();
601 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
602 ARMCP::CPValue, PCAdj);
603 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
606 MachineInstrBuilder MIB;
607 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
609 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
610 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
611 .addConstantPoolIndex(Idx);
612 if (RelocM == Reloc::PIC_)
615 // The extra immediate is for addrmode2.
616 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
618 .addConstantPoolIndex(Idx)
621 AddOptionalDefs(MIB);
623 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
624 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
626 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
627 TII.get(ARM::t2LDRi12), NewDestReg)
631 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
635 DestReg = NewDestReg;
636 AddOptionalDefs(MIB);
642 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
643 EVT VT = TLI.getValueType(C->getType(), true);
645 // Only handle simple types.
646 if (!VT.isSimple()) return 0;
648 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
649 return ARMMaterializeFP(CFP, VT);
650 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
651 return ARMMaterializeGV(GV, VT);
652 else if (isa<ConstantInt>(C))
653 return ARMMaterializeInt(C, VT);
658 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
659 // Don't handle dynamic allocas.
660 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
663 if (!isLoadTypeLegal(AI->getType(), VT)) return false;
665 DenseMap<const AllocaInst*, int>::iterator SI =
666 FuncInfo.StaticAllocaMap.find(AI);
668 // This will get lowered later into the correct offsets and registers
669 // via rewriteXFrameIndex.
670 if (SI != FuncInfo.StaticAllocaMap.end()) {
671 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
672 unsigned ResultReg = createResultReg(RC);
673 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
674 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
675 TII.get(Opc), ResultReg)
676 .addFrameIndex(SI->second)
684 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
685 EVT evt = TLI.getValueType(Ty, true);
687 // Only handle simple types.
688 if (evt == MVT::Other || !evt.isSimple()) return false;
689 VT = evt.getSimpleVT();
691 // Handle all legal types, i.e. a register that will directly hold this
693 return TLI.isTypeLegal(VT);
696 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
697 if (isTypeLegal(Ty, VT)) return true;
699 // If this is a type than can be sign or zero-extended to a basic operation
700 // go ahead and accept it now.
701 if (VT == MVT::i8 || VT == MVT::i16)
707 // Computes the address to get to an object.
708 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
709 // Some boilerplate from the X86 FastISel.
710 const User *U = NULL;
711 unsigned Opcode = Instruction::UserOp1;
712 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
713 // Don't walk into other basic blocks unless the object is an alloca from
714 // another block, otherwise it may not have a virtual register assigned.
715 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
716 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
717 Opcode = I->getOpcode();
720 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
721 Opcode = C->getOpcode();
725 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
726 if (Ty->getAddressSpace() > 255)
727 // Fast instruction selection doesn't support the special
734 case Instruction::BitCast: {
735 // Look through bitcasts.
736 return ARMComputeAddress(U->getOperand(0), Addr);
738 case Instruction::IntToPtr: {
739 // Look past no-op inttoptrs.
740 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
741 return ARMComputeAddress(U->getOperand(0), Addr);
744 case Instruction::PtrToInt: {
745 // Look past no-op ptrtoints.
746 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
747 return ARMComputeAddress(U->getOperand(0), Addr);
750 case Instruction::GetElementPtr: {
751 Address SavedAddr = Addr;
752 int TmpOffset = Addr.Offset;
754 // Iterate through the GEP folding the constants into offsets where
756 gep_type_iterator GTI = gep_type_begin(U);
757 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
758 i != e; ++i, ++GTI) {
759 const Value *Op = *i;
760 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
761 const StructLayout *SL = TD.getStructLayout(STy);
762 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
763 TmpOffset += SL->getElementOffset(Idx);
765 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
767 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
768 // Constant-offset addressing.
769 TmpOffset += CI->getSExtValue() * S;
772 if (isa<AddOperator>(Op) &&
773 (!isa<Instruction>(Op) ||
774 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
776 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
777 // An add (in the same block) with a constant operand. Fold the
780 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
781 TmpOffset += CI->getSExtValue() * S;
782 // Iterate on the other operand.
783 Op = cast<AddOperator>(Op)->getOperand(0);
787 goto unsupported_gep;
792 // Try to grab the base operand now.
793 Addr.Offset = TmpOffset;
794 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
796 // We failed, restore everything and try the other options.
802 case Instruction::Alloca: {
803 const AllocaInst *AI = cast<AllocaInst>(Obj);
804 DenseMap<const AllocaInst*, int>::iterator SI =
805 FuncInfo.StaticAllocaMap.find(AI);
806 if (SI != FuncInfo.StaticAllocaMap.end()) {
807 Addr.BaseType = Address::FrameIndexBase;
808 Addr.Base.FI = SI->second;
815 // Materialize the global variable's address into a reg which can
816 // then be used later to load the variable.
817 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
818 unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
819 if (Tmp == 0) return false;
825 // Try to get this in a register if nothing else has worked.
826 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
827 return Addr.Base.Reg != 0;
830 void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
832 assert(VT.isSimple() && "Non-simple types are invalid here!");
834 bool needsLowering = false;
835 switch (VT.getSimpleVT().SimpleTy) {
837 assert(false && "Unhandled load/store type!");
842 // Integer loads/stores handle 12-bit offsets.
843 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
847 // Floating point operands handle 8-bit offsets.
848 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
852 // If this is a stack pointer and the offset needs to be simplified then
853 // put the alloca address into a register, set the base type back to
854 // register and continue. This should almost never happen.
855 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
856 TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
857 ARM::GPRRegisterClass;
858 unsigned ResultReg = createResultReg(RC);
859 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
860 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
861 TII.get(Opc), ResultReg)
862 .addFrameIndex(Addr.Base.FI)
864 Addr.Base.Reg = ResultReg;
865 Addr.BaseType = Address::RegBase;
868 // Since the offset is too large for the load/store instruction
869 // get the reg+offset into a register.
871 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
872 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
877 void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
878 const MachineInstrBuilder &MIB,
880 // addrmode5 output depends on the selection dag addressing dividing the
881 // offset by 4 that it then later multiplies. Do this here as well.
882 if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
883 VT.getSimpleVT().SimpleTy == MVT::f64)
886 // Frame base works a bit differently. Handle it separately.
887 if (Addr.BaseType == Address::FrameIndexBase) {
888 int FI = Addr.Base.FI;
889 int Offset = Addr.Offset;
890 MachineMemOperand *MMO =
891 FuncInfo.MF->getMachineMemOperand(
892 MachinePointerInfo::getFixedStack(FI, Offset),
894 MFI.getObjectSize(FI),
895 MFI.getObjectAlignment(FI));
896 // Now add the rest of the operands.
897 MIB.addFrameIndex(FI);
899 // ARM halfword load/stores need an additional operand.
900 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
902 MIB.addImm(Addr.Offset);
903 MIB.addMemOperand(MMO);
905 // Now add the rest of the operands.
906 MIB.addReg(Addr.Base.Reg);
908 // ARM halfword load/stores need an additional operand.
909 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
911 MIB.addImm(Addr.Offset);
913 AddOptionalDefs(MIB);
916 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
918 assert(VT.isSimple() && "Non-simple types are invalid here!");
920 TargetRegisterClass *RC;
921 switch (VT.getSimpleVT().SimpleTy) {
922 // This is mostly going to be Neon/vector support.
923 default: return false;
925 Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
926 RC = ARM::GPRRegisterClass;
929 Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
930 RC = ARM::GPRRegisterClass;
933 Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12;
934 RC = ARM::GPRRegisterClass;
938 RC = TLI.getRegClassFor(VT);
942 RC = TLI.getRegClassFor(VT);
945 // Simplify this down to something we can handle.
946 ARMSimplifyAddress(Addr, VT);
948 // Create the base instruction, then add the operands.
949 ResultReg = createResultReg(RC);
950 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
951 TII.get(Opc), ResultReg);
952 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad);
956 bool ARMFastISel::SelectLoad(const Instruction *I) {
957 // Atomic loads need special handling.
958 if (cast<LoadInst>(I)->isAtomic())
961 // Verify we have a legal type before going any further.
963 if (!isLoadTypeLegal(I->getType(), VT))
966 // See if we can handle this address.
968 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
971 if (!ARMEmitLoad(VT, ResultReg, Addr)) return false;
972 UpdateValueMap(I, ResultReg);
976 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
978 switch (VT.getSimpleVT().SimpleTy) {
979 // This is mostly going to be Neon/vector support.
980 default: return false;
982 unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass :
983 ARM::GPRRegisterClass);
984 unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
985 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
987 .addReg(SrcReg).addImm(1));
989 } // Fallthrough here.
991 StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
994 StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
997 StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
1000 if (!Subtarget->hasVFP2()) return false;
1001 StrOpc = ARM::VSTRS;
1004 if (!Subtarget->hasVFP2()) return false;
1005 StrOpc = ARM::VSTRD;
1008 // Simplify this down to something we can handle.
1009 ARMSimplifyAddress(Addr, VT);
1011 // Create the base instruction, then add the operands.
1012 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1014 .addReg(SrcReg, getKillRegState(true));
1015 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore);
1019 bool ARMFastISel::SelectStore(const Instruction *I) {
1020 Value *Op0 = I->getOperand(0);
1021 unsigned SrcReg = 0;
1023 // Atomic stores need special handling.
1024 if (cast<StoreInst>(I)->isAtomic())
1027 // Verify we have a legal type before going any further.
1029 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1032 // Get the value to be stored into a register.
1033 SrcReg = getRegForValue(Op0);
1034 if (SrcReg == 0) return false;
1036 // See if we can handle this address.
1038 if (!ARMComputeAddress(I->getOperand(1), Addr))
1041 if (!ARMEmitStore(VT, SrcReg, Addr)) return false;
1045 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1047 // Needs two compares...
1048 case CmpInst::FCMP_ONE:
1049 case CmpInst::FCMP_UEQ:
1051 // AL is our "false" for now. The other two need more compares.
1053 case CmpInst::ICMP_EQ:
1054 case CmpInst::FCMP_OEQ:
1056 case CmpInst::ICMP_SGT:
1057 case CmpInst::FCMP_OGT:
1059 case CmpInst::ICMP_SGE:
1060 case CmpInst::FCMP_OGE:
1062 case CmpInst::ICMP_UGT:
1063 case CmpInst::FCMP_UGT:
1065 case CmpInst::FCMP_OLT:
1067 case CmpInst::ICMP_ULE:
1068 case CmpInst::FCMP_OLE:
1070 case CmpInst::FCMP_ORD:
1072 case CmpInst::FCMP_UNO:
1074 case CmpInst::FCMP_UGE:
1076 case CmpInst::ICMP_SLT:
1077 case CmpInst::FCMP_ULT:
1079 case CmpInst::ICMP_SLE:
1080 case CmpInst::FCMP_ULE:
1082 case CmpInst::FCMP_UNE:
1083 case CmpInst::ICMP_NE:
1085 case CmpInst::ICMP_UGE:
1087 case CmpInst::ICMP_ULT:
1092 bool ARMFastISel::SelectBranch(const Instruction *I) {
1093 const BranchInst *BI = cast<BranchInst>(I);
1094 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1095 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1097 // Simple branch support.
1099 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1101 // TODO: Factor this out.
1102 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1104 Type *Ty = CI->getOperand(0)->getType();
1105 if (CI->hasOneUse() && (CI->getParent() == I->getParent())
1106 && isTypeLegal(Ty, SourceVT)) {
1107 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1108 if (isFloat && !Subtarget->hasVFP2())
1112 switch (SourceVT.SimpleTy) {
1113 default: return false;
1114 // TODO: Verify compares.
1116 CmpOpc = ARM::VCMPES;
1119 CmpOpc = ARM::VCMPED;
1122 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1126 // Get the compare predicate.
1127 // Try to take advantage of fallthrough opportunities.
1128 CmpInst::Predicate Predicate = CI->getPredicate();
1129 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1130 std::swap(TBB, FBB);
1131 Predicate = CmpInst::getInversePredicate(Predicate);
1134 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1136 // We may not handle every CC for now.
1137 if (ARMPred == ARMCC::AL) return false;
1139 unsigned Arg1 = getRegForValue(CI->getOperand(0));
1140 if (Arg1 == 0) return false;
1142 unsigned Arg2 = getRegForValue(CI->getOperand(1));
1143 if (Arg2 == 0) return false;
1145 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1147 .addReg(Arg1).addReg(Arg2));
1149 // For floating point we need to move the result to a comparison register
1150 // that we can then use for branches.
1152 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1153 TII.get(ARM::FMSTAT)));
1155 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1156 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1157 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1158 FastEmitBranch(FBB, DL);
1159 FuncInfo.MBB->addSuccessor(TBB);
1162 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1164 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1165 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1166 unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1167 unsigned OpReg = getRegForValue(TI->getOperand(0));
1168 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1170 .addReg(OpReg).addImm(1));
1172 unsigned CCMode = ARMCC::NE;
1173 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1174 std::swap(TBB, FBB);
1178 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1180 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1182 FastEmitBranch(FBB, DL);
1183 FuncInfo.MBB->addSuccessor(TBB);
1188 unsigned CmpReg = getRegForValue(BI->getCondition());
1189 if (CmpReg == 0) return false;
1191 // We've been divorced from our compare! Our block was split, and
1192 // now our compare lives in a predecessor block. We musn't
1193 // re-compare here, as the children of the compare aren't guaranteed
1194 // live across the block boundary (we *could* check for this).
1195 // Regardless, the compare has been done in the predecessor block,
1196 // and it left a value for us in a virtual register. Ergo, we test
1197 // the one-bit value left in the virtual register.
1198 unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1199 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1200 .addReg(CmpReg).addImm(1));
1202 unsigned CCMode = ARMCC::NE;
1203 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1204 std::swap(TBB, FBB);
1208 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1209 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1210 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1211 FastEmitBranch(FBB, DL);
1212 FuncInfo.MBB->addSuccessor(TBB);
1216 bool ARMFastISel::SelectCmp(const Instruction *I) {
1217 const CmpInst *CI = cast<CmpInst>(I);
1220 Type *Ty = CI->getOperand(0)->getType();
1221 if (!isTypeLegal(Ty, VT))
1224 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1225 if (isFloat && !Subtarget->hasVFP2())
1230 switch (VT.SimpleTy) {
1231 default: return false;
1232 // TODO: Verify compares.
1234 CmpOpc = ARM::VCMPES;
1235 CondReg = ARM::FPSCR;
1238 CmpOpc = ARM::VCMPED;
1239 CondReg = ARM::FPSCR;
1242 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1243 CondReg = ARM::CPSR;
1247 // Get the compare predicate.
1248 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1250 // We may not handle every CC for now.
1251 if (ARMPred == ARMCC::AL) return false;
1253 unsigned Arg1 = getRegForValue(CI->getOperand(0));
1254 if (Arg1 == 0) return false;
1256 unsigned Arg2 = getRegForValue(CI->getOperand(1));
1257 if (Arg2 == 0) return false;
1259 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1260 .addReg(Arg1).addReg(Arg2));
1262 // For floating point we need to move the result to a comparison register
1263 // that we can then use for branches.
1265 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1266 TII.get(ARM::FMSTAT)));
1268 // Now set a register based on the comparison. Explicitly set the predicates
1270 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1271 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1272 : ARM::GPRRegisterClass;
1273 unsigned DestReg = createResultReg(RC);
1275 = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1276 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1277 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1278 .addReg(ZeroReg).addImm(1)
1279 .addImm(ARMPred).addReg(CondReg);
1281 UpdateValueMap(I, DestReg);
1285 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1286 // Make sure we have VFP and that we're extending float to double.
1287 if (!Subtarget->hasVFP2()) return false;
1289 Value *V = I->getOperand(0);
1290 if (!I->getType()->isDoubleTy() ||
1291 !V->getType()->isFloatTy()) return false;
1293 unsigned Op = getRegForValue(V);
1294 if (Op == 0) return false;
1296 unsigned Result = createResultReg(ARM::DPRRegisterClass);
1297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1298 TII.get(ARM::VCVTDS), Result)
1300 UpdateValueMap(I, Result);
1304 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1305 // Make sure we have VFP and that we're truncating double to float.
1306 if (!Subtarget->hasVFP2()) return false;
1308 Value *V = I->getOperand(0);
1309 if (!(I->getType()->isFloatTy() &&
1310 V->getType()->isDoubleTy())) return false;
1312 unsigned Op = getRegForValue(V);
1313 if (Op == 0) return false;
1315 unsigned Result = createResultReg(ARM::SPRRegisterClass);
1316 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1317 TII.get(ARM::VCVTSD), Result)
1319 UpdateValueMap(I, Result);
1323 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1324 // Make sure we have VFP.
1325 if (!Subtarget->hasVFP2()) return false;
1328 Type *Ty = I->getType();
1329 if (!isTypeLegal(Ty, DstVT))
1332 // FIXME: Handle sign-extension where necessary.
1333 if (!I->getOperand(0)->getType()->isIntegerTy(32))
1336 unsigned Op = getRegForValue(I->getOperand(0));
1337 if (Op == 0) return false;
1339 // The conversion routine works on fp-reg to fp-reg and the operand above
1340 // was an integer, move it to the fp registers if possible.
1341 unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1342 if (FP == 0) return false;
1345 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1346 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1349 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1350 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1353 UpdateValueMap(I, ResultReg);
1357 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1358 // Make sure we have VFP.
1359 if (!Subtarget->hasVFP2()) return false;
1362 Type *RetTy = I->getType();
1363 if (!isTypeLegal(RetTy, DstVT))
1366 unsigned Op = getRegForValue(I->getOperand(0));
1367 if (Op == 0) return false;
1370 Type *OpTy = I->getOperand(0)->getType();
1371 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1372 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1375 // f64->s32 or f32->s32 both need an intermediate f32 reg.
1376 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1377 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1381 // This result needs to be in an integer register, but the conversion only
1382 // takes place in fp-regs.
1383 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1384 if (IntReg == 0) return false;
1386 UpdateValueMap(I, IntReg);
1390 bool ARMFastISel::SelectSelect(const Instruction *I) {
1392 if (!isTypeLegal(I->getType(), VT))
1395 // Things need to be register sized for register moves.
1396 if (VT != MVT::i32) return false;
1397 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1399 unsigned CondReg = getRegForValue(I->getOperand(0));
1400 if (CondReg == 0) return false;
1401 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1402 if (Op1Reg == 0) return false;
1403 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1404 if (Op2Reg == 0) return false;
1406 unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1407 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1408 .addReg(CondReg).addImm(1));
1409 unsigned ResultReg = createResultReg(RC);
1410 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1411 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1412 .addReg(Op1Reg).addReg(Op2Reg)
1413 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1414 UpdateValueMap(I, ResultReg);
1418 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1420 Type *Ty = I->getType();
1421 if (!isTypeLegal(Ty, VT))
1424 // If we have integer div support we should have selected this automagically.
1425 // In case we have a real miss go ahead and return false and we'll pick
1427 if (Subtarget->hasDivide()) return false;
1429 // Otherwise emit a libcall.
1430 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1432 LC = RTLIB::SDIV_I8;
1433 else if (VT == MVT::i16)
1434 LC = RTLIB::SDIV_I16;
1435 else if (VT == MVT::i32)
1436 LC = RTLIB::SDIV_I32;
1437 else if (VT == MVT::i64)
1438 LC = RTLIB::SDIV_I64;
1439 else if (VT == MVT::i128)
1440 LC = RTLIB::SDIV_I128;
1441 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1443 return ARMEmitLibcall(I, LC);
1446 bool ARMFastISel::SelectSRem(const Instruction *I) {
1448 Type *Ty = I->getType();
1449 if (!isTypeLegal(Ty, VT))
1452 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1454 LC = RTLIB::SREM_I8;
1455 else if (VT == MVT::i16)
1456 LC = RTLIB::SREM_I16;
1457 else if (VT == MVT::i32)
1458 LC = RTLIB::SREM_I32;
1459 else if (VT == MVT::i64)
1460 LC = RTLIB::SREM_I64;
1461 else if (VT == MVT::i128)
1462 LC = RTLIB::SREM_I128;
1463 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1465 return ARMEmitLibcall(I, LC);
1468 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1469 EVT VT = TLI.getValueType(I->getType(), true);
1471 // We can get here in the case when we want to use NEON for our fp
1472 // operations, but can't figure out how to. Just use the vfp instructions
1474 // FIXME: It'd be nice to use NEON instructions.
1475 Type *Ty = I->getType();
1476 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1477 if (isFloat && !Subtarget->hasVFP2())
1480 unsigned Op1 = getRegForValue(I->getOperand(0));
1481 if (Op1 == 0) return false;
1483 unsigned Op2 = getRegForValue(I->getOperand(1));
1484 if (Op2 == 0) return false;
1487 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1488 switch (ISDOpcode) {
1489 default: return false;
1491 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1494 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1497 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1500 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1501 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1502 TII.get(Opc), ResultReg)
1503 .addReg(Op1).addReg(Op2));
1504 UpdateValueMap(I, ResultReg);
1508 // Call Handling Code
1510 bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src,
1511 EVT SrcVT, unsigned &ResultReg) {
1512 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1513 Src, /*TODO: Kill=*/false);
1522 // This is largely taken directly from CCAssignFnForNode - we don't support
1523 // varargs in FastISel so that part has been removed.
1524 // TODO: We may not support all of this.
1525 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1528 llvm_unreachable("Unsupported calling convention");
1529 case CallingConv::Fast:
1530 // Ignore fastcc. Silence compiler warnings.
1531 (void)RetFastCC_ARM_APCS;
1532 (void)FastCC_ARM_APCS;
1534 case CallingConv::C:
1535 // Use target triple & subtarget features to do actual dispatch.
1536 if (Subtarget->isAAPCS_ABI()) {
1537 if (Subtarget->hasVFP2() &&
1538 FloatABIType == FloatABI::Hard)
1539 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1541 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1543 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1544 case CallingConv::ARM_AAPCS_VFP:
1545 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1546 case CallingConv::ARM_AAPCS:
1547 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1548 case CallingConv::ARM_APCS:
1549 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1553 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1554 SmallVectorImpl<unsigned> &ArgRegs,
1555 SmallVectorImpl<MVT> &ArgVTs,
1556 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1557 SmallVectorImpl<unsigned> &RegArgs,
1559 unsigned &NumBytes) {
1560 SmallVector<CCValAssign, 16> ArgLocs;
1561 CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1562 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1564 // Get a count of how many bytes are to be pushed on the stack.
1565 NumBytes = CCInfo.getNextStackOffset();
1567 // Issue CALLSEQ_START
1568 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1569 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1570 TII.get(AdjStackDown))
1573 // Process the args.
1574 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1575 CCValAssign &VA = ArgLocs[i];
1576 unsigned Arg = ArgRegs[VA.getValNo()];
1577 MVT ArgVT = ArgVTs[VA.getValNo()];
1579 // We don't handle NEON/vector parameters yet.
1580 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1583 // Handle arg promotion, etc.
1584 switch (VA.getLocInfo()) {
1585 case CCValAssign::Full: break;
1586 case CCValAssign::SExt: {
1587 bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1589 assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
1591 ArgVT = VA.getLocVT();
1594 case CCValAssign::ZExt: {
1595 bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1597 assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
1599 ArgVT = VA.getLocVT();
1602 case CCValAssign::AExt: {
1603 bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1606 Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1609 Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1612 assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
1613 ArgVT = VA.getLocVT();
1616 case CCValAssign::BCvt: {
1617 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1618 /*TODO: Kill=*/false);
1619 assert(BC != 0 && "Failed to emit a bitcast!");
1621 ArgVT = VA.getLocVT();
1624 default: llvm_unreachable("Unknown arg promotion!");
1627 // Now copy/store arg to correct locations.
1628 if (VA.isRegLoc() && !VA.needsCustom()) {
1629 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1632 RegArgs.push_back(VA.getLocReg());
1633 } else if (VA.needsCustom()) {
1634 // TODO: We need custom lowering for vector (v2f64) args.
1635 if (VA.getLocVT() != MVT::f64) return false;
1637 CCValAssign &NextVA = ArgLocs[++i];
1639 // TODO: Only handle register args for now.
1640 if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1642 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1643 TII.get(ARM::VMOVRRD), VA.getLocReg())
1644 .addReg(NextVA.getLocReg(), RegState::Define)
1646 RegArgs.push_back(VA.getLocReg());
1647 RegArgs.push_back(NextVA.getLocReg());
1649 assert(VA.isMemLoc());
1650 // Need to store on the stack.
1652 Addr.BaseType = Address::RegBase;
1653 Addr.Base.Reg = ARM::SP;
1654 Addr.Offset = VA.getLocMemOffset();
1656 if (!ARMEmitStore(ArgVT, Arg, Addr)) return false;
1662 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1663 const Instruction *I, CallingConv::ID CC,
1664 unsigned &NumBytes) {
1665 // Issue CALLSEQ_END
1666 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1667 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1668 TII.get(AdjStackUp))
1669 .addImm(NumBytes).addImm(0));
1671 // Now the return value.
1672 if (RetVT != MVT::isVoid) {
1673 SmallVector<CCValAssign, 16> RVLocs;
1674 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1675 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1677 // Copy all of the result registers out of their specified physreg.
1678 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1679 // For this move we copy into two registers and then move into the
1680 // double fp reg we want.
1681 EVT DestVT = RVLocs[0].getValVT();
1682 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1683 unsigned ResultReg = createResultReg(DstRC);
1684 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1685 TII.get(ARM::VMOVDRR), ResultReg)
1686 .addReg(RVLocs[0].getLocReg())
1687 .addReg(RVLocs[1].getLocReg()));
1689 UsedRegs.push_back(RVLocs[0].getLocReg());
1690 UsedRegs.push_back(RVLocs[1].getLocReg());
1692 // Finally update the result.
1693 UpdateValueMap(I, ResultReg);
1695 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1696 EVT CopyVT = RVLocs[0].getValVT();
1697 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1699 unsigned ResultReg = createResultReg(DstRC);
1700 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1701 ResultReg).addReg(RVLocs[0].getLocReg());
1702 UsedRegs.push_back(RVLocs[0].getLocReg());
1704 // Finally update the result.
1705 UpdateValueMap(I, ResultReg);
1712 bool ARMFastISel::SelectRet(const Instruction *I) {
1713 const ReturnInst *Ret = cast<ReturnInst>(I);
1714 const Function &F = *I->getParent()->getParent();
1716 if (!FuncInfo.CanLowerReturn)
1722 CallingConv::ID CC = F.getCallingConv();
1723 if (Ret->getNumOperands() > 0) {
1724 SmallVector<ISD::OutputArg, 4> Outs;
1725 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
1728 // Analyze operands of the call, assigning locations to each operand.
1729 SmallVector<CCValAssign, 16> ValLocs;
1730 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
1731 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
1733 const Value *RV = Ret->getOperand(0);
1734 unsigned Reg = getRegForValue(RV);
1738 // Only handle a single return value for now.
1739 if (ValLocs.size() != 1)
1742 CCValAssign &VA = ValLocs[0];
1744 // Don't bother handling odd stuff for now.
1745 if (VA.getLocInfo() != CCValAssign::Full)
1747 // Only handle register returns for now.
1750 // TODO: For now, don't try to handle cases where getLocInfo()
1751 // says Full but the types don't match.
1752 if (TLI.getValueType(RV->getType()) != VA.getValVT())
1756 unsigned SrcReg = Reg + VA.getValNo();
1757 unsigned DstReg = VA.getLocReg();
1758 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
1759 // Avoid a cross-class copy. This is very unlikely.
1760 if (!SrcRC->contains(DstReg))
1762 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1763 DstReg).addReg(SrcReg);
1765 // Mark the register as live out of the function.
1766 MRI.addLiveOut(VA.getLocReg());
1769 unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET;
1770 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1775 unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) {
1777 // Darwin needs the r9 versions of the opcodes.
1778 bool isDarwin = Subtarget->isTargetDarwin();
1780 return isDarwin ? ARM::tBLr9 : ARM::tBL;
1782 return isDarwin ? ARM::BLr9 : ARM::BL;
1786 // A quick function that will emit a call for a named libcall in F with the
1787 // vector of passed arguments for the Instruction in I. We can assume that we
1788 // can emit a call for any libcall we can produce. This is an abridged version
1789 // of the full call infrastructure since we won't need to worry about things
1790 // like computed function pointers or strange arguments at call sites.
1791 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1793 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1794 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1796 // Handle *simple* calls for now.
1797 Type *RetTy = I->getType();
1799 if (RetTy->isVoidTy())
1800 RetVT = MVT::isVoid;
1801 else if (!isTypeLegal(RetTy, RetVT))
1804 // TODO: For now if we have long calls specified we don't handle the call.
1805 if (EnableARMLongCalls) return false;
1807 // Set up the argument vectors.
1808 SmallVector<Value*, 8> Args;
1809 SmallVector<unsigned, 8> ArgRegs;
1810 SmallVector<MVT, 8> ArgVTs;
1811 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1812 Args.reserve(I->getNumOperands());
1813 ArgRegs.reserve(I->getNumOperands());
1814 ArgVTs.reserve(I->getNumOperands());
1815 ArgFlags.reserve(I->getNumOperands());
1816 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1817 Value *Op = I->getOperand(i);
1818 unsigned Arg = getRegForValue(Op);
1819 if (Arg == 0) return false;
1821 Type *ArgTy = Op->getType();
1823 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1825 ISD::ArgFlagsTy Flags;
1826 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1827 Flags.setOrigAlign(OriginalAlignment);
1830 ArgRegs.push_back(Arg);
1831 ArgVTs.push_back(ArgVT);
1832 ArgFlags.push_back(Flags);
1835 // Handle the arguments now that we've gotten them.
1836 SmallVector<unsigned, 4> RegArgs;
1838 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1841 // Issue the call, BLr9 for darwin, BL otherwise.
1842 // TODO: Turn this into the table of arm call ops.
1843 MachineInstrBuilder MIB;
1844 unsigned CallOpc = ARMSelectCallOp(NULL);
1846 // Explicitly adding the predicate here.
1847 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1849 .addExternalSymbol(TLI.getLibcallName(Call));
1851 // Explicitly adding the predicate here.
1852 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1854 .addExternalSymbol(TLI.getLibcallName(Call)));
1856 // Add implicit physical register uses to the call.
1857 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1858 MIB.addReg(RegArgs[i]);
1860 // Finish off the call including any return values.
1861 SmallVector<unsigned, 4> UsedRegs;
1862 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1864 // Set all unused physreg defs as dead.
1865 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1870 bool ARMFastISel::SelectCall(const Instruction *I) {
1871 const CallInst *CI = cast<CallInst>(I);
1872 const Value *Callee = CI->getCalledValue();
1874 // Can't handle inline asm or worry about intrinsics yet.
1875 if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1877 // Only handle global variable Callees.
1878 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1882 // Check the calling convention.
1883 ImmutableCallSite CS(CI);
1884 CallingConv::ID CC = CS.getCallingConv();
1886 // TODO: Avoid some calling conventions?
1888 // Let SDISel handle vararg functions.
1889 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1890 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1891 if (FTy->isVarArg())
1894 // Handle *simple* calls for now.
1895 Type *RetTy = I->getType();
1897 if (RetTy->isVoidTy())
1898 RetVT = MVT::isVoid;
1899 else if (!isTypeLegal(RetTy, RetVT))
1902 // TODO: For now if we have long calls specified we don't handle the call.
1903 if (EnableARMLongCalls) return false;
1905 // Set up the argument vectors.
1906 SmallVector<Value*, 8> Args;
1907 SmallVector<unsigned, 8> ArgRegs;
1908 SmallVector<MVT, 8> ArgVTs;
1909 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1910 Args.reserve(CS.arg_size());
1911 ArgRegs.reserve(CS.arg_size());
1912 ArgVTs.reserve(CS.arg_size());
1913 ArgFlags.reserve(CS.arg_size());
1914 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1916 unsigned Arg = getRegForValue(*i);
1920 ISD::ArgFlagsTy Flags;
1921 unsigned AttrInd = i - CS.arg_begin() + 1;
1922 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1924 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1927 // FIXME: Only handle *easy* calls for now.
1928 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1929 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1930 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1931 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1934 Type *ArgTy = (*i)->getType();
1936 if (!isTypeLegal(ArgTy, ArgVT))
1938 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1939 Flags.setOrigAlign(OriginalAlignment);
1942 ArgRegs.push_back(Arg);
1943 ArgVTs.push_back(ArgVT);
1944 ArgFlags.push_back(Flags);
1947 // Handle the arguments now that we've gotten them.
1948 SmallVector<unsigned, 4> RegArgs;
1950 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1953 // Issue the call, BLr9 for darwin, BL otherwise.
1954 // TODO: Turn this into the table of arm call ops.
1955 MachineInstrBuilder MIB;
1956 unsigned CallOpc = ARMSelectCallOp(GV);
1957 // Explicitly adding the predicate here.
1959 // Explicitly adding the predicate here.
1960 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1962 .addGlobalAddress(GV, 0, 0);
1964 // Explicitly adding the predicate here.
1965 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1967 .addGlobalAddress(GV, 0, 0));
1969 // Add implicit physical register uses to the call.
1970 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1971 MIB.addReg(RegArgs[i]);
1973 // Finish off the call including any return values.
1974 SmallVector<unsigned, 4> UsedRegs;
1975 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1977 // Set all unused physreg defs as dead.
1978 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1984 bool ARMFastISel::SelectIntCast(const Instruction *I) {
1985 // On ARM, in general, integer casts don't involve legal types; this code
1986 // handles promotable integers. The high bits for a type smaller than
1987 // the register size are assumed to be undefined.
1988 Type *DestTy = I->getType();
1989 Value *Op = I->getOperand(0);
1990 Type *SrcTy = Op->getType();
1993 SrcVT = TLI.getValueType(SrcTy, true);
1994 DestVT = TLI.getValueType(DestTy, true);
1996 if (isa<TruncInst>(I)) {
1997 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1999 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2002 unsigned SrcReg = getRegForValue(Op);
2003 if (!SrcReg) return false;
2005 // Because the high bits are undefined, a truncate doesn't generate
2007 UpdateValueMap(I, SrcReg);
2010 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2014 bool isZext = isa<ZExtInst>(I);
2015 bool isBoolZext = false;
2016 if (!SrcVT.isSimple())
2018 switch (SrcVT.getSimpleVT().SimpleTy) {
2019 default: return false;
2021 if (!Subtarget->hasV6Ops()) return false;
2023 Opc = isThumb ? ARM::t2UXTH : ARM::UXTH;
2025 Opc = isThumb ? ARM::t2SXTH : ARM::SXTH;
2028 if (!Subtarget->hasV6Ops()) return false;
2030 Opc = isThumb ? ARM::t2UXTB : ARM::UXTB;
2032 Opc = isThumb ? ARM::t2SXTB : ARM::SXTB;
2036 Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
2043 // FIXME: We could save an instruction in many cases by special-casing
2044 // load instructions.
2045 unsigned SrcReg = getRegForValue(Op);
2046 if (!SrcReg) return false;
2048 unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2049 MachineInstrBuilder MIB;
2050 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
2056 AddOptionalDefs(MIB);
2057 UpdateValueMap(I, DestReg);
2061 // TODO: SoftFP support.
2062 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2064 switch (I->getOpcode()) {
2065 case Instruction::Load:
2066 return SelectLoad(I);
2067 case Instruction::Store:
2068 return SelectStore(I);
2069 case Instruction::Br:
2070 return SelectBranch(I);
2071 case Instruction::ICmp:
2072 case Instruction::FCmp:
2073 return SelectCmp(I);
2074 case Instruction::FPExt:
2075 return SelectFPExt(I);
2076 case Instruction::FPTrunc:
2077 return SelectFPTrunc(I);
2078 case Instruction::SIToFP:
2079 return SelectSIToFP(I);
2080 case Instruction::FPToSI:
2081 return SelectFPToSI(I);
2082 case Instruction::FAdd:
2083 return SelectBinaryOp(I, ISD::FADD);
2084 case Instruction::FSub:
2085 return SelectBinaryOp(I, ISD::FSUB);
2086 case Instruction::FMul:
2087 return SelectBinaryOp(I, ISD::FMUL);
2088 case Instruction::SDiv:
2089 return SelectSDiv(I);
2090 case Instruction::SRem:
2091 return SelectSRem(I);
2092 case Instruction::Call:
2093 return SelectCall(I);
2094 case Instruction::Select:
2095 return SelectSelect(I);
2096 case Instruction::Ret:
2097 return SelectRet(I);
2098 case Instruction::Trunc:
2099 case Instruction::ZExt:
2100 case Instruction::SExt:
2101 return SelectIntCast(I);
2108 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
2109 // Completely untested on non-darwin.
2110 const TargetMachine &TM = funcInfo.MF->getTarget();
2112 // Darwin and thumb1 only for now.
2113 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2114 if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() &&
2115 !DisableARMFastISel)
2116 return new ARMFastISel(funcInfo);