1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "ARMConstantPoolValue.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/Analysis.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/FunctionLoweringInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineConstantPool.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/Support/CallSite.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/GetElementPtrTypeIterator.h"
41 #include "llvm/Target/TargetData.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
49 EnableARMFastISel("arm-fast-isel",
50 cl::desc("Turn on experimental ARM fast-isel support"),
51 cl::init(false), cl::Hidden);
55 class ARMFastISel : public FastISel {
57 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
58 /// make the right decision when generating code for different targets.
59 const ARMSubtarget *Subtarget;
60 const TargetMachine &TM;
61 const TargetInstrInfo &TII;
62 const TargetLowering &TLI;
65 // Convenience variables to avoid some queries.
70 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
72 TM(funcInfo.MF->getTarget()),
73 TII(*TM.getInstrInfo()),
74 TLI(*TM.getTargetLowering()) {
75 Subtarget = &TM.getSubtarget<ARMSubtarget>();
76 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
77 isThumb = AFI->isThumbFunction();
78 Context = &funcInfo.Fn->getContext();
81 // Code from FastISel.cpp.
82 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
83 const TargetRegisterClass *RC);
84 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
85 const TargetRegisterClass *RC,
86 unsigned Op0, bool Op0IsKill);
87 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
88 const TargetRegisterClass *RC,
89 unsigned Op0, bool Op0IsKill,
90 unsigned Op1, bool Op1IsKill);
91 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
92 const TargetRegisterClass *RC,
93 unsigned Op0, bool Op0IsKill,
95 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
96 const TargetRegisterClass *RC,
97 unsigned Op0, bool Op0IsKill,
98 const ConstantFP *FPImm);
99 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
100 const TargetRegisterClass *RC,
102 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
103 const TargetRegisterClass *RC,
104 unsigned Op0, bool Op0IsKill,
105 unsigned Op1, bool Op1IsKill,
107 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
108 unsigned Op0, bool Op0IsKill,
111 // Backend specific FastISel code.
112 virtual bool TargetSelectInstruction(const Instruction *I);
113 virtual unsigned TargetMaterializeConstant(const Constant *C);
114 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
116 #include "ARMGenFastISel.inc"
118 // Instruction selection routines.
120 virtual bool SelectLoad(const Instruction *I);
121 virtual bool SelectStore(const Instruction *I);
122 virtual bool SelectBranch(const Instruction *I);
123 virtual bool SelectCmp(const Instruction *I);
124 virtual bool SelectFPExt(const Instruction *I);
125 virtual bool SelectFPTrunc(const Instruction *I);
126 virtual bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
127 virtual bool SelectSIToFP(const Instruction *I);
128 virtual bool SelectFPToSI(const Instruction *I);
129 virtual bool SelectSDiv(const Instruction *I);
130 virtual bool SelectSRem(const Instruction *I);
131 virtual bool SelectCall(const Instruction *I);
132 virtual bool SelectSelect(const Instruction *I);
136 bool isTypeLegal(const Type *Ty, EVT &VT);
137 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
138 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
139 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
140 bool ARMLoadAlloca(const Instruction *I, EVT VT);
141 bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
142 bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
143 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
144 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
145 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
146 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
147 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
149 // Call handling routines.
151 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
152 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
153 SmallVectorImpl<unsigned> &ArgRegs,
154 SmallVectorImpl<EVT> &ArgVTs,
155 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
156 SmallVectorImpl<unsigned> &RegArgs,
159 bool FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
160 const Instruction *I, CallingConv::ID CC,
162 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
164 // OptionalDef handling routines.
166 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
167 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
170 } // end anonymous namespace
172 #include "ARMGenCallingConv.inc"
174 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
175 // we don't care about implicit defs here, just places we'll need to add a
176 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
177 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
178 const TargetInstrDesc &TID = MI->getDesc();
179 if (!TID.hasOptionalDef())
182 // Look to see if our OptionalDef is defining CPSR or CCR.
183 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
184 const MachineOperand &MO = MI->getOperand(i);
185 if (!MO.isReg() || !MO.isDef()) continue;
186 if (MO.getReg() == ARM::CPSR)
192 // If the machine is predicable go ahead and add the predicate operands, if
193 // it needs default CC operands add those.
194 const MachineInstrBuilder &
195 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
196 MachineInstr *MI = &*MIB;
198 // Do we use a predicate?
199 if (TII.isPredicable(MI))
202 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
203 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
205 if (DefinesOptionalPredicate(MI, &CPSR)) {
214 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
215 const TargetRegisterClass* RC) {
216 unsigned ResultReg = createResultReg(RC);
217 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
219 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
223 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
224 const TargetRegisterClass *RC,
225 unsigned Op0, bool Op0IsKill) {
226 unsigned ResultReg = createResultReg(RC);
227 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
229 if (II.getNumDefs() >= 1)
230 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
231 .addReg(Op0, Op0IsKill * RegState::Kill));
233 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
234 .addReg(Op0, Op0IsKill * RegState::Kill));
235 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
236 TII.get(TargetOpcode::COPY), ResultReg)
237 .addReg(II.ImplicitDefs[0]));
242 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
243 const TargetRegisterClass *RC,
244 unsigned Op0, bool Op0IsKill,
245 unsigned Op1, bool Op1IsKill) {
246 unsigned ResultReg = createResultReg(RC);
247 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
249 if (II.getNumDefs() >= 1)
250 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
251 .addReg(Op0, Op0IsKill * RegState::Kill)
252 .addReg(Op1, Op1IsKill * RegState::Kill));
254 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
255 .addReg(Op0, Op0IsKill * RegState::Kill)
256 .addReg(Op1, Op1IsKill * RegState::Kill));
257 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
258 TII.get(TargetOpcode::COPY), ResultReg)
259 .addReg(II.ImplicitDefs[0]));
264 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
265 const TargetRegisterClass *RC,
266 unsigned Op0, bool Op0IsKill,
268 unsigned ResultReg = createResultReg(RC);
269 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
271 if (II.getNumDefs() >= 1)
272 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
273 .addReg(Op0, Op0IsKill * RegState::Kill)
276 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
277 .addReg(Op0, Op0IsKill * RegState::Kill)
279 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
280 TII.get(TargetOpcode::COPY), ResultReg)
281 .addReg(II.ImplicitDefs[0]));
286 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
287 const TargetRegisterClass *RC,
288 unsigned Op0, bool Op0IsKill,
289 const ConstantFP *FPImm) {
290 unsigned ResultReg = createResultReg(RC);
291 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
293 if (II.getNumDefs() >= 1)
294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
295 .addReg(Op0, Op0IsKill * RegState::Kill)
298 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
299 .addReg(Op0, Op0IsKill * RegState::Kill)
301 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
302 TII.get(TargetOpcode::COPY), ResultReg)
303 .addReg(II.ImplicitDefs[0]));
308 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
309 const TargetRegisterClass *RC,
310 unsigned Op0, bool Op0IsKill,
311 unsigned Op1, bool Op1IsKill,
313 unsigned ResultReg = createResultReg(RC);
314 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
316 if (II.getNumDefs() >= 1)
317 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
318 .addReg(Op0, Op0IsKill * RegState::Kill)
319 .addReg(Op1, Op1IsKill * RegState::Kill)
322 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
323 .addReg(Op0, Op0IsKill * RegState::Kill)
324 .addReg(Op1, Op1IsKill * RegState::Kill)
326 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
327 TII.get(TargetOpcode::COPY), ResultReg)
328 .addReg(II.ImplicitDefs[0]));
333 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
334 const TargetRegisterClass *RC,
336 unsigned ResultReg = createResultReg(RC);
337 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
339 if (II.getNumDefs() >= 1)
340 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
343 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
345 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
346 TII.get(TargetOpcode::COPY), ResultReg)
347 .addReg(II.ImplicitDefs[0]));
352 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
353 unsigned Op0, bool Op0IsKill,
355 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
356 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
357 "Cannot yet extract from physregs");
358 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
359 DL, TII.get(TargetOpcode::COPY), ResultReg)
360 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
364 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
365 // checks from the various callers.
366 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
367 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
369 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
370 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
371 TII.get(ARM::VMOVRS), MoveReg)
376 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
377 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
379 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
380 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
381 TII.get(ARM::VMOVSR), MoveReg)
386 // For double width floating point we need to materialize two constants
387 // (the high and the low) into integer registers then use a move to get
388 // the combined constant into an FP reg.
389 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
390 const APFloat Val = CFP->getValueAPF();
391 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
393 // This checks to see if we can use VFP3 instructions to materialize
394 // a constant, otherwise we have to go through the constant pool.
395 if (TLI.isFPImmLegal(Val, VT)) {
396 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
397 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
398 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
404 // Require VFP2 for loading fp constants.
405 if (!Subtarget->hasVFP2()) return false;
407 // MachineConstantPool wants an explicit alignment.
408 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
410 // TODO: Figure out if this is correct.
411 Align = TD.getTypeAllocSize(CFP->getType());
413 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
414 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
415 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
417 // The extra reg is for addrmode5.
418 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
420 .addConstantPoolIndex(Idx)
425 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
427 // For now 32-bit only.
428 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
430 // MachineConstantPool wants an explicit alignment.
431 unsigned Align = TD.getPrefTypeAlignment(C->getType());
433 // TODO: Figure out if this is correct.
434 Align = TD.getTypeAllocSize(C->getType());
436 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
437 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
440 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
441 TII.get(ARM::t2LDRpci), DestReg)
442 .addConstantPoolIndex(Idx));
444 // The extra reg and immediate are for addrmode2.
445 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
446 TII.get(ARM::LDRcp), DestReg)
447 .addConstantPoolIndex(Idx)
448 .addReg(0).addImm(0));
453 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
454 // For now 32-bit only.
455 if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0;
457 Reloc::Model RelocM = TM.getRelocationModel();
459 // TODO: No external globals for now.
460 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
462 // TODO: Need more magic for ARM PIC.
463 if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
465 // MachineConstantPool wants an explicit alignment.
466 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
468 // TODO: Figure out if this is correct.
469 Align = TD.getTypeAllocSize(GV->getType());
473 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
474 unsigned Id = AFI->createConstPoolEntryUId();
475 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
476 ARMCP::CPValue, PCAdj);
477 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
480 MachineInstrBuilder MIB;
481 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
483 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
484 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
485 .addConstantPoolIndex(Idx);
486 if (RelocM == Reloc::PIC_)
489 // The extra reg and immediate are for addrmode2.
490 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
492 .addConstantPoolIndex(Idx)
493 .addReg(0).addImm(0);
495 AddOptionalDefs(MIB);
499 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
500 EVT VT = TLI.getValueType(C->getType(), true);
502 // Only handle simple types.
503 if (!VT.isSimple()) return 0;
505 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
506 return ARMMaterializeFP(CFP, VT);
507 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
508 return ARMMaterializeGV(GV, VT);
509 else if (isa<ConstantInt>(C))
510 return ARMMaterializeInt(C, VT);
515 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
516 // Don't handle dynamic allocas.
517 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
520 if (!isTypeLegal(AI->getType(), VT)) return false;
522 DenseMap<const AllocaInst*, int>::iterator SI =
523 FuncInfo.StaticAllocaMap.find(AI);
525 // This will get lowered later into the correct offsets and registers
526 // via rewriteXFrameIndex.
527 if (SI != FuncInfo.StaticAllocaMap.end()) {
528 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
529 unsigned ResultReg = createResultReg(RC);
530 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
531 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
532 TII.get(Opc), ResultReg)
533 .addFrameIndex(SI->second)
541 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
542 VT = TLI.getValueType(Ty, true);
544 // Only handle simple types.
545 if (VT == MVT::Other || !VT.isSimple()) return false;
547 // Handle all legal types, i.e. a register that will directly hold this
549 return TLI.isTypeLegal(VT);
552 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
553 if (isTypeLegal(Ty, VT)) return true;
555 // If this is a type than can be sign or zero-extended to a basic operation
556 // go ahead and accept it now.
557 if (VT == MVT::i8 || VT == MVT::i16)
563 // Computes the Reg+Offset to get to an object.
564 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
566 // Some boilerplate from the X86 FastISel.
567 const User *U = NULL;
568 unsigned Opcode = Instruction::UserOp1;
569 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
570 // Don't walk into other basic blocks; it's possible we haven't
571 // visited them yet, so the instructions may not yet be assigned
572 // virtual registers.
573 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
575 Opcode = I->getOpcode();
577 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
578 Opcode = C->getOpcode();
582 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
583 if (Ty->getAddressSpace() > 255)
584 // Fast instruction selection doesn't support the special
591 case Instruction::BitCast: {
592 // Look through bitcasts.
593 return ARMComputeRegOffset(U->getOperand(0), Reg, Offset);
595 case Instruction::IntToPtr: {
596 // Look past no-op inttoptrs.
597 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
598 return ARMComputeRegOffset(U->getOperand(0), Reg, Offset);
601 case Instruction::PtrToInt: {
602 // Look past no-op ptrtoints.
603 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
604 return ARMComputeRegOffset(U->getOperand(0), Reg, Offset);
607 case Instruction::Alloca: {
608 // Don't handle dynamic allocas.
609 assert(!FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Obj)) &&
610 "Alloca should have been handled earlier!");
615 // FIXME: Handle global variables.
616 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
621 // Try to get this in a register if nothing else has worked.
622 Reg = getRegForValue(Obj);
623 if (Reg == 0) return false;
625 // Since the offset may be too large for the load instruction
626 // get the reg+offset into a register.
627 // TODO: Verify the additions work, otherwise we'll need to add the
628 // offset instead of 0 to the instructions and do all sorts of operand
630 // TODO: Optimize this somewhat.
632 ARMCC::CondCodes Pred = ARMCC::AL;
633 unsigned PredReg = 0;
636 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
637 Reg, Reg, Offset, Pred, PredReg,
638 static_cast<const ARMBaseInstrInfo&>(TII));
640 assert(AFI->isThumb2Function());
641 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
642 Reg, Reg, Offset, Pred, PredReg,
643 static_cast<const ARMBaseInstrInfo&>(TII));
649 bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
650 Value *Op0 = I->getOperand(0);
652 // Promote load/store types.
653 if (VT == MVT::i8 || VT == MVT::i16) VT = MVT::i32;
655 // Verify it's an alloca.
656 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
657 DenseMap<const AllocaInst*, int>::iterator SI =
658 FuncInfo.StaticAllocaMap.find(AI);
660 if (SI != FuncInfo.StaticAllocaMap.end()) {
661 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
662 unsigned ResultReg = createResultReg(RC);
663 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
664 ResultReg, SI->second, RC,
665 TM.getRegisterInfo());
666 UpdateValueMap(I, ResultReg);
673 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
674 unsigned Reg, int Offset) {
676 assert(VT.isSimple() && "Non-simple types are invalid here!");
678 TargetRegisterClass *RC;
679 bool isFloat = false;
680 switch (VT.getSimpleVT().SimpleTy) {
682 // This is mostly going to be Neon/vector support.
685 Opc = isThumb ? ARM::t2LDRHi8 : ARM::LDRH;
686 RC = ARM::GPRRegisterClass;
690 Opc = isThumb ? ARM::t2LDRBi8 : ARM::LDRB;
691 RC = ARM::GPRRegisterClass;
695 Opc = isThumb ? ARM::t2LDRi8 : ARM::LDR;
696 RC = ARM::GPRRegisterClass;
700 RC = TLI.getRegClassFor(VT);
705 RC = TLI.getRegClassFor(VT);
710 ResultReg = createResultReg(RC);
712 // For now with the additions above the offset should be zero - thus we
713 // can always fit into an i8.
714 assert(Offset == 0 && "Offset not zero!");
716 // The thumb and floating point instructions both take 2 operands, ARM takes
718 if (isFloat || isThumb)
719 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
720 TII.get(Opc), ResultReg)
721 .addReg(Reg).addImm(Offset));
723 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
724 TII.get(Opc), ResultReg)
725 .addReg(Reg).addReg(0).addImm(Offset));
729 bool ARMFastISel::SelectLoad(const Instruction *I) {
730 // Verify we have a legal type before going any further.
732 if (!isLoadTypeLegal(I->getType(), VT))
735 // If we're an alloca we know we have a frame index and can emit the load
736 // directly in short order.
737 if (ARMLoadAlloca(I, VT))
740 // Our register and offset with innocuous defaults.
744 // See if we can handle this as Reg + Offset
745 if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
749 if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
751 UpdateValueMap(I, ResultReg);
755 bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
756 Value *Op1 = I->getOperand(1);
758 // Promote load/store types.
759 if (VT == MVT::i8 || VT == MVT::i16) VT = MVT::i32;
761 // Verify it's an alloca.
762 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
763 DenseMap<const AllocaInst*, int>::iterator SI =
764 FuncInfo.StaticAllocaMap.find(AI);
766 if (SI != FuncInfo.StaticAllocaMap.end()) {
767 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
768 assert(SrcReg != 0 && "Nothing to store!");
769 TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
770 SrcReg, true /*isKill*/, SI->second, RC,
771 TM.getRegisterInfo());
778 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
779 unsigned DstReg, int Offset) {
781 bool isFloat = false;
782 switch (VT.getSimpleVT().SimpleTy) {
783 default: return false;
785 case MVT::i8: StrOpc = isThumb ? ARM::t2STRBi8 : ARM::STRB; break;
786 case MVT::i16: StrOpc = isThumb ? ARM::t2STRHi8 : ARM::STRH; break;
787 case MVT::i32: StrOpc = isThumb ? ARM::t2STRi8 : ARM::STR; break;
789 if (!Subtarget->hasVFP2()) return false;
794 if (!Subtarget->hasVFP2()) return false;
800 // The thumb addressing mode has operands swapped from the arm addressing
801 // mode, the floating point one only has two operands.
802 if (isFloat || isThumb)
803 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
805 .addReg(SrcReg).addReg(DstReg).addImm(Offset));
807 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
809 .addReg(SrcReg).addReg(DstReg).addReg(0).addImm(Offset));
814 bool ARMFastISel::SelectStore(const Instruction *I) {
815 Value *Op0 = I->getOperand(0);
818 // Yay type legalization
820 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
823 // Get the value to be stored into a register.
824 SrcReg = getRegForValue(Op0);
828 // If we're an alloca we know we have a frame index and can emit the store
830 if (ARMStoreAlloca(I, SrcReg, VT))
833 // Our register and offset with innocuous defaults.
837 // See if we can handle this as Reg + Offset
838 if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
841 if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
846 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
848 // Needs two compares...
849 case CmpInst::FCMP_ONE:
850 case CmpInst::FCMP_UEQ:
852 assert(false && "Unhandled CmpInst::Predicate!");
854 case CmpInst::ICMP_EQ:
855 case CmpInst::FCMP_OEQ:
857 case CmpInst::ICMP_SGT:
858 case CmpInst::FCMP_OGT:
860 case CmpInst::ICMP_SGE:
861 case CmpInst::FCMP_OGE:
863 case CmpInst::ICMP_UGT:
864 case CmpInst::FCMP_UGT:
866 case CmpInst::FCMP_OLT:
868 case CmpInst::ICMP_ULE:
869 case CmpInst::FCMP_OLE:
871 case CmpInst::FCMP_ORD:
873 case CmpInst::FCMP_UNO:
875 case CmpInst::FCMP_UGE:
877 case CmpInst::ICMP_SLT:
878 case CmpInst::FCMP_ULT:
880 case CmpInst::ICMP_SLE:
881 case CmpInst::FCMP_ULE:
883 case CmpInst::FCMP_UNE:
884 case CmpInst::ICMP_NE:
886 case CmpInst::ICMP_UGE:
888 case CmpInst::ICMP_ULT:
893 bool ARMFastISel::SelectBranch(const Instruction *I) {
894 const BranchInst *BI = cast<BranchInst>(I);
895 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
896 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
898 // Simple branch support.
899 // TODO: Try to avoid the re-computation in some places.
900 unsigned CondReg = getRegForValue(BI->getCondition());
901 if (CondReg == 0) return false;
903 // Re-set the flags just in case.
904 unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri;
905 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
906 .addReg(CondReg).addImm(1));
908 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
909 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
910 .addMBB(TBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
911 FastEmitBranch(FBB, DL);
912 FuncInfo.MBB->addSuccessor(TBB);
916 bool ARMFastISel::SelectCmp(const Instruction *I) {
917 const CmpInst *CI = cast<CmpInst>(I);
920 const Type *Ty = CI->getOperand(0)->getType();
921 if (!isTypeLegal(Ty, VT))
924 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
925 if (isFloat && !Subtarget->hasVFP2())
930 switch (VT.getSimpleVT().SimpleTy) {
931 default: return false;
932 // TODO: Verify compares.
934 CmpOpc = ARM::VCMPES;
935 CondReg = ARM::FPSCR;
938 CmpOpc = ARM::VCMPED;
939 CondReg = ARM::FPSCR;
942 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
947 // Get the compare predicate.
948 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
950 // We may not handle every CC for now.
951 if (ARMPred == ARMCC::AL) return false;
953 unsigned Arg1 = getRegForValue(CI->getOperand(0));
954 if (Arg1 == 0) return false;
956 unsigned Arg2 = getRegForValue(CI->getOperand(1));
957 if (Arg2 == 0) return false;
959 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
960 .addReg(Arg1).addReg(Arg2));
962 // For floating point we need to move the result to a comparison register
963 // that we can then use for branches.
965 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
966 TII.get(ARM::FMSTAT)));
968 // Now set a register based on the comparison. Explicitly set the predicates
970 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
971 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
972 : ARM::GPRRegisterClass;
973 unsigned DestReg = createResultReg(RC);
975 = ConstantInt::get(Type::getInt32Ty(*Context), 0);
976 unsigned ZeroReg = TargetMaterializeConstant(Zero);
977 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
978 .addReg(ZeroReg).addImm(1)
979 .addImm(ARMPred).addReg(CondReg);
981 UpdateValueMap(I, DestReg);
985 bool ARMFastISel::SelectFPExt(const Instruction *I) {
986 // Make sure we have VFP and that we're extending float to double.
987 if (!Subtarget->hasVFP2()) return false;
989 Value *V = I->getOperand(0);
990 if (!I->getType()->isDoubleTy() ||
991 !V->getType()->isFloatTy()) return false;
993 unsigned Op = getRegForValue(V);
994 if (Op == 0) return false;
996 unsigned Result = createResultReg(ARM::DPRRegisterClass);
997 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
998 TII.get(ARM::VCVTDS), Result)
1000 UpdateValueMap(I, Result);
1004 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1005 // Make sure we have VFP and that we're truncating double to float.
1006 if (!Subtarget->hasVFP2()) return false;
1008 Value *V = I->getOperand(0);
1009 if (!(I->getType()->isFloatTy() &&
1010 V->getType()->isDoubleTy())) return false;
1012 unsigned Op = getRegForValue(V);
1013 if (Op == 0) return false;
1015 unsigned Result = createResultReg(ARM::SPRRegisterClass);
1016 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1017 TII.get(ARM::VCVTSD), Result)
1019 UpdateValueMap(I, Result);
1023 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1024 // Make sure we have VFP.
1025 if (!Subtarget->hasVFP2()) return false;
1028 const Type *Ty = I->getType();
1029 if (!isTypeLegal(Ty, DstVT))
1032 unsigned Op = getRegForValue(I->getOperand(0));
1033 if (Op == 0) return false;
1035 // The conversion routine works on fp-reg to fp-reg and the operand above
1036 // was an integer, move it to the fp registers if possible.
1037 unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1038 if (FP == 0) return false;
1041 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1042 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1045 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1046 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1049 UpdateValueMap(I, ResultReg);
1053 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1054 // Make sure we have VFP.
1055 if (!Subtarget->hasVFP2()) return false;
1058 const Type *RetTy = I->getType();
1059 if (!isTypeLegal(RetTy, DstVT))
1062 unsigned Op = getRegForValue(I->getOperand(0));
1063 if (Op == 0) return false;
1066 const Type *OpTy = I->getOperand(0)->getType();
1067 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1068 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1071 // f64->s32 or f32->s32 both need an intermediate f32 reg.
1072 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1073 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1077 // This result needs to be in an integer register, but the conversion only
1078 // takes place in fp-regs.
1079 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1080 if (IntReg == 0) return false;
1082 UpdateValueMap(I, IntReg);
1086 bool ARMFastISel::SelectSelect(const Instruction *I) {
1087 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1088 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1091 // Things need to be register sized for register moves.
1092 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
1093 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1095 unsigned CondReg = getRegForValue(I->getOperand(0));
1096 if (CondReg == 0) return false;
1097 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1098 if (Op1Reg == 0) return false;
1099 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1100 if (Op2Reg == 0) return false;
1102 unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1103 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1104 .addReg(CondReg).addImm(1));
1105 unsigned ResultReg = createResultReg(RC);
1106 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1107 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1108 .addReg(Op1Reg).addReg(Op2Reg)
1109 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1110 UpdateValueMap(I, ResultReg);
1114 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1116 const Type *Ty = I->getType();
1117 if (!isTypeLegal(Ty, VT))
1120 // If we have integer div support we should have selected this automagically.
1121 // In case we have a real miss go ahead and return false and we'll pick
1123 if (Subtarget->hasDivide()) return false;
1125 // Otherwise emit a libcall.
1126 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1128 LC = RTLIB::SDIV_I8;
1129 else if (VT == MVT::i16)
1130 LC = RTLIB::SDIV_I16;
1131 else if (VT == MVT::i32)
1132 LC = RTLIB::SDIV_I32;
1133 else if (VT == MVT::i64)
1134 LC = RTLIB::SDIV_I64;
1135 else if (VT == MVT::i128)
1136 LC = RTLIB::SDIV_I128;
1137 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1139 return ARMEmitLibcall(I, LC);
1142 bool ARMFastISel::SelectSRem(const Instruction *I) {
1144 const Type *Ty = I->getType();
1145 if (!isTypeLegal(Ty, VT))
1148 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1150 LC = RTLIB::SREM_I8;
1151 else if (VT == MVT::i16)
1152 LC = RTLIB::SREM_I16;
1153 else if (VT == MVT::i32)
1154 LC = RTLIB::SREM_I32;
1155 else if (VT == MVT::i64)
1156 LC = RTLIB::SREM_I64;
1157 else if (VT == MVT::i128)
1158 LC = RTLIB::SREM_I128;
1159 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1161 return ARMEmitLibcall(I, LC);
1164 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1165 EVT VT = TLI.getValueType(I->getType(), true);
1167 // We can get here in the case when we want to use NEON for our fp
1168 // operations, but can't figure out how to. Just use the vfp instructions
1170 // FIXME: It'd be nice to use NEON instructions.
1171 const Type *Ty = I->getType();
1172 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1173 if (isFloat && !Subtarget->hasVFP2())
1176 unsigned Op1 = getRegForValue(I->getOperand(0));
1177 if (Op1 == 0) return false;
1179 unsigned Op2 = getRegForValue(I->getOperand(1));
1180 if (Op2 == 0) return false;
1183 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
1184 VT.getSimpleVT().SimpleTy == MVT::i64;
1185 switch (ISDOpcode) {
1186 default: return false;
1188 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1191 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1194 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1197 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1198 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1199 TII.get(Opc), ResultReg)
1200 .addReg(Op1).addReg(Op2));
1201 UpdateValueMap(I, ResultReg);
1205 // Call Handling Code
1207 // This is largely taken directly from CCAssignFnForNode - we don't support
1208 // varargs in FastISel so that part has been removed.
1209 // TODO: We may not support all of this.
1210 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1213 llvm_unreachable("Unsupported calling convention");
1214 case CallingConv::C:
1215 case CallingConv::Fast:
1216 // Use target triple & subtarget features to do actual dispatch.
1217 if (Subtarget->isAAPCS_ABI()) {
1218 if (Subtarget->hasVFP2() &&
1219 FloatABIType == FloatABI::Hard)
1220 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1222 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1224 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1225 case CallingConv::ARM_AAPCS_VFP:
1226 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1227 case CallingConv::ARM_AAPCS:
1228 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1229 case CallingConv::ARM_APCS:
1230 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1234 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1235 SmallVectorImpl<unsigned> &ArgRegs,
1236 SmallVectorImpl<EVT> &ArgVTs,
1237 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1238 SmallVectorImpl<unsigned> &RegArgs,
1240 unsigned &NumBytes) {
1241 SmallVector<CCValAssign, 16> ArgLocs;
1242 CCState CCInfo(CC, false, TM, ArgLocs, *Context);
1243 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1245 // Get a count of how many bytes are to be pushed on the stack.
1246 NumBytes = CCInfo.getNextStackOffset();
1248 // Issue CALLSEQ_START
1249 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1250 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1251 TII.get(AdjStackDown))
1254 // Process the args.
1255 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1256 CCValAssign &VA = ArgLocs[i];
1257 unsigned Arg = ArgRegs[VA.getValNo()];
1258 EVT ArgVT = ArgVTs[VA.getValNo()];
1260 // Handle arg promotion, etc.
1261 switch (VA.getLocInfo()) {
1262 case CCValAssign::Full: break;
1264 // TODO: Handle arg promotion.
1268 // Now copy/store arg to correct locations.
1269 // TODO: We need custom lowering for f64 args.
1270 if (VA.isRegLoc() && !VA.needsCustom()) {
1271 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1274 RegArgs.push_back(VA.getLocReg());
1284 bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1285 const Instruction *I, CallingConv::ID CC,
1286 unsigned &NumBytes) {
1287 // Issue CALLSEQ_END
1288 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1289 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1290 TII.get(AdjStackUp))
1291 .addImm(NumBytes).addImm(0));
1293 // Now the return value.
1294 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1295 SmallVector<CCValAssign, 16> RVLocs;
1296 CCState CCInfo(CC, false, TM, RVLocs, *Context);
1297 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1299 // Copy all of the result registers out of their specified physreg.
1300 if (RVLocs.size() == 2 && RetVT.getSimpleVT().SimpleTy == MVT::f64) {
1301 // For this move we copy into two registers and then move into the
1302 // double fp reg we want.
1303 // TODO: Are the copies necessary?
1304 TargetRegisterClass *CopyRC = TLI.getRegClassFor(MVT::i32);
1305 unsigned Copy1 = createResultReg(CopyRC);
1306 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1307 Copy1).addReg(RVLocs[0].getLocReg());
1308 UsedRegs.push_back(RVLocs[0].getLocReg());
1310 unsigned Copy2 = createResultReg(CopyRC);
1311 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1312 Copy2).addReg(RVLocs[1].getLocReg());
1313 UsedRegs.push_back(RVLocs[1].getLocReg());
1315 EVT DestVT = RVLocs[0].getValVT();
1316 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1317 unsigned ResultReg = createResultReg(DstRC);
1318 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1319 TII.get(ARM::VMOVDRR), ResultReg)
1320 .addReg(Copy1).addReg(Copy2));
1322 // Finally update the result.
1323 UpdateValueMap(I, ResultReg);
1325 assert(RVLocs.size() == 1 && "Can't handle non-double multi-reg retvals!");
1326 EVT CopyVT = RVLocs[0].getValVT();
1327 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1329 unsigned ResultReg = createResultReg(DstRC);
1330 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1331 ResultReg).addReg(RVLocs[0].getLocReg());
1332 UsedRegs.push_back(RVLocs[0].getLocReg());
1334 // Finally update the result.
1335 UpdateValueMap(I, ResultReg);
1342 // A quick function that will emit a call for a named libcall in F with the
1343 // vector of passed arguments for the Instruction in I. We can assume that we
1344 // can emit a call for any libcall we can produce. This is an abridged version
1345 // of the full call infrastructure since we won't need to worry about things
1346 // like computed function pointers or strange arguments at call sites.
1347 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1349 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1350 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1352 // Handle *simple* calls for now.
1353 const Type *RetTy = I->getType();
1355 if (RetTy->isVoidTy())
1356 RetVT = MVT::isVoid;
1357 else if (!isTypeLegal(RetTy, RetVT))
1360 // For now we're using BLX etc on the assumption that we have v5t ops.
1361 if (!Subtarget->hasV5TOps()) return false;
1363 // Set up the argument vectors.
1364 SmallVector<Value*, 8> Args;
1365 SmallVector<unsigned, 8> ArgRegs;
1366 SmallVector<EVT, 8> ArgVTs;
1367 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1368 Args.reserve(I->getNumOperands());
1369 ArgRegs.reserve(I->getNumOperands());
1370 ArgVTs.reserve(I->getNumOperands());
1371 ArgFlags.reserve(I->getNumOperands());
1372 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1373 Value *Op = I->getOperand(i);
1374 unsigned Arg = getRegForValue(Op);
1375 if (Arg == 0) return false;
1377 const Type *ArgTy = Op->getType();
1379 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1381 ISD::ArgFlagsTy Flags;
1382 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1383 Flags.setOrigAlign(OriginalAlignment);
1386 ArgRegs.push_back(Arg);
1387 ArgVTs.push_back(ArgVT);
1388 ArgFlags.push_back(Flags);
1391 // Handle the arguments now that we've gotten them.
1392 SmallVector<unsigned, 4> RegArgs;
1394 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1397 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1398 // TODO: Turn this into the table of arm call ops.
1399 MachineInstrBuilder MIB;
1402 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1404 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1405 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1406 .addExternalSymbol(TLI.getLibcallName(Call));
1408 // Add implicit physical register uses to the call.
1409 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1410 MIB.addReg(RegArgs[i]);
1412 // Finish off the call including any return values.
1413 SmallVector<unsigned, 4> UsedRegs;
1414 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1416 // Set all unused physreg defs as dead.
1417 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1422 bool ARMFastISel::SelectCall(const Instruction *I) {
1423 const CallInst *CI = cast<CallInst>(I);
1424 const Value *Callee = CI->getCalledValue();
1426 // Can't handle inline asm or worry about intrinsics yet.
1427 if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1429 // Only handle global variable Callees that are direct calls.
1430 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1431 if (!GV || Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()))
1434 // Check the calling convention.
1435 ImmutableCallSite CS(CI);
1436 CallingConv::ID CC = CS.getCallingConv();
1437 // TODO: Avoid some calling conventions?
1438 if (CC != CallingConv::C) {
1439 // errs() << "Can't handle calling convention: " << CC << "\n";
1443 // Let SDISel handle vararg functions.
1444 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1445 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1446 if (FTy->isVarArg())
1449 // Handle *simple* calls for now.
1450 const Type *RetTy = I->getType();
1452 if (RetTy->isVoidTy())
1453 RetVT = MVT::isVoid;
1454 else if (!isTypeLegal(RetTy, RetVT))
1457 // For now we're using BLX etc on the assumption that we have v5t ops.
1459 if (!Subtarget->hasV5TOps()) return false;
1461 // Set up the argument vectors.
1462 SmallVector<Value*, 8> Args;
1463 SmallVector<unsigned, 8> ArgRegs;
1464 SmallVector<EVT, 8> ArgVTs;
1465 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1466 Args.reserve(CS.arg_size());
1467 ArgRegs.reserve(CS.arg_size());
1468 ArgVTs.reserve(CS.arg_size());
1469 ArgFlags.reserve(CS.arg_size());
1470 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1472 unsigned Arg = getRegForValue(*i);
1476 ISD::ArgFlagsTy Flags;
1477 unsigned AttrInd = i - CS.arg_begin() + 1;
1478 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1480 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1483 // FIXME: Only handle *easy* calls for now.
1484 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1485 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1486 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1487 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1490 const Type *ArgTy = (*i)->getType();
1492 if (!isTypeLegal(ArgTy, ArgVT))
1494 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1495 Flags.setOrigAlign(OriginalAlignment);
1498 ArgRegs.push_back(Arg);
1499 ArgVTs.push_back(ArgVT);
1500 ArgFlags.push_back(Flags);
1503 // Handle the arguments now that we've gotten them.
1504 SmallVector<unsigned, 4> RegArgs;
1506 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1509 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1510 // TODO: Turn this into the table of arm call ops.
1511 MachineInstrBuilder MIB;
1514 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1516 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1517 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1518 .addGlobalAddress(GV, 0, 0);
1520 // Add implicit physical register uses to the call.
1521 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1522 MIB.addReg(RegArgs[i]);
1524 // Finish off the call including any return values.
1525 SmallVector<unsigned, 4> UsedRegs;
1526 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1528 // Set all unused physreg defs as dead.
1529 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1535 // TODO: SoftFP support.
1536 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1537 // No Thumb-1 for now.
1538 if (isThumb && !AFI->isThumb2Function()) return false;
1540 switch (I->getOpcode()) {
1541 case Instruction::Load:
1542 return SelectLoad(I);
1543 case Instruction::Store:
1544 return SelectStore(I);
1545 case Instruction::Br:
1546 return SelectBranch(I);
1547 case Instruction::ICmp:
1548 case Instruction::FCmp:
1549 return SelectCmp(I);
1550 case Instruction::FPExt:
1551 return SelectFPExt(I);
1552 case Instruction::FPTrunc:
1553 return SelectFPTrunc(I);
1554 case Instruction::SIToFP:
1555 return SelectSIToFP(I);
1556 case Instruction::FPToSI:
1557 return SelectFPToSI(I);
1558 case Instruction::FAdd:
1559 return SelectBinaryOp(I, ISD::FADD);
1560 case Instruction::FSub:
1561 return SelectBinaryOp(I, ISD::FSUB);
1562 case Instruction::FMul:
1563 return SelectBinaryOp(I, ISD::FMUL);
1564 case Instruction::SDiv:
1565 return SelectSDiv(I);
1566 case Instruction::SRem:
1567 return SelectSRem(I);
1568 case Instruction::Call:
1569 return SelectCall(I);
1570 case Instruction::Select:
1571 return SelectSelect(I);
1578 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1579 // Completely untested on non-darwin.
1580 const TargetMachine &TM = funcInfo.MF->getTarget();
1581 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
1582 if (Subtarget->isTargetDarwin() && EnableARMFastISel)
1583 return new ARMFastISel(funcInfo);