1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/GetElementPtrTypeIterator.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Module.h"
43 #include "llvm/IR/Operator.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
52 extern cl::opt<bool> EnableARMLongCalls;
56 // All possible address modes, plus some.
57 typedef struct Address {
70 // Innocuous defaults for our address.
72 : BaseType(RegBase), Offset(0) {
77 class ARMFastISel final : public FastISel {
79 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
80 /// make the right decision when generating code for different targets.
81 const ARMSubtarget *Subtarget;
83 const TargetMachine &TM;
84 const TargetInstrInfo &TII;
85 const TargetLowering &TLI;
88 // Convenience variables to avoid some queries.
93 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
94 const TargetLibraryInfo *libInfo)
95 : FastISel(funcInfo, libInfo),
96 M(const_cast<Module&>(*funcInfo.Fn->getParent())),
97 TM(funcInfo.MF->getTarget()),
98 TII(*TM.getInstrInfo()),
99 TLI(*TM.getTargetLowering()) {
100 Subtarget = &TM.getSubtarget<ARMSubtarget>();
101 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
102 isThumb2 = AFI->isThumbFunction();
103 Context = &funcInfo.Fn->getContext();
106 // Code from FastISel.cpp.
108 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
109 const TargetRegisterClass *RC,
110 unsigned Op0, bool Op0IsKill);
111 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
112 const TargetRegisterClass *RC,
113 unsigned Op0, bool Op0IsKill,
114 unsigned Op1, bool Op1IsKill);
115 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
116 const TargetRegisterClass *RC,
117 unsigned Op0, bool Op0IsKill,
118 unsigned Op1, bool Op1IsKill,
119 unsigned Op2, bool Op2IsKill);
120 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
121 const TargetRegisterClass *RC,
122 unsigned Op0, bool Op0IsKill,
124 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
125 const TargetRegisterClass *RC,
126 unsigned Op0, bool Op0IsKill,
127 unsigned Op1, bool Op1IsKill,
129 unsigned FastEmitInst_i(unsigned MachineInstOpcode,
130 const TargetRegisterClass *RC,
133 // Backend specific FastISel code.
135 bool TargetSelectInstruction(const Instruction *I) override;
136 unsigned TargetMaterializeConstant(const Constant *C) override;
137 unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
138 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
139 const LoadInst *LI) override;
140 bool FastLowerArguments() override;
142 #include "ARMGenFastISel.inc"
144 // Instruction selection routines.
146 bool SelectLoad(const Instruction *I);
147 bool SelectStore(const Instruction *I);
148 bool SelectBranch(const Instruction *I);
149 bool SelectIndirectBr(const Instruction *I);
150 bool SelectCmp(const Instruction *I);
151 bool SelectFPExt(const Instruction *I);
152 bool SelectFPTrunc(const Instruction *I);
153 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
154 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
155 bool SelectIToFP(const Instruction *I, bool isSigned);
156 bool SelectFPToI(const Instruction *I, bool isSigned);
157 bool SelectDiv(const Instruction *I, bool isSigned);
158 bool SelectRem(const Instruction *I, bool isSigned);
159 bool SelectCall(const Instruction *I, const char *IntrMemName);
160 bool SelectIntrinsicCall(const IntrinsicInst &I);
161 bool SelectSelect(const Instruction *I);
162 bool SelectRet(const Instruction *I);
163 bool SelectTrunc(const Instruction *I);
164 bool SelectIntExt(const Instruction *I);
165 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
169 bool isTypeLegal(Type *Ty, MVT &VT);
170 bool isLoadTypeLegal(Type *Ty, MVT &VT);
171 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
173 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
174 unsigned Alignment = 0, bool isZExt = true,
175 bool allocReg = true);
176 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
177 unsigned Alignment = 0);
178 bool ARMComputeAddress(const Value *Obj, Address &Addr);
179 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
180 bool ARMIsMemCpySmall(uint64_t Len);
181 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
183 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
184 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
185 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
186 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
187 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
188 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
189 unsigned ARMSelectCallOp(bool UseReg);
190 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
192 const TargetLowering *getTargetLowering() { return TM.getTargetLowering(); }
194 // Call handling routines.
196 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
199 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
200 SmallVectorImpl<unsigned> &ArgRegs,
201 SmallVectorImpl<MVT> &ArgVTs,
202 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
203 SmallVectorImpl<unsigned> &RegArgs,
207 unsigned getLibcallReg(const Twine &Name);
208 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
209 const Instruction *I, CallingConv::ID CC,
210 unsigned &NumBytes, bool isVarArg);
211 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
213 // OptionalDef handling routines.
215 bool isARMNEONPred(const MachineInstr *MI);
216 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
217 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
218 void AddLoadStoreOperands(MVT VT, Address &Addr,
219 const MachineInstrBuilder &MIB,
220 unsigned Flags, bool useAM3);
223 } // end anonymous namespace
225 #include "ARMGenCallingConv.inc"
227 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
228 // we don't care about implicit defs here, just places we'll need to add a
229 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
230 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
231 if (!MI->hasOptionalDef())
234 // Look to see if our OptionalDef is defining CPSR or CCR.
235 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
236 const MachineOperand &MO = MI->getOperand(i);
237 if (!MO.isReg() || !MO.isDef()) continue;
238 if (MO.getReg() == ARM::CPSR)
244 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
245 const MCInstrDesc &MCID = MI->getDesc();
247 // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
248 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
249 AFI->isThumb2Function())
250 return MI->isPredicable();
252 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
253 if (MCID.OpInfo[i].isPredicate())
259 // If the machine is predicable go ahead and add the predicate operands, if
260 // it needs default CC operands add those.
261 // TODO: If we want to support thumb1 then we'll need to deal with optional
262 // CPSR defs that need to be added before the remaining operands. See s_cc_out
263 // for descriptions why.
264 const MachineInstrBuilder &
265 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
266 MachineInstr *MI = &*MIB;
268 // Do we use a predicate? or...
269 // Are we NEON in ARM mode and have a predicate operand? If so, I know
270 // we're not predicable but add it anyways.
271 if (isARMNEONPred(MI))
274 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
275 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
277 if (DefinesOptionalPredicate(MI, &CPSR)) {
286 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
287 const TargetRegisterClass *RC,
288 unsigned Op0, bool Op0IsKill) {
289 unsigned ResultReg = createResultReg(RC);
290 const MCInstrDesc &II = TII.get(MachineInstOpcode);
292 // Make sure the input operand is sufficiently constrained to be legal
293 // for this instruction.
294 Op0 = constrainOperandRegClass(II, Op0, 1);
295 if (II.getNumDefs() >= 1) {
296 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
297 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
300 .addReg(Op0, Op0IsKill * RegState::Kill));
301 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
302 TII.get(TargetOpcode::COPY), ResultReg)
303 .addReg(II.ImplicitDefs[0]));
308 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
309 const TargetRegisterClass *RC,
310 unsigned Op0, bool Op0IsKill,
311 unsigned Op1, bool Op1IsKill) {
312 unsigned ResultReg = createResultReg(RC);
313 const MCInstrDesc &II = TII.get(MachineInstOpcode);
315 // Make sure the input operands are sufficiently constrained to be legal
316 // for this instruction.
317 Op0 = constrainOperandRegClass(II, Op0, 1);
318 Op1 = constrainOperandRegClass(II, Op1, 2);
320 if (II.getNumDefs() >= 1) {
322 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
323 .addReg(Op0, Op0IsKill * RegState::Kill)
324 .addReg(Op1, Op1IsKill * RegState::Kill));
326 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
327 .addReg(Op0, Op0IsKill * RegState::Kill)
328 .addReg(Op1, Op1IsKill * RegState::Kill));
329 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
330 TII.get(TargetOpcode::COPY), ResultReg)
331 .addReg(II.ImplicitDefs[0]));
336 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
337 const TargetRegisterClass *RC,
338 unsigned Op0, bool Op0IsKill,
339 unsigned Op1, bool Op1IsKill,
340 unsigned Op2, bool Op2IsKill) {
341 unsigned ResultReg = createResultReg(RC);
342 const MCInstrDesc &II = TII.get(MachineInstOpcode);
344 // Make sure the input operands are sufficiently constrained to be legal
345 // for this instruction.
346 Op0 = constrainOperandRegClass(II, Op0, 1);
347 Op1 = constrainOperandRegClass(II, Op1, 2);
348 Op2 = constrainOperandRegClass(II, Op1, 3);
350 if (II.getNumDefs() >= 1) {
352 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
353 .addReg(Op0, Op0IsKill * RegState::Kill)
354 .addReg(Op1, Op1IsKill * RegState::Kill)
355 .addReg(Op2, Op2IsKill * RegState::Kill));
357 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
358 .addReg(Op0, Op0IsKill * RegState::Kill)
359 .addReg(Op1, Op1IsKill * RegState::Kill)
360 .addReg(Op2, Op2IsKill * RegState::Kill));
361 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
362 TII.get(TargetOpcode::COPY), ResultReg)
363 .addReg(II.ImplicitDefs[0]));
368 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
369 const TargetRegisterClass *RC,
370 unsigned Op0, bool Op0IsKill,
372 unsigned ResultReg = createResultReg(RC);
373 const MCInstrDesc &II = TII.get(MachineInstOpcode);
375 // Make sure the input operand is sufficiently constrained to be legal
376 // for this instruction.
377 Op0 = constrainOperandRegClass(II, Op0, 1);
378 if (II.getNumDefs() >= 1) {
380 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
381 .addReg(Op0, Op0IsKill * RegState::Kill)
384 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
385 .addReg(Op0, Op0IsKill * RegState::Kill)
387 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
388 TII.get(TargetOpcode::COPY), ResultReg)
389 .addReg(II.ImplicitDefs[0]));
394 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
395 const TargetRegisterClass *RC,
396 unsigned Op0, bool Op0IsKill,
397 unsigned Op1, bool Op1IsKill,
399 unsigned ResultReg = createResultReg(RC);
400 const MCInstrDesc &II = TII.get(MachineInstOpcode);
402 // Make sure the input operands are sufficiently constrained to be legal
403 // for this instruction.
404 Op0 = constrainOperandRegClass(II, Op0, 1);
405 Op1 = constrainOperandRegClass(II, Op1, 2);
406 if (II.getNumDefs() >= 1) {
408 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
409 .addReg(Op0, Op0IsKill * RegState::Kill)
410 .addReg(Op1, Op1IsKill * RegState::Kill)
413 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
414 .addReg(Op0, Op0IsKill * RegState::Kill)
415 .addReg(Op1, Op1IsKill * RegState::Kill)
417 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
418 TII.get(TargetOpcode::COPY), ResultReg)
419 .addReg(II.ImplicitDefs[0]));
424 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
425 const TargetRegisterClass *RC,
427 unsigned ResultReg = createResultReg(RC);
428 const MCInstrDesc &II = TII.get(MachineInstOpcode);
430 if (II.getNumDefs() >= 1) {
431 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
432 ResultReg).addImm(Imm));
434 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
436 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
437 TII.get(TargetOpcode::COPY), ResultReg)
438 .addReg(II.ImplicitDefs[0]));
443 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
444 // checks from the various callers.
445 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
446 if (VT == MVT::f64) return 0;
448 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
449 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
450 TII.get(ARM::VMOVSR), MoveReg)
455 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
456 if (VT == MVT::i64) return 0;
458 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
459 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
460 TII.get(ARM::VMOVRS), MoveReg)
465 // For double width floating point we need to materialize two constants
466 // (the high and the low) into integer registers then use a move to get
467 // the combined constant into an FP reg.
468 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
469 const APFloat Val = CFP->getValueAPF();
470 bool is64bit = VT == MVT::f64;
472 // This checks to see if we can use VFP3 instructions to materialize
473 // a constant, otherwise we have to go through the constant pool.
474 if (TLI.isFPImmLegal(Val, VT)) {
478 Imm = ARM_AM::getFP64Imm(Val);
481 Imm = ARM_AM::getFP32Imm(Val);
484 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
485 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
486 TII.get(Opc), DestReg).addImm(Imm));
490 // Require VFP2 for loading fp constants.
491 if (!Subtarget->hasVFP2()) return false;
493 // MachineConstantPool wants an explicit alignment.
494 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
496 // TODO: Figure out if this is correct.
497 Align = DL.getTypeAllocSize(CFP->getType());
499 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
500 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
501 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
503 // The extra reg is for addrmode5.
505 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
506 .addConstantPoolIndex(Idx)
511 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
513 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
516 // If we can do this in a single instruction without a constant pool entry
518 const ConstantInt *CI = cast<ConstantInt>(C);
519 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
520 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
521 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
523 unsigned ImmReg = createResultReg(RC);
524 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
525 TII.get(Opc), ImmReg)
526 .addImm(CI->getZExtValue()));
530 // Use MVN to emit negative constants.
531 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
532 unsigned Imm = (unsigned)~(CI->getSExtValue());
533 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
534 (ARM_AM::getSOImmVal(Imm) != -1);
536 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
537 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
538 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
539 TII.get(Opc), ImmReg)
545 // Load from constant pool. For now 32-bit only.
549 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
551 // MachineConstantPool wants an explicit alignment.
552 unsigned Align = DL.getPrefTypeAlignment(C->getType());
554 // TODO: Figure out if this is correct.
555 Align = DL.getTypeAllocSize(C->getType());
557 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
560 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
561 TII.get(ARM::t2LDRpci), DestReg)
562 .addConstantPoolIndex(Idx));
564 // The extra immediate is for addrmode2.
565 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
566 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
567 TII.get(ARM::LDRcp), DestReg)
568 .addConstantPoolIndex(Idx)
575 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
576 // For now 32-bit only.
577 if (VT != MVT::i32) return 0;
579 Reloc::Model RelocM = TM.getRelocationModel();
580 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
581 const TargetRegisterClass *RC = isThumb2 ?
582 (const TargetRegisterClass*)&ARM::rGPRRegClass :
583 (const TargetRegisterClass*)&ARM::GPRRegClass;
584 unsigned DestReg = createResultReg(RC);
586 // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
587 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
588 bool IsThreadLocal = GVar && GVar->isThreadLocal();
589 if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
591 // Use movw+movt when possible, it avoids constant pool entries.
592 // Non-darwin targets only support static movt relocations in FastISel.
593 if (Subtarget->useMovt() &&
594 (Subtarget->isTargetMachO() || RelocM == Reloc::Static)) {
596 unsigned char TF = 0;
597 if (Subtarget->isTargetMachO())
598 TF = ARMII::MO_NONLAZY;
602 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
605 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
608 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
609 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
611 // MachineConstantPool wants an explicit alignment.
612 unsigned Align = DL.getPrefTypeAlignment(GV->getType());
614 // TODO: Figure out if this is correct.
615 Align = DL.getTypeAllocSize(GV->getType());
618 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
619 return ARMLowerPICELF(GV, Align, VT);
622 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
623 (Subtarget->isThumb() ? 4 : 8);
624 unsigned Id = AFI->createPICLabelUId();
625 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
628 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
631 MachineInstrBuilder MIB;
633 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
634 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
635 DestReg).addConstantPoolIndex(Idx);
636 if (RelocM == Reloc::PIC_)
638 AddOptionalDefs(MIB);
640 // The extra immediate is for addrmode2.
641 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
642 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
643 TII.get(ARM::LDRcp), DestReg)
644 .addConstantPoolIndex(Idx)
646 AddOptionalDefs(MIB);
648 if (RelocM == Reloc::PIC_) {
649 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
650 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
652 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
653 DbgLoc, TII.get(Opc), NewDestReg)
656 AddOptionalDefs(MIB);
663 MachineInstrBuilder MIB;
664 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
666 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
667 TII.get(ARM::t2LDRi12), NewDestReg)
671 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
672 TII.get(ARM::LDRi12), NewDestReg)
675 DestReg = NewDestReg;
676 AddOptionalDefs(MIB);
682 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
683 EVT CEVT = TLI.getValueType(C->getType(), true);
685 // Only handle simple types.
686 if (!CEVT.isSimple()) return 0;
687 MVT VT = CEVT.getSimpleVT();
689 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
690 return ARMMaterializeFP(CFP, VT);
691 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
692 return ARMMaterializeGV(GV, VT);
693 else if (isa<ConstantInt>(C))
694 return ARMMaterializeInt(C, VT);
699 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
701 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
702 // Don't handle dynamic allocas.
703 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
706 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
708 DenseMap<const AllocaInst*, int>::iterator SI =
709 FuncInfo.StaticAllocaMap.find(AI);
711 // This will get lowered later into the correct offsets and registers
712 // via rewriteXFrameIndex.
713 if (SI != FuncInfo.StaticAllocaMap.end()) {
714 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
715 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
716 unsigned ResultReg = createResultReg(RC);
717 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
719 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
720 TII.get(Opc), ResultReg)
721 .addFrameIndex(SI->second)
729 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
730 EVT evt = TLI.getValueType(Ty, true);
732 // Only handle simple types.
733 if (evt == MVT::Other || !evt.isSimple()) return false;
734 VT = evt.getSimpleVT();
736 // Handle all legal types, i.e. a register that will directly hold this
738 return TLI.isTypeLegal(VT);
741 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
742 if (isTypeLegal(Ty, VT)) return true;
744 // If this is a type than can be sign or zero-extended to a basic operation
745 // go ahead and accept it now.
746 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
752 // Computes the address to get to an object.
753 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
754 // Some boilerplate from the X86 FastISel.
755 const User *U = nullptr;
756 unsigned Opcode = Instruction::UserOp1;
757 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
758 // Don't walk into other basic blocks unless the object is an alloca from
759 // another block, otherwise it may not have a virtual register assigned.
760 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
761 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
762 Opcode = I->getOpcode();
765 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
766 Opcode = C->getOpcode();
770 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
771 if (Ty->getAddressSpace() > 255)
772 // Fast instruction selection doesn't support the special
779 case Instruction::BitCast:
780 // Look through bitcasts.
781 return ARMComputeAddress(U->getOperand(0), Addr);
782 case Instruction::IntToPtr:
783 // Look past no-op inttoptrs.
784 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
785 return ARMComputeAddress(U->getOperand(0), Addr);
787 case Instruction::PtrToInt:
788 // Look past no-op ptrtoints.
789 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
790 return ARMComputeAddress(U->getOperand(0), Addr);
792 case Instruction::GetElementPtr: {
793 Address SavedAddr = Addr;
794 int TmpOffset = Addr.Offset;
796 // Iterate through the GEP folding the constants into offsets where
798 gep_type_iterator GTI = gep_type_begin(U);
799 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
800 i != e; ++i, ++GTI) {
801 const Value *Op = *i;
802 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
803 const StructLayout *SL = DL.getStructLayout(STy);
804 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
805 TmpOffset += SL->getElementOffset(Idx);
807 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
809 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
810 // Constant-offset addressing.
811 TmpOffset += CI->getSExtValue() * S;
814 if (canFoldAddIntoGEP(U, Op)) {
815 // A compatible add with a constant operand. Fold the constant.
817 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
818 TmpOffset += CI->getSExtValue() * S;
819 // Iterate on the other operand.
820 Op = cast<AddOperator>(Op)->getOperand(0);
824 goto unsupported_gep;
829 // Try to grab the base operand now.
830 Addr.Offset = TmpOffset;
831 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
833 // We failed, restore everything and try the other options.
839 case Instruction::Alloca: {
840 const AllocaInst *AI = cast<AllocaInst>(Obj);
841 DenseMap<const AllocaInst*, int>::iterator SI =
842 FuncInfo.StaticAllocaMap.find(AI);
843 if (SI != FuncInfo.StaticAllocaMap.end()) {
844 Addr.BaseType = Address::FrameIndexBase;
845 Addr.Base.FI = SI->second;
852 // Try to get this in a register if nothing else has worked.
853 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
854 return Addr.Base.Reg != 0;
857 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
858 bool needsLowering = false;
859 switch (VT.SimpleTy) {
860 default: llvm_unreachable("Unhandled load/store type!");
866 // Integer loads/stores handle 12-bit offsets.
867 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
868 // Handle negative offsets.
869 if (needsLowering && isThumb2)
870 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
873 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
874 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
879 // Floating point operands handle 8-bit offsets.
880 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
884 // If this is a stack pointer and the offset needs to be simplified then
885 // put the alloca address into a register, set the base type back to
886 // register and continue. This should almost never happen.
887 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
888 const TargetRegisterClass *RC = isThumb2 ?
889 (const TargetRegisterClass*)&ARM::tGPRRegClass :
890 (const TargetRegisterClass*)&ARM::GPRRegClass;
891 unsigned ResultReg = createResultReg(RC);
892 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
893 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
894 TII.get(Opc), ResultReg)
895 .addFrameIndex(Addr.Base.FI)
897 Addr.Base.Reg = ResultReg;
898 Addr.BaseType = Address::RegBase;
901 // Since the offset is too large for the load/store instruction
902 // get the reg+offset into a register.
904 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
905 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
910 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
911 const MachineInstrBuilder &MIB,
912 unsigned Flags, bool useAM3) {
913 // addrmode5 output depends on the selection dag addressing dividing the
914 // offset by 4 that it then later multiplies. Do this here as well.
915 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
918 // Frame base works a bit differently. Handle it separately.
919 if (Addr.BaseType == Address::FrameIndexBase) {
920 int FI = Addr.Base.FI;
921 int Offset = Addr.Offset;
922 MachineMemOperand *MMO =
923 FuncInfo.MF->getMachineMemOperand(
924 MachinePointerInfo::getFixedStack(FI, Offset),
926 MFI.getObjectSize(FI),
927 MFI.getObjectAlignment(FI));
928 // Now add the rest of the operands.
929 MIB.addFrameIndex(FI);
931 // ARM halfword load/stores and signed byte loads need an additional
934 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
938 MIB.addImm(Addr.Offset);
940 MIB.addMemOperand(MMO);
942 // Now add the rest of the operands.
943 MIB.addReg(Addr.Base.Reg);
945 // ARM halfword load/stores and signed byte loads need an additional
948 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
952 MIB.addImm(Addr.Offset);
955 AddOptionalDefs(MIB);
958 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
959 unsigned Alignment, bool isZExt, bool allocReg) {
962 bool needVMOV = false;
963 const TargetRegisterClass *RC;
964 switch (VT.SimpleTy) {
965 // This is mostly going to be Neon/vector support.
966 default: return false;
970 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
971 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
973 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
982 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
985 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
989 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
990 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
992 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
994 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
997 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1000 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1004 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1007 Opc = ARM::t2LDRi12;
1011 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1014 if (!Subtarget->hasVFP2()) return false;
1015 // Unaligned loads need special handling. Floats require word-alignment.
1016 if (Alignment && Alignment < 4) {
1019 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1020 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1023 RC = TLI.getRegClassFor(VT);
1027 if (!Subtarget->hasVFP2()) return false;
1028 // FIXME: Unaligned loads need special handling. Doublewords require
1030 if (Alignment && Alignment < 4)
1034 RC = TLI.getRegClassFor(VT);
1037 // Simplify this down to something we can handle.
1038 ARMSimplifyAddress(Addr, VT, useAM3);
1040 // Create the base instruction, then add the operands.
1042 ResultReg = createResultReg(RC);
1043 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1044 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1045 TII.get(Opc), ResultReg);
1046 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1048 // If we had an unaligned load of a float we've converted it to an regular
1049 // load. Now we must move from the GRP to the FP register.
1051 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1052 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1053 TII.get(ARM::VMOVSR), MoveReg)
1054 .addReg(ResultReg));
1055 ResultReg = MoveReg;
1060 bool ARMFastISel::SelectLoad(const Instruction *I) {
1061 // Atomic loads need special handling.
1062 if (cast<LoadInst>(I)->isAtomic())
1065 // Verify we have a legal type before going any further.
1067 if (!isLoadTypeLegal(I->getType(), VT))
1070 // See if we can handle this address.
1072 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1075 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1077 UpdateValueMap(I, ResultReg);
1081 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1082 unsigned Alignment) {
1084 bool useAM3 = false;
1085 switch (VT.SimpleTy) {
1086 // This is mostly going to be Neon/vector support.
1087 default: return false;
1089 unsigned Res = createResultReg(isThumb2 ?
1090 (const TargetRegisterClass*)&ARM::tGPRRegClass :
1091 (const TargetRegisterClass*)&ARM::GPRRegClass);
1092 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1093 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1094 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1096 .addReg(SrcReg).addImm(1));
1098 } // Fallthrough here.
1101 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1102 StrOpc = ARM::t2STRBi8;
1104 StrOpc = ARM::t2STRBi12;
1106 StrOpc = ARM::STRBi12;
1110 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1114 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1115 StrOpc = ARM::t2STRHi8;
1117 StrOpc = ARM::t2STRHi12;
1124 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1128 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1129 StrOpc = ARM::t2STRi8;
1131 StrOpc = ARM::t2STRi12;
1133 StrOpc = ARM::STRi12;
1137 if (!Subtarget->hasVFP2()) return false;
1138 // Unaligned stores need special handling. Floats require word-alignment.
1139 if (Alignment && Alignment < 4) {
1140 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1141 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1142 TII.get(ARM::VMOVRS), MoveReg)
1146 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1148 StrOpc = ARM::VSTRS;
1152 if (!Subtarget->hasVFP2()) return false;
1153 // FIXME: Unaligned stores need special handling. Doublewords require
1155 if (Alignment && Alignment < 4)
1158 StrOpc = ARM::VSTRD;
1161 // Simplify this down to something we can handle.
1162 ARMSimplifyAddress(Addr, VT, useAM3);
1164 // Create the base instruction, then add the operands.
1165 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1166 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1169 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1173 bool ARMFastISel::SelectStore(const Instruction *I) {
1174 Value *Op0 = I->getOperand(0);
1175 unsigned SrcReg = 0;
1177 // Atomic stores need special handling.
1178 if (cast<StoreInst>(I)->isAtomic())
1181 // Verify we have a legal type before going any further.
1183 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1186 // Get the value to be stored into a register.
1187 SrcReg = getRegForValue(Op0);
1188 if (SrcReg == 0) return false;
1190 // See if we can handle this address.
1192 if (!ARMComputeAddress(I->getOperand(1), Addr))
1195 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1200 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1202 // Needs two compares...
1203 case CmpInst::FCMP_ONE:
1204 case CmpInst::FCMP_UEQ:
1206 // AL is our "false" for now. The other two need more compares.
1208 case CmpInst::ICMP_EQ:
1209 case CmpInst::FCMP_OEQ:
1211 case CmpInst::ICMP_SGT:
1212 case CmpInst::FCMP_OGT:
1214 case CmpInst::ICMP_SGE:
1215 case CmpInst::FCMP_OGE:
1217 case CmpInst::ICMP_UGT:
1218 case CmpInst::FCMP_UGT:
1220 case CmpInst::FCMP_OLT:
1222 case CmpInst::ICMP_ULE:
1223 case CmpInst::FCMP_OLE:
1225 case CmpInst::FCMP_ORD:
1227 case CmpInst::FCMP_UNO:
1229 case CmpInst::FCMP_UGE:
1231 case CmpInst::ICMP_SLT:
1232 case CmpInst::FCMP_ULT:
1234 case CmpInst::ICMP_SLE:
1235 case CmpInst::FCMP_ULE:
1237 case CmpInst::FCMP_UNE:
1238 case CmpInst::ICMP_NE:
1240 case CmpInst::ICMP_UGE:
1242 case CmpInst::ICMP_ULT:
1247 bool ARMFastISel::SelectBranch(const Instruction *I) {
1248 const BranchInst *BI = cast<BranchInst>(I);
1249 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1250 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1252 // Simple branch support.
1254 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1256 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1257 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1259 // Get the compare predicate.
1260 // Try to take advantage of fallthrough opportunities.
1261 CmpInst::Predicate Predicate = CI->getPredicate();
1262 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1263 std::swap(TBB, FBB);
1264 Predicate = CmpInst::getInversePredicate(Predicate);
1267 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1269 // We may not handle every CC for now.
1270 if (ARMPred == ARMCC::AL) return false;
1272 // Emit the compare.
1273 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1276 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1277 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1278 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1279 FastEmitBranch(FBB, DbgLoc);
1280 FuncInfo.MBB->addSuccessor(TBB);
1283 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1285 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1286 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1287 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1288 unsigned OpReg = getRegForValue(TI->getOperand(0));
1289 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1290 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1292 .addReg(OpReg).addImm(1));
1294 unsigned CCMode = ARMCC::NE;
1295 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1296 std::swap(TBB, FBB);
1300 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1301 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1302 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1304 FastEmitBranch(FBB, DbgLoc);
1305 FuncInfo.MBB->addSuccessor(TBB);
1308 } else if (const ConstantInt *CI =
1309 dyn_cast<ConstantInt>(BI->getCondition())) {
1310 uint64_t Imm = CI->getZExtValue();
1311 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1312 FastEmitBranch(Target, DbgLoc);
1316 unsigned CmpReg = getRegForValue(BI->getCondition());
1317 if (CmpReg == 0) return false;
1319 // We've been divorced from our compare! Our block was split, and
1320 // now our compare lives in a predecessor block. We musn't
1321 // re-compare here, as the children of the compare aren't guaranteed
1322 // live across the block boundary (we *could* check for this).
1323 // Regardless, the compare has been done in the predecessor block,
1324 // and it left a value for us in a virtual register. Ergo, we test
1325 // the one-bit value left in the virtual register.
1326 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1327 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1329 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1333 unsigned CCMode = ARMCC::NE;
1334 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1335 std::swap(TBB, FBB);
1339 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1340 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1341 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1342 FastEmitBranch(FBB, DbgLoc);
1343 FuncInfo.MBB->addSuccessor(TBB);
1347 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1348 unsigned AddrReg = getRegForValue(I->getOperand(0));
1349 if (AddrReg == 0) return false;
1351 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1352 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1353 TII.get(Opc)).addReg(AddrReg));
1355 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1356 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1357 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1362 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1364 Type *Ty = Src1Value->getType();
1365 EVT SrcEVT = TLI.getValueType(Ty, true);
1366 if (!SrcEVT.isSimple()) return false;
1367 MVT SrcVT = SrcEVT.getSimpleVT();
1369 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1370 if (isFloat && !Subtarget->hasVFP2())
1373 // Check to see if the 2nd operand is a constant that we can encode directly
1376 bool UseImm = false;
1377 bool isNegativeImm = false;
1378 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1379 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1380 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1381 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1383 const APInt &CIVal = ConstInt->getValue();
1384 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1385 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1386 // then a cmn, because there is no way to represent 2147483648 as a
1387 // signed 32-bit int.
1388 if (Imm < 0 && Imm != (int)0x80000000) {
1389 isNegativeImm = true;
1392 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1393 (ARM_AM::getSOImmVal(Imm) != -1);
1395 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1396 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1397 if (ConstFP->isZero() && !ConstFP->isNegative())
1403 bool needsExt = false;
1404 switch (SrcVT.SimpleTy) {
1405 default: return false;
1406 // TODO: Verify compares.
1409 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1413 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1419 // Intentional fall-through.
1423 CmpOpc = ARM::t2CMPrr;
1425 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1428 CmpOpc = ARM::CMPrr;
1430 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1435 unsigned SrcReg1 = getRegForValue(Src1Value);
1436 if (SrcReg1 == 0) return false;
1438 unsigned SrcReg2 = 0;
1440 SrcReg2 = getRegForValue(Src2Value);
1441 if (SrcReg2 == 0) return false;
1444 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1446 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1447 if (SrcReg1 == 0) return false;
1449 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1450 if (SrcReg2 == 0) return false;
1454 const MCInstrDesc &II = TII.get(CmpOpc);
1455 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1457 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1458 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1459 .addReg(SrcReg1).addReg(SrcReg2));
1461 MachineInstrBuilder MIB;
1462 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1465 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1468 AddOptionalDefs(MIB);
1471 // For floating point we need to move the result to a comparison register
1472 // that we can then use for branches.
1473 if (Ty->isFloatTy() || Ty->isDoubleTy())
1474 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1475 TII.get(ARM::FMSTAT)));
1479 bool ARMFastISel::SelectCmp(const Instruction *I) {
1480 const CmpInst *CI = cast<CmpInst>(I);
1482 // Get the compare predicate.
1483 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1485 // We may not handle every CC for now.
1486 if (ARMPred == ARMCC::AL) return false;
1488 // Emit the compare.
1489 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1492 // Now set a register based on the comparison. Explicitly set the predicates
1494 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1495 const TargetRegisterClass *RC = isThumb2 ?
1496 (const TargetRegisterClass*)&ARM::rGPRRegClass :
1497 (const TargetRegisterClass*)&ARM::GPRRegClass;
1498 unsigned DestReg = createResultReg(RC);
1499 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1500 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1501 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1502 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
1503 .addReg(ZeroReg).addImm(1)
1504 .addImm(ARMPred).addReg(ARM::CPSR);
1506 UpdateValueMap(I, DestReg);
1510 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1511 // Make sure we have VFP and that we're extending float to double.
1512 if (!Subtarget->hasVFP2()) return false;
1514 Value *V = I->getOperand(0);
1515 if (!I->getType()->isDoubleTy() ||
1516 !V->getType()->isFloatTy()) return false;
1518 unsigned Op = getRegForValue(V);
1519 if (Op == 0) return false;
1521 unsigned Result = createResultReg(&ARM::DPRRegClass);
1522 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1523 TII.get(ARM::VCVTDS), Result)
1525 UpdateValueMap(I, Result);
1529 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1530 // Make sure we have VFP and that we're truncating double to float.
1531 if (!Subtarget->hasVFP2()) return false;
1533 Value *V = I->getOperand(0);
1534 if (!(I->getType()->isFloatTy() &&
1535 V->getType()->isDoubleTy())) return false;
1537 unsigned Op = getRegForValue(V);
1538 if (Op == 0) return false;
1540 unsigned Result = createResultReg(&ARM::SPRRegClass);
1541 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1542 TII.get(ARM::VCVTSD), Result)
1544 UpdateValueMap(I, Result);
1548 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1549 // Make sure we have VFP.
1550 if (!Subtarget->hasVFP2()) return false;
1553 Type *Ty = I->getType();
1554 if (!isTypeLegal(Ty, DstVT))
1557 Value *Src = I->getOperand(0);
1558 EVT SrcEVT = TLI.getValueType(Src->getType(), true);
1559 if (!SrcEVT.isSimple())
1561 MVT SrcVT = SrcEVT.getSimpleVT();
1562 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1565 unsigned SrcReg = getRegForValue(Src);
1566 if (SrcReg == 0) return false;
1568 // Handle sign-extension.
1569 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1570 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1571 /*isZExt*/!isSigned);
1572 if (SrcReg == 0) return false;
1575 // The conversion routine works on fp-reg to fp-reg and the operand above
1576 // was an integer, move it to the fp registers if possible.
1577 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1578 if (FP == 0) return false;
1581 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1582 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1585 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1586 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1587 TII.get(Opc), ResultReg).addReg(FP));
1588 UpdateValueMap(I, ResultReg);
1592 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1593 // Make sure we have VFP.
1594 if (!Subtarget->hasVFP2()) return false;
1597 Type *RetTy = I->getType();
1598 if (!isTypeLegal(RetTy, DstVT))
1601 unsigned Op = getRegForValue(I->getOperand(0));
1602 if (Op == 0) return false;
1605 Type *OpTy = I->getOperand(0)->getType();
1606 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1607 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1610 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1611 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1612 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1613 TII.get(Opc), ResultReg).addReg(Op));
1615 // This result needs to be in an integer register, but the conversion only
1616 // takes place in fp-regs.
1617 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1618 if (IntReg == 0) return false;
1620 UpdateValueMap(I, IntReg);
1624 bool ARMFastISel::SelectSelect(const Instruction *I) {
1626 if (!isTypeLegal(I->getType(), VT))
1629 // Things need to be register sized for register moves.
1630 if (VT != MVT::i32) return false;
1632 unsigned CondReg = getRegForValue(I->getOperand(0));
1633 if (CondReg == 0) return false;
1634 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1635 if (Op1Reg == 0) return false;
1637 // Check to see if we can use an immediate in the conditional move.
1639 bool UseImm = false;
1640 bool isNegativeImm = false;
1641 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1642 assert (VT == MVT::i32 && "Expecting an i32.");
1643 Imm = (int)ConstInt->getValue().getZExtValue();
1645 isNegativeImm = true;
1648 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1649 (ARM_AM::getSOImmVal(Imm) != -1);
1652 unsigned Op2Reg = 0;
1654 Op2Reg = getRegForValue(I->getOperand(2));
1655 if (Op2Reg == 0) return false;
1658 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1659 CondReg = constrainOperandRegClass(TII.get(CmpOpc), CondReg, 0);
1661 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
1666 const TargetRegisterClass *RC;
1668 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1669 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1671 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1673 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1675 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1677 unsigned ResultReg = createResultReg(RC);
1679 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1680 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1681 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1688 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1689 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1696 UpdateValueMap(I, ResultReg);
1700 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1702 Type *Ty = I->getType();
1703 if (!isTypeLegal(Ty, VT))
1706 // If we have integer div support we should have selected this automagically.
1707 // In case we have a real miss go ahead and return false and we'll pick
1709 if (Subtarget->hasDivide()) return false;
1711 // Otherwise emit a libcall.
1712 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1714 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1715 else if (VT == MVT::i16)
1716 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1717 else if (VT == MVT::i32)
1718 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1719 else if (VT == MVT::i64)
1720 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1721 else if (VT == MVT::i128)
1722 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1723 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1725 return ARMEmitLibcall(I, LC);
1728 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1730 Type *Ty = I->getType();
1731 if (!isTypeLegal(Ty, VT))
1734 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1736 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1737 else if (VT == MVT::i16)
1738 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1739 else if (VT == MVT::i32)
1740 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1741 else if (VT == MVT::i64)
1742 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1743 else if (VT == MVT::i128)
1744 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1745 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1747 return ARMEmitLibcall(I, LC);
1750 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1751 EVT DestVT = TLI.getValueType(I->getType(), true);
1753 // We can get here in the case when we have a binary operation on a non-legal
1754 // type and the target independent selector doesn't know how to handle it.
1755 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1759 switch (ISDOpcode) {
1760 default: return false;
1762 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1765 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1768 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1772 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1773 if (SrcReg1 == 0) return false;
1775 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1776 // in the instruction, rather then materializing the value in a register.
1777 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1778 if (SrcReg2 == 0) return false;
1780 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1781 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1782 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1783 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1784 TII.get(Opc), ResultReg)
1785 .addReg(SrcReg1).addReg(SrcReg2));
1786 UpdateValueMap(I, ResultReg);
1790 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1791 EVT FPVT = TLI.getValueType(I->getType(), true);
1792 if (!FPVT.isSimple()) return false;
1793 MVT VT = FPVT.getSimpleVT();
1795 // We can get here in the case when we want to use NEON for our fp
1796 // operations, but can't figure out how to. Just use the vfp instructions
1798 // FIXME: It'd be nice to use NEON instructions.
1799 Type *Ty = I->getType();
1800 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1801 if (isFloat && !Subtarget->hasVFP2())
1805 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1806 switch (ISDOpcode) {
1807 default: return false;
1809 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1812 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1815 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1818 unsigned Op1 = getRegForValue(I->getOperand(0));
1819 if (Op1 == 0) return false;
1821 unsigned Op2 = getRegForValue(I->getOperand(1));
1822 if (Op2 == 0) return false;
1824 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1825 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1826 TII.get(Opc), ResultReg)
1827 .addReg(Op1).addReg(Op2));
1828 UpdateValueMap(I, ResultReg);
1832 // Call Handling Code
1834 // This is largely taken directly from CCAssignFnForNode
1835 // TODO: We may not support all of this.
1836 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1841 llvm_unreachable("Unsupported calling convention");
1842 case CallingConv::Fast:
1843 if (Subtarget->hasVFP2() && !isVarArg) {
1844 if (!Subtarget->isAAPCS_ABI())
1845 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1846 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1847 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1850 case CallingConv::C:
1851 // Use target triple & subtarget features to do actual dispatch.
1852 if (Subtarget->isAAPCS_ABI()) {
1853 if (Subtarget->hasVFP2() &&
1854 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1855 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1857 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1859 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1860 case CallingConv::ARM_AAPCS_VFP:
1862 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1863 // Fall through to soft float variant, variadic functions don't
1864 // use hard floating point ABI.
1865 case CallingConv::ARM_AAPCS:
1866 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1867 case CallingConv::ARM_APCS:
1868 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1869 case CallingConv::GHC:
1871 llvm_unreachable("Can't return in GHC call convention");
1873 return CC_ARM_APCS_GHC;
1877 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1878 SmallVectorImpl<unsigned> &ArgRegs,
1879 SmallVectorImpl<MVT> &ArgVTs,
1880 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1881 SmallVectorImpl<unsigned> &RegArgs,
1885 SmallVector<CCValAssign, 16> ArgLocs;
1886 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1887 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1888 CCAssignFnForCall(CC, false, isVarArg));
1890 // Check that we can handle all of the arguments. If we can't, then bail out
1891 // now before we add code to the MBB.
1892 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1893 CCValAssign &VA = ArgLocs[i];
1894 MVT ArgVT = ArgVTs[VA.getValNo()];
1896 // We don't handle NEON/vector parameters yet.
1897 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1900 // Now copy/store arg to correct locations.
1901 if (VA.isRegLoc() && !VA.needsCustom()) {
1903 } else if (VA.needsCustom()) {
1904 // TODO: We need custom lowering for vector (v2f64) args.
1905 if (VA.getLocVT() != MVT::f64 ||
1906 // TODO: Only handle register args for now.
1907 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1910 switch (ArgVT.SimpleTy) {
1919 if (!Subtarget->hasVFP2())
1923 if (!Subtarget->hasVFP2())
1930 // At the point, we are able to handle the call's arguments in fast isel.
1932 // Get a count of how many bytes are to be pushed on the stack.
1933 NumBytes = CCInfo.getNextStackOffset();
1935 // Issue CALLSEQ_START
1936 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1937 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1938 TII.get(AdjStackDown))
1941 // Process the args.
1942 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1943 CCValAssign &VA = ArgLocs[i];
1944 unsigned Arg = ArgRegs[VA.getValNo()];
1945 MVT ArgVT = ArgVTs[VA.getValNo()];
1947 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1948 "We don't handle NEON/vector parameters yet.");
1950 // Handle arg promotion, etc.
1951 switch (VA.getLocInfo()) {
1952 case CCValAssign::Full: break;
1953 case CCValAssign::SExt: {
1954 MVT DestVT = VA.getLocVT();
1955 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1956 assert (Arg != 0 && "Failed to emit a sext");
1960 case CCValAssign::AExt:
1961 // Intentional fall-through. Handle AExt and ZExt.
1962 case CCValAssign::ZExt: {
1963 MVT DestVT = VA.getLocVT();
1964 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1965 assert (Arg != 0 && "Failed to emit a zext");
1969 case CCValAssign::BCvt: {
1970 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1971 /*TODO: Kill=*/false);
1972 assert(BC != 0 && "Failed to emit a bitcast!");
1974 ArgVT = VA.getLocVT();
1977 default: llvm_unreachable("Unknown arg promotion!");
1980 // Now copy/store arg to correct locations.
1981 if (VA.isRegLoc() && !VA.needsCustom()) {
1982 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1983 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
1984 RegArgs.push_back(VA.getLocReg());
1985 } else if (VA.needsCustom()) {
1986 // TODO: We need custom lowering for vector (v2f64) args.
1987 assert(VA.getLocVT() == MVT::f64 &&
1988 "Custom lowering for v2f64 args not available");
1990 CCValAssign &NextVA = ArgLocs[++i];
1992 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
1993 "We only handle register args!");
1995 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1996 TII.get(ARM::VMOVRRD), VA.getLocReg())
1997 .addReg(NextVA.getLocReg(), RegState::Define)
1999 RegArgs.push_back(VA.getLocReg());
2000 RegArgs.push_back(NextVA.getLocReg());
2002 assert(VA.isMemLoc());
2003 // Need to store on the stack.
2005 Addr.BaseType = Address::RegBase;
2006 Addr.Base.Reg = ARM::SP;
2007 Addr.Offset = VA.getLocMemOffset();
2009 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2010 assert(EmitRet && "Could not emit a store for argument!");
2017 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2018 const Instruction *I, CallingConv::ID CC,
2019 unsigned &NumBytes, bool isVarArg) {
2020 // Issue CALLSEQ_END
2021 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2022 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2023 TII.get(AdjStackUp))
2024 .addImm(NumBytes).addImm(0));
2026 // Now the return value.
2027 if (RetVT != MVT::isVoid) {
2028 SmallVector<CCValAssign, 16> RVLocs;
2029 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2030 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2032 // Copy all of the result registers out of their specified physreg.
2033 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2034 // For this move we copy into two registers and then move into the
2035 // double fp reg we want.
2036 MVT DestVT = RVLocs[0].getValVT();
2037 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2038 unsigned ResultReg = createResultReg(DstRC);
2039 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2040 TII.get(ARM::VMOVDRR), ResultReg)
2041 .addReg(RVLocs[0].getLocReg())
2042 .addReg(RVLocs[1].getLocReg()));
2044 UsedRegs.push_back(RVLocs[0].getLocReg());
2045 UsedRegs.push_back(RVLocs[1].getLocReg());
2047 // Finally update the result.
2048 UpdateValueMap(I, ResultReg);
2050 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2051 MVT CopyVT = RVLocs[0].getValVT();
2053 // Special handling for extended integers.
2054 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2057 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2059 unsigned ResultReg = createResultReg(DstRC);
2060 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2061 TII.get(TargetOpcode::COPY),
2062 ResultReg).addReg(RVLocs[0].getLocReg());
2063 UsedRegs.push_back(RVLocs[0].getLocReg());
2065 // Finally update the result.
2066 UpdateValueMap(I, ResultReg);
2073 bool ARMFastISel::SelectRet(const Instruction *I) {
2074 const ReturnInst *Ret = cast<ReturnInst>(I);
2075 const Function &F = *I->getParent()->getParent();
2077 if (!FuncInfo.CanLowerReturn)
2080 // Build a list of return value registers.
2081 SmallVector<unsigned, 4> RetRegs;
2083 CallingConv::ID CC = F.getCallingConv();
2084 if (Ret->getNumOperands() > 0) {
2085 SmallVector<ISD::OutputArg, 4> Outs;
2086 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
2088 // Analyze operands of the call, assigning locations to each operand.
2089 SmallVector<CCValAssign, 16> ValLocs;
2090 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
2091 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2094 const Value *RV = Ret->getOperand(0);
2095 unsigned Reg = getRegForValue(RV);
2099 // Only handle a single return value for now.
2100 if (ValLocs.size() != 1)
2103 CCValAssign &VA = ValLocs[0];
2105 // Don't bother handling odd stuff for now.
2106 if (VA.getLocInfo() != CCValAssign::Full)
2108 // Only handle register returns for now.
2112 unsigned SrcReg = Reg + VA.getValNo();
2113 EVT RVEVT = TLI.getValueType(RV->getType());
2114 if (!RVEVT.isSimple()) return false;
2115 MVT RVVT = RVEVT.getSimpleVT();
2116 MVT DestVT = VA.getValVT();
2117 // Special handling for extended integers.
2118 if (RVVT != DestVT) {
2119 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2122 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2124 // Perform extension if flagged as either zext or sext. Otherwise, do
2126 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2127 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2128 if (SrcReg == 0) return false;
2133 unsigned DstReg = VA.getLocReg();
2134 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2135 // Avoid a cross-class copy. This is very unlikely.
2136 if (!SrcRC->contains(DstReg))
2138 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2139 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2141 // Add register to return instruction.
2142 RetRegs.push_back(VA.getLocReg());
2145 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2146 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2148 AddOptionalDefs(MIB);
2149 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2150 MIB.addReg(RetRegs[i], RegState::Implicit);
2154 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2156 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2158 return isThumb2 ? ARM::tBL : ARM::BL;
2161 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2162 // Manually compute the global's type to avoid building it when unnecessary.
2163 Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2164 EVT LCREVT = TLI.getValueType(GVTy);
2165 if (!LCREVT.isSimple()) return 0;
2167 GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
2168 GlobalValue::ExternalLinkage, nullptr,
2170 assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2171 return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2174 // A quick function that will emit a call for a named libcall in F with the
2175 // vector of passed arguments for the Instruction in I. We can assume that we
2176 // can emit a call for any libcall we can produce. This is an abridged version
2177 // of the full call infrastructure since we won't need to worry about things
2178 // like computed function pointers or strange arguments at call sites.
2179 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2181 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2182 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2184 // Handle *simple* calls for now.
2185 Type *RetTy = I->getType();
2187 if (RetTy->isVoidTy())
2188 RetVT = MVT::isVoid;
2189 else if (!isTypeLegal(RetTy, RetVT))
2192 // Can't handle non-double multi-reg retvals.
2193 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2194 SmallVector<CCValAssign, 16> RVLocs;
2195 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
2196 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2197 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2201 // Set up the argument vectors.
2202 SmallVector<Value*, 8> Args;
2203 SmallVector<unsigned, 8> ArgRegs;
2204 SmallVector<MVT, 8> ArgVTs;
2205 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2206 Args.reserve(I->getNumOperands());
2207 ArgRegs.reserve(I->getNumOperands());
2208 ArgVTs.reserve(I->getNumOperands());
2209 ArgFlags.reserve(I->getNumOperands());
2210 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2211 Value *Op = I->getOperand(i);
2212 unsigned Arg = getRegForValue(Op);
2213 if (Arg == 0) return false;
2215 Type *ArgTy = Op->getType();
2217 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2219 ISD::ArgFlagsTy Flags;
2220 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2221 Flags.setOrigAlign(OriginalAlignment);
2224 ArgRegs.push_back(Arg);
2225 ArgVTs.push_back(ArgVT);
2226 ArgFlags.push_back(Flags);
2229 // Handle the arguments now that we've gotten them.
2230 SmallVector<unsigned, 4> RegArgs;
2232 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2233 RegArgs, CC, NumBytes, false))
2236 unsigned CalleeReg = 0;
2237 if (EnableARMLongCalls) {
2238 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2239 if (CalleeReg == 0) return false;
2243 unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
2244 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2245 DbgLoc, TII.get(CallOpc));
2246 // BL / BLX don't take a predicate, but tBL / tBLX do.
2248 AddDefaultPred(MIB);
2249 if (EnableARMLongCalls)
2250 MIB.addReg(CalleeReg);
2252 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2254 // Add implicit physical register uses to the call.
2255 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2256 MIB.addReg(RegArgs[i], RegState::Implicit);
2258 // Add a register mask with the call-preserved registers.
2259 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2260 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2262 // Finish off the call including any return values.
2263 SmallVector<unsigned, 4> UsedRegs;
2264 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2266 // Set all unused physreg defs as dead.
2267 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2272 bool ARMFastISel::SelectCall(const Instruction *I,
2273 const char *IntrMemName = nullptr) {
2274 const CallInst *CI = cast<CallInst>(I);
2275 const Value *Callee = CI->getCalledValue();
2277 // Can't handle inline asm.
2278 if (isa<InlineAsm>(Callee)) return false;
2280 // Allow SelectionDAG isel to handle tail calls.
2281 if (CI->isTailCall()) return false;
2283 // Check the calling convention.
2284 ImmutableCallSite CS(CI);
2285 CallingConv::ID CC = CS.getCallingConv();
2287 // TODO: Avoid some calling conventions?
2289 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2290 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2291 bool isVarArg = FTy->isVarArg();
2293 // Handle *simple* calls for now.
2294 Type *RetTy = I->getType();
2296 if (RetTy->isVoidTy())
2297 RetVT = MVT::isVoid;
2298 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2299 RetVT != MVT::i8 && RetVT != MVT::i1)
2302 // Can't handle non-double multi-reg retvals.
2303 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2304 RetVT != MVT::i16 && RetVT != MVT::i32) {
2305 SmallVector<CCValAssign, 16> RVLocs;
2306 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2307 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2308 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2312 // Set up the argument vectors.
2313 SmallVector<Value*, 8> Args;
2314 SmallVector<unsigned, 8> ArgRegs;
2315 SmallVector<MVT, 8> ArgVTs;
2316 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2317 unsigned arg_size = CS.arg_size();
2318 Args.reserve(arg_size);
2319 ArgRegs.reserve(arg_size);
2320 ArgVTs.reserve(arg_size);
2321 ArgFlags.reserve(arg_size);
2322 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2324 // If we're lowering a memory intrinsic instead of a regular call, skip the
2325 // last two arguments, which shouldn't be passed to the underlying function.
2326 if (IntrMemName && e-i <= 2)
2329 ISD::ArgFlagsTy Flags;
2330 unsigned AttrInd = i - CS.arg_begin() + 1;
2331 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2333 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2336 // FIXME: Only handle *easy* calls for now.
2337 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2338 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2339 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2340 CS.paramHasAttr(AttrInd, Attribute::ByVal))
2343 Type *ArgTy = (*i)->getType();
2345 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2349 unsigned Arg = getRegForValue(*i);
2353 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2354 Flags.setOrigAlign(OriginalAlignment);
2357 ArgRegs.push_back(Arg);
2358 ArgVTs.push_back(ArgVT);
2359 ArgFlags.push_back(Flags);
2362 // Handle the arguments now that we've gotten them.
2363 SmallVector<unsigned, 4> RegArgs;
2365 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2366 RegArgs, CC, NumBytes, isVarArg))
2369 bool UseReg = false;
2370 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2371 if (!GV || EnableARMLongCalls) UseReg = true;
2373 unsigned CalleeReg = 0;
2376 CalleeReg = getLibcallReg(IntrMemName);
2378 CalleeReg = getRegForValue(Callee);
2380 if (CalleeReg == 0) return false;
2384 unsigned CallOpc = ARMSelectCallOp(UseReg);
2385 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2386 DbgLoc, TII.get(CallOpc));
2388 unsigned char OpFlags = 0;
2390 // Add MO_PLT for global address or external symbol in the PIC relocation
2392 if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_)
2393 OpFlags = ARMII::MO_PLT;
2395 // ARM calls don't take a predicate, but tBL / tBLX do.
2397 AddDefaultPred(MIB);
2399 MIB.addReg(CalleeReg);
2400 else if (!IntrMemName)
2401 MIB.addGlobalAddress(GV, 0, OpFlags);
2403 MIB.addExternalSymbol(IntrMemName, OpFlags);
2405 // Add implicit physical register uses to the call.
2406 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2407 MIB.addReg(RegArgs[i], RegState::Implicit);
2409 // Add a register mask with the call-preserved registers.
2410 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2411 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2413 // Finish off the call including any return values.
2414 SmallVector<unsigned, 4> UsedRegs;
2415 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2418 // Set all unused physreg defs as dead.
2419 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2424 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2428 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2429 uint64_t Len, unsigned Alignment) {
2430 // Make sure we don't bloat code by inlining very large memcpy's.
2431 if (!ARMIsMemCpySmall(Len))
2436 if (!Alignment || Alignment >= 4) {
2442 assert (Len == 1 && "Expected a length of 1!");
2446 // Bound based on alignment.
2447 if (Len >= 2 && Alignment == 2)
2456 RV = ARMEmitLoad(VT, ResultReg, Src);
2457 assert (RV == true && "Should be able to handle this load.");
2458 RV = ARMEmitStore(VT, ResultReg, Dest);
2459 assert (RV == true && "Should be able to handle this store.");
2462 unsigned Size = VT.getSizeInBits()/8;
2464 Dest.Offset += Size;
2471 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2472 // FIXME: Handle more intrinsics.
2473 switch (I.getIntrinsicID()) {
2474 default: return false;
2475 case Intrinsic::frameaddress: {
2476 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2477 MFI->setFrameAddressIsTaken(true);
2480 const TargetRegisterClass *RC;
2482 LdrOpc = ARM::t2LDRi12;
2483 RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2485 LdrOpc = ARM::LDRi12;
2486 RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2489 const ARMBaseRegisterInfo *RegInfo =
2490 static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
2491 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2492 unsigned SrcReg = FramePtr;
2494 // Recursively load frame address
2500 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2502 DestReg = createResultReg(RC);
2503 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2504 TII.get(LdrOpc), DestReg)
2505 .addReg(SrcReg).addImm(0));
2508 UpdateValueMap(&I, SrcReg);
2511 case Intrinsic::memcpy:
2512 case Intrinsic::memmove: {
2513 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2514 // Don't handle volatile.
2515 if (MTI.isVolatile())
2518 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2519 // we would emit dead code because we don't currently handle memmoves.
2520 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2521 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2522 // Small memcpy's are common enough that we want to do them without a call
2524 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2525 if (ARMIsMemCpySmall(Len)) {
2527 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2528 !ARMComputeAddress(MTI.getRawSource(), Src))
2530 unsigned Alignment = MTI.getAlignment();
2531 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2536 if (!MTI.getLength()->getType()->isIntegerTy(32))
2539 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2542 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2543 return SelectCall(&I, IntrMemName);
2545 case Intrinsic::memset: {
2546 const MemSetInst &MSI = cast<MemSetInst>(I);
2547 // Don't handle volatile.
2548 if (MSI.isVolatile())
2551 if (!MSI.getLength()->getType()->isIntegerTy(32))
2554 if (MSI.getDestAddressSpace() > 255)
2557 return SelectCall(&I, "memset");
2559 case Intrinsic::trap: {
2560 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
2561 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2567 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2568 // The high bits for a type smaller than the register size are assumed to be
2570 Value *Op = I->getOperand(0);
2573 SrcVT = TLI.getValueType(Op->getType(), true);
2574 DestVT = TLI.getValueType(I->getType(), true);
2576 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2578 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2581 unsigned SrcReg = getRegForValue(Op);
2582 if (!SrcReg) return false;
2584 // Because the high bits are undefined, a truncate doesn't generate
2586 UpdateValueMap(I, SrcReg);
2590 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2592 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2594 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2597 // Table of which combinations can be emitted as a single instruction,
2598 // and which will require two.
2599 static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2601 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2602 // ext: s z s z s z s z
2603 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2604 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2605 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2608 // Target registers for:
2609 // - For ARM can never be PC.
2610 // - For 16-bit Thumb are restricted to lower 8 registers.
2611 // - For 32-bit Thumb are restricted to non-SP and non-PC.
2612 static const TargetRegisterClass *RCTbl[2][2] = {
2613 // Instructions: Two Single
2614 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2615 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2618 // Table governing the instruction(s) to be emitted.
2619 static const struct InstructionTable {
2621 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2622 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2623 uint32_t Imm : 8; // All instructions have either a shift or a mask.
2624 } IT[2][2][3][2] = {
2625 { // Two instructions (first is left shift, second is in this table).
2626 { // ARM Opc S Shift Imm
2627 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2628 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2629 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2630 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2631 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2632 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2634 { // Thumb Opc S Shift Imm
2635 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2636 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2637 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2638 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2639 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2640 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2643 { // Single instruction.
2644 { // ARM Opc S Shift Imm
2645 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2646 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2647 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2648 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2649 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2650 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2652 { // Thumb Opc S Shift Imm
2653 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2654 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2655 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2656 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2657 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2658 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2663 unsigned SrcBits = SrcVT.getSizeInBits();
2664 unsigned DestBits = DestVT.getSizeInBits();
2666 assert((SrcBits < DestBits) && "can only extend to larger types");
2667 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2668 "other sizes unimplemented");
2669 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2670 "other sizes unimplemented");
2672 bool hasV6Ops = Subtarget->hasV6Ops();
2673 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2674 assert((Bitness < 3) && "sanity-check table bounds");
2676 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2677 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2678 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2679 unsigned Opc = ITP->Opc;
2680 assert(ARM::KILL != Opc && "Invalid table entry");
2681 unsigned hasS = ITP->hasS;
2682 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2683 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2684 "only MOVsi has shift operand addressing mode");
2685 unsigned Imm = ITP->Imm;
2687 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2688 bool setsCPSR = &ARM::tGPRRegClass == RC;
2689 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2691 // MOVsi encodes shift and immediate in shift operand addressing mode.
2692 // The following condition has the same value when emitting two
2693 // instruction sequences: both are shifts.
2694 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2696 // Either one or two instructions are emitted.
2697 // They're always of the form:
2699 // CPSR is set only by 16-bit Thumb instructions.
2700 // Predicate, if any, is AL.
2701 // S bit, if available, is always 0.
2702 // When two are emitted the first's result will feed as the second's input,
2703 // that value is then dead.
2704 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2705 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2706 ResultReg = createResultReg(RC);
2707 bool isLsl = (0 == Instr) && !isSingleInstr;
2708 unsigned Opcode = isLsl ? LSLOpc : Opc;
2709 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2710 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2711 bool isKill = 1 == Instr;
2712 MachineInstrBuilder MIB = BuildMI(
2713 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2715 MIB.addReg(ARM::CPSR, RegState::Define);
2716 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2717 AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
2720 // Second instruction consumes the first's result.
2727 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2728 // On ARM, in general, integer casts don't involve legal types; this code
2729 // handles promotable integers.
2730 Type *DestTy = I->getType();
2731 Value *Src = I->getOperand(0);
2732 Type *SrcTy = Src->getType();
2734 bool isZExt = isa<ZExtInst>(I);
2735 unsigned SrcReg = getRegForValue(Src);
2736 if (!SrcReg) return false;
2738 EVT SrcEVT, DestEVT;
2739 SrcEVT = TLI.getValueType(SrcTy, true);
2740 DestEVT = TLI.getValueType(DestTy, true);
2741 if (!SrcEVT.isSimple()) return false;
2742 if (!DestEVT.isSimple()) return false;
2744 MVT SrcVT = SrcEVT.getSimpleVT();
2745 MVT DestVT = DestEVT.getSimpleVT();
2746 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2747 if (ResultReg == 0) return false;
2748 UpdateValueMap(I, ResultReg);
2752 bool ARMFastISel::SelectShift(const Instruction *I,
2753 ARM_AM::ShiftOpc ShiftTy) {
2754 // We handle thumb2 mode by target independent selector
2755 // or SelectionDAG ISel.
2759 // Only handle i32 now.
2760 EVT DestVT = TLI.getValueType(I->getType(), true);
2761 if (DestVT != MVT::i32)
2764 unsigned Opc = ARM::MOVsr;
2766 Value *Src2Value = I->getOperand(1);
2767 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2768 ShiftImm = CI->getZExtValue();
2770 // Fall back to selection DAG isel if the shift amount
2771 // is zero or greater than the width of the value type.
2772 if (ShiftImm == 0 || ShiftImm >=32)
2778 Value *Src1Value = I->getOperand(0);
2779 unsigned Reg1 = getRegForValue(Src1Value);
2780 if (Reg1 == 0) return false;
2783 if (Opc == ARM::MOVsr) {
2784 Reg2 = getRegForValue(Src2Value);
2785 if (Reg2 == 0) return false;
2788 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2789 if(ResultReg == 0) return false;
2791 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2792 TII.get(Opc), ResultReg)
2795 if (Opc == ARM::MOVsi)
2796 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2797 else if (Opc == ARM::MOVsr) {
2799 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2802 AddOptionalDefs(MIB);
2803 UpdateValueMap(I, ResultReg);
2807 // TODO: SoftFP support.
2808 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2810 switch (I->getOpcode()) {
2811 case Instruction::Load:
2812 return SelectLoad(I);
2813 case Instruction::Store:
2814 return SelectStore(I);
2815 case Instruction::Br:
2816 return SelectBranch(I);
2817 case Instruction::IndirectBr:
2818 return SelectIndirectBr(I);
2819 case Instruction::ICmp:
2820 case Instruction::FCmp:
2821 return SelectCmp(I);
2822 case Instruction::FPExt:
2823 return SelectFPExt(I);
2824 case Instruction::FPTrunc:
2825 return SelectFPTrunc(I);
2826 case Instruction::SIToFP:
2827 return SelectIToFP(I, /*isSigned*/ true);
2828 case Instruction::UIToFP:
2829 return SelectIToFP(I, /*isSigned*/ false);
2830 case Instruction::FPToSI:
2831 return SelectFPToI(I, /*isSigned*/ true);
2832 case Instruction::FPToUI:
2833 return SelectFPToI(I, /*isSigned*/ false);
2834 case Instruction::Add:
2835 return SelectBinaryIntOp(I, ISD::ADD);
2836 case Instruction::Or:
2837 return SelectBinaryIntOp(I, ISD::OR);
2838 case Instruction::Sub:
2839 return SelectBinaryIntOp(I, ISD::SUB);
2840 case Instruction::FAdd:
2841 return SelectBinaryFPOp(I, ISD::FADD);
2842 case Instruction::FSub:
2843 return SelectBinaryFPOp(I, ISD::FSUB);
2844 case Instruction::FMul:
2845 return SelectBinaryFPOp(I, ISD::FMUL);
2846 case Instruction::SDiv:
2847 return SelectDiv(I, /*isSigned*/ true);
2848 case Instruction::UDiv:
2849 return SelectDiv(I, /*isSigned*/ false);
2850 case Instruction::SRem:
2851 return SelectRem(I, /*isSigned*/ true);
2852 case Instruction::URem:
2853 return SelectRem(I, /*isSigned*/ false);
2854 case Instruction::Call:
2855 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2856 return SelectIntrinsicCall(*II);
2857 return SelectCall(I);
2858 case Instruction::Select:
2859 return SelectSelect(I);
2860 case Instruction::Ret:
2861 return SelectRet(I);
2862 case Instruction::Trunc:
2863 return SelectTrunc(I);
2864 case Instruction::ZExt:
2865 case Instruction::SExt:
2866 return SelectIntExt(I);
2867 case Instruction::Shl:
2868 return SelectShift(I, ARM_AM::lsl);
2869 case Instruction::LShr:
2870 return SelectShift(I, ARM_AM::lsr);
2871 case Instruction::AShr:
2872 return SelectShift(I, ARM_AM::asr);
2879 // This table describes sign- and zero-extend instructions which can be
2880 // folded into a preceding load. All of these extends have an immediate
2881 // (sometimes a mask and sometimes a shift) that's applied after
2883 const struct FoldableLoadExtendsStruct {
2884 uint16_t Opc[2]; // ARM, Thumb.
2885 uint8_t ExpectedImm;
2887 uint8_t ExpectedVT : 7;
2888 } FoldableLoadExtends[] = {
2889 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2890 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2891 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2892 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2893 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2897 /// \brief The specified machine instr operand is a vreg, and that
2898 /// vreg is being provided by the specified load instruction. If possible,
2899 /// try to fold the load as an operand to the instruction, returning true if
2901 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2902 const LoadInst *LI) {
2903 // Verify we have a legal type before going any further.
2905 if (!isLoadTypeLegal(LI->getType(), VT))
2908 // Combine load followed by zero- or sign-extend.
2909 // ldrb r1, [r0] ldrb r1, [r0]
2911 // mov r3, r2 mov r3, r1
2912 if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2914 const uint64_t Imm = MI->getOperand(2).getImm();
2918 for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends);
2920 if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&
2921 (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm &&
2922 MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) {
2924 isZExt = FoldableLoadExtends[i].isZExt;
2927 if (!Found) return false;
2929 // See if we can handle this address.
2931 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2933 unsigned ResultReg = MI->getOperand(0).getReg();
2934 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2936 MI->eraseFromParent();
2940 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2941 unsigned Align, MVT VT) {
2942 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2943 ARMConstantPoolConstant *CPV =
2944 ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2945 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
2948 unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
2951 DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0);
2952 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2953 TII.get(ARM::t2LDRpci), DestReg1)
2954 .addConstantPoolIndex(Idx));
2955 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
2957 // The extra immediate is for addrmode2.
2958 DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0);
2959 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2960 DbgLoc, TII.get(ARM::LDRcp), DestReg1)
2961 .addConstantPoolIndex(Idx).addImm(0));
2962 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
2965 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
2966 if (GlobalBaseReg == 0) {
2967 GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
2968 AFI->setGlobalBaseReg(GlobalBaseReg);
2971 unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
2972 DestReg2 = constrainOperandRegClass(TII.get(Opc), DestReg2, 0);
2973 DestReg1 = constrainOperandRegClass(TII.get(Opc), DestReg1, 1);
2974 GlobalBaseReg = constrainOperandRegClass(TII.get(Opc), GlobalBaseReg, 2);
2975 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2976 DbgLoc, TII.get(Opc), DestReg2)
2978 .addReg(GlobalBaseReg);
2981 AddOptionalDefs(MIB);
2986 bool ARMFastISel::FastLowerArguments() {
2987 if (!FuncInfo.CanLowerReturn)
2990 const Function *F = FuncInfo.Fn;
2994 CallingConv::ID CC = F->getCallingConv();
2998 case CallingConv::Fast:
2999 case CallingConv::C:
3000 case CallingConv::ARM_AAPCS_VFP:
3001 case CallingConv::ARM_AAPCS:
3002 case CallingConv::ARM_APCS:
3006 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3007 // which are passed in r0 - r3.
3009 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3010 I != E; ++I, ++Idx) {
3014 if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
3015 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
3016 F->getAttributes().hasAttribute(Idx, Attribute::ByVal))
3019 Type *ArgTy = I->getType();
3020 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3023 EVT ArgVT = TLI.getValueType(ArgTy);
3024 if (!ArgVT.isSimple()) return false;
3025 switch (ArgVT.getSimpleVT().SimpleTy) {
3036 static const uint16_t GPRArgRegs[] = {
3037 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3040 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3042 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3043 I != E; ++I, ++Idx) {
3044 unsigned SrcReg = GPRArgRegs[Idx];
3045 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3046 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3047 // Without this, EmitLiveInCopies may eliminate the livein if its only
3048 // use is a bitcast (which isn't turned into an instruction).
3049 unsigned ResultReg = createResultReg(RC);
3050 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3051 TII.get(TargetOpcode::COPY),
3052 ResultReg).addReg(DstReg, getKillRegState(true));
3053 UpdateValueMap(I, ResultReg);
3060 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3061 const TargetLibraryInfo *libInfo) {
3062 const TargetMachine &TM = funcInfo.MF->getTarget();
3064 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
3065 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
3066 bool UseFastISel = false;
3067 UseFastISel |= Subtarget->isTargetMachO() && !Subtarget->isThumb1Only();
3068 UseFastISel |= Subtarget->isTargetLinux() && !Subtarget->isThumb();
3069 UseFastISel |= Subtarget->isTargetNaCl() && !Subtarget->isThumb();
3072 // iOS always has a FP for backtracking, force other targets
3073 // to keep their FP when doing FastISel. The emitted code is
3074 // currently superior, and in cases like test-suite's lencod
3075 // FastISel isn't quite correct when FP is eliminated.
3076 TM.Options.NoFramePointerElim = true;
3077 return new ARMFastISel(funcInfo, libInfo);