1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMRegisterInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/Analysis.h"
27 #include "llvm/CodeGen/FastISel.h"
28 #include "llvm/CodeGen/FunctionLoweringInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineConstantPool.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/Support/CallSite.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/GetElementPtrTypeIterator.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
46 EnableARMFastISel("arm-fast-isel",
47 cl::desc("Turn on experimental ARM fast-isel support"),
48 cl::init(false), cl::Hidden);
52 class ARMFastISel : public FastISel {
54 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
55 /// make the right decision when generating code for different targets.
56 const ARMSubtarget *Subtarget;
57 const TargetMachine &TM;
58 const TargetInstrInfo &TII;
59 const TargetLowering &TLI;
60 const ARMFunctionInfo *AFI;
62 // Convenience variable to avoid checking all the time.
66 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
68 TM(funcInfo.MF->getTarget()),
69 TII(*TM.getInstrInfo()),
70 TLI(*TM.getTargetLowering()) {
71 Subtarget = &TM.getSubtarget<ARMSubtarget>();
72 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
73 isThumb = AFI->isThumbFunction();
76 // Code from FastISel.cpp.
77 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
78 const TargetRegisterClass *RC);
79 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
80 const TargetRegisterClass *RC,
81 unsigned Op0, bool Op0IsKill);
82 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
83 const TargetRegisterClass *RC,
84 unsigned Op0, bool Op0IsKill,
85 unsigned Op1, bool Op1IsKill);
86 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
87 const TargetRegisterClass *RC,
88 unsigned Op0, bool Op0IsKill,
90 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
91 const TargetRegisterClass *RC,
92 unsigned Op0, bool Op0IsKill,
93 const ConstantFP *FPImm);
94 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
95 const TargetRegisterClass *RC,
97 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
98 const TargetRegisterClass *RC,
99 unsigned Op0, bool Op0IsKill,
100 unsigned Op1, bool Op1IsKill,
102 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
103 unsigned Op0, bool Op0IsKill,
106 // Backend specific FastISel code.
107 virtual bool TargetSelectInstruction(const Instruction *I);
108 virtual unsigned TargetMaterializeConstant(const Constant *C);
110 #include "ARMGenFastISel.inc"
112 // Instruction selection routines.
113 virtual bool ARMSelectLoad(const Instruction *I);
114 virtual bool ARMSelectStore(const Instruction *I);
115 virtual bool ARMSelectBranch(const Instruction *I);
116 virtual bool ARMSelectCmp(const Instruction *I);
117 virtual bool ARMSelectFPExt(const Instruction *I);
118 virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
119 virtual bool ARMSelectSIToFP(const Instruction *I);
120 virtual bool ARMSelectFPToSI(const Instruction *I);
124 bool isTypeLegal(const Type *Ty, EVT &VT);
125 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
126 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
127 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
128 bool ARMLoadAlloca(const Instruction *I, EVT VT);
129 bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
130 bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
131 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
132 unsigned ARMMaterializeInt(const Constant *C);
134 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
135 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
138 } // end anonymous namespace
140 // #include "ARMGenCallingConv.inc"
142 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
143 // we don't care about implicit defs here, just places we'll need to add a
144 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
145 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
146 const TargetInstrDesc &TID = MI->getDesc();
147 if (!TID.hasOptionalDef())
150 // Look to see if our OptionalDef is defining CPSR or CCR.
151 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
152 const MachineOperand &MO = MI->getOperand(i);
153 if (!MO.isReg() || !MO.isDef()) continue;
154 if (MO.getReg() == ARM::CPSR)
160 // If the machine is predicable go ahead and add the predicate operands, if
161 // it needs default CC operands add those.
162 const MachineInstrBuilder &
163 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
164 MachineInstr *MI = &*MIB;
166 // Do we use a predicate?
167 if (TII.isPredicable(MI))
170 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
171 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
173 if (DefinesOptionalPredicate(MI, &CPSR)) {
182 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
183 const TargetRegisterClass* RC) {
184 unsigned ResultReg = createResultReg(RC);
185 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
187 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
191 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
192 const TargetRegisterClass *RC,
193 unsigned Op0, bool Op0IsKill) {
194 unsigned ResultReg = createResultReg(RC);
195 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
197 if (II.getNumDefs() >= 1)
198 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
199 .addReg(Op0, Op0IsKill * RegState::Kill));
201 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
202 .addReg(Op0, Op0IsKill * RegState::Kill));
203 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
204 TII.get(TargetOpcode::COPY), ResultReg)
205 .addReg(II.ImplicitDefs[0]));
210 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
211 const TargetRegisterClass *RC,
212 unsigned Op0, bool Op0IsKill,
213 unsigned Op1, bool Op1IsKill) {
214 unsigned ResultReg = createResultReg(RC);
215 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
217 if (II.getNumDefs() >= 1)
218 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
219 .addReg(Op0, Op0IsKill * RegState::Kill)
220 .addReg(Op1, Op1IsKill * RegState::Kill));
222 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
223 .addReg(Op0, Op0IsKill * RegState::Kill)
224 .addReg(Op1, Op1IsKill * RegState::Kill));
225 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
226 TII.get(TargetOpcode::COPY), ResultReg)
227 .addReg(II.ImplicitDefs[0]));
232 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
233 const TargetRegisterClass *RC,
234 unsigned Op0, bool Op0IsKill,
236 unsigned ResultReg = createResultReg(RC);
237 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
239 if (II.getNumDefs() >= 1)
240 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
241 .addReg(Op0, Op0IsKill * RegState::Kill)
244 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
245 .addReg(Op0, Op0IsKill * RegState::Kill)
247 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
248 TII.get(TargetOpcode::COPY), ResultReg)
249 .addReg(II.ImplicitDefs[0]));
254 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
255 const TargetRegisterClass *RC,
256 unsigned Op0, bool Op0IsKill,
257 const ConstantFP *FPImm) {
258 unsigned ResultReg = createResultReg(RC);
259 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
261 if (II.getNumDefs() >= 1)
262 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
263 .addReg(Op0, Op0IsKill * RegState::Kill)
266 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
267 .addReg(Op0, Op0IsKill * RegState::Kill)
269 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
270 TII.get(TargetOpcode::COPY), ResultReg)
271 .addReg(II.ImplicitDefs[0]));
276 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
277 const TargetRegisterClass *RC,
278 unsigned Op0, bool Op0IsKill,
279 unsigned Op1, bool Op1IsKill,
281 unsigned ResultReg = createResultReg(RC);
282 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
284 if (II.getNumDefs() >= 1)
285 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
286 .addReg(Op0, Op0IsKill * RegState::Kill)
287 .addReg(Op1, Op1IsKill * RegState::Kill)
290 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
291 .addReg(Op0, Op0IsKill * RegState::Kill)
292 .addReg(Op1, Op1IsKill * RegState::Kill)
294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
295 TII.get(TargetOpcode::COPY), ResultReg)
296 .addReg(II.ImplicitDefs[0]));
301 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
302 const TargetRegisterClass *RC,
304 unsigned ResultReg = createResultReg(RC);
305 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
307 if (II.getNumDefs() >= 1)
308 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
311 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
313 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
314 TII.get(TargetOpcode::COPY), ResultReg)
315 .addReg(II.ImplicitDefs[0]));
320 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
321 unsigned Op0, bool Op0IsKill,
323 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
324 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
325 "Cannot yet extract from physregs");
326 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
327 DL, TII.get(TargetOpcode::COPY), ResultReg)
328 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
332 // For double width floating point we need to materialize two constants
333 // (the high and the low) into integer registers then use a move to get
334 // the combined constant into an FP reg.
335 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
336 const APFloat Val = CFP->getValueAPF();
337 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
339 // This checks to see if we can use VFP3 instructions to materialize
340 // a constant, otherwise we have to go through the constant pool.
341 if (TLI.isFPImmLegal(Val, VT)) {
342 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
343 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
344 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
350 // No 64-bit at the moment.
351 if (is64bit) return 0;
353 // Load this from the constant pool.
354 unsigned DestReg = ARMMaterializeInt(cast<Constant>(CFP));
356 // If we have a floating point constant we expect it in a floating point
358 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
359 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
360 TII.get(ARM::VMOVRS), MoveReg)
365 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) {
366 // MachineConstantPool wants an explicit alignment.
367 unsigned Align = TD.getPrefTypeAlignment(C->getType());
369 // TODO: Figure out if this is correct.
370 Align = TD.getTypeAllocSize(C->getType());
372 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
374 unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
376 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
377 TII.get(ARM::t2LDRpci))
378 .addReg(DestReg).addConstantPoolIndex(Idx));
380 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
382 .addReg(DestReg).addConstantPoolIndex(Idx)
383 .addReg(0).addImm(0));
388 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
389 EVT VT = TLI.getValueType(C->getType(), true);
391 // Only handle simple types.
392 if (!VT.isSimple()) return 0;
394 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
395 return ARMMaterializeFP(CFP, VT);
396 return ARMMaterializeInt(C);
399 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
400 VT = TLI.getValueType(Ty, true);
402 // Only handle simple types.
403 if (VT == MVT::Other || !VT.isSimple()) return false;
405 // Handle all legal types, i.e. a register that will directly hold this
407 return TLI.isTypeLegal(VT);
410 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
411 if (isTypeLegal(Ty, VT)) return true;
413 // If this is a type than can be sign or zero-extended to a basic operation
414 // go ahead and accept it now.
415 if (VT == MVT::i8 || VT == MVT::i16)
421 // Computes the Reg+Offset to get to an object.
422 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
424 // Some boilerplate from the X86 FastISel.
425 const User *U = NULL;
426 unsigned Opcode = Instruction::UserOp1;
427 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
428 // Don't walk into other basic blocks; it's possible we haven't
429 // visited them yet, so the instructions may not yet be assigned
430 // virtual registers.
431 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
434 Opcode = I->getOpcode();
436 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
437 Opcode = C->getOpcode();
441 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
442 if (Ty->getAddressSpace() > 255)
443 // Fast instruction selection doesn't support the special
449 //errs() << "Failing Opcode is: " << *Op1 << "\n";
451 case Instruction::Alloca: {
452 assert(false && "Alloca should have been handled earlier!");
457 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
458 //errs() << "Failing GV is: " << GV << "\n";
463 // Try to get this in a register if nothing else has worked.
464 Reg = getRegForValue(Obj);
465 if (Reg == 0) return false;
467 // Since the offset may be too large for the load instruction
468 // get the reg+offset into a register.
469 // TODO: Verify the additions work, otherwise we'll need to add the
470 // offset instead of 0 to the instructions and do all sorts of operand
472 // TODO: Optimize this somewhat.
474 ARMCC::CondCodes Pred = ARMCC::AL;
475 unsigned PredReg = 0;
478 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
479 Reg, Reg, Offset, Pred, PredReg,
480 static_cast<const ARMBaseInstrInfo&>(TII));
482 assert(AFI->isThumb2Function());
483 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
484 Reg, Reg, Offset, Pred, PredReg,
485 static_cast<const ARMBaseInstrInfo&>(TII));
492 bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
493 Value *Op0 = I->getOperand(0);
495 // Verify it's an alloca.
496 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
497 DenseMap<const AllocaInst*, int>::iterator SI =
498 FuncInfo.StaticAllocaMap.find(AI);
500 if (SI != FuncInfo.StaticAllocaMap.end()) {
501 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
502 unsigned ResultReg = createResultReg(RC);
503 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
504 ResultReg, SI->second, RC,
505 TM.getRegisterInfo());
506 UpdateValueMap(I, ResultReg);
513 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
514 unsigned Reg, int Offset) {
516 assert(VT.isSimple() && "Non-simple types are invalid here!");
519 switch (VT.getSimpleVT().SimpleTy) {
521 assert(false && "Trying to emit for an unhandled type!");
524 Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
528 Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
532 Opc = isThumb ? ARM::tLDR : ARM::LDR;
536 ResultReg = createResultReg(TLI.getRegClassFor(VT));
538 // TODO: Fix the Addressing modes so that these can share some code.
539 // Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
541 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
542 TII.get(Opc), ResultReg)
543 .addReg(Reg).addImm(Offset).addReg(0));
545 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
546 TII.get(Opc), ResultReg)
547 .addReg(Reg).addReg(0).addImm(Offset));
552 bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
553 Value *Op1 = I->getOperand(1);
555 // Verify it's an alloca.
556 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
557 DenseMap<const AllocaInst*, int>::iterator SI =
558 FuncInfo.StaticAllocaMap.find(AI);
560 if (SI != FuncInfo.StaticAllocaMap.end()) {
561 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
562 assert(SrcReg != 0 && "Nothing to store!");
563 TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
564 SrcReg, true /*isKill*/, SI->second, RC,
565 TM.getRegisterInfo());
572 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
573 unsigned DstReg, int Offset) {
575 switch (VT.getSimpleVT().SimpleTy) {
576 default: return false;
578 case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break;
579 case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break;
580 case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break;
582 if (!Subtarget->hasVFP2()) return false;
586 if (!Subtarget->hasVFP2()) return false;
592 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
593 TII.get(StrOpc), SrcReg)
594 .addReg(DstReg).addImm(Offset).addReg(0));
596 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
597 TII.get(StrOpc), SrcReg)
598 .addReg(DstReg).addReg(0).addImm(Offset));
603 bool ARMFastISel::ARMSelectStore(const Instruction *I) {
604 Value *Op0 = I->getOperand(0);
607 // Yay type legalization
609 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
612 // Get the value to be stored into a register.
613 SrcReg = getRegForValue(Op0);
617 // If we're an alloca we know we have a frame index and can emit the store
619 if (ARMStoreAlloca(I, SrcReg, VT))
622 // Our register and offset with innocuous defaults.
626 // See if we can handle this as Reg + Offset
627 if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
630 if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
636 bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
637 // Verify we have a legal type before going any further.
639 if (!isLoadTypeLegal(I->getType(), VT))
642 // If we're an alloca we know we have a frame index and can emit the load
643 // directly in short order.
644 if (ARMLoadAlloca(I, VT))
647 // Our register and offset with innocuous defaults.
651 // See if we can handle this as Reg + Offset
652 if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
656 if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
658 UpdateValueMap(I, ResultReg);
662 bool ARMFastISel::ARMSelectBranch(const Instruction *I) {
663 const BranchInst *BI = cast<BranchInst>(I);
664 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
665 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
667 // Simple branch support.
668 unsigned CondReg = getRegForValue(BI->getCondition());
669 if (CondReg == 0) return false;
671 unsigned CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
672 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
673 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
674 .addReg(CondReg).addReg(CondReg));
675 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
676 .addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
677 FastEmitBranch(FBB, DL);
678 FuncInfo.MBB->addSuccessor(TBB);
682 bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
683 const CmpInst *CI = cast<CmpInst>(I);
686 const Type *Ty = CI->getOperand(0)->getType();
687 if (!isTypeLegal(Ty, VT))
690 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
691 if (isFloat && !Subtarget->hasVFP2())
695 switch (VT.getSimpleVT().SimpleTy) {
696 default: return false;
697 // TODO: Verify compares.
699 CmpOpc = ARM::VCMPES;
702 CmpOpc = ARM::VCMPED;
705 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
709 unsigned Arg1 = getRegForValue(CI->getOperand(0));
710 if (Arg1 == 0) return false;
712 unsigned Arg2 = getRegForValue(CI->getOperand(1));
713 if (Arg2 == 0) return false;
715 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
716 .addReg(Arg1).addReg(Arg2));
718 // For floating point we need to move the result to a register we can
719 // actually do something with.
721 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
722 TII.get(ARM::FMSTAT)));
726 bool ARMFastISel::ARMSelectFPExt(const Instruction *I) {
727 // Make sure we have VFP and that we're extending float to double.
728 if (!Subtarget->hasVFP2()) return false;
730 Value *V = I->getOperand(0);
731 if (!I->getType()->isDoubleTy() ||
732 !V->getType()->isFloatTy()) return false;
734 unsigned Op = getRegForValue(V);
735 if (Op == 0) return false;
737 unsigned Result = createResultReg(ARM::DPRRegisterClass);
739 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
740 TII.get(ARM::VCVTDS), Result)
742 UpdateValueMap(I, Result);
746 bool ARMFastISel::ARMSelectSIToFP(const Instruction *I) {
747 // Make sure we have VFP.
748 if (!Subtarget->hasVFP2()) return false;
751 const Type *Ty = I->getType();
752 if (!isTypeLegal(Ty, VT))
755 unsigned Op = getRegForValue(I->getOperand(0));
756 if (Op == 0) return false;
759 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
760 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
763 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
764 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
770 bool ARMFastISel::ARMSelectFPToSI(const Instruction *I) {
771 // Make sure we have VFP.
772 if (!Subtarget->hasVFP2()) return false;
775 const Type *RetTy = I->getType();
776 if (!isTypeLegal(RetTy, VT))
779 unsigned Op = getRegForValue(I->getOperand(0));
780 if (Op == 0) return false;
783 const Type *OpTy = I->getOperand(0)->getType();
784 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
785 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
788 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
789 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
795 bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
796 EVT VT = TLI.getValueType(I->getType(), true);
798 // We can get here in the case when we want to use NEON for our fp
799 // operations, but can't figure out how to. Just use the vfp instructions
801 // FIXME: It'd be nice to use NEON instructions.
802 const Type *Ty = I->getType();
803 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
804 if (isFloat && !Subtarget->hasVFP2())
807 unsigned Op1 = getRegForValue(I->getOperand(0));
808 if (Op1 == 0) return false;
810 unsigned Op2 = getRegForValue(I->getOperand(1));
811 if (Op2 == 0) return false;
814 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
815 VT.getSimpleVT().SimpleTy == MVT::i64;
817 default: return false;
819 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
822 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
825 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
828 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
829 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
830 TII.get(Opc), ResultReg)
831 .addReg(Op1).addReg(Op2));
835 // TODO: SoftFP support.
836 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
837 // No Thumb-1 for now.
838 if (isThumb && !AFI->isThumb2Function()) return false;
840 switch (I->getOpcode()) {
841 case Instruction::Load:
842 return ARMSelectLoad(I);
843 case Instruction::Store:
844 return ARMSelectStore(I);
845 case Instruction::Br:
846 return ARMSelectBranch(I);
847 case Instruction::ICmp:
848 case Instruction::FCmp:
849 return ARMSelectCmp(I);
850 case Instruction::FPExt:
851 return ARMSelectFPExt(I);
852 case Instruction::SIToFP:
853 return ARMSelectSIToFP(I);
854 case Instruction::FPToSI:
855 return ARMSelectFPToSI(I);
856 case Instruction::FAdd:
857 return ARMSelectBinaryOp(I, ISD::FADD);
858 case Instruction::FSub:
859 return ARMSelectBinaryOp(I, ISD::FSUB);
860 case Instruction::FMul:
861 return ARMSelectBinaryOp(I, ISD::FMUL);
868 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
869 if (EnableARMFastISel) return new ARMFastISel(funcInfo);