1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/Module.h"
28 #include "llvm/CodeGen/Analysis.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/FunctionLoweringInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineConstantPool.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/Support/CallSite.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/GetElementPtrTypeIterator.h"
40 #include "llvm/Target/TargetData.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
48 EnableARMFastISel("arm-fast-isel",
49 cl::desc("Turn on experimental ARM fast-isel support"),
50 cl::init(false), cl::Hidden);
54 class ARMFastISel : public FastISel {
56 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
57 /// make the right decision when generating code for different targets.
58 const ARMSubtarget *Subtarget;
59 const TargetMachine &TM;
60 const TargetInstrInfo &TII;
61 const TargetLowering &TLI;
62 const ARMFunctionInfo *AFI;
64 // Convenience variable to avoid checking all the time.
68 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
70 TM(funcInfo.MF->getTarget()),
71 TII(*TM.getInstrInfo()),
72 TLI(*TM.getTargetLowering()) {
73 Subtarget = &TM.getSubtarget<ARMSubtarget>();
74 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
75 isThumb = AFI->isThumbFunction();
78 // Code from FastISel.cpp.
79 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
80 const TargetRegisterClass *RC);
81 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
82 const TargetRegisterClass *RC,
83 unsigned Op0, bool Op0IsKill);
84 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
85 const TargetRegisterClass *RC,
86 unsigned Op0, bool Op0IsKill,
87 unsigned Op1, bool Op1IsKill);
88 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
89 const TargetRegisterClass *RC,
90 unsigned Op0, bool Op0IsKill,
92 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
93 const TargetRegisterClass *RC,
94 unsigned Op0, bool Op0IsKill,
95 const ConstantFP *FPImm);
96 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
97 const TargetRegisterClass *RC,
99 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
100 const TargetRegisterClass *RC,
101 unsigned Op0, bool Op0IsKill,
102 unsigned Op1, bool Op1IsKill,
104 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
105 unsigned Op0, bool Op0IsKill,
108 // Backend specific FastISel code.
109 virtual bool TargetSelectInstruction(const Instruction *I);
110 virtual unsigned TargetMaterializeConstant(const Constant *C);
112 #include "ARMGenFastISel.inc"
114 // Instruction selection routines.
116 virtual bool ARMSelectLoad(const Instruction *I);
117 virtual bool ARMSelectStore(const Instruction *I);
118 virtual bool ARMSelectBranch(const Instruction *I);
119 virtual bool ARMSelectCmp(const Instruction *I);
120 virtual bool ARMSelectFPExt(const Instruction *I);
121 virtual bool ARMSelectFPTrunc(const Instruction *I);
122 virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
123 virtual bool ARMSelectSIToFP(const Instruction *I);
124 virtual bool ARMSelectFPToSI(const Instruction *I);
125 virtual bool ARMSelectSDiv(const Instruction *I);
129 bool isTypeLegal(const Type *Ty, EVT &VT);
130 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
131 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
132 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
133 bool ARMLoadAlloca(const Instruction *I, EVT VT);
134 bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
135 bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
136 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
137 unsigned ARMMaterializeInt(const Constant *C);
138 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
139 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
141 // Call handling routines.
143 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
144 bool ARMEmitLibcall(const Instruction *I, Function *F);
146 // OptionalDef handling routines.
148 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
149 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
152 } // end anonymous namespace
154 #include "ARMGenCallingConv.inc"
156 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
157 // we don't care about implicit defs here, just places we'll need to add a
158 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
159 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
160 const TargetInstrDesc &TID = MI->getDesc();
161 if (!TID.hasOptionalDef())
164 // Look to see if our OptionalDef is defining CPSR or CCR.
165 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
166 const MachineOperand &MO = MI->getOperand(i);
167 if (!MO.isReg() || !MO.isDef()) continue;
168 if (MO.getReg() == ARM::CPSR)
174 // If the machine is predicable go ahead and add the predicate operands, if
175 // it needs default CC operands add those.
176 const MachineInstrBuilder &
177 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
178 MachineInstr *MI = &*MIB;
180 // Do we use a predicate?
181 if (TII.isPredicable(MI))
184 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
185 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
187 if (DefinesOptionalPredicate(MI, &CPSR)) {
196 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
197 const TargetRegisterClass* RC) {
198 unsigned ResultReg = createResultReg(RC);
199 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
201 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
205 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
206 const TargetRegisterClass *RC,
207 unsigned Op0, bool Op0IsKill) {
208 unsigned ResultReg = createResultReg(RC);
209 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
211 if (II.getNumDefs() >= 1)
212 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
213 .addReg(Op0, Op0IsKill * RegState::Kill));
215 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
216 .addReg(Op0, Op0IsKill * RegState::Kill));
217 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
218 TII.get(TargetOpcode::COPY), ResultReg)
219 .addReg(II.ImplicitDefs[0]));
224 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
225 const TargetRegisterClass *RC,
226 unsigned Op0, bool Op0IsKill,
227 unsigned Op1, bool Op1IsKill) {
228 unsigned ResultReg = createResultReg(RC);
229 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
231 if (II.getNumDefs() >= 1)
232 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
233 .addReg(Op0, Op0IsKill * RegState::Kill)
234 .addReg(Op1, Op1IsKill * RegState::Kill));
236 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
237 .addReg(Op0, Op0IsKill * RegState::Kill)
238 .addReg(Op1, Op1IsKill * RegState::Kill));
239 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
240 TII.get(TargetOpcode::COPY), ResultReg)
241 .addReg(II.ImplicitDefs[0]));
246 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
247 const TargetRegisterClass *RC,
248 unsigned Op0, bool Op0IsKill,
250 unsigned ResultReg = createResultReg(RC);
251 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
253 if (II.getNumDefs() >= 1)
254 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
255 .addReg(Op0, Op0IsKill * RegState::Kill)
258 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
259 .addReg(Op0, Op0IsKill * RegState::Kill)
261 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
262 TII.get(TargetOpcode::COPY), ResultReg)
263 .addReg(II.ImplicitDefs[0]));
268 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
269 const TargetRegisterClass *RC,
270 unsigned Op0, bool Op0IsKill,
271 const ConstantFP *FPImm) {
272 unsigned ResultReg = createResultReg(RC);
273 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
275 if (II.getNumDefs() >= 1)
276 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
277 .addReg(Op0, Op0IsKill * RegState::Kill)
280 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
281 .addReg(Op0, Op0IsKill * RegState::Kill)
283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
284 TII.get(TargetOpcode::COPY), ResultReg)
285 .addReg(II.ImplicitDefs[0]));
290 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
291 const TargetRegisterClass *RC,
292 unsigned Op0, bool Op0IsKill,
293 unsigned Op1, bool Op1IsKill,
295 unsigned ResultReg = createResultReg(RC);
296 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
298 if (II.getNumDefs() >= 1)
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
300 .addReg(Op0, Op0IsKill * RegState::Kill)
301 .addReg(Op1, Op1IsKill * RegState::Kill)
304 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
305 .addReg(Op0, Op0IsKill * RegState::Kill)
306 .addReg(Op1, Op1IsKill * RegState::Kill)
308 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
309 TII.get(TargetOpcode::COPY), ResultReg)
310 .addReg(II.ImplicitDefs[0]));
315 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
316 const TargetRegisterClass *RC,
318 unsigned ResultReg = createResultReg(RC);
319 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
321 if (II.getNumDefs() >= 1)
322 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
325 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
327 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
328 TII.get(TargetOpcode::COPY), ResultReg)
329 .addReg(II.ImplicitDefs[0]));
334 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
335 unsigned Op0, bool Op0IsKill,
337 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
338 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
339 "Cannot yet extract from physregs");
340 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
341 DL, TII.get(TargetOpcode::COPY), ResultReg)
342 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
346 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
347 // checks from the various callers.
348 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
349 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
351 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
352 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
353 TII.get(ARM::VMOVRS), MoveReg)
358 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
359 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
361 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
362 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
363 TII.get(ARM::VMOVSR), MoveReg)
368 // For double width floating point we need to materialize two constants
369 // (the high and the low) into integer registers then use a move to get
370 // the combined constant into an FP reg.
371 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
372 const APFloat Val = CFP->getValueAPF();
373 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
375 // This checks to see if we can use VFP3 instructions to materialize
376 // a constant, otherwise we have to go through the constant pool.
377 if (TLI.isFPImmLegal(Val, VT)) {
378 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
379 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
380 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
386 // Require VFP2 for loading fp constants.
387 if (!Subtarget->hasVFP2()) return false;
389 // MachineConstantPool wants an explicit alignment.
390 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
392 // TODO: Figure out if this is correct.
393 Align = TD.getTypeAllocSize(CFP->getType());
395 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
396 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
397 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
399 // The extra reg is for addrmode5.
400 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
401 .addReg(DestReg).addConstantPoolIndex(Idx)
406 // TODO: Verify 64-bit.
407 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) {
408 // MachineConstantPool wants an explicit alignment.
409 unsigned Align = TD.getPrefTypeAlignment(C->getType());
411 // TODO: Figure out if this is correct.
412 Align = TD.getTypeAllocSize(C->getType());
414 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
415 unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
418 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
419 TII.get(ARM::t2LDRpci))
420 .addReg(DestReg).addConstantPoolIndex(Idx));
422 // The extra reg and immediate are for addrmode2.
423 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
425 .addReg(DestReg).addConstantPoolIndex(Idx)
426 .addReg(0).addImm(0));
431 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
432 EVT VT = TLI.getValueType(C->getType(), true);
434 // Only handle simple types.
435 if (!VT.isSimple()) return 0;
437 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
438 return ARMMaterializeFP(CFP, VT);
439 return ARMMaterializeInt(C);
442 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
443 VT = TLI.getValueType(Ty, true);
445 // Only handle simple types.
446 if (VT == MVT::Other || !VT.isSimple()) return false;
448 // Handle all legal types, i.e. a register that will directly hold this
450 return TLI.isTypeLegal(VT);
453 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
454 if (isTypeLegal(Ty, VT)) return true;
456 // If this is a type than can be sign or zero-extended to a basic operation
457 // go ahead and accept it now.
458 if (VT == MVT::i8 || VT == MVT::i16)
464 // Computes the Reg+Offset to get to an object.
465 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
467 // Some boilerplate from the X86 FastISel.
468 const User *U = NULL;
469 unsigned Opcode = Instruction::UserOp1;
470 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
471 // Don't walk into other basic blocks; it's possible we haven't
472 // visited them yet, so the instructions may not yet be assigned
473 // virtual registers.
474 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
476 Opcode = I->getOpcode();
478 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
479 Opcode = C->getOpcode();
483 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
484 if (Ty->getAddressSpace() > 255)
485 // Fast instruction selection doesn't support the special
492 case Instruction::Alloca: {
493 assert(false && "Alloca should have been handled earlier!");
498 // FIXME: Handle global variables.
499 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
504 // Try to get this in a register if nothing else has worked.
505 Reg = getRegForValue(Obj);
506 if (Reg == 0) return false;
508 // Since the offset may be too large for the load instruction
509 // get the reg+offset into a register.
510 // TODO: Verify the additions work, otherwise we'll need to add the
511 // offset instead of 0 to the instructions and do all sorts of operand
513 // TODO: Optimize this somewhat.
515 ARMCC::CondCodes Pred = ARMCC::AL;
516 unsigned PredReg = 0;
519 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
520 Reg, Reg, Offset, Pred, PredReg,
521 static_cast<const ARMBaseInstrInfo&>(TII));
523 assert(AFI->isThumb2Function());
524 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
525 Reg, Reg, Offset, Pred, PredReg,
526 static_cast<const ARMBaseInstrInfo&>(TII));
532 bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
533 Value *Op0 = I->getOperand(0);
535 // Verify it's an alloca.
536 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
537 DenseMap<const AllocaInst*, int>::iterator SI =
538 FuncInfo.StaticAllocaMap.find(AI);
540 if (SI != FuncInfo.StaticAllocaMap.end()) {
541 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
542 unsigned ResultReg = createResultReg(RC);
543 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
544 ResultReg, SI->second, RC,
545 TM.getRegisterInfo());
546 UpdateValueMap(I, ResultReg);
553 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
554 unsigned Reg, int Offset) {
556 assert(VT.isSimple() && "Non-simple types are invalid here!");
558 switch (VT.getSimpleVT().SimpleTy) {
560 assert(false && "Trying to emit for an unhandled type!");
563 Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
567 Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
571 Opc = isThumb ? ARM::tLDR : ARM::LDR;
575 ResultReg = createResultReg(TLI.getRegClassFor(VT));
577 // TODO: Fix the Addressing modes so that these can share some code.
578 // Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
580 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
581 TII.get(Opc), ResultReg)
582 .addReg(Reg).addImm(Offset).addReg(0));
584 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
585 TII.get(Opc), ResultReg)
586 .addReg(Reg).addReg(0).addImm(Offset));
590 bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
591 // Verify we have a legal type before going any further.
593 if (!isLoadTypeLegal(I->getType(), VT))
596 // If we're an alloca we know we have a frame index and can emit the load
597 // directly in short order.
598 if (ARMLoadAlloca(I, VT))
601 // Our register and offset with innocuous defaults.
605 // See if we can handle this as Reg + Offset
606 if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
610 if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
612 UpdateValueMap(I, ResultReg);
616 bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
617 Value *Op1 = I->getOperand(1);
619 // Verify it's an alloca.
620 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
621 DenseMap<const AllocaInst*, int>::iterator SI =
622 FuncInfo.StaticAllocaMap.find(AI);
624 if (SI != FuncInfo.StaticAllocaMap.end()) {
625 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
626 assert(SrcReg != 0 && "Nothing to store!");
627 TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
628 SrcReg, true /*isKill*/, SI->second, RC,
629 TM.getRegisterInfo());
636 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
637 unsigned DstReg, int Offset) {
639 bool isFloat = false;
640 switch (VT.getSimpleVT().SimpleTy) {
641 default: return false;
643 case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break;
644 case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break;
645 case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break;
647 if (!Subtarget->hasVFP2()) return false;
652 if (!Subtarget->hasVFP2()) return false;
658 // The thumb addressing mode has operands swapped from the arm addressing
659 // mode, the floating point one only has two operands.
661 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
662 TII.get(StrOpc), SrcReg)
663 .addReg(DstReg).addImm(Offset).addReg(0));
665 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
666 TII.get(StrOpc), SrcReg)
667 .addReg(DstReg).addImm(Offset));
669 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
670 TII.get(StrOpc), SrcReg)
671 .addReg(DstReg).addReg(0).addImm(Offset));
676 bool ARMFastISel::ARMSelectStore(const Instruction *I) {
677 Value *Op0 = I->getOperand(0);
680 // Yay type legalization
682 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
685 // Get the value to be stored into a register.
686 SrcReg = getRegForValue(Op0);
690 // If we're an alloca we know we have a frame index and can emit the store
692 if (ARMStoreAlloca(I, SrcReg, VT))
695 // Our register and offset with innocuous defaults.
699 // See if we can handle this as Reg + Offset
700 if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
703 if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
708 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
710 // Needs two compares...
711 case CmpInst::FCMP_ONE:
712 case CmpInst::FCMP_UEQ:
714 assert(false && "Unhandled CmpInst::Predicate!");
716 case CmpInst::ICMP_EQ:
717 case CmpInst::FCMP_OEQ:
719 case CmpInst::ICMP_SGT:
720 case CmpInst::FCMP_OGT:
722 case CmpInst::ICMP_SGE:
723 case CmpInst::FCMP_OGE:
725 case CmpInst::ICMP_UGT:
726 case CmpInst::FCMP_UGT:
728 case CmpInst::FCMP_OLT:
730 case CmpInst::ICMP_ULE:
731 case CmpInst::FCMP_OLE:
733 case CmpInst::FCMP_ORD:
735 case CmpInst::FCMP_UNO:
737 case CmpInst::FCMP_UGE:
739 case CmpInst::ICMP_SLT:
740 case CmpInst::FCMP_ULT:
742 case CmpInst::ICMP_SLE:
743 case CmpInst::FCMP_ULE:
745 case CmpInst::FCMP_UNE:
746 case CmpInst::ICMP_NE:
748 case CmpInst::ICMP_UGE:
750 case CmpInst::ICMP_ULT:
755 bool ARMFastISel::ARMSelectBranch(const Instruction *I) {
756 const BranchInst *BI = cast<BranchInst>(I);
757 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
758 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
760 // Simple branch support.
761 // TODO: Hopefully we've already handled the condition since we won't
762 // have left an update in the value map. See the TODO below in ARMSelectCMP.
763 Value *Cond = BI->getCondition();
764 unsigned CondReg = getRegForValue(Cond);
765 if (CondReg == 0) return false;
767 ARMCC::CondCodes ARMPred = ARMCC::NE;
768 CmpInst *CI = dyn_cast<CmpInst>(Cond);
769 if (!CI) return false;
771 // Get the compare predicate.
772 ARMPred = getComparePred(CI->getPredicate());
774 // We may not handle every CC for now.
775 if (ARMPred == ARMCC::AL) return false;
777 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
778 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
779 .addMBB(TBB).addImm(ARMPred).addReg(CondReg);
780 FastEmitBranch(FBB, DL);
781 FuncInfo.MBB->addSuccessor(TBB);
785 bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
786 const CmpInst *CI = cast<CmpInst>(I);
789 const Type *Ty = CI->getOperand(0)->getType();
790 if (!isTypeLegal(Ty, VT))
793 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
794 if (isFloat && !Subtarget->hasVFP2())
799 switch (VT.getSimpleVT().SimpleTy) {
800 default: return false;
801 // TODO: Verify compares.
803 CmpOpc = ARM::VCMPES;
804 DestReg = ARM::FPSCR;
807 CmpOpc = ARM::VCMPED;
808 DestReg = ARM::FPSCR;
811 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
816 unsigned Arg1 = getRegForValue(CI->getOperand(0));
817 if (Arg1 == 0) return false;
819 unsigned Arg2 = getRegForValue(CI->getOperand(1));
820 if (Arg2 == 0) return false;
822 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
823 .addReg(Arg1).addReg(Arg2));
825 // For floating point we need to move the result to a comparison register
826 // that we can then use for branches.
828 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
829 TII.get(ARM::FMSTAT)));
831 // Update the value to the implicit def reg.
832 UpdateValueMap(I, DestReg);
836 bool ARMFastISel::ARMSelectFPExt(const Instruction *I) {
837 // Make sure we have VFP and that we're extending float to double.
838 if (!Subtarget->hasVFP2()) return false;
840 Value *V = I->getOperand(0);
841 if (!I->getType()->isDoubleTy() ||
842 !V->getType()->isFloatTy()) return false;
844 unsigned Op = getRegForValue(V);
845 if (Op == 0) return false;
847 unsigned Result = createResultReg(ARM::DPRRegisterClass);
848 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
849 TII.get(ARM::VCVTDS), Result)
851 UpdateValueMap(I, Result);
855 bool ARMFastISel::ARMSelectFPTrunc(const Instruction *I) {
856 // Make sure we have VFP and that we're truncating double to float.
857 if (!Subtarget->hasVFP2()) return false;
859 Value *V = I->getOperand(0);
860 if (!I->getType()->isFloatTy() ||
861 !V->getType()->isDoubleTy()) return false;
863 unsigned Op = getRegForValue(V);
864 if (Op == 0) return false;
866 unsigned Result = createResultReg(ARM::SPRRegisterClass);
867 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
868 TII.get(ARM::VCVTSD), Result)
870 UpdateValueMap(I, Result);
874 bool ARMFastISel::ARMSelectSIToFP(const Instruction *I) {
875 // Make sure we have VFP.
876 if (!Subtarget->hasVFP2()) return false;
879 const Type *Ty = I->getType();
880 if (!isTypeLegal(Ty, DstVT))
883 unsigned Op = getRegForValue(I->getOperand(0));
884 if (Op == 0) return false;
886 // The conversion routine works on fp-reg to fp-reg and the operand above
887 // was an integer, move it to the fp registers if possible.
888 unsigned FP = ARMMoveToFPReg(DstVT, Op);
889 if (FP == 0) return false;
892 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
893 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
896 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
897 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
900 UpdateValueMap(I, ResultReg);
904 bool ARMFastISel::ARMSelectFPToSI(const Instruction *I) {
905 // Make sure we have VFP.
906 if (!Subtarget->hasVFP2()) return false;
909 const Type *RetTy = I->getType();
910 if (!isTypeLegal(RetTy, DstVT))
913 unsigned Op = getRegForValue(I->getOperand(0));
914 if (Op == 0) return false;
917 const Type *OpTy = I->getOperand(0)->getType();
918 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
919 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
921 EVT OpVT = TLI.getValueType(OpTy, true);
923 unsigned ResultReg = createResultReg(TLI.getRegClassFor(OpVT));
924 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
928 // This result needs to be in an integer register, but the conversion only
929 // takes place in fp-regs.
930 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
931 if (IntReg == 0) return false;
933 UpdateValueMap(I, IntReg);
937 bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
938 EVT VT = TLI.getValueType(I->getType(), true);
940 // We can get here in the case when we want to use NEON for our fp
941 // operations, but can't figure out how to. Just use the vfp instructions
943 // FIXME: It'd be nice to use NEON instructions.
944 const Type *Ty = I->getType();
945 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
946 if (isFloat && !Subtarget->hasVFP2())
949 unsigned Op1 = getRegForValue(I->getOperand(0));
950 if (Op1 == 0) return false;
952 unsigned Op2 = getRegForValue(I->getOperand(1));
953 if (Op2 == 0) return false;
956 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
957 VT.getSimpleVT().SimpleTy == MVT::i64;
959 default: return false;
961 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
964 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
967 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
970 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
971 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
972 TII.get(Opc), ResultReg)
973 .addReg(Op1).addReg(Op2));
974 UpdateValueMap(I, ResultReg);
978 // Call Handling Code
980 // This is largely taken directly from CCAssignFnForNode - we don't support
981 // varargs in FastISel so that part has been removed.
982 // TODO: We may not support all of this.
983 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
986 llvm_unreachable("Unsupported calling convention");
988 case CallingConv::Fast:
989 // Use target triple & subtarget features to do actual dispatch.
990 if (Subtarget->isAAPCS_ABI()) {
991 if (Subtarget->hasVFP2() &&
992 FloatABIType == FloatABI::Hard)
993 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
995 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
997 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
998 case CallingConv::ARM_AAPCS_VFP:
999 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1000 case CallingConv::ARM_AAPCS:
1001 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1002 case CallingConv::ARM_APCS:
1003 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1007 // A quick function that will emit a call for a named libcall in F with the
1008 // vector of passed arguments for the Instruction in I. We can assume that we
1009 // can emit a call for any libcall we can produce. This is an abridged version
1010 // of the full call infrastructure since we won't need to worry about things
1011 // like computed function pointers or strange arguments at call sites.
1012 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1014 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, Function *F) {
1015 CallingConv::ID CC = F->getCallingConv();
1017 // Handle *simple* calls for now.
1018 const Type *RetTy = F->getReturnType();
1020 if (RetTy->isVoidTy())
1021 RetVT = MVT::isVoid;
1022 else if (!isTypeLegal(RetTy, RetVT))
1025 assert(!F->isVarArg() && "Vararg libcall?!");
1027 // Abridged from the X86 FastISel call selection mechanism
1028 SmallVector<Value*, 8> Args;
1029 SmallVector<unsigned, 8> ArgRegs;
1030 SmallVector<EVT, 8> ArgVTs;
1031 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1032 Args.reserve(I->getNumOperands());
1033 ArgRegs.reserve(I->getNumOperands());
1034 ArgVTs.reserve(I->getNumOperands());
1035 ArgFlags.reserve(I->getNumOperands());
1036 for (unsigned i = 0; i < Args.size(); ++i) {
1037 Value *Op = I->getOperand(i);
1038 unsigned Arg = getRegForValue(Op);
1039 if (Arg == 0) return false;
1041 const Type *ArgTy = Op->getType();
1043 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1045 ISD::ArgFlagsTy Flags;
1046 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1047 Flags.setOrigAlign(OriginalAlignment);
1050 ArgRegs.push_back(Arg);
1051 ArgVTs.push_back(ArgVT);
1052 ArgFlags.push_back(Flags);
1055 SmallVector<CCValAssign, 16> ArgLocs;
1056 CCState CCInfo(CC, false, TM, ArgLocs, F->getContext());
1057 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1059 // Process the args.
1060 SmallVector<unsigned, 4> RegArgs;
1061 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1062 CCValAssign &VA = ArgLocs[i];
1063 unsigned Arg = ArgRegs[VA.getValNo()];
1064 EVT ArgVT = ArgVTs[VA.getValNo()];
1066 // Should we ever have to promote?
1067 switch (VA.getLocInfo()) {
1068 case CCValAssign::Full: break;
1070 assert(false && "Handle arg promotion for libcalls?");
1074 // Now copy/store arg to correct locations.
1075 if (VA.isRegLoc()) {
1076 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1077 VA.getLocReg()).addReg(Arg);
1078 RegArgs.push_back(VA.getLocReg());
1085 // Issue the call, BLr9 for darwin, BL otherwise.
1086 MachineInstrBuilder MIB;
1087 unsigned CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1088 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1089 .addGlobalAddress(F, 0, 0);
1091 // Add implicit physical register uses to the call.
1092 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1093 MIB.addReg(RegArgs[i]);
1095 // Now the return value.
1096 SmallVector<unsigned, 4> UsedRegs;
1097 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1098 SmallVector<CCValAssign, 16> RVLocs;
1099 CCState CCInfo(CC, false, TM, RVLocs, F->getContext());
1100 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1102 // Copy all of the result registers out of their specified physreg.
1103 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1104 EVT CopyVT = RVLocs[0].getValVT();
1105 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1107 unsigned ResultReg = createResultReg(DstRC);
1108 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1109 ResultReg).addReg(RVLocs[0].getLocReg());
1110 UsedRegs.push_back(RVLocs[0].getLocReg());
1112 // Finally update the result.
1113 UpdateValueMap(I, ResultReg);
1116 // Set all unused physreg defs as dead.
1117 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1122 bool ARMFastISel::ARMSelectSDiv(const Instruction *I) {
1124 const Type *Ty = I->getType();
1125 if (!isTypeLegal(Ty, VT))
1128 // If we have integer div support we should have gotten already, emit a
1130 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1132 LC = RTLIB::SDIV_I16;
1133 else if (VT == MVT::i32)
1134 LC = RTLIB::SDIV_I32;
1135 else if (VT == MVT::i64)
1136 LC = RTLIB::SDIV_I64;
1137 else if (VT == MVT::i128)
1138 LC = RTLIB::SDIV_I128;
1139 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1141 // Binary operand with all the same type.
1142 std::vector<const Type*> ArgTys;
1143 ArgTys.push_back(Ty);
1144 ArgTys.push_back(Ty);
1145 const FunctionType *FTy = FunctionType::get(Ty, ArgTys, false);
1146 Function *F = Function::Create(FTy, GlobalValue::ExternalLinkage,
1147 TLI.getLibcallName(LC));
1148 if (Subtarget->isAAPCS_ABI())
1149 F->setCallingConv(CallingConv::ARM_AAPCS);
1151 F->setCallingConv(I->getParent()->getParent()->getCallingConv());
1153 return ARMEmitLibcall(I, F);
1156 // TODO: SoftFP support.
1157 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1158 // No Thumb-1 for now.
1159 if (isThumb && !AFI->isThumb2Function()) return false;
1161 switch (I->getOpcode()) {
1162 case Instruction::Load:
1163 return ARMSelectLoad(I);
1164 case Instruction::Store:
1165 return ARMSelectStore(I);
1166 case Instruction::Br:
1167 return ARMSelectBranch(I);
1168 case Instruction::ICmp:
1169 case Instruction::FCmp:
1170 return ARMSelectCmp(I);
1171 case Instruction::FPExt:
1172 return ARMSelectFPExt(I);
1173 case Instruction::FPTrunc:
1174 return ARMSelectFPTrunc(I);
1175 case Instruction::SIToFP:
1176 return ARMSelectSIToFP(I);
1177 case Instruction::FPToSI:
1178 return ARMSelectFPToSI(I);
1179 case Instruction::FAdd:
1180 return ARMSelectBinaryOp(I, ISD::FADD);
1181 case Instruction::FSub:
1182 return ARMSelectBinaryOp(I, ISD::FSUB);
1183 case Instruction::FMul:
1184 return ARMSelectBinaryOp(I, ISD::FMUL);
1185 case Instruction::SDiv:
1186 return ARMSelectSDiv(I);
1193 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1194 if (EnableARMFastISel) return new ARMFastISel(funcInfo);