1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMRegisterInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/Analysis.h"
27 #include "llvm/CodeGen/FastISel.h"
28 #include "llvm/CodeGen/FunctionLoweringInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineConstantPool.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/Support/CallSite.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/GetElementPtrTypeIterator.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
46 EnableARMFastISel("arm-fast-isel",
47 cl::desc("Turn on experimental ARM fast-isel support"),
48 cl::init(false), cl::Hidden);
52 class ARMFastISel : public FastISel {
54 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
55 /// make the right decision when generating code for different targets.
56 const ARMSubtarget *Subtarget;
57 const TargetMachine &TM;
58 const TargetInstrInfo &TII;
59 const TargetLowering &TLI;
60 const ARMFunctionInfo *AFI;
62 // Convenience variable to avoid checking all the time.
66 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
68 TM(funcInfo.MF->getTarget()),
69 TII(*TM.getInstrInfo()),
70 TLI(*TM.getTargetLowering()) {
71 Subtarget = &TM.getSubtarget<ARMSubtarget>();
72 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
73 isThumb = AFI->isThumbFunction();
76 // Code from FastISel.cpp.
77 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
78 const TargetRegisterClass *RC);
79 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
80 const TargetRegisterClass *RC,
81 unsigned Op0, bool Op0IsKill);
82 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
83 const TargetRegisterClass *RC,
84 unsigned Op0, bool Op0IsKill,
85 unsigned Op1, bool Op1IsKill);
86 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
87 const TargetRegisterClass *RC,
88 unsigned Op0, bool Op0IsKill,
90 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
91 const TargetRegisterClass *RC,
92 unsigned Op0, bool Op0IsKill,
93 const ConstantFP *FPImm);
94 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
95 const TargetRegisterClass *RC,
97 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
98 const TargetRegisterClass *RC,
99 unsigned Op0, bool Op0IsKill,
100 unsigned Op1, bool Op1IsKill,
102 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
103 unsigned Op0, bool Op0IsKill,
106 // Backend specific FastISel code.
107 virtual bool TargetSelectInstruction(const Instruction *I);
108 virtual unsigned TargetMaterializeConstant(const Constant *C);
110 #include "ARMGenFastISel.inc"
112 // Instruction selection routines.
113 virtual bool ARMSelectLoad(const Instruction *I);
114 virtual bool ARMSelectStore(const Instruction *I);
115 virtual bool ARMSelectBranch(const Instruction *I);
116 virtual bool ARMSelectCmp(const Instruction *I);
117 virtual bool ARMSelectFPExt(const Instruction *I);
118 virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
122 bool isTypeLegal(const Type *Ty, EVT &VT);
123 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
124 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
125 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
126 bool ARMLoadAlloca(const Instruction *I, EVT VT);
127 bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
128 bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
129 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
130 unsigned ARMMaterializeInt(const Constant *C);
132 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
133 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
136 } // end anonymous namespace
138 // #include "ARMGenCallingConv.inc"
140 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
141 // we don't care about implicit defs here, just places we'll need to add a
142 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
143 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
144 const TargetInstrDesc &TID = MI->getDesc();
145 if (!TID.hasOptionalDef())
148 // Look to see if our OptionalDef is defining CPSR or CCR.
149 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
150 const MachineOperand &MO = MI->getOperand(i);
151 if (!MO.isReg() || !MO.isDef()) continue;
152 if (MO.getReg() == ARM::CPSR)
158 // If the machine is predicable go ahead and add the predicate operands, if
159 // it needs default CC operands add those.
160 const MachineInstrBuilder &
161 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
162 MachineInstr *MI = &*MIB;
164 // Do we use a predicate?
165 if (TII.isPredicable(MI))
168 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
169 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
171 if (DefinesOptionalPredicate(MI, &CPSR)) {
180 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
181 const TargetRegisterClass* RC) {
182 unsigned ResultReg = createResultReg(RC);
183 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
185 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
189 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
190 const TargetRegisterClass *RC,
191 unsigned Op0, bool Op0IsKill) {
192 unsigned ResultReg = createResultReg(RC);
193 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
195 if (II.getNumDefs() >= 1)
196 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
197 .addReg(Op0, Op0IsKill * RegState::Kill));
199 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
200 .addReg(Op0, Op0IsKill * RegState::Kill));
201 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
202 TII.get(TargetOpcode::COPY), ResultReg)
203 .addReg(II.ImplicitDefs[0]));
208 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
209 const TargetRegisterClass *RC,
210 unsigned Op0, bool Op0IsKill,
211 unsigned Op1, bool Op1IsKill) {
212 unsigned ResultReg = createResultReg(RC);
213 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
215 if (II.getNumDefs() >= 1)
216 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
217 .addReg(Op0, Op0IsKill * RegState::Kill)
218 .addReg(Op1, Op1IsKill * RegState::Kill));
220 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
221 .addReg(Op0, Op0IsKill * RegState::Kill)
222 .addReg(Op1, Op1IsKill * RegState::Kill));
223 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
224 TII.get(TargetOpcode::COPY), ResultReg)
225 .addReg(II.ImplicitDefs[0]));
230 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
231 const TargetRegisterClass *RC,
232 unsigned Op0, bool Op0IsKill,
234 unsigned ResultReg = createResultReg(RC);
235 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
237 if (II.getNumDefs() >= 1)
238 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
239 .addReg(Op0, Op0IsKill * RegState::Kill)
242 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
243 .addReg(Op0, Op0IsKill * RegState::Kill)
245 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
246 TII.get(TargetOpcode::COPY), ResultReg)
247 .addReg(II.ImplicitDefs[0]));
252 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
253 const TargetRegisterClass *RC,
254 unsigned Op0, bool Op0IsKill,
255 const ConstantFP *FPImm) {
256 unsigned ResultReg = createResultReg(RC);
257 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
259 if (II.getNumDefs() >= 1)
260 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
261 .addReg(Op0, Op0IsKill * RegState::Kill)
264 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
265 .addReg(Op0, Op0IsKill * RegState::Kill)
267 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
268 TII.get(TargetOpcode::COPY), ResultReg)
269 .addReg(II.ImplicitDefs[0]));
274 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
275 const TargetRegisterClass *RC,
276 unsigned Op0, bool Op0IsKill,
277 unsigned Op1, bool Op1IsKill,
279 unsigned ResultReg = createResultReg(RC);
280 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
282 if (II.getNumDefs() >= 1)
283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
284 .addReg(Op0, Op0IsKill * RegState::Kill)
285 .addReg(Op1, Op1IsKill * RegState::Kill)
288 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
289 .addReg(Op0, Op0IsKill * RegState::Kill)
290 .addReg(Op1, Op1IsKill * RegState::Kill)
292 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
293 TII.get(TargetOpcode::COPY), ResultReg)
294 .addReg(II.ImplicitDefs[0]));
299 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
300 const TargetRegisterClass *RC,
302 unsigned ResultReg = createResultReg(RC);
303 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
305 if (II.getNumDefs() >= 1)
306 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
309 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
311 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
312 TII.get(TargetOpcode::COPY), ResultReg)
313 .addReg(II.ImplicitDefs[0]));
318 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
319 unsigned Op0, bool Op0IsKill,
321 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
322 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
323 "Cannot yet extract from physregs");
324 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
325 DL, TII.get(TargetOpcode::COPY), ResultReg)
326 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
330 // For double width floating point we need to materialize two constants
331 // (the high and the low) into integer registers then use a move to get
332 // the combined constant into an FP reg.
333 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
334 const APFloat Val = CFP->getValueAPF();
335 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
337 // This checks to see if we can use VFP3 instructions to materialize
338 // a constant, otherwise we have to go through the constant pool.
339 if (TLI.isFPImmLegal(Val, VT)) {
340 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
341 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
342 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
348 // No 64-bit at the moment.
349 if (is64bit) return 0;
351 // Load this from the constant pool.
352 unsigned DestReg = ARMMaterializeInt(cast<Constant>(CFP));
354 // If we have a floating point constant we expect it in a floating point
356 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
357 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
358 TII.get(ARM::VMOVRS), MoveReg)
363 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) {
364 // MachineConstantPool wants an explicit alignment.
365 unsigned Align = TD.getPrefTypeAlignment(C->getType());
367 // TODO: Figure out if this is correct.
368 Align = TD.getTypeAllocSize(C->getType());
370 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
372 unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
374 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
375 TII.get(ARM::t2LDRpci))
376 .addReg(DestReg).addConstantPoolIndex(Idx));
378 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
380 .addReg(DestReg).addConstantPoolIndex(Idx)
381 .addReg(0).addImm(0));
386 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
387 EVT VT = TLI.getValueType(C->getType(), true);
389 // Only handle simple types.
390 if (!VT.isSimple()) return 0;
392 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
393 return ARMMaterializeFP(CFP, VT);
394 return ARMMaterializeInt(C);
397 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
398 VT = TLI.getValueType(Ty, true);
400 // Only handle simple types.
401 if (VT == MVT::Other || !VT.isSimple()) return false;
403 // Handle all legal types, i.e. a register that will directly hold this
405 return TLI.isTypeLegal(VT);
408 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
409 if (isTypeLegal(Ty, VT)) return true;
411 // If this is a type than can be sign or zero-extended to a basic operation
412 // go ahead and accept it now.
413 if (VT == MVT::i8 || VT == MVT::i16)
419 // Computes the Reg+Offset to get to an object.
420 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
422 // Some boilerplate from the X86 FastISel.
423 const User *U = NULL;
424 unsigned Opcode = Instruction::UserOp1;
425 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
426 // Don't walk into other basic blocks; it's possible we haven't
427 // visited them yet, so the instructions may not yet be assigned
428 // virtual registers.
429 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
432 Opcode = I->getOpcode();
434 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
435 Opcode = C->getOpcode();
439 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
440 if (Ty->getAddressSpace() > 255)
441 // Fast instruction selection doesn't support the special
447 //errs() << "Failing Opcode is: " << *Op1 << "\n";
449 case Instruction::Alloca: {
450 assert(false && "Alloca should have been handled earlier!");
455 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
456 //errs() << "Failing GV is: " << GV << "\n";
461 // Try to get this in a register if nothing else has worked.
462 Reg = getRegForValue(Obj);
463 if (Reg == 0) return false;
465 // Since the offset may be too large for the load instruction
466 // get the reg+offset into a register.
467 // TODO: Verify the additions work, otherwise we'll need to add the
468 // offset instead of 0 to the instructions and do all sorts of operand
470 // TODO: Optimize this somewhat.
472 ARMCC::CondCodes Pred = ARMCC::AL;
473 unsigned PredReg = 0;
476 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
477 Reg, Reg, Offset, Pred, PredReg,
478 static_cast<const ARMBaseInstrInfo&>(TII));
480 assert(AFI->isThumb2Function());
481 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
482 Reg, Reg, Offset, Pred, PredReg,
483 static_cast<const ARMBaseInstrInfo&>(TII));
490 bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
491 Value *Op0 = I->getOperand(0);
493 // Verify it's an alloca.
494 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
495 DenseMap<const AllocaInst*, int>::iterator SI =
496 FuncInfo.StaticAllocaMap.find(AI);
498 if (SI != FuncInfo.StaticAllocaMap.end()) {
499 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
500 unsigned ResultReg = createResultReg(RC);
501 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
502 ResultReg, SI->second, RC,
503 TM.getRegisterInfo());
504 UpdateValueMap(I, ResultReg);
511 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
512 unsigned Reg, int Offset) {
514 assert(VT.isSimple() && "Non-simple types are invalid here!");
517 switch (VT.getSimpleVT().SimpleTy) {
519 assert(false && "Trying to emit for an unhandled type!");
522 Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
526 Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
530 Opc = isThumb ? ARM::tLDR : ARM::LDR;
534 ResultReg = createResultReg(TLI.getRegClassFor(VT));
536 // TODO: Fix the Addressing modes so that these can share some code.
537 // Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
539 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
540 TII.get(Opc), ResultReg)
541 .addReg(Reg).addImm(Offset).addReg(0));
543 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
544 TII.get(Opc), ResultReg)
545 .addReg(Reg).addReg(0).addImm(Offset));
550 bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
551 Value *Op1 = I->getOperand(1);
553 // Verify it's an alloca.
554 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
555 DenseMap<const AllocaInst*, int>::iterator SI =
556 FuncInfo.StaticAllocaMap.find(AI);
558 if (SI != FuncInfo.StaticAllocaMap.end()) {
559 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
560 assert(SrcReg != 0 && "Nothing to store!");
561 TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
562 SrcReg, true /*isKill*/, SI->second, RC,
563 TM.getRegisterInfo());
570 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
571 unsigned DstReg, int Offset) {
573 switch (VT.getSimpleVT().SimpleTy) {
574 default: return false;
576 case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break;
577 case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break;
578 case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break;
580 if (!Subtarget->hasVFP2()) return false;
584 if (!Subtarget->hasVFP2()) return false;
590 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
591 TII.get(StrOpc), SrcReg)
592 .addReg(DstReg).addImm(Offset).addReg(0));
594 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
595 TII.get(StrOpc), SrcReg)
596 .addReg(DstReg).addReg(0).addImm(Offset));
601 bool ARMFastISel::ARMSelectStore(const Instruction *I) {
602 Value *Op0 = I->getOperand(0);
605 // Yay type legalization
607 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
610 // Get the value to be stored into a register.
611 SrcReg = getRegForValue(Op0);
615 // If we're an alloca we know we have a frame index and can emit the store
617 if (ARMStoreAlloca(I, SrcReg, VT))
620 // Our register and offset with innocuous defaults.
624 // See if we can handle this as Reg + Offset
625 if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
628 if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
634 bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
635 // Verify we have a legal type before going any further.
637 if (!isLoadTypeLegal(I->getType(), VT))
640 // If we're an alloca we know we have a frame index and can emit the load
641 // directly in short order.
642 if (ARMLoadAlloca(I, VT))
645 // Our register and offset with innocuous defaults.
649 // See if we can handle this as Reg + Offset
650 if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
654 if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
656 UpdateValueMap(I, ResultReg);
660 bool ARMFastISel::ARMSelectBranch(const Instruction *I) {
661 const BranchInst *BI = cast<BranchInst>(I);
662 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
663 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
665 // Simple branch support.
666 unsigned CondReg = getRegForValue(BI->getCondition());
667 if (CondReg == 0) return false;
669 unsigned CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
670 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
671 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
672 .addReg(CondReg).addReg(CondReg));
673 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
674 .addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
675 FastEmitBranch(FBB, DL);
676 FuncInfo.MBB->addSuccessor(TBB);
680 bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
681 const CmpInst *CI = cast<CmpInst>(I);
684 const Type *Ty = CI->getOperand(0)->getType();
685 if (!isTypeLegal(Ty, VT))
688 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
689 if (isFloat && !Subtarget->hasVFP2())
693 switch (VT.getSimpleVT().SimpleTy) {
694 default: return false;
695 // TODO: Verify compares.
697 CmpOpc = ARM::VCMPES;
700 CmpOpc = ARM::VCMPED;
703 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
707 unsigned Arg1 = getRegForValue(CI->getOperand(0));
708 if (Arg1 == 0) return false;
710 unsigned Arg2 = getRegForValue(CI->getOperand(1));
711 if (Arg2 == 0) return false;
713 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
714 .addReg(Arg1).addReg(Arg2));
716 // For floating point we need to move the result to a register we can
717 // actually do something with.
719 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
720 TII.get(ARM::FMSTAT)));
724 bool ARMFastISel::ARMSelectFPExt(const Instruction *I) {
725 // Make sure we have VFP and that we're extending float to double.
726 if (!Subtarget->hasVFP2()) return false;
728 Value *V = I->getOperand(0);
729 if (!I->getType()->isDoubleTy() ||
730 !V->getType()->isFloatTy()) return false;
732 unsigned Op = getRegForValue(V);
733 if (Op == 0) return false;
735 unsigned Result = createResultReg(ARM::DPRRegisterClass);
737 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
738 TII.get(ARM::VCVTDS), Result)
740 UpdateValueMap(I, Result);
744 bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
745 EVT VT = TLI.getValueType(I->getType(), true);
747 // We can get here in the case when we want to use NEON for our fp
748 // operations, but can't figure out how to. Just use the vfp instructions
750 // FIXME: It'd be nice to use NEON instructions.
751 const Type *Ty = I->getType();
752 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
753 if (isFloat && !Subtarget->hasVFP2())
756 unsigned Op1 = getRegForValue(I->getOperand(0));
757 if (Op1 == 0) return false;
759 unsigned Op2 = getRegForValue(I->getOperand(1));
760 if (Op2 == 0) return false;
763 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
764 VT.getSimpleVT().SimpleTy == MVT::i64;
766 default: return false;
768 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
771 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
774 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
777 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
778 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
779 TII.get(Opc), ResultReg)
780 .addReg(Op1).addReg(Op2));
784 // TODO: SoftFP support.
785 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
786 // No Thumb-1 for now.
787 if (isThumb && !AFI->isThumb2Function()) return false;
789 switch (I->getOpcode()) {
790 case Instruction::Load:
791 return ARMSelectLoad(I);
792 case Instruction::Store:
793 return ARMSelectStore(I);
794 case Instruction::Br:
795 return ARMSelectBranch(I);
796 case Instruction::ICmp:
797 case Instruction::FCmp:
798 return ARMSelectCmp(I);
799 case Instruction::FPExt:
800 return ARMSelectFPExt(I);
801 case Instruction::FAdd:
802 return ARMSelectBinaryOp(I, ISD::FADD);
803 case Instruction::FSub:
804 return ARMSelectBinaryOp(I, ISD::FSUB);
805 case Instruction::FMul:
806 return ARMSelectBinaryOp(I, ISD::FMUL);
813 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
814 if (EnableARMFastISel) return new ARMFastISel(funcInfo);