1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/GlobalVariable.h"
37 #include "llvm/IR/Instructions.h"
38 #include "llvm/IR/IntrinsicInst.h"
39 #include "llvm/IR/Module.h"
40 #include "llvm/IR/Operator.h"
41 #include "llvm/Support/CallSite.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/GetElementPtrTypeIterator.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetLowering.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetOptions.h"
51 extern cl::opt<bool> EnableARMLongCalls;
55 // All possible address modes, plus some.
56 typedef struct Address {
69 // Innocuous defaults for our address.
71 : BaseType(RegBase), Offset(0) {
76 class ARMFastISel : public FastISel {
78 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
79 /// make the right decision when generating code for different targets.
80 const ARMSubtarget *Subtarget;
81 const TargetMachine &TM;
82 const TargetInstrInfo &TII;
83 const TargetLowering &TLI;
86 // Convenience variables to avoid some queries.
91 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
92 const TargetLibraryInfo *libInfo)
93 : FastISel(funcInfo, libInfo),
94 TM(funcInfo.MF->getTarget()),
95 TII(*TM.getInstrInfo()),
96 TLI(*TM.getTargetLowering()) {
97 Subtarget = &TM.getSubtarget<ARMSubtarget>();
98 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
99 isThumb2 = AFI->isThumbFunction();
100 Context = &funcInfo.Fn->getContext();
103 // Code from FastISel.cpp.
105 unsigned FastEmitInst_(unsigned MachineInstOpcode,
106 const TargetRegisterClass *RC);
107 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
108 const TargetRegisterClass *RC,
109 unsigned Op0, bool Op0IsKill);
110 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
111 const TargetRegisterClass *RC,
112 unsigned Op0, bool Op0IsKill,
113 unsigned Op1, bool Op1IsKill);
114 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
115 const TargetRegisterClass *RC,
116 unsigned Op0, bool Op0IsKill,
117 unsigned Op1, bool Op1IsKill,
118 unsigned Op2, bool Op2IsKill);
119 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
120 const TargetRegisterClass *RC,
121 unsigned Op0, bool Op0IsKill,
123 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
124 const TargetRegisterClass *RC,
125 unsigned Op0, bool Op0IsKill,
126 const ConstantFP *FPImm);
127 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
128 const TargetRegisterClass *RC,
129 unsigned Op0, bool Op0IsKill,
130 unsigned Op1, bool Op1IsKill,
132 unsigned FastEmitInst_i(unsigned MachineInstOpcode,
133 const TargetRegisterClass *RC,
135 unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
136 const TargetRegisterClass *RC,
137 uint64_t Imm1, uint64_t Imm2);
139 unsigned FastEmitInst_extractsubreg(MVT RetVT,
140 unsigned Op0, bool Op0IsKill,
143 // Backend specific FastISel code.
145 virtual bool TargetSelectInstruction(const Instruction *I);
146 virtual unsigned TargetMaterializeConstant(const Constant *C);
147 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
148 virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
150 virtual bool FastLowerArguments();
152 #include "ARMGenFastISel.inc"
154 // Instruction selection routines.
156 bool SelectLoad(const Instruction *I);
157 bool SelectStore(const Instruction *I);
158 bool SelectBranch(const Instruction *I);
159 bool SelectIndirectBr(const Instruction *I);
160 bool SelectCmp(const Instruction *I);
161 bool SelectFPExt(const Instruction *I);
162 bool SelectFPTrunc(const Instruction *I);
163 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
164 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
165 bool SelectIToFP(const Instruction *I, bool isSigned);
166 bool SelectFPToI(const Instruction *I, bool isSigned);
167 bool SelectDiv(const Instruction *I, bool isSigned);
168 bool SelectRem(const Instruction *I, bool isSigned);
169 bool SelectCall(const Instruction *I, const char *IntrMemName);
170 bool SelectIntrinsicCall(const IntrinsicInst &I);
171 bool SelectSelect(const Instruction *I);
172 bool SelectRet(const Instruction *I);
173 bool SelectTrunc(const Instruction *I);
174 bool SelectIntExt(const Instruction *I);
175 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
179 bool isTypeLegal(Type *Ty, MVT &VT);
180 bool isLoadTypeLegal(Type *Ty, MVT &VT);
181 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
183 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
184 unsigned Alignment = 0, bool isZExt = true,
185 bool allocReg = true);
186 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
187 unsigned Alignment = 0);
188 bool ARMComputeAddress(const Value *Obj, Address &Addr);
189 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
190 bool ARMIsMemCpySmall(uint64_t Len);
191 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
193 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
194 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
195 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
196 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
197 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
198 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
199 unsigned ARMSelectCallOp(bool UseReg);
200 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
202 // Call handling routines.
204 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
207 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
208 SmallVectorImpl<unsigned> &ArgRegs,
209 SmallVectorImpl<MVT> &ArgVTs,
210 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
211 SmallVectorImpl<unsigned> &RegArgs,
215 unsigned getLibcallReg(const Twine &Name);
216 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
217 const Instruction *I, CallingConv::ID CC,
218 unsigned &NumBytes, bool isVarArg);
219 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
221 // OptionalDef handling routines.
223 bool isARMNEONPred(const MachineInstr *MI);
224 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
225 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
226 void AddLoadStoreOperands(MVT VT, Address &Addr,
227 const MachineInstrBuilder &MIB,
228 unsigned Flags, bool useAM3);
231 } // end anonymous namespace
233 #include "ARMGenCallingConv.inc"
235 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
236 // we don't care about implicit defs here, just places we'll need to add a
237 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
238 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
239 if (!MI->hasOptionalDef())
242 // Look to see if our OptionalDef is defining CPSR or CCR.
243 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
244 const MachineOperand &MO = MI->getOperand(i);
245 if (!MO.isReg() || !MO.isDef()) continue;
246 if (MO.getReg() == ARM::CPSR)
252 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
253 const MCInstrDesc &MCID = MI->getDesc();
255 // If we're a thumb2 or not NEON function we were handled via isPredicable.
256 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
257 AFI->isThumb2Function())
260 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
261 if (MCID.OpInfo[i].isPredicate())
267 // If the machine is predicable go ahead and add the predicate operands, if
268 // it needs default CC operands add those.
269 // TODO: If we want to support thumb1 then we'll need to deal with optional
270 // CPSR defs that need to be added before the remaining operands. See s_cc_out
271 // for descriptions why.
272 const MachineInstrBuilder &
273 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
274 MachineInstr *MI = &*MIB;
276 // Do we use a predicate? or...
277 // Are we NEON in ARM mode and have a predicate operand? If so, I know
278 // we're not predicable but add it anyways.
279 if (TII.isPredicable(MI) || isARMNEONPred(MI))
282 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
283 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
285 if (DefinesOptionalPredicate(MI, &CPSR)) {
294 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
295 const TargetRegisterClass* RC) {
296 unsigned ResultReg = createResultReg(RC);
297 const MCInstrDesc &II = TII.get(MachineInstOpcode);
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
303 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
304 const TargetRegisterClass *RC,
305 unsigned Op0, bool Op0IsKill) {
306 unsigned ResultReg = createResultReg(RC);
307 const MCInstrDesc &II = TII.get(MachineInstOpcode);
309 if (II.getNumDefs() >= 1) {
310 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
311 .addReg(Op0, Op0IsKill * RegState::Kill));
313 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
314 .addReg(Op0, Op0IsKill * RegState::Kill));
315 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
316 TII.get(TargetOpcode::COPY), ResultReg)
317 .addReg(II.ImplicitDefs[0]));
322 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
323 const TargetRegisterClass *RC,
324 unsigned Op0, bool Op0IsKill,
325 unsigned Op1, bool Op1IsKill) {
326 unsigned ResultReg = createResultReg(RC);
327 const MCInstrDesc &II = TII.get(MachineInstOpcode);
329 if (II.getNumDefs() >= 1) {
330 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
331 .addReg(Op0, Op0IsKill * RegState::Kill)
332 .addReg(Op1, Op1IsKill * RegState::Kill));
334 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
335 .addReg(Op0, Op0IsKill * RegState::Kill)
336 .addReg(Op1, Op1IsKill * RegState::Kill));
337 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
338 TII.get(TargetOpcode::COPY), ResultReg)
339 .addReg(II.ImplicitDefs[0]));
344 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
345 const TargetRegisterClass *RC,
346 unsigned Op0, bool Op0IsKill,
347 unsigned Op1, bool Op1IsKill,
348 unsigned Op2, bool Op2IsKill) {
349 unsigned ResultReg = createResultReg(RC);
350 const MCInstrDesc &II = TII.get(MachineInstOpcode);
352 if (II.getNumDefs() >= 1) {
353 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
354 .addReg(Op0, Op0IsKill * RegState::Kill)
355 .addReg(Op1, Op1IsKill * RegState::Kill)
356 .addReg(Op2, Op2IsKill * RegState::Kill));
358 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
359 .addReg(Op0, Op0IsKill * RegState::Kill)
360 .addReg(Op1, Op1IsKill * RegState::Kill)
361 .addReg(Op2, Op2IsKill * RegState::Kill));
362 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
363 TII.get(TargetOpcode::COPY), ResultReg)
364 .addReg(II.ImplicitDefs[0]));
369 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
370 const TargetRegisterClass *RC,
371 unsigned Op0, bool Op0IsKill,
373 unsigned ResultReg = createResultReg(RC);
374 const MCInstrDesc &II = TII.get(MachineInstOpcode);
376 if (II.getNumDefs() >= 1) {
377 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
378 .addReg(Op0, Op0IsKill * RegState::Kill)
381 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
382 .addReg(Op0, Op0IsKill * RegState::Kill)
384 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
385 TII.get(TargetOpcode::COPY), ResultReg)
386 .addReg(II.ImplicitDefs[0]));
391 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
392 const TargetRegisterClass *RC,
393 unsigned Op0, bool Op0IsKill,
394 const ConstantFP *FPImm) {
395 unsigned ResultReg = createResultReg(RC);
396 const MCInstrDesc &II = TII.get(MachineInstOpcode);
398 if (II.getNumDefs() >= 1) {
399 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
400 .addReg(Op0, Op0IsKill * RegState::Kill)
403 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
404 .addReg(Op0, Op0IsKill * RegState::Kill)
406 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
407 TII.get(TargetOpcode::COPY), ResultReg)
408 .addReg(II.ImplicitDefs[0]));
413 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
414 const TargetRegisterClass *RC,
415 unsigned Op0, bool Op0IsKill,
416 unsigned Op1, bool Op1IsKill,
418 unsigned ResultReg = createResultReg(RC);
419 const MCInstrDesc &II = TII.get(MachineInstOpcode);
421 if (II.getNumDefs() >= 1) {
422 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
423 .addReg(Op0, Op0IsKill * RegState::Kill)
424 .addReg(Op1, Op1IsKill * RegState::Kill)
427 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
428 .addReg(Op0, Op0IsKill * RegState::Kill)
429 .addReg(Op1, Op1IsKill * RegState::Kill)
431 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
432 TII.get(TargetOpcode::COPY), ResultReg)
433 .addReg(II.ImplicitDefs[0]));
438 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
439 const TargetRegisterClass *RC,
441 unsigned ResultReg = createResultReg(RC);
442 const MCInstrDesc &II = TII.get(MachineInstOpcode);
444 if (II.getNumDefs() >= 1) {
445 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
450 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
451 TII.get(TargetOpcode::COPY), ResultReg)
452 .addReg(II.ImplicitDefs[0]));
457 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
458 const TargetRegisterClass *RC,
459 uint64_t Imm1, uint64_t Imm2) {
460 unsigned ResultReg = createResultReg(RC);
461 const MCInstrDesc &II = TII.get(MachineInstOpcode);
463 if (II.getNumDefs() >= 1) {
464 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
465 .addImm(Imm1).addImm(Imm2));
467 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
468 .addImm(Imm1).addImm(Imm2));
469 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
470 TII.get(TargetOpcode::COPY),
472 .addReg(II.ImplicitDefs[0]));
477 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
478 unsigned Op0, bool Op0IsKill,
480 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
481 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
482 "Cannot yet extract from physregs");
484 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
485 DL, TII.get(TargetOpcode::COPY), ResultReg)
486 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
490 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
491 // checks from the various callers.
492 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
493 if (VT == MVT::f64) return 0;
495 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
496 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
497 TII.get(ARM::VMOVSR), MoveReg)
502 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
503 if (VT == MVT::i64) return 0;
505 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
506 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
507 TII.get(ARM::VMOVRS), MoveReg)
512 // For double width floating point we need to materialize two constants
513 // (the high and the low) into integer registers then use a move to get
514 // the combined constant into an FP reg.
515 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
516 const APFloat Val = CFP->getValueAPF();
517 bool is64bit = VT == MVT::f64;
519 // This checks to see if we can use VFP3 instructions to materialize
520 // a constant, otherwise we have to go through the constant pool.
521 if (TLI.isFPImmLegal(Val, VT)) {
525 Imm = ARM_AM::getFP64Imm(Val);
528 Imm = ARM_AM::getFP32Imm(Val);
531 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
532 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
538 // Require VFP2 for loading fp constants.
539 if (!Subtarget->hasVFP2()) return false;
541 // MachineConstantPool wants an explicit alignment.
542 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
544 // TODO: Figure out if this is correct.
545 Align = TD.getTypeAllocSize(CFP->getType());
547 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
548 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
549 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
551 // The extra reg is for addrmode5.
552 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
554 .addConstantPoolIndex(Idx)
559 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
561 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
564 // If we can do this in a single instruction without a constant pool entry
566 const ConstantInt *CI = cast<ConstantInt>(C);
567 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
568 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
569 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
571 unsigned ImmReg = createResultReg(RC);
572 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
573 TII.get(Opc), ImmReg)
574 .addImm(CI->getZExtValue()));
578 // Use MVN to emit negative constants.
579 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
580 unsigned Imm = (unsigned)~(CI->getSExtValue());
581 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
582 (ARM_AM::getSOImmVal(Imm) != -1);
584 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
585 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
586 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
587 TII.get(Opc), ImmReg)
593 // Load from constant pool. For now 32-bit only.
597 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
599 // MachineConstantPool wants an explicit alignment.
600 unsigned Align = TD.getPrefTypeAlignment(C->getType());
602 // TODO: Figure out if this is correct.
603 Align = TD.getTypeAllocSize(C->getType());
605 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
608 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
609 TII.get(ARM::t2LDRpci), DestReg)
610 .addConstantPoolIndex(Idx));
612 // The extra immediate is for addrmode2.
613 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
614 TII.get(ARM::LDRcp), DestReg)
615 .addConstantPoolIndex(Idx)
621 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
622 // For now 32-bit only.
623 if (VT != MVT::i32) return 0;
625 Reloc::Model RelocM = TM.getRelocationModel();
626 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
627 const TargetRegisterClass *RC = isThumb2 ?
628 (const TargetRegisterClass*)&ARM::rGPRRegClass :
629 (const TargetRegisterClass*)&ARM::GPRRegClass;
630 unsigned DestReg = createResultReg(RC);
632 // FastISel TLS support on non-Darwin is broken, punt to SelectionDAG.
633 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
634 bool IsThreadLocal = GVar && GVar->isThreadLocal();
635 if (!Subtarget->isTargetDarwin() && IsThreadLocal) return 0;
637 // Use movw+movt when possible, it avoids constant pool entries.
638 // Darwin targets don't support movt with Reloc::Static, see
639 // ARMTargetLowering::LowerGlobalAddressDarwin. Other targets only support
640 // static movt relocations.
641 if (Subtarget->useMovt() &&
642 Subtarget->isTargetDarwin() == (RelocM != Reloc::Static)) {
646 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
648 case Reloc::DynamicNoPIC:
649 Opc = isThumb2 ? ARM::t2MOV_ga_dyn : ARM::MOV_ga_dyn;
652 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
655 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
656 DestReg).addGlobalAddress(GV));
658 // MachineConstantPool wants an explicit alignment.
659 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
661 // TODO: Figure out if this is correct.
662 Align = TD.getTypeAllocSize(GV->getType());
665 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
666 return ARMLowerPICELF(GV, Align, VT);
669 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
670 (Subtarget->isThumb() ? 4 : 8);
671 unsigned Id = AFI->createPICLabelUId();
672 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
675 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
678 MachineInstrBuilder MIB;
680 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
681 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
682 .addConstantPoolIndex(Idx);
683 if (RelocM == Reloc::PIC_)
685 AddOptionalDefs(MIB);
687 // The extra immediate is for addrmode2.
688 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
690 .addConstantPoolIndex(Idx)
692 AddOptionalDefs(MIB);
694 if (RelocM == Reloc::PIC_) {
695 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
696 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
698 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
699 DL, TII.get(Opc), NewDestReg)
702 AddOptionalDefs(MIB);
709 MachineInstrBuilder MIB;
710 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
712 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
713 TII.get(ARM::t2LDRi12), NewDestReg)
717 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
721 DestReg = NewDestReg;
722 AddOptionalDefs(MIB);
728 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
729 EVT CEVT = TLI.getValueType(C->getType(), true);
731 // Only handle simple types.
732 if (!CEVT.isSimple()) return 0;
733 MVT VT = CEVT.getSimpleVT();
735 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
736 return ARMMaterializeFP(CFP, VT);
737 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
738 return ARMMaterializeGV(GV, VT);
739 else if (isa<ConstantInt>(C))
740 return ARMMaterializeInt(C, VT);
745 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
747 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
748 // Don't handle dynamic allocas.
749 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
752 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
754 DenseMap<const AllocaInst*, int>::iterator SI =
755 FuncInfo.StaticAllocaMap.find(AI);
757 // This will get lowered later into the correct offsets and registers
758 // via rewriteXFrameIndex.
759 if (SI != FuncInfo.StaticAllocaMap.end()) {
760 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
761 unsigned ResultReg = createResultReg(RC);
762 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
763 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
764 TII.get(Opc), ResultReg)
765 .addFrameIndex(SI->second)
773 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
774 EVT evt = TLI.getValueType(Ty, true);
776 // Only handle simple types.
777 if (evt == MVT::Other || !evt.isSimple()) return false;
778 VT = evt.getSimpleVT();
780 // Handle all legal types, i.e. a register that will directly hold this
782 return TLI.isTypeLegal(VT);
785 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
786 if (isTypeLegal(Ty, VT)) return true;
788 // If this is a type than can be sign or zero-extended to a basic operation
789 // go ahead and accept it now.
790 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
796 // Computes the address to get to an object.
797 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
798 // Some boilerplate from the X86 FastISel.
799 const User *U = NULL;
800 unsigned Opcode = Instruction::UserOp1;
801 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
802 // Don't walk into other basic blocks unless the object is an alloca from
803 // another block, otherwise it may not have a virtual register assigned.
804 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
805 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
806 Opcode = I->getOpcode();
809 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
810 Opcode = C->getOpcode();
814 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
815 if (Ty->getAddressSpace() > 255)
816 // Fast instruction selection doesn't support the special
823 case Instruction::BitCast:
824 // Look through bitcasts.
825 return ARMComputeAddress(U->getOperand(0), Addr);
826 case Instruction::IntToPtr:
827 // Look past no-op inttoptrs.
828 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
829 return ARMComputeAddress(U->getOperand(0), Addr);
831 case Instruction::PtrToInt:
832 // Look past no-op ptrtoints.
833 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
834 return ARMComputeAddress(U->getOperand(0), Addr);
836 case Instruction::GetElementPtr: {
837 Address SavedAddr = Addr;
838 int TmpOffset = Addr.Offset;
840 // Iterate through the GEP folding the constants into offsets where
842 gep_type_iterator GTI = gep_type_begin(U);
843 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
844 i != e; ++i, ++GTI) {
845 const Value *Op = *i;
846 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
847 const StructLayout *SL = TD.getStructLayout(STy);
848 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
849 TmpOffset += SL->getElementOffset(Idx);
851 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
853 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
854 // Constant-offset addressing.
855 TmpOffset += CI->getSExtValue() * S;
858 if (isa<AddOperator>(Op) &&
859 (!isa<Instruction>(Op) ||
860 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
862 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
863 // An add (in the same block) with a constant operand. Fold the
866 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
867 TmpOffset += CI->getSExtValue() * S;
868 // Iterate on the other operand.
869 Op = cast<AddOperator>(Op)->getOperand(0);
873 goto unsupported_gep;
878 // Try to grab the base operand now.
879 Addr.Offset = TmpOffset;
880 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
882 // We failed, restore everything and try the other options.
888 case Instruction::Alloca: {
889 const AllocaInst *AI = cast<AllocaInst>(Obj);
890 DenseMap<const AllocaInst*, int>::iterator SI =
891 FuncInfo.StaticAllocaMap.find(AI);
892 if (SI != FuncInfo.StaticAllocaMap.end()) {
893 Addr.BaseType = Address::FrameIndexBase;
894 Addr.Base.FI = SI->second;
901 // Try to get this in a register if nothing else has worked.
902 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
903 return Addr.Base.Reg != 0;
906 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
907 bool needsLowering = false;
908 switch (VT.SimpleTy) {
909 default: llvm_unreachable("Unhandled load/store type!");
915 // Integer loads/stores handle 12-bit offsets.
916 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
917 // Handle negative offsets.
918 if (needsLowering && isThumb2)
919 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
922 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
923 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
928 // Floating point operands handle 8-bit offsets.
929 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
933 // If this is a stack pointer and the offset needs to be simplified then
934 // put the alloca address into a register, set the base type back to
935 // register and continue. This should almost never happen.
936 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
937 const TargetRegisterClass *RC = isThumb2 ?
938 (const TargetRegisterClass*)&ARM::tGPRRegClass :
939 (const TargetRegisterClass*)&ARM::GPRRegClass;
940 unsigned ResultReg = createResultReg(RC);
941 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
942 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
943 TII.get(Opc), ResultReg)
944 .addFrameIndex(Addr.Base.FI)
946 Addr.Base.Reg = ResultReg;
947 Addr.BaseType = Address::RegBase;
950 // Since the offset is too large for the load/store instruction
951 // get the reg+offset into a register.
953 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
954 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
959 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
960 const MachineInstrBuilder &MIB,
961 unsigned Flags, bool useAM3) {
962 // addrmode5 output depends on the selection dag addressing dividing the
963 // offset by 4 that it then later multiplies. Do this here as well.
964 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
967 // Frame base works a bit differently. Handle it separately.
968 if (Addr.BaseType == Address::FrameIndexBase) {
969 int FI = Addr.Base.FI;
970 int Offset = Addr.Offset;
971 MachineMemOperand *MMO =
972 FuncInfo.MF->getMachineMemOperand(
973 MachinePointerInfo::getFixedStack(FI, Offset),
975 MFI.getObjectSize(FI),
976 MFI.getObjectAlignment(FI));
977 // Now add the rest of the operands.
978 MIB.addFrameIndex(FI);
980 // ARM halfword load/stores and signed byte loads need an additional
983 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
987 MIB.addImm(Addr.Offset);
989 MIB.addMemOperand(MMO);
991 // Now add the rest of the operands.
992 MIB.addReg(Addr.Base.Reg);
994 // ARM halfword load/stores and signed byte loads need an additional
997 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
1001 MIB.addImm(Addr.Offset);
1004 AddOptionalDefs(MIB);
1007 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
1008 unsigned Alignment, bool isZExt, bool allocReg) {
1010 bool useAM3 = false;
1011 bool needVMOV = false;
1012 const TargetRegisterClass *RC;
1013 switch (VT.SimpleTy) {
1014 // This is mostly going to be Neon/vector support.
1015 default: return false;
1019 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1020 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
1022 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
1031 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1034 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1038 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1039 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
1041 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1043 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1046 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1049 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1053 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1056 Opc = ARM::t2LDRi12;
1060 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1063 if (!Subtarget->hasVFP2()) return false;
1064 // Unaligned loads need special handling. Floats require word-alignment.
1065 if (Alignment && Alignment < 4) {
1068 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1069 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1072 RC = TLI.getRegClassFor(VT);
1076 if (!Subtarget->hasVFP2()) return false;
1077 // FIXME: Unaligned loads need special handling. Doublewords require
1079 if (Alignment && Alignment < 4)
1083 RC = TLI.getRegClassFor(VT);
1086 // Simplify this down to something we can handle.
1087 ARMSimplifyAddress(Addr, VT, useAM3);
1089 // Create the base instruction, then add the operands.
1091 ResultReg = createResultReg(RC);
1092 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1093 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1094 TII.get(Opc), ResultReg);
1095 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1097 // If we had an unaligned load of a float we've converted it to an regular
1098 // load. Now we must move from the GRP to the FP register.
1100 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1101 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1102 TII.get(ARM::VMOVSR), MoveReg)
1103 .addReg(ResultReg));
1104 ResultReg = MoveReg;
1109 bool ARMFastISel::SelectLoad(const Instruction *I) {
1110 // Atomic loads need special handling.
1111 if (cast<LoadInst>(I)->isAtomic())
1114 // Verify we have a legal type before going any further.
1116 if (!isLoadTypeLegal(I->getType(), VT))
1119 // See if we can handle this address.
1121 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1124 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1126 UpdateValueMap(I, ResultReg);
1130 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1131 unsigned Alignment) {
1133 bool useAM3 = false;
1134 switch (VT.SimpleTy) {
1135 // This is mostly going to be Neon/vector support.
1136 default: return false;
1138 unsigned Res = createResultReg(isThumb2 ?
1139 (const TargetRegisterClass*)&ARM::tGPRRegClass :
1140 (const TargetRegisterClass*)&ARM::GPRRegClass);
1141 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1142 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1144 .addReg(SrcReg).addImm(1));
1146 } // Fallthrough here.
1149 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1150 StrOpc = ARM::t2STRBi8;
1152 StrOpc = ARM::t2STRBi12;
1154 StrOpc = ARM::STRBi12;
1158 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1162 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1163 StrOpc = ARM::t2STRHi8;
1165 StrOpc = ARM::t2STRHi12;
1172 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1176 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1177 StrOpc = ARM::t2STRi8;
1179 StrOpc = ARM::t2STRi12;
1181 StrOpc = ARM::STRi12;
1185 if (!Subtarget->hasVFP2()) return false;
1186 // Unaligned stores need special handling. Floats require word-alignment.
1187 if (Alignment && Alignment < 4) {
1188 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1189 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1190 TII.get(ARM::VMOVRS), MoveReg)
1194 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1196 StrOpc = ARM::VSTRS;
1200 if (!Subtarget->hasVFP2()) return false;
1201 // FIXME: Unaligned stores need special handling. Doublewords require
1203 if (Alignment && Alignment < 4)
1206 StrOpc = ARM::VSTRD;
1209 // Simplify this down to something we can handle.
1210 ARMSimplifyAddress(Addr, VT, useAM3);
1212 // Create the base instruction, then add the operands.
1213 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1216 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1220 bool ARMFastISel::SelectStore(const Instruction *I) {
1221 Value *Op0 = I->getOperand(0);
1222 unsigned SrcReg = 0;
1224 // Atomic stores need special handling.
1225 if (cast<StoreInst>(I)->isAtomic())
1228 // Verify we have a legal type before going any further.
1230 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1233 // Get the value to be stored into a register.
1234 SrcReg = getRegForValue(Op0);
1235 if (SrcReg == 0) return false;
1237 // See if we can handle this address.
1239 if (!ARMComputeAddress(I->getOperand(1), Addr))
1242 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1247 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1249 // Needs two compares...
1250 case CmpInst::FCMP_ONE:
1251 case CmpInst::FCMP_UEQ:
1253 // AL is our "false" for now. The other two need more compares.
1255 case CmpInst::ICMP_EQ:
1256 case CmpInst::FCMP_OEQ:
1258 case CmpInst::ICMP_SGT:
1259 case CmpInst::FCMP_OGT:
1261 case CmpInst::ICMP_SGE:
1262 case CmpInst::FCMP_OGE:
1264 case CmpInst::ICMP_UGT:
1265 case CmpInst::FCMP_UGT:
1267 case CmpInst::FCMP_OLT:
1269 case CmpInst::ICMP_ULE:
1270 case CmpInst::FCMP_OLE:
1272 case CmpInst::FCMP_ORD:
1274 case CmpInst::FCMP_UNO:
1276 case CmpInst::FCMP_UGE:
1278 case CmpInst::ICMP_SLT:
1279 case CmpInst::FCMP_ULT:
1281 case CmpInst::ICMP_SLE:
1282 case CmpInst::FCMP_ULE:
1284 case CmpInst::FCMP_UNE:
1285 case CmpInst::ICMP_NE:
1287 case CmpInst::ICMP_UGE:
1289 case CmpInst::ICMP_ULT:
1294 bool ARMFastISel::SelectBranch(const Instruction *I) {
1295 const BranchInst *BI = cast<BranchInst>(I);
1296 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1297 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1299 // Simple branch support.
1301 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1303 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1304 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1306 // Get the compare predicate.
1307 // Try to take advantage of fallthrough opportunities.
1308 CmpInst::Predicate Predicate = CI->getPredicate();
1309 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1310 std::swap(TBB, FBB);
1311 Predicate = CmpInst::getInversePredicate(Predicate);
1314 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1316 // We may not handle every CC for now.
1317 if (ARMPred == ARMCC::AL) return false;
1319 // Emit the compare.
1320 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1323 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1324 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1325 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1326 FastEmitBranch(FBB, DL);
1327 FuncInfo.MBB->addSuccessor(TBB);
1330 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1332 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1333 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1334 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1335 unsigned OpReg = getRegForValue(TI->getOperand(0));
1336 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1338 .addReg(OpReg).addImm(1));
1340 unsigned CCMode = ARMCC::NE;
1341 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1342 std::swap(TBB, FBB);
1346 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1347 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1348 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1350 FastEmitBranch(FBB, DL);
1351 FuncInfo.MBB->addSuccessor(TBB);
1354 } else if (const ConstantInt *CI =
1355 dyn_cast<ConstantInt>(BI->getCondition())) {
1356 uint64_t Imm = CI->getZExtValue();
1357 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1358 FastEmitBranch(Target, DL);
1362 unsigned CmpReg = getRegForValue(BI->getCondition());
1363 if (CmpReg == 0) return false;
1365 // We've been divorced from our compare! Our block was split, and
1366 // now our compare lives in a predecessor block. We musn't
1367 // re-compare here, as the children of the compare aren't guaranteed
1368 // live across the block boundary (we *could* check for this).
1369 // Regardless, the compare has been done in the predecessor block,
1370 // and it left a value for us in a virtual register. Ergo, we test
1371 // the one-bit value left in the virtual register.
1372 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1373 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1374 .addReg(CmpReg).addImm(1));
1376 unsigned CCMode = ARMCC::NE;
1377 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1378 std::swap(TBB, FBB);
1382 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1383 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1384 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1385 FastEmitBranch(FBB, DL);
1386 FuncInfo.MBB->addSuccessor(TBB);
1390 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1391 unsigned AddrReg = getRegForValue(I->getOperand(0));
1392 if (AddrReg == 0) return false;
1394 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1395 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
1398 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1399 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1400 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1405 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1407 Type *Ty = Src1Value->getType();
1408 EVT SrcEVT = TLI.getValueType(Ty, true);
1409 if (!SrcEVT.isSimple()) return false;
1410 MVT SrcVT = SrcEVT.getSimpleVT();
1412 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1413 if (isFloat && !Subtarget->hasVFP2())
1416 // Check to see if the 2nd operand is a constant that we can encode directly
1419 bool UseImm = false;
1420 bool isNegativeImm = false;
1421 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1422 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1423 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1424 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1426 const APInt &CIVal = ConstInt->getValue();
1427 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1428 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1429 // then a cmn, because there is no way to represent 2147483648 as a
1430 // signed 32-bit int.
1431 if (Imm < 0 && Imm != (int)0x80000000) {
1432 isNegativeImm = true;
1435 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1436 (ARM_AM::getSOImmVal(Imm) != -1);
1438 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1439 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1440 if (ConstFP->isZero() && !ConstFP->isNegative())
1446 bool needsExt = false;
1447 switch (SrcVT.SimpleTy) {
1448 default: return false;
1449 // TODO: Verify compares.
1452 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1456 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1462 // Intentional fall-through.
1466 CmpOpc = ARM::t2CMPrr;
1468 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1471 CmpOpc = ARM::CMPrr;
1473 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1478 unsigned SrcReg1 = getRegForValue(Src1Value);
1479 if (SrcReg1 == 0) return false;
1481 unsigned SrcReg2 = 0;
1483 SrcReg2 = getRegForValue(Src2Value);
1484 if (SrcReg2 == 0) return false;
1487 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1489 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1490 if (SrcReg1 == 0) return false;
1492 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1493 if (SrcReg2 == 0) return false;
1498 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1500 .addReg(SrcReg1).addReg(SrcReg2));
1502 MachineInstrBuilder MIB;
1503 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1506 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1509 AddOptionalDefs(MIB);
1512 // For floating point we need to move the result to a comparison register
1513 // that we can then use for branches.
1514 if (Ty->isFloatTy() || Ty->isDoubleTy())
1515 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1516 TII.get(ARM::FMSTAT)));
1520 bool ARMFastISel::SelectCmp(const Instruction *I) {
1521 const CmpInst *CI = cast<CmpInst>(I);
1523 // Get the compare predicate.
1524 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1526 // We may not handle every CC for now.
1527 if (ARMPred == ARMCC::AL) return false;
1529 // Emit the compare.
1530 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1533 // Now set a register based on the comparison. Explicitly set the predicates
1535 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1536 const TargetRegisterClass *RC = isThumb2 ?
1537 (const TargetRegisterClass*)&ARM::rGPRRegClass :
1538 (const TargetRegisterClass*)&ARM::GPRRegClass;
1539 unsigned DestReg = createResultReg(RC);
1540 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1541 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1542 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1543 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1544 .addReg(ZeroReg).addImm(1)
1545 .addImm(ARMPred).addReg(ARM::CPSR);
1547 UpdateValueMap(I, DestReg);
1551 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1552 // Make sure we have VFP and that we're extending float to double.
1553 if (!Subtarget->hasVFP2()) return false;
1555 Value *V = I->getOperand(0);
1556 if (!I->getType()->isDoubleTy() ||
1557 !V->getType()->isFloatTy()) return false;
1559 unsigned Op = getRegForValue(V);
1560 if (Op == 0) return false;
1562 unsigned Result = createResultReg(&ARM::DPRRegClass);
1563 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1564 TII.get(ARM::VCVTDS), Result)
1566 UpdateValueMap(I, Result);
1570 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1571 // Make sure we have VFP and that we're truncating double to float.
1572 if (!Subtarget->hasVFP2()) return false;
1574 Value *V = I->getOperand(0);
1575 if (!(I->getType()->isFloatTy() &&
1576 V->getType()->isDoubleTy())) return false;
1578 unsigned Op = getRegForValue(V);
1579 if (Op == 0) return false;
1581 unsigned Result = createResultReg(&ARM::SPRRegClass);
1582 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1583 TII.get(ARM::VCVTSD), Result)
1585 UpdateValueMap(I, Result);
1589 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1590 // Make sure we have VFP.
1591 if (!Subtarget->hasVFP2()) return false;
1594 Type *Ty = I->getType();
1595 if (!isTypeLegal(Ty, DstVT))
1598 Value *Src = I->getOperand(0);
1599 EVT SrcEVT = TLI.getValueType(Src->getType(), true);
1600 if (!SrcEVT.isSimple())
1602 MVT SrcVT = SrcEVT.getSimpleVT();
1603 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1606 unsigned SrcReg = getRegForValue(Src);
1607 if (SrcReg == 0) return false;
1609 // Handle sign-extension.
1610 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1611 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1612 /*isZExt*/!isSigned);
1613 if (SrcReg == 0) return false;
1616 // The conversion routine works on fp-reg to fp-reg and the operand above
1617 // was an integer, move it to the fp registers if possible.
1618 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1619 if (FP == 0) return false;
1622 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1623 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1626 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1627 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1630 UpdateValueMap(I, ResultReg);
1634 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1635 // Make sure we have VFP.
1636 if (!Subtarget->hasVFP2()) return false;
1639 Type *RetTy = I->getType();
1640 if (!isTypeLegal(RetTy, DstVT))
1643 unsigned Op = getRegForValue(I->getOperand(0));
1644 if (Op == 0) return false;
1647 Type *OpTy = I->getOperand(0)->getType();
1648 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1649 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1652 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1653 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1654 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1658 // This result needs to be in an integer register, but the conversion only
1659 // takes place in fp-regs.
1660 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1661 if (IntReg == 0) return false;
1663 UpdateValueMap(I, IntReg);
1667 bool ARMFastISel::SelectSelect(const Instruction *I) {
1669 if (!isTypeLegal(I->getType(), VT))
1672 // Things need to be register sized for register moves.
1673 if (VT != MVT::i32) return false;
1675 unsigned CondReg = getRegForValue(I->getOperand(0));
1676 if (CondReg == 0) return false;
1677 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1678 if (Op1Reg == 0) return false;
1680 // Check to see if we can use an immediate in the conditional move.
1682 bool UseImm = false;
1683 bool isNegativeImm = false;
1684 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1685 assert (VT == MVT::i32 && "Expecting an i32.");
1686 Imm = (int)ConstInt->getValue().getZExtValue();
1688 isNegativeImm = true;
1691 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1692 (ARM_AM::getSOImmVal(Imm) != -1);
1695 unsigned Op2Reg = 0;
1697 Op2Reg = getRegForValue(I->getOperand(2));
1698 if (Op2Reg == 0) return false;
1701 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1702 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1703 .addReg(CondReg).addImm(0));
1706 const TargetRegisterClass *RC;
1708 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1709 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1711 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1713 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1715 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1717 unsigned ResultReg = createResultReg(RC);
1719 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1720 .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1722 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1723 .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1724 UpdateValueMap(I, ResultReg);
1728 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1730 Type *Ty = I->getType();
1731 if (!isTypeLegal(Ty, VT))
1734 // If we have integer div support we should have selected this automagically.
1735 // In case we have a real miss go ahead and return false and we'll pick
1737 if (Subtarget->hasDivide()) return false;
1739 // Otherwise emit a libcall.
1740 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1742 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1743 else if (VT == MVT::i16)
1744 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1745 else if (VT == MVT::i32)
1746 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1747 else if (VT == MVT::i64)
1748 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1749 else if (VT == MVT::i128)
1750 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1751 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1753 return ARMEmitLibcall(I, LC);
1756 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1758 Type *Ty = I->getType();
1759 if (!isTypeLegal(Ty, VT))
1762 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1764 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1765 else if (VT == MVT::i16)
1766 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1767 else if (VT == MVT::i32)
1768 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1769 else if (VT == MVT::i64)
1770 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1771 else if (VT == MVT::i128)
1772 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1773 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1775 return ARMEmitLibcall(I, LC);
1778 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1779 EVT DestVT = TLI.getValueType(I->getType(), true);
1781 // We can get here in the case when we have a binary operation on a non-legal
1782 // type and the target independent selector doesn't know how to handle it.
1783 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1787 switch (ISDOpcode) {
1788 default: return false;
1790 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1793 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1796 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1800 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1801 if (SrcReg1 == 0) return false;
1803 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1804 // in the instruction, rather then materializing the value in a register.
1805 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1806 if (SrcReg2 == 0) return false;
1808 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1809 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1810 TII.get(Opc), ResultReg)
1811 .addReg(SrcReg1).addReg(SrcReg2));
1812 UpdateValueMap(I, ResultReg);
1816 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1817 EVT FPVT = TLI.getValueType(I->getType(), true);
1818 if (!FPVT.isSimple()) return false;
1819 MVT VT = FPVT.getSimpleVT();
1821 // We can get here in the case when we want to use NEON for our fp
1822 // operations, but can't figure out how to. Just use the vfp instructions
1824 // FIXME: It'd be nice to use NEON instructions.
1825 Type *Ty = I->getType();
1826 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1827 if (isFloat && !Subtarget->hasVFP2())
1831 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1832 switch (ISDOpcode) {
1833 default: return false;
1835 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1838 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1841 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1844 unsigned Op1 = getRegForValue(I->getOperand(0));
1845 if (Op1 == 0) return false;
1847 unsigned Op2 = getRegForValue(I->getOperand(1));
1848 if (Op2 == 0) return false;
1850 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1851 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1852 TII.get(Opc), ResultReg)
1853 .addReg(Op1).addReg(Op2));
1854 UpdateValueMap(I, ResultReg);
1858 // Call Handling Code
1860 // This is largely taken directly from CCAssignFnForNode
1861 // TODO: We may not support all of this.
1862 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1867 llvm_unreachable("Unsupported calling convention");
1868 case CallingConv::Fast:
1869 if (Subtarget->hasVFP2() && !isVarArg) {
1870 if (!Subtarget->isAAPCS_ABI())
1871 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1872 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1873 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1876 case CallingConv::C:
1877 // Use target triple & subtarget features to do actual dispatch.
1878 if (Subtarget->isAAPCS_ABI()) {
1879 if (Subtarget->hasVFP2() &&
1880 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1881 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1883 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1885 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1886 case CallingConv::ARM_AAPCS_VFP:
1888 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1889 // Fall through to soft float variant, variadic functions don't
1890 // use hard floating point ABI.
1891 case CallingConv::ARM_AAPCS:
1892 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1893 case CallingConv::ARM_APCS:
1894 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1895 case CallingConv::GHC:
1897 llvm_unreachable("Can't return in GHC call convention");
1899 return CC_ARM_APCS_GHC;
1903 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1904 SmallVectorImpl<unsigned> &ArgRegs,
1905 SmallVectorImpl<MVT> &ArgVTs,
1906 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1907 SmallVectorImpl<unsigned> &RegArgs,
1911 SmallVector<CCValAssign, 16> ArgLocs;
1912 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1913 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1914 CCAssignFnForCall(CC, false, isVarArg));
1916 // Check that we can handle all of the arguments. If we can't, then bail out
1917 // now before we add code to the MBB.
1918 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1919 CCValAssign &VA = ArgLocs[i];
1920 MVT ArgVT = ArgVTs[VA.getValNo()];
1922 // We don't handle NEON/vector parameters yet.
1923 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1926 // Now copy/store arg to correct locations.
1927 if (VA.isRegLoc() && !VA.needsCustom()) {
1929 } else if (VA.needsCustom()) {
1930 // TODO: We need custom lowering for vector (v2f64) args.
1931 if (VA.getLocVT() != MVT::f64 ||
1932 // TODO: Only handle register args for now.
1933 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1936 switch (static_cast<EVT>(ArgVT).getSimpleVT().SimpleTy) {
1945 if (!Subtarget->hasVFP2())
1949 if (!Subtarget->hasVFP2())
1956 // At the point, we are able to handle the call's arguments in fast isel.
1958 // Get a count of how many bytes are to be pushed on the stack.
1959 NumBytes = CCInfo.getNextStackOffset();
1961 // Issue CALLSEQ_START
1962 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1963 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1964 TII.get(AdjStackDown))
1967 // Process the args.
1968 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1969 CCValAssign &VA = ArgLocs[i];
1970 unsigned Arg = ArgRegs[VA.getValNo()];
1971 MVT ArgVT = ArgVTs[VA.getValNo()];
1973 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1974 "We don't handle NEON/vector parameters yet.");
1976 // Handle arg promotion, etc.
1977 switch (VA.getLocInfo()) {
1978 case CCValAssign::Full: break;
1979 case CCValAssign::SExt: {
1980 MVT DestVT = VA.getLocVT();
1981 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1982 assert (Arg != 0 && "Failed to emit a sext");
1986 case CCValAssign::AExt:
1987 // Intentional fall-through. Handle AExt and ZExt.
1988 case CCValAssign::ZExt: {
1989 MVT DestVT = VA.getLocVT();
1990 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1991 assert (Arg != 0 && "Failed to emit a zext");
1995 case CCValAssign::BCvt: {
1996 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1997 /*TODO: Kill=*/false);
1998 assert(BC != 0 && "Failed to emit a bitcast!");
2000 ArgVT = VA.getLocVT();
2003 default: llvm_unreachable("Unknown arg promotion!");
2006 // Now copy/store arg to correct locations.
2007 if (VA.isRegLoc() && !VA.needsCustom()) {
2008 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2011 RegArgs.push_back(VA.getLocReg());
2012 } else if (VA.needsCustom()) {
2013 // TODO: We need custom lowering for vector (v2f64) args.
2014 assert(VA.getLocVT() == MVT::f64 &&
2015 "Custom lowering for v2f64 args not available");
2017 CCValAssign &NextVA = ArgLocs[++i];
2019 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2020 "We only handle register args!");
2022 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2023 TII.get(ARM::VMOVRRD), VA.getLocReg())
2024 .addReg(NextVA.getLocReg(), RegState::Define)
2026 RegArgs.push_back(VA.getLocReg());
2027 RegArgs.push_back(NextVA.getLocReg());
2029 assert(VA.isMemLoc());
2030 // Need to store on the stack.
2032 Addr.BaseType = Address::RegBase;
2033 Addr.Base.Reg = ARM::SP;
2034 Addr.Offset = VA.getLocMemOffset();
2036 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2037 assert(EmitRet && "Could not emit a store for argument!");
2044 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2045 const Instruction *I, CallingConv::ID CC,
2046 unsigned &NumBytes, bool isVarArg) {
2047 // Issue CALLSEQ_END
2048 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2049 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2050 TII.get(AdjStackUp))
2051 .addImm(NumBytes).addImm(0));
2053 // Now the return value.
2054 if (RetVT != MVT::isVoid) {
2055 SmallVector<CCValAssign, 16> RVLocs;
2056 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2057 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2059 // Copy all of the result registers out of their specified physreg.
2060 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2061 // For this move we copy into two registers and then move into the
2062 // double fp reg we want.
2063 MVT DestVT = RVLocs[0].getValVT();
2064 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2065 unsigned ResultReg = createResultReg(DstRC);
2066 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2067 TII.get(ARM::VMOVDRR), ResultReg)
2068 .addReg(RVLocs[0].getLocReg())
2069 .addReg(RVLocs[1].getLocReg()));
2071 UsedRegs.push_back(RVLocs[0].getLocReg());
2072 UsedRegs.push_back(RVLocs[1].getLocReg());
2074 // Finally update the result.
2075 UpdateValueMap(I, ResultReg);
2077 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2078 MVT CopyVT = RVLocs[0].getValVT();
2080 // Special handling for extended integers.
2081 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2084 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2086 unsigned ResultReg = createResultReg(DstRC);
2087 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2088 ResultReg).addReg(RVLocs[0].getLocReg());
2089 UsedRegs.push_back(RVLocs[0].getLocReg());
2091 // Finally update the result.
2092 UpdateValueMap(I, ResultReg);
2099 bool ARMFastISel::SelectRet(const Instruction *I) {
2100 const ReturnInst *Ret = cast<ReturnInst>(I);
2101 const Function &F = *I->getParent()->getParent();
2103 if (!FuncInfo.CanLowerReturn)
2106 // Build a list of return value registers.
2107 SmallVector<unsigned, 4> RetRegs;
2109 CallingConv::ID CC = F.getCallingConv();
2110 if (Ret->getNumOperands() > 0) {
2111 SmallVector<ISD::OutputArg, 4> Outs;
2112 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
2114 // Analyze operands of the call, assigning locations to each operand.
2115 SmallVector<CCValAssign, 16> ValLocs;
2116 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
2117 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2120 const Value *RV = Ret->getOperand(0);
2121 unsigned Reg = getRegForValue(RV);
2125 // Only handle a single return value for now.
2126 if (ValLocs.size() != 1)
2129 CCValAssign &VA = ValLocs[0];
2131 // Don't bother handling odd stuff for now.
2132 if (VA.getLocInfo() != CCValAssign::Full)
2134 // Only handle register returns for now.
2138 unsigned SrcReg = Reg + VA.getValNo();
2139 EVT RVEVT = TLI.getValueType(RV->getType());
2140 if (!RVEVT.isSimple()) return false;
2141 MVT RVVT = RVEVT.getSimpleVT();
2142 MVT DestVT = VA.getValVT();
2143 // Special handling for extended integers.
2144 if (RVVT != DestVT) {
2145 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2148 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2150 // Perform extension if flagged as either zext or sext. Otherwise, do
2152 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2153 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2154 if (SrcReg == 0) return false;
2159 unsigned DstReg = VA.getLocReg();
2160 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2161 // Avoid a cross-class copy. This is very unlikely.
2162 if (!SrcRC->contains(DstReg))
2164 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2165 DstReg).addReg(SrcReg);
2167 // Add register to return instruction.
2168 RetRegs.push_back(VA.getLocReg());
2171 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2172 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2174 AddOptionalDefs(MIB);
2175 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2176 MIB.addReg(RetRegs[i], RegState::Implicit);
2180 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2182 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2184 return isThumb2 ? ARM::tBL : ARM::BL;
2187 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2188 GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false,
2189 GlobalValue::ExternalLinkage, 0, Name);
2190 EVT LCREVT = TLI.getValueType(GV->getType());
2191 if (!LCREVT.isSimple()) return 0;
2192 return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2195 // A quick function that will emit a call for a named libcall in F with the
2196 // vector of passed arguments for the Instruction in I. We can assume that we
2197 // can emit a call for any libcall we can produce. This is an abridged version
2198 // of the full call infrastructure since we won't need to worry about things
2199 // like computed function pointers or strange arguments at call sites.
2200 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2202 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2203 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2205 // Handle *simple* calls for now.
2206 Type *RetTy = I->getType();
2208 if (RetTy->isVoidTy())
2209 RetVT = MVT::isVoid;
2210 else if (!isTypeLegal(RetTy, RetVT))
2213 // Can't handle non-double multi-reg retvals.
2214 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2215 SmallVector<CCValAssign, 16> RVLocs;
2216 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
2217 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2218 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2222 // Set up the argument vectors.
2223 SmallVector<Value*, 8> Args;
2224 SmallVector<unsigned, 8> ArgRegs;
2225 SmallVector<MVT, 8> ArgVTs;
2226 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2227 Args.reserve(I->getNumOperands());
2228 ArgRegs.reserve(I->getNumOperands());
2229 ArgVTs.reserve(I->getNumOperands());
2230 ArgFlags.reserve(I->getNumOperands());
2231 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2232 Value *Op = I->getOperand(i);
2233 unsigned Arg = getRegForValue(Op);
2234 if (Arg == 0) return false;
2236 Type *ArgTy = Op->getType();
2238 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2240 ISD::ArgFlagsTy Flags;
2241 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2242 Flags.setOrigAlign(OriginalAlignment);
2245 ArgRegs.push_back(Arg);
2246 ArgVTs.push_back(ArgVT);
2247 ArgFlags.push_back(Flags);
2250 // Handle the arguments now that we've gotten them.
2251 SmallVector<unsigned, 4> RegArgs;
2253 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2254 RegArgs, CC, NumBytes, false))
2257 unsigned CalleeReg = 0;
2258 if (EnableARMLongCalls) {
2259 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2260 if (CalleeReg == 0) return false;
2264 unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
2265 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2266 DL, TII.get(CallOpc));
2267 // BL / BLX don't take a predicate, but tBL / tBLX do.
2269 AddDefaultPred(MIB);
2270 if (EnableARMLongCalls)
2271 MIB.addReg(CalleeReg);
2273 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2275 // Add implicit physical register uses to the call.
2276 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2277 MIB.addReg(RegArgs[i], RegState::Implicit);
2279 // Add a register mask with the call-preserved registers.
2280 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2281 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2283 // Finish off the call including any return values.
2284 SmallVector<unsigned, 4> UsedRegs;
2285 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2287 // Set all unused physreg defs as dead.
2288 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2293 bool ARMFastISel::SelectCall(const Instruction *I,
2294 const char *IntrMemName = 0) {
2295 const CallInst *CI = cast<CallInst>(I);
2296 const Value *Callee = CI->getCalledValue();
2298 // Can't handle inline asm.
2299 if (isa<InlineAsm>(Callee)) return false;
2301 // Allow SelectionDAG isel to handle tail calls.
2302 if (CI->isTailCall()) return false;
2304 // Check the calling convention.
2305 ImmutableCallSite CS(CI);
2306 CallingConv::ID CC = CS.getCallingConv();
2308 // TODO: Avoid some calling conventions?
2310 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2311 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2312 bool isVarArg = FTy->isVarArg();
2314 // Handle *simple* calls for now.
2315 Type *RetTy = I->getType();
2317 if (RetTy->isVoidTy())
2318 RetVT = MVT::isVoid;
2319 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2320 RetVT != MVT::i8 && RetVT != MVT::i1)
2323 // Can't handle non-double multi-reg retvals.
2324 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2325 RetVT != MVT::i16 && RetVT != MVT::i32) {
2326 SmallVector<CCValAssign, 16> RVLocs;
2327 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2328 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2329 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2333 // Set up the argument vectors.
2334 SmallVector<Value*, 8> Args;
2335 SmallVector<unsigned, 8> ArgRegs;
2336 SmallVector<MVT, 8> ArgVTs;
2337 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2338 unsigned arg_size = CS.arg_size();
2339 Args.reserve(arg_size);
2340 ArgRegs.reserve(arg_size);
2341 ArgVTs.reserve(arg_size);
2342 ArgFlags.reserve(arg_size);
2343 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2345 // If we're lowering a memory intrinsic instead of a regular call, skip the
2346 // last two arguments, which shouldn't be passed to the underlying function.
2347 if (IntrMemName && e-i <= 2)
2350 ISD::ArgFlagsTy Flags;
2351 unsigned AttrInd = i - CS.arg_begin() + 1;
2352 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2354 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2357 // FIXME: Only handle *easy* calls for now.
2358 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2359 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2360 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2361 CS.paramHasAttr(AttrInd, Attribute::ByVal))
2364 Type *ArgTy = (*i)->getType();
2366 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2370 unsigned Arg = getRegForValue(*i);
2374 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2375 Flags.setOrigAlign(OriginalAlignment);
2378 ArgRegs.push_back(Arg);
2379 ArgVTs.push_back(ArgVT);
2380 ArgFlags.push_back(Flags);
2383 // Handle the arguments now that we've gotten them.
2384 SmallVector<unsigned, 4> RegArgs;
2386 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2387 RegArgs, CC, NumBytes, isVarArg))
2390 bool UseReg = false;
2391 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2392 if (!GV || EnableARMLongCalls) UseReg = true;
2394 unsigned CalleeReg = 0;
2397 CalleeReg = getLibcallReg(IntrMemName);
2399 CalleeReg = getRegForValue(Callee);
2401 if (CalleeReg == 0) return false;
2405 unsigned CallOpc = ARMSelectCallOp(UseReg);
2406 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2407 DL, TII.get(CallOpc));
2409 // ARM calls don't take a predicate, but tBL / tBLX do.
2411 AddDefaultPred(MIB);
2413 MIB.addReg(CalleeReg);
2414 else if (!IntrMemName)
2415 MIB.addGlobalAddress(GV, 0, 0);
2417 MIB.addExternalSymbol(IntrMemName, 0);
2419 // Add implicit physical register uses to the call.
2420 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2421 MIB.addReg(RegArgs[i], RegState::Implicit);
2423 // Add a register mask with the call-preserved registers.
2424 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2425 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2427 // Finish off the call including any return values.
2428 SmallVector<unsigned, 4> UsedRegs;
2429 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2432 // Set all unused physreg defs as dead.
2433 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2438 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2442 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2443 uint64_t Len, unsigned Alignment) {
2444 // Make sure we don't bloat code by inlining very large memcpy's.
2445 if (!ARMIsMemCpySmall(Len))
2450 if (!Alignment || Alignment >= 4) {
2456 assert (Len == 1 && "Expected a length of 1!");
2460 // Bound based on alignment.
2461 if (Len >= 2 && Alignment == 2)
2470 RV = ARMEmitLoad(VT, ResultReg, Src);
2471 assert (RV == true && "Should be able to handle this load.");
2472 RV = ARMEmitStore(VT, ResultReg, Dest);
2473 assert (RV == true && "Should be able to handle this store.");
2476 unsigned Size = VT.getSizeInBits()/8;
2478 Dest.Offset += Size;
2485 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2486 // FIXME: Handle more intrinsics.
2487 switch (I.getIntrinsicID()) {
2488 default: return false;
2489 case Intrinsic::frameaddress: {
2490 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2491 MFI->setFrameAddressIsTaken(true);
2494 const TargetRegisterClass *RC;
2496 LdrOpc = ARM::t2LDRi12;
2497 RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2499 LdrOpc = ARM::LDRi12;
2500 RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2503 const ARMBaseRegisterInfo *RegInfo =
2504 static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
2505 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2506 unsigned SrcReg = FramePtr;
2508 // Recursively load frame address
2514 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2516 DestReg = createResultReg(RC);
2517 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2518 TII.get(LdrOpc), DestReg)
2519 .addReg(SrcReg).addImm(0));
2522 UpdateValueMap(&I, SrcReg);
2525 case Intrinsic::memcpy:
2526 case Intrinsic::memmove: {
2527 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2528 // Don't handle volatile.
2529 if (MTI.isVolatile())
2532 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2533 // we would emit dead code because we don't currently handle memmoves.
2534 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2535 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2536 // Small memcpy's are common enough that we want to do them without a call
2538 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2539 if (ARMIsMemCpySmall(Len)) {
2541 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2542 !ARMComputeAddress(MTI.getRawSource(), Src))
2544 unsigned Alignment = MTI.getAlignment();
2545 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2550 if (!MTI.getLength()->getType()->isIntegerTy(32))
2553 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2556 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2557 return SelectCall(&I, IntrMemName);
2559 case Intrinsic::memset: {
2560 const MemSetInst &MSI = cast<MemSetInst>(I);
2561 // Don't handle volatile.
2562 if (MSI.isVolatile())
2565 if (!MSI.getLength()->getType()->isIntegerTy(32))
2568 if (MSI.getDestAddressSpace() > 255)
2571 return SelectCall(&I, "memset");
2573 case Intrinsic::trap: {
2574 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(
2575 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2581 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2582 // The high bits for a type smaller than the register size are assumed to be
2584 Value *Op = I->getOperand(0);
2587 SrcVT = TLI.getValueType(Op->getType(), true);
2588 DestVT = TLI.getValueType(I->getType(), true);
2590 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2592 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2595 unsigned SrcReg = getRegForValue(Op);
2596 if (!SrcReg) return false;
2598 // Because the high bits are undefined, a truncate doesn't generate
2600 UpdateValueMap(I, SrcReg);
2604 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2606 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2608 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2611 // Table of which combinations can be emitted as a single instruction,
2612 // and which will require two.
2613 static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2615 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2616 // ext: s z s z s z s z
2617 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2618 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2619 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2622 // Target registers for:
2623 // - For ARM can never be PC.
2624 // - For 16-bit Thumb are restricted to lower 8 registers.
2625 // - For 32-bit Thumb are restricted to non-SP and non-PC.
2626 static const TargetRegisterClass *RCTbl[2][2] = {
2627 // Instructions: Two Single
2628 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2629 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2632 // Table governing the instruction(s) to be emitted.
2633 static const struct InstructionTable {
2635 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2636 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2637 uint32_t Imm : 8; // All instructions have either a shift or a mask.
2638 } IT[2][2][3][2] = {
2639 { // Two instructions (first is left shift, second is in this table).
2640 { // ARM Opc S Shift Imm
2641 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2642 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2643 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2644 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2645 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2646 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2648 { // Thumb Opc S Shift Imm
2649 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2650 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2651 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2652 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2653 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2654 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2657 { // Single instruction.
2658 { // ARM Opc S Shift Imm
2659 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2660 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2661 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2662 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2663 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2664 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2666 { // Thumb Opc S Shift Imm
2667 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2668 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2669 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2670 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2671 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2672 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2677 unsigned SrcBits = SrcVT.getSizeInBits();
2678 unsigned DestBits = DestVT.getSizeInBits();
2680 assert((SrcBits < DestBits) && "can only extend to larger types");
2681 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2682 "other sizes unimplemented");
2683 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2684 "other sizes unimplemented");
2686 bool hasV6Ops = Subtarget->hasV6Ops();
2687 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2688 assert((Bitness < 3) && "sanity-check table bounds");
2690 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2691 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2692 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2693 unsigned Opc = ITP->Opc;
2694 assert(ARM::KILL != Opc && "Invalid table entry");
2695 unsigned hasS = ITP->hasS;
2696 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2697 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2698 "only MOVsi has shift operand addressing mode");
2699 unsigned Imm = ITP->Imm;
2701 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2702 bool setsCPSR = &ARM::tGPRRegClass == RC;
2703 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2705 // MOVsi encodes shift and immediate in shift operand addressing mode.
2706 // The following condition has the same value when emitting two
2707 // instruction sequences: both are shifts.
2708 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2710 // Either one or two instructions are emitted.
2711 // They're always of the form:
2713 // CPSR is set only by 16-bit Thumb instructions.
2714 // Predicate, if any, is AL.
2715 // S bit, if available, is always 0.
2716 // When two are emitted the first's result will feed as the second's input,
2717 // that value is then dead.
2718 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2719 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2720 ResultReg = createResultReg(RC);
2721 bool isLsl = (0 == Instr) && !isSingleInstr;
2722 unsigned Opcode = isLsl ? LSLOpc : Opc;
2723 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2724 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2725 bool isKill = 1 == Instr;
2726 MachineInstrBuilder MIB = BuildMI(
2727 *FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opcode), ResultReg);
2729 MIB.addReg(ARM::CPSR, RegState::Define);
2730 AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
2733 // Second instruction consumes the first's result.
2740 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2741 // On ARM, in general, integer casts don't involve legal types; this code
2742 // handles promotable integers.
2743 Type *DestTy = I->getType();
2744 Value *Src = I->getOperand(0);
2745 Type *SrcTy = Src->getType();
2747 bool isZExt = isa<ZExtInst>(I);
2748 unsigned SrcReg = getRegForValue(Src);
2749 if (!SrcReg) return false;
2751 EVT SrcEVT, DestEVT;
2752 SrcEVT = TLI.getValueType(SrcTy, true);
2753 DestEVT = TLI.getValueType(DestTy, true);
2754 if (!SrcEVT.isSimple()) return false;
2755 if (!DestEVT.isSimple()) return false;
2757 MVT SrcVT = SrcEVT.getSimpleVT();
2758 MVT DestVT = DestEVT.getSimpleVT();
2759 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2760 if (ResultReg == 0) return false;
2761 UpdateValueMap(I, ResultReg);
2765 bool ARMFastISel::SelectShift(const Instruction *I,
2766 ARM_AM::ShiftOpc ShiftTy) {
2767 // We handle thumb2 mode by target independent selector
2768 // or SelectionDAG ISel.
2772 // Only handle i32 now.
2773 EVT DestVT = TLI.getValueType(I->getType(), true);
2774 if (DestVT != MVT::i32)
2777 unsigned Opc = ARM::MOVsr;
2779 Value *Src2Value = I->getOperand(1);
2780 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2781 ShiftImm = CI->getZExtValue();
2783 // Fall back to selection DAG isel if the shift amount
2784 // is zero or greater than the width of the value type.
2785 if (ShiftImm == 0 || ShiftImm >=32)
2791 Value *Src1Value = I->getOperand(0);
2792 unsigned Reg1 = getRegForValue(Src1Value);
2793 if (Reg1 == 0) return false;
2796 if (Opc == ARM::MOVsr) {
2797 Reg2 = getRegForValue(Src2Value);
2798 if (Reg2 == 0) return false;
2801 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2802 if(ResultReg == 0) return false;
2804 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2805 TII.get(Opc), ResultReg)
2808 if (Opc == ARM::MOVsi)
2809 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2810 else if (Opc == ARM::MOVsr) {
2812 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2815 AddOptionalDefs(MIB);
2816 UpdateValueMap(I, ResultReg);
2820 // TODO: SoftFP support.
2821 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2823 switch (I->getOpcode()) {
2824 case Instruction::Load:
2825 return SelectLoad(I);
2826 case Instruction::Store:
2827 return SelectStore(I);
2828 case Instruction::Br:
2829 return SelectBranch(I);
2830 case Instruction::IndirectBr:
2831 return SelectIndirectBr(I);
2832 case Instruction::ICmp:
2833 case Instruction::FCmp:
2834 return SelectCmp(I);
2835 case Instruction::FPExt:
2836 return SelectFPExt(I);
2837 case Instruction::FPTrunc:
2838 return SelectFPTrunc(I);
2839 case Instruction::SIToFP:
2840 return SelectIToFP(I, /*isSigned*/ true);
2841 case Instruction::UIToFP:
2842 return SelectIToFP(I, /*isSigned*/ false);
2843 case Instruction::FPToSI:
2844 return SelectFPToI(I, /*isSigned*/ true);
2845 case Instruction::FPToUI:
2846 return SelectFPToI(I, /*isSigned*/ false);
2847 case Instruction::Add:
2848 return SelectBinaryIntOp(I, ISD::ADD);
2849 case Instruction::Or:
2850 return SelectBinaryIntOp(I, ISD::OR);
2851 case Instruction::Sub:
2852 return SelectBinaryIntOp(I, ISD::SUB);
2853 case Instruction::FAdd:
2854 return SelectBinaryFPOp(I, ISD::FADD);
2855 case Instruction::FSub:
2856 return SelectBinaryFPOp(I, ISD::FSUB);
2857 case Instruction::FMul:
2858 return SelectBinaryFPOp(I, ISD::FMUL);
2859 case Instruction::SDiv:
2860 return SelectDiv(I, /*isSigned*/ true);
2861 case Instruction::UDiv:
2862 return SelectDiv(I, /*isSigned*/ false);
2863 case Instruction::SRem:
2864 return SelectRem(I, /*isSigned*/ true);
2865 case Instruction::URem:
2866 return SelectRem(I, /*isSigned*/ false);
2867 case Instruction::Call:
2868 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2869 return SelectIntrinsicCall(*II);
2870 return SelectCall(I);
2871 case Instruction::Select:
2872 return SelectSelect(I);
2873 case Instruction::Ret:
2874 return SelectRet(I);
2875 case Instruction::Trunc:
2876 return SelectTrunc(I);
2877 case Instruction::ZExt:
2878 case Instruction::SExt:
2879 return SelectIntExt(I);
2880 case Instruction::Shl:
2881 return SelectShift(I, ARM_AM::lsl);
2882 case Instruction::LShr:
2883 return SelectShift(I, ARM_AM::lsr);
2884 case Instruction::AShr:
2885 return SelectShift(I, ARM_AM::asr);
2892 // This table describes sign- and zero-extend instructions which can be
2893 // folded into a preceding load. All of these extends have an immediate
2894 // (sometimes a mask and sometimes a shift) that's applied after
2896 const struct FoldableLoadExtendsStruct {
2897 uint16_t Opc[2]; // ARM, Thumb.
2898 uint8_t ExpectedImm;
2900 uint8_t ExpectedVT : 7;
2901 } FoldableLoadExtends[] = {
2902 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2903 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2904 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2905 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2906 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2910 /// \brief The specified machine instr operand is a vreg, and that
2911 /// vreg is being provided by the specified load instruction. If possible,
2912 /// try to fold the load as an operand to the instruction, returning true if
2914 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2915 const LoadInst *LI) {
2916 // Verify we have a legal type before going any further.
2918 if (!isLoadTypeLegal(LI->getType(), VT))
2921 // Combine load followed by zero- or sign-extend.
2922 // ldrb r1, [r0] ldrb r1, [r0]
2924 // mov r3, r2 mov r3, r1
2925 if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2927 const uint64_t Imm = MI->getOperand(2).getImm();
2931 for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends);
2933 if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&
2934 (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm &&
2935 MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) {
2937 isZExt = FoldableLoadExtends[i].isZExt;
2940 if (!Found) return false;
2942 // See if we can handle this address.
2944 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2946 unsigned ResultReg = MI->getOperand(0).getReg();
2947 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2949 MI->eraseFromParent();
2953 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2954 unsigned Align, MVT VT) {
2955 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2956 ARMConstantPoolConstant *CPV =
2957 ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2958 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
2961 unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
2964 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2965 TII.get(ARM::t2LDRpci), DestReg1)
2966 .addConstantPoolIndex(Idx));
2967 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
2969 // The extra immediate is for addrmode2.
2970 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2971 DL, TII.get(ARM::LDRcp), DestReg1)
2972 .addConstantPoolIndex(Idx).addImm(0));
2973 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
2976 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
2977 if (GlobalBaseReg == 0) {
2978 GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
2979 AFI->setGlobalBaseReg(GlobalBaseReg);
2982 unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
2983 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2984 DL, TII.get(Opc), DestReg2)
2986 .addReg(GlobalBaseReg);
2989 AddOptionalDefs(MIB);
2994 bool ARMFastISel::FastLowerArguments() {
2995 if (!FuncInfo.CanLowerReturn)
2998 const Function *F = FuncInfo.Fn;
3002 CallingConv::ID CC = F->getCallingConv();
3006 case CallingConv::Fast:
3007 case CallingConv::C:
3008 case CallingConv::ARM_AAPCS_VFP:
3009 case CallingConv::ARM_AAPCS:
3010 case CallingConv::ARM_APCS:
3014 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3015 // which are passed in r0 - r3.
3017 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3018 I != E; ++I, ++Idx) {
3022 if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
3023 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
3024 F->getAttributes().hasAttribute(Idx, Attribute::ByVal))
3027 Type *ArgTy = I->getType();
3028 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3031 EVT ArgVT = TLI.getValueType(ArgTy);
3032 if (!ArgVT.isSimple()) return false;
3033 switch (ArgVT.getSimpleVT().SimpleTy) {
3044 static const uint16_t GPRArgRegs[] = {
3045 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3048 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::i32);
3050 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3051 I != E; ++I, ++Idx) {
3052 unsigned SrcReg = GPRArgRegs[Idx];
3053 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3054 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3055 // Without this, EmitLiveInCopies may eliminate the livein if its only
3056 // use is a bitcast (which isn't turned into an instruction).
3057 unsigned ResultReg = createResultReg(RC);
3058 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
3059 ResultReg).addReg(DstReg, getKillRegState(true));
3060 UpdateValueMap(I, ResultReg);
3067 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3068 const TargetLibraryInfo *libInfo) {
3069 const TargetMachine &TM = funcInfo.MF->getTarget();
3071 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
3072 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
3073 bool UseFastISel = false;
3074 UseFastISel |= Subtarget->isTargetIOS() && !Subtarget->isThumb1Only();
3075 UseFastISel |= Subtarget->isTargetLinux() && !Subtarget->isThumb();
3076 UseFastISel |= Subtarget->isTargetNaCl() && !Subtarget->isThumb();
3079 // iOS always has a FP for backtracking, force other targets
3080 // to keep their FP when doing FastISel. The emitted code is
3081 // currently superior, and in cases like test-suite's lencod
3082 // FastISel isn't quite correct when FP is eliminated.
3083 TM.Options.NoFramePointerElim = true;
3084 return new ARMFastISel(funcInfo, libInfo);