1 //===-- ARM/ARMFixupKinds.h - ARM Specific Fixup Entries --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_ARM_ARMFIXUPKINDS_H
11 #define LLVM_ARM_ARMFIXUPKINDS_H
13 #include "llvm/MC/MCFixup.h"
18 // fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol
20 fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
22 // fixup_t2_ldst_pcrel_12 - Equivalent to fixup_arm_ldst_pcrel_12, with
23 // the 16-bit halfwords reordered.
24 fixup_t2_ldst_pcrel_12,
26 // fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
27 // used in VFP instructions where the lower 2 bits are not encoded
28 // (so it's encoded as an 8-bit immediate).
30 // fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
31 // the short-swapped encoding of Thumb2 instructions.
33 // fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol
34 // addresses where the lower 2 bits are not encoded (so it's encoded as an
36 fixup_thumb_adr_pcrel_10,
37 // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
39 fixup_arm_adr_pcrel_12,
40 // fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
42 fixup_t2_adr_pcrel_12,
43 // fixup_arm_branch - 24-bit PC relative relocation for direct branch
46 // fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct
47 // uconditional branch instructions.
49 // fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct
50 // branch unconditional branch instructions.
51 fixup_t2_uncondbranch,
53 // fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.
56 // fixup_arm_thumb_blx - Fixup for Thumb BL instructions.
59 // fixup_arm_thumb_blx - Fixup for Thumb BLX instructions.
62 // fixup_arm_thumb_cb - Fixup for Thumb branch instructions.
65 // fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
68 // fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions.
71 // The next two are for the movt/movw pair
72 // the 16bit imm field are split into imm{15-12} and imm{11-0}
73 fixup_arm_movt_hi16, // :upper16:
74 fixup_arm_movw_lo16, // :lower16:
75 fixup_t2_movt_hi16, // :upper16:
76 fixup_t2_movw_lo16, // :lower16:
78 // It is possible to create an "immediate" that happens to be pcrel.
79 // movw r0, :lower16:Foo-(Bar+8) and movt r0, :upper16:Foo-(Bar+8)
80 // result in different reloc tags than the above two.
81 // Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC
82 fixup_arm_movt_hi16_pcrel, // :upper16:
83 fixup_arm_movw_lo16_pcrel, // :lower16:
84 fixup_t2_movt_hi16_pcrel, // :upper16:
85 fixup_t2_movw_lo16_pcrel, // :lower16:
89 NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind