1 //=======- ARMFrameInfo.cpp - ARM Frame Information ------------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameInfo.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/RegisterScavenging.h"
22 #include "llvm/Target/TargetOptions.h"
26 /// hasFP - Return true if the specified function should have a dedicated frame
27 /// pointer register. This is true if the function has variable sized allocas
28 /// or if frame pointer elimination is disabled.
30 bool ARMFrameInfo::hasFP(const MachineFunction &MF) const {
31 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
33 // Mac OS X requires FP not to be clobbered for backtracing purpose.
34 if (STI.isTargetDarwin())
37 const MachineFrameInfo *MFI = MF.getFrameInfo();
38 // Always eliminate non-leaf frame pointers.
39 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
40 RegInfo->needsStackRealignment(MF) ||
41 MFI->hasVarSizedObjects() ||
42 MFI->isFrameAddressTaken());
45 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
46 // not required, we reserve argument space for call sites in the function
47 // immediately on entry to the current function. This eliminates the need for
48 // add/sub sp brackets around call sites. Returns true if the call frame is
49 // included as part of the stack frame.
50 bool ARMFrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
51 const MachineFrameInfo *FFI = MF.getFrameInfo();
52 unsigned CFSize = FFI->getMaxCallFrameSize();
53 // It's not always a good idea to include the call frame as part of the
54 // stack frame. ARM (especially Thumb) has small immediate offset to
55 // address the stack frame. So a large call frame can cause poor codegen
56 // and may even makes it impossible to scavenge a register.
57 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
60 return !MF.getFrameInfo()->hasVarSizedObjects();
63 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
64 // call frame pseudos can be simplified. Unlike most targets, having a FP
65 // is not sufficient here since we still may reference some objects via SP
66 // even when FP is available in Thumb2 mode.
67 bool ARMFrameInfo::canSimplifyCallFramePseudos(const MachineFunction &MF)const {
68 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
71 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
72 for (unsigned i = 0; CSRegs[i]; ++i)
78 static bool isCSRestore(MachineInstr *MI,
79 const ARMBaseInstrInfo &TII,
80 const unsigned *CSRegs) {
81 // Integer spill area is handled with "pop".
82 if (MI->getOpcode() == ARM::LDMIA_RET ||
83 MI->getOpcode() == ARM::t2LDMIA_RET ||
84 MI->getOpcode() == ARM::LDMIA_UPD ||
85 MI->getOpcode() == ARM::t2LDMIA_UPD ||
86 MI->getOpcode() == ARM::VLDMDIA_UPD) {
87 // The first two operands are predicates. The last two are
88 // imp-def and imp-use of SP. Check everything in between.
89 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
90 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
99 emitSPUpdate(bool isARM,
100 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
101 DebugLoc dl, const ARMBaseInstrInfo &TII,
103 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
105 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
108 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
112 void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
113 MachineBasicBlock &MBB = MF.front();
114 MachineBasicBlock::iterator MBBI = MBB.begin();
115 MachineFrameInfo *MFI = MF.getFrameInfo();
116 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
117 const ARMBaseRegisterInfo *RegInfo =
118 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
119 const ARMBaseInstrInfo &TII =
120 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
121 assert(!AFI->isThumb1OnlyFunction() &&
122 "This emitPrologue does not support Thumb1!");
123 bool isARM = !AFI->isThumbFunction();
124 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
125 unsigned NumBytes = MFI->getStackSize();
126 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
127 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
128 unsigned FramePtr = RegInfo->getFrameRegister(MF);
130 // Determine the sizes of each callee-save spill areas and record which frame
131 // belongs to which callee-save spill areas.
132 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
133 int FramePtrSpillFI = 0;
135 // Allocate the vararg register save area. This is not counted in NumBytes.
137 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
139 if (!AFI->hasStackFrame()) {
141 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
145 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
146 unsigned Reg = CSI[i].getReg();
147 int FI = CSI[i].getFrameIdx();
155 FramePtrSpillFI = FI;
156 AFI->addGPRCalleeSavedArea1Frame(FI);
164 FramePtrSpillFI = FI;
165 if (STI.isTargetDarwin()) {
166 AFI->addGPRCalleeSavedArea2Frame(FI);
169 AFI->addGPRCalleeSavedArea1Frame(FI);
174 AFI->addDPRCalleeSavedAreaFrame(FI);
180 if (GPRCS1Size > 0) MBBI++;
182 // Set FP to point to the stack slot that contains the previous FP.
183 // For Darwin, FP is R7, which has now been stored in spill area 1.
184 // Otherwise, if this is not Darwin, all the callee-saved registers go
185 // into spill area 1, including the FP in R11. In either case, it is
186 // now safe to emit this assignment.
187 bool HasFP = hasFP(MF);
189 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
190 MachineInstrBuilder MIB =
191 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
192 .addFrameIndex(FramePtrSpillFI).addImm(0);
193 AddDefaultCC(AddDefaultPred(MIB));
197 if (GPRCS2Size > 0) MBBI++;
199 // Determine starting offsets of spill areas.
200 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
201 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
202 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
204 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
206 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
207 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
208 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
211 if (DPRCSSize > 0) MBBI++;
213 NumBytes = DPRCSOffset;
215 // Adjust SP after all the callee-save spills.
216 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
218 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
219 // Note it's not safe to do this in Thumb2 mode because it would have
220 // taken two instructions:
223 // If an interrupt is taken between the two instructions, then sp is in
224 // an inconsistent state (pointing to the middle of callee-saved area).
225 // The interrupt handler can end up clobbering the registers.
226 AFI->setShouldRestoreSPFromFP(true);
229 if (STI.isTargetELF() && hasFP(MF))
230 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
231 AFI->getFramePtrSpillOffset());
233 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
234 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
235 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
237 // If we need dynamic stack realignment, do it here. Be paranoid and make
238 // sure if we also have VLAs, we have a base pointer for frame access.
239 if (RegInfo->needsStackRealignment(MF)) {
240 unsigned MaxAlign = MFI->getMaxAlignment();
241 assert (!AFI->isThumb1OnlyFunction());
242 if (!AFI->isThumbFunction()) {
243 // Emit bic sp, sp, MaxAlign
244 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
245 TII.get(ARM::BICri), ARM::SP)
246 .addReg(ARM::SP, RegState::Kill)
247 .addImm(MaxAlign-1)));
249 // We cannot use sp as source/dest register here, thus we're emitting the
250 // following sequence:
252 // bic r4, r4, MaxAlign
254 // FIXME: It will be better just to find spare register here.
255 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
256 .addReg(ARM::SP, RegState::Kill);
257 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
258 TII.get(ARM::t2BICri), ARM::R4)
259 .addReg(ARM::R4, RegState::Kill)
260 .addImm(MaxAlign-1)));
261 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
262 .addReg(ARM::R4, RegState::Kill);
265 AFI->setShouldRestoreSPFromFP(true);
268 // If we need a base pointer, set it up here. It's whatever the value
269 // of the stack pointer is at this point. Any variable size objects
270 // will be allocated after this, so we can still use the base pointer
271 // to reference locals.
272 if (RegInfo->hasBasePointer(MF)) {
274 BuildMI(MBB, MBBI, dl,
275 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
277 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
279 BuildMI(MBB, MBBI, dl,
280 TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister())
284 // If the frame has variable sized objects then the epilogue must restore
286 if (MFI->hasVarSizedObjects())
287 AFI->setShouldRestoreSPFromFP(true);
290 void ARMFrameInfo::emitEpilogue(MachineFunction &MF,
291 MachineBasicBlock &MBB) const {
292 MachineBasicBlock::iterator MBBI = prior(MBB.end());
293 assert(MBBI->getDesc().isReturn() &&
294 "Can only insert epilog into returning blocks");
295 unsigned RetOpcode = MBBI->getOpcode();
296 DebugLoc dl = MBBI->getDebugLoc();
297 MachineFrameInfo *MFI = MF.getFrameInfo();
298 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
299 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
300 const ARMBaseInstrInfo &TII =
301 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
302 assert(!AFI->isThumb1OnlyFunction() &&
303 "This emitEpilogue does not support Thumb1!");
304 bool isARM = !AFI->isThumbFunction();
306 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
307 int NumBytes = (int)MFI->getStackSize();
308 unsigned FramePtr = RegInfo->getFrameRegister(MF);
310 if (!AFI->hasStackFrame()) {
312 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
314 // Unwind MBBI to point to first LDR / VLDRD.
315 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
316 if (MBBI != MBB.begin()) {
319 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
320 if (!isCSRestore(MBBI, TII, CSRegs))
324 // Move SP to start of FP callee save spill area.
325 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
326 AFI->getGPRCalleeSavedArea2Size() +
327 AFI->getDPRCalleeSavedAreaSize());
329 // Reset SP based on frame pointer only if the stack frame extends beyond
330 // frame pointer stack slot or target is ELF and the function has FP.
331 if (AFI->shouldRestoreSPFromFP()) {
332 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
335 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
338 // It's not possible to restore SP from FP in a single instruction.
339 // For Darwin, this looks like:
342 // This is bad, if an interrupt is taken after the mov, sp is in an
343 // inconsistent state.
344 // Use the first callee-saved register as a scratch register.
345 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
346 "No scratch register to restore SP from FP!");
347 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
349 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
355 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
356 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
358 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
362 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
364 // Increment past our save areas.
365 if (AFI->getDPRCalleeSavedAreaSize()) MBBI++;
366 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
367 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
370 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
371 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
372 // Tail call return: adjust the stack pointer and jump to callee.
373 MBBI = prior(MBB.end());
374 MachineOperand &JumpTarget = MBBI->getOperand(0);
376 // Jump to label or value in register.
377 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND) {
378 unsigned TCOpcode = (RetOpcode == ARM::TCRETURNdi)
379 ? (STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)
380 : (STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND);
381 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
382 if (JumpTarget.isGlobal())
383 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
384 JumpTarget.getTargetFlags());
386 assert(JumpTarget.isSymbol());
387 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
388 JumpTarget.getTargetFlags());
390 } else if (RetOpcode == ARM::TCRETURNri) {
391 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
392 addReg(JumpTarget.getReg(), RegState::Kill);
393 } else if (RetOpcode == ARM::TCRETURNriND) {
394 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
395 addReg(JumpTarget.getReg(), RegState::Kill);
398 MachineInstr *NewMI = prior(MBBI);
399 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
400 NewMI->addOperand(MBBI->getOperand(i));
402 // Delete the pseudo instruction TCRETURN.
407 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
410 // Provide a base+offset reference to an FI slot for debug info. It's the
411 // same as what we use for resolving the code-gen references for now.
412 // FIXME: This can go wrong when references are SP-relative and simple call
413 // frames aren't used.
415 ARMFrameInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
416 unsigned &FrameReg) const {
417 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
421 ARMFrameInfo::ResolveFrameIndexReference(const MachineFunction &MF,
425 const MachineFrameInfo *MFI = MF.getFrameInfo();
426 const ARMBaseRegisterInfo *RegInfo =
427 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
428 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
429 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
430 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
431 bool isFixed = MFI->isFixedObjectIndex(FI);
435 if (AFI->isGPRCalleeSavedArea1Frame(FI))
436 return Offset - AFI->getGPRCalleeSavedArea1Offset();
437 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
438 return Offset - AFI->getGPRCalleeSavedArea2Offset();
439 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
440 return Offset - AFI->getDPRCalleeSavedAreaOffset();
442 // When dynamically realigning the stack, use the frame pointer for
443 // parameters, and the stack/base pointer for locals.
444 if (RegInfo->needsStackRealignment(MF)) {
445 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
447 FrameReg = RegInfo->getFrameRegister(MF);
449 } else if (MFI->hasVarSizedObjects()) {
450 assert(RegInfo->hasBasePointer(MF) &&
451 "VLAs and dynamic stack alignment, but missing base pointer!");
452 FrameReg = RegInfo->getBaseRegister();
457 // If there is a frame pointer, use it when we can.
458 if (hasFP(MF) && AFI->hasStackFrame()) {
459 // Use frame pointer to reference fixed objects. Use it for locals if
460 // there are VLAs (and thus the SP isn't reliable as a base).
461 if (isFixed || (MFI->hasVarSizedObjects() && !RegInfo->hasBasePointer(MF))) {
462 FrameReg = RegInfo->getFrameRegister(MF);
464 } else if (MFI->hasVarSizedObjects()) {
465 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
466 // Try to use the frame pointer if we can, else use the base pointer
467 // since it's available. This is handy for the emergency spill slot, in
469 if (AFI->isThumb2Function()) {
470 if (FPOffset >= -255 && FPOffset < 0) {
471 FrameReg = RegInfo->getFrameRegister(MF);
475 FrameReg = RegInfo->getBaseRegister();
476 } else if (AFI->isThumb2Function()) {
477 // In Thumb2 mode, the negative offset is very limited. Try to avoid
478 // out of range references.
479 if (FPOffset >= -255 && FPOffset < 0) {
480 FrameReg = RegInfo->getFrameRegister(MF);
483 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
484 // Otherwise, use SP or FP, whichever is closer to the stack slot.
485 FrameReg = RegInfo->getFrameRegister(MF);
489 // Use the base pointer if we have one.
490 if (RegInfo->hasBasePointer(MF))
491 FrameReg = RegInfo->getBaseRegister();
495 int ARMFrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
497 return getFrameIndexReference(MF, FI, FrameReg);
500 void ARMFrameInfo::emitPushInst(MachineBasicBlock &MBB,
501 MachineBasicBlock::iterator MI,
502 const std::vector<CalleeSavedInfo> &CSI,
503 unsigned Opc, bool NoGap,
504 bool(*Func)(unsigned, bool)) const {
505 MachineFunction &MF = *MBB.getParent();
506 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
509 if (MI != MBB.end()) DL = MI->getDebugLoc();
511 SmallVector<std::pair<unsigned,bool>, 4> Regs;
512 unsigned i = CSI.size();
514 unsigned LastReg = 0;
515 for (; i != 0; --i) {
516 unsigned Reg = CSI[i-1].getReg();
517 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
519 // Add the callee-saved register as live-in unless it's LR and
520 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
521 // then it's already added to the function and entry block live-in sets.
523 if (Reg == ARM::LR) {
524 if (MF.getFrameInfo()->isReturnAddressTaken() &&
525 MF.getRegInfo().isLiveIn(Reg))
532 // If NoGap is true, pop consecutive registers and then leave the rest
533 // for other instructions. e.g.
534 // vpush {d8, d10, d11} -> vpush {d8}, vpop {d10, d11}
535 if (NoGap && LastReg && LastReg != Reg-1)
538 Regs.push_back(std::make_pair(Reg, isKill));
542 MachineInstrBuilder MIB =
543 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc),ARM::SP)
545 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
546 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
552 void ARMFrameInfo::emitPopInst(MachineBasicBlock &MBB,
553 MachineBasicBlock::iterator MI,
554 const std::vector<CalleeSavedInfo> &CSI,
555 unsigned Opc, bool isVarArg, bool NoGap,
556 bool(*Func)(unsigned, bool)) const {
557 MachineFunction &MF = *MBB.getParent();
558 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
559 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
560 DebugLoc DL = MI->getDebugLoc();
562 SmallVector<unsigned, 4> Regs;
563 unsigned i = CSI.size();
565 unsigned LastReg = 0;
566 bool DeleteRet = false;
567 for (; i != 0; --i) {
568 unsigned Reg = CSI[i-1].getReg();
569 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
571 if (Reg == ARM::LR && !isVarArg) {
573 Opc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
574 // Fold the return instruction into the LDM.
578 // If NoGap is true, pop consecutive registers and then leave the rest
579 // for other instructions. e.g.
580 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
581 if (NoGap && LastReg && LastReg != Reg-1)
589 MachineInstrBuilder MIB =
590 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
592 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
593 MIB.addReg(Regs[i], getDefRegState(true));
595 MI->eraseFromParent();
602 bool ARMFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
603 MachineBasicBlock::iterator MI,
604 const std::vector<CalleeSavedInfo> &CSI,
605 const TargetRegisterInfo *TRI) const {
609 MachineFunction &MF = *MBB.getParent();
610 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
611 DebugLoc DL = MI->getDebugLoc();
613 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
614 unsigned FltOpc = ARM::VSTMDDB_UPD;
615 emitPushInst(MBB, MI, CSI, PushOpc, false, &isARMArea1Register);
616 emitPushInst(MBB, MI, CSI, PushOpc, false, &isARMArea2Register);
617 emitPushInst(MBB, MI, CSI, FltOpc, true, &isARMArea3Register);
622 bool ARMFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
623 MachineBasicBlock::iterator MI,
624 const std::vector<CalleeSavedInfo> &CSI,
625 const TargetRegisterInfo *TRI) const {
629 MachineFunction &MF = *MBB.getParent();
630 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
631 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
632 DebugLoc DL = MI->getDebugLoc();
634 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
635 unsigned FltOpc = ARM::VLDMDIA_UPD;
636 emitPopInst(MBB, MI, CSI, FltOpc, isVarArg, true, &isARMArea3Register);
637 emitPopInst(MBB, MI, CSI, PopOpc, isVarArg, false, &isARMArea2Register);
638 emitPopInst(MBB, MI, CSI, PopOpc, isVarArg, false, &isARMArea1Register);
643 // FIXME: Make generic?
644 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
645 const ARMBaseInstrInfo &TII) {
647 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
649 const MachineBasicBlock &MBB = *MBBI;
650 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
652 FnSize += TII.GetInstSizeInBytes(I);
657 /// estimateStackSize - Estimate and return the size of the frame.
658 /// FIXME: Make generic?
659 static unsigned estimateStackSize(MachineFunction &MF) {
660 const MachineFrameInfo *FFI = MF.getFrameInfo();
662 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
663 int FixedOff = -FFI->getObjectOffset(i);
664 if (FixedOff > Offset) Offset = FixedOff;
666 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
667 if (FFI->isDeadObjectIndex(i))
669 Offset += FFI->getObjectSize(i);
670 unsigned Align = FFI->getObjectAlignment(i);
671 // Adjust to alignment boundary
672 Offset = (Offset+Align-1)/Align*Align;
674 return (unsigned)Offset;
677 /// estimateRSStackSizeLimit - Look at each instruction that references stack
678 /// frames and return the stack size limit beyond which some of these
679 /// instructions will require a scratch register during their expansion later.
680 // FIXME: Move to TII?
681 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
682 const TargetFrameInfo *TFI) {
683 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
684 unsigned Limit = (1 << 12) - 1;
685 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
686 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
688 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
689 if (!I->getOperand(i).isFI()) continue;
691 // When using ADDri to get the address of a stack object, 255 is the
692 // largest offset guaranteed to fit in the immediate offset.
693 if (I->getOpcode() == ARM::ADDri) {
694 Limit = std::min(Limit, (1U << 8) - 1);
698 // Otherwise check the addressing mode.
699 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
700 case ARMII::AddrMode3:
701 case ARMII::AddrModeT2_i8:
702 Limit = std::min(Limit, (1U << 8) - 1);
704 case ARMII::AddrMode5:
705 case ARMII::AddrModeT2_i8s4:
706 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
708 case ARMII::AddrModeT2_i12:
709 // i12 supports only positive offset so these will be converted to
710 // i8 opcodes. See llvm::rewriteT2FrameIndex.
711 if (TFI->hasFP(MF) && AFI->hasStackFrame())
712 Limit = std::min(Limit, (1U << 8) - 1);
714 case ARMII::AddrMode4:
715 case ARMII::AddrMode6:
716 // Addressing modes 4 & 6 (load/store) instructions can't encode an
717 // immediate offset for stack references.
722 break; // At most one FI per instruction
731 ARMFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
732 RegScavenger *RS) const {
733 // This tells PEI to spill the FP as if it is any other callee-save register
734 // to take advantage the eliminateFrameIndex machinery. This also ensures it
735 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
736 // to combine multiple loads / stores.
737 bool CanEliminateFrame = true;
738 bool CS1Spilled = false;
739 bool LRSpilled = false;
740 unsigned NumGPRSpills = 0;
741 SmallVector<unsigned, 4> UnspilledCS1GPRs;
742 SmallVector<unsigned, 4> UnspilledCS2GPRs;
743 const ARMBaseRegisterInfo *RegInfo =
744 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
745 const ARMBaseInstrInfo &TII =
746 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
747 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
748 MachineFrameInfo *MFI = MF.getFrameInfo();
749 unsigned FramePtr = RegInfo->getFrameRegister(MF);
751 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
752 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
753 // since it's always posible to restore sp from fp in a single instruction.
754 // FIXME: It will be better just to find spare register here.
755 if (AFI->isThumb2Function() &&
756 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
757 MF.getRegInfo().setPhysRegUsed(ARM::R4);
759 // Spill LR if Thumb1 function uses variable length argument lists.
760 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
761 MF.getRegInfo().setPhysRegUsed(ARM::LR);
763 // Spill the BasePtr if it's used.
764 if (RegInfo->hasBasePointer(MF))
765 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
767 // Don't spill FP if the frame can be eliminated. This is determined
768 // by scanning the callee-save registers to see if any is used.
769 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
770 for (unsigned i = 0; CSRegs[i]; ++i) {
771 unsigned Reg = CSRegs[i];
772 bool Spilled = false;
773 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
774 AFI->setCSRegisterIsSpilled(Reg);
776 CanEliminateFrame = false;
778 // Check alias registers too.
779 for (const unsigned *Aliases =
780 RegInfo->getAliasSet(Reg); *Aliases; ++Aliases) {
781 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
783 CanEliminateFrame = false;
788 if (!ARM::GPRRegisterClass->contains(Reg))
794 if (!STI.isTargetDarwin()) {
801 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
806 case ARM::R4: case ARM::R5:
807 case ARM::R6: case ARM::R7:
814 if (!STI.isTargetDarwin()) {
815 UnspilledCS1GPRs.push_back(Reg);
820 case ARM::R4: case ARM::R5:
821 case ARM::R6: case ARM::R7:
823 UnspilledCS1GPRs.push_back(Reg);
826 UnspilledCS2GPRs.push_back(Reg);
832 bool ForceLRSpill = false;
833 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
834 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
835 // Force LR to be spilled if the Thumb function size is > 2048. This enables
836 // use of BL to implement far jump. If it turns out that it's not needed
837 // then the branch fix up path will undo it.
838 if (FnSize >= (1 << 11)) {
839 CanEliminateFrame = false;
844 // If any of the stack slot references may be out of range of an immediate
845 // offset, make sure a register (or a spill slot) is available for the
846 // register scavenger. Note that if we're indexing off the frame pointer, the
847 // effective stack size is 4 bytes larger since the FP points to the stack
848 // slot of the previous FP. Also, if we have variable sized objects in the
849 // function, stack slot references will often be negative, and some of
850 // our instructions are positive-offset only, so conservatively consider
851 // that case to want a spill slot (or register) as well. Similarly, if
852 // the function adjusts the stack pointer during execution and the
853 // adjustments aren't already part of our stack size estimate, our offset
854 // calculations may be off, so be conservative.
855 // FIXME: We could add logic to be more precise about negative offsets
856 // and which instructions will need a scratch register for them. Is it
857 // worth the effort and added fragility?
860 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
861 estimateRSStackSizeLimit(MF, this)))
862 || MFI->hasVarSizedObjects()
863 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
865 bool ExtraCSSpill = false;
866 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
867 AFI->setHasStackFrame(true);
869 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
870 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
871 if (!LRSpilled && CS1Spilled) {
872 MF.getRegInfo().setPhysRegUsed(ARM::LR);
873 AFI->setCSRegisterIsSpilled(ARM::LR);
875 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
876 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
877 ForceLRSpill = false;
882 MF.getRegInfo().setPhysRegUsed(FramePtr);
886 // If stack and double are 8-byte aligned and we are spilling an odd number
887 // of GPRs, spill one extra callee save GPR so we won't have to pad between
888 // the integer and double callee save areas.
889 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
890 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
891 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
892 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
893 unsigned Reg = UnspilledCS1GPRs[i];
894 // Don't spill high register if the function is thumb1
895 if (!AFI->isThumb1OnlyFunction() ||
896 isARMLowRegister(Reg) || Reg == ARM::LR) {
897 MF.getRegInfo().setPhysRegUsed(Reg);
898 AFI->setCSRegisterIsSpilled(Reg);
899 if (!RegInfo->isReservedReg(MF, Reg))
904 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
905 unsigned Reg = UnspilledCS2GPRs.front();
906 MF.getRegInfo().setPhysRegUsed(Reg);
907 AFI->setCSRegisterIsSpilled(Reg);
908 if (!RegInfo->isReservedReg(MF, Reg))
913 // Estimate if we might need to scavenge a register at some point in order
914 // to materialize a stack offset. If so, either spill one additional
915 // callee-saved register or reserve a special spill slot to facilitate
916 // register scavenging. Thumb1 needs a spill slot for stack pointer
917 // adjustments also, even when the frame itself is small.
918 if (BigStack && !ExtraCSSpill) {
919 // If any non-reserved CS register isn't spilled, just spill one or two
920 // extra. That should take care of it!
921 unsigned NumExtras = TargetAlign / 4;
922 SmallVector<unsigned, 2> Extras;
923 while (NumExtras && !UnspilledCS1GPRs.empty()) {
924 unsigned Reg = UnspilledCS1GPRs.back();
925 UnspilledCS1GPRs.pop_back();
926 if (!RegInfo->isReservedReg(MF, Reg) &&
927 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
929 Extras.push_back(Reg);
933 // For non-Thumb1 functions, also check for hi-reg CS registers
934 if (!AFI->isThumb1OnlyFunction()) {
935 while (NumExtras && !UnspilledCS2GPRs.empty()) {
936 unsigned Reg = UnspilledCS2GPRs.back();
937 UnspilledCS2GPRs.pop_back();
938 if (!RegInfo->isReservedReg(MF, Reg)) {
939 Extras.push_back(Reg);
944 if (Extras.size() && NumExtras == 0) {
945 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
946 MF.getRegInfo().setPhysRegUsed(Extras[i]);
947 AFI->setCSRegisterIsSpilled(Extras[i]);
949 } else if (!AFI->isThumb1OnlyFunction()) {
950 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
951 // closest to SP or frame pointer.
952 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
953 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
961 MF.getRegInfo().setPhysRegUsed(ARM::LR);
962 AFI->setCSRegisterIsSpilled(ARM::LR);
963 AFI->setLRIsSpilledForFarJump(true);