1 //=======- ARMFrameInfo.cpp - ARM Frame Information ------------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameInfo.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 /// Move iterator past the next bunch of callee save load / store ops for
24 /// the particular spill area (1: integer area 1, 2: integer area 2,
25 /// 3: fp area, 0: don't care).
26 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
27 MachineBasicBlock::iterator &MBBI,
28 int Opc1, int Opc2, unsigned Area,
29 const ARMSubtarget &STI) {
30 while (MBBI != MBB.end() &&
31 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
32 MBBI->getOperand(1).isFI()) {
35 unsigned Category = 0;
36 switch (MBBI->getOperand(0).getReg()) {
37 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
41 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
42 Category = STI.isTargetDarwin() ? 2 : 1;
44 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
45 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
52 if (Done || Category != Area)
60 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
61 for (unsigned i = 0; CSRegs[i]; ++i)
67 static bool isCSRestore(MachineInstr *MI,
68 const ARMBaseInstrInfo &TII,
69 const unsigned *CSRegs) {
70 return ((MI->getOpcode() == (int)ARM::VLDRD ||
71 MI->getOpcode() == (int)ARM::LDRi12 ||
72 MI->getOpcode() == (int)ARM::t2LDRi12) &&
73 MI->getOperand(1).isFI() &&
74 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
78 emitSPUpdate(bool isARM,
79 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
80 DebugLoc dl, const ARMBaseInstrInfo &TII,
82 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
84 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
87 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
91 void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
92 MachineBasicBlock &MBB = MF.front();
93 MachineBasicBlock::iterator MBBI = MBB.begin();
94 MachineFrameInfo *MFI = MF.getFrameInfo();
95 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
96 const ARMBaseRegisterInfo *RegInfo =
97 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
98 const ARMBaseInstrInfo &TII =
99 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
100 assert(!AFI->isThumb1OnlyFunction() &&
101 "This emitPrologue does not support Thumb1!");
102 bool isARM = !AFI->isThumbFunction();
103 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
104 unsigned NumBytes = MFI->getStackSize();
105 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
106 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
107 unsigned FramePtr = RegInfo->getFrameRegister(MF);
109 // Determine the sizes of each callee-save spill areas and record which frame
110 // belongs to which callee-save spill areas.
111 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
112 int FramePtrSpillFI = 0;
114 // Allocate the vararg register save area. This is not counted in NumBytes.
116 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
118 if (!AFI->hasStackFrame()) {
120 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
124 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
125 unsigned Reg = CSI[i].getReg();
126 int FI = CSI[i].getFrameIdx();
134 FramePtrSpillFI = FI;
135 AFI->addGPRCalleeSavedArea1Frame(FI);
143 FramePtrSpillFI = FI;
144 if (STI.isTargetDarwin()) {
145 AFI->addGPRCalleeSavedArea2Frame(FI);
148 AFI->addGPRCalleeSavedArea1Frame(FI);
153 AFI->addDPRCalleeSavedAreaFrame(FI);
158 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
159 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
160 movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI);
162 // Set FP to point to the stack slot that contains the previous FP.
163 // For Darwin, FP is R7, which has now been stored in spill area 1.
164 // Otherwise, if this is not Darwin, all the callee-saved registers go
165 // into spill area 1, including the FP in R11. In either case, it is
166 // now safe to emit this assignment.
167 bool HasFP = RegInfo->hasFP(MF);
169 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
170 MachineInstrBuilder MIB =
171 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
172 .addFrameIndex(FramePtrSpillFI).addImm(0);
173 AddDefaultCC(AddDefaultPred(MIB));
176 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
177 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
179 // Build the new SUBri to adjust SP for FP callee-save spill area.
180 movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 2, STI);
181 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
183 // Determine starting offsets of spill areas.
184 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
185 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
186 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
188 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
190 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
191 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
192 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
194 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
195 NumBytes = DPRCSOffset;
197 // Adjust SP after all the callee-save spills.
198 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
200 AFI->setShouldRestoreSPFromFP(true);
203 if (STI.isTargetELF() && RegInfo->hasFP(MF)) {
204 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
205 AFI->getFramePtrSpillOffset());
206 AFI->setShouldRestoreSPFromFP(true);
209 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
210 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
211 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
213 // If we need dynamic stack realignment, do it here. Be paranoid and make
214 // sure if we also have VLAs, we have a base pointer for frame access.
215 if (RegInfo->needsStackRealignment(MF)) {
216 unsigned MaxAlign = MFI->getMaxAlignment();
217 assert (!AFI->isThumb1OnlyFunction());
218 if (!AFI->isThumbFunction()) {
219 // Emit bic sp, sp, MaxAlign
220 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
221 TII.get(ARM::BICri), ARM::SP)
222 .addReg(ARM::SP, RegState::Kill)
223 .addImm(MaxAlign-1)));
225 // We cannot use sp as source/dest register here, thus we're emitting the
226 // following sequence:
228 // bic r4, r4, MaxAlign
230 // FIXME: It will be better just to find spare register here.
231 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
232 .addReg(ARM::SP, RegState::Kill);
233 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
234 TII.get(ARM::t2BICri), ARM::R4)
235 .addReg(ARM::R4, RegState::Kill)
236 .addImm(MaxAlign-1)));
237 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
238 .addReg(ARM::R4, RegState::Kill);
241 AFI->setShouldRestoreSPFromFP(true);
244 // If we need a base pointer, set it up here. It's whatever the value
245 // of the stack pointer is at this point. Any variable size objects
246 // will be allocated after this, so we can still use the base pointer
247 // to reference locals.
248 if (RegInfo->hasBasePointer(MF)) {
250 BuildMI(MBB, MBBI, dl,
251 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
253 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
255 BuildMI(MBB, MBBI, dl,
256 TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister())
260 // If the frame has variable sized objects then the epilogue must restore
262 if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
263 AFI->setShouldRestoreSPFromFP(true);
266 void ARMFrameInfo::emitEpilogue(MachineFunction &MF,
267 MachineBasicBlock &MBB) const {
268 MachineBasicBlock::iterator MBBI = prior(MBB.end());
269 assert(MBBI->getDesc().isReturn() &&
270 "Can only insert epilog into returning blocks");
271 unsigned RetOpcode = MBBI->getOpcode();
272 DebugLoc dl = MBBI->getDebugLoc();
273 MachineFrameInfo *MFI = MF.getFrameInfo();
274 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
275 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
276 const ARMBaseInstrInfo &TII =
277 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
278 assert(!AFI->isThumb1OnlyFunction() &&
279 "This emitEpilogue does not support Thumb1!");
280 bool isARM = !AFI->isThumbFunction();
282 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
283 int NumBytes = (int)MFI->getStackSize();
284 unsigned FramePtr = RegInfo->getFrameRegister(MF);
286 if (!AFI->hasStackFrame()) {
288 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
290 // Unwind MBBI to point to first LDR / VLDRD.
291 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
292 if (MBBI != MBB.begin()) {
295 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
296 if (!isCSRestore(MBBI, TII, CSRegs))
300 // Move SP to start of FP callee save spill area.
301 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
302 AFI->getGPRCalleeSavedArea2Size() +
303 AFI->getDPRCalleeSavedAreaSize());
305 // Reset SP based on frame pointer only if the stack frame extends beyond
306 // frame pointer stack slot or target is ELF and the function has FP.
307 if (AFI->shouldRestoreSPFromFP()) {
308 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
311 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
314 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
319 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
320 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
322 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
326 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
328 // Move SP to start of integer callee save spill area 2.
329 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
330 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
332 // Move SP to start of integer callee save spill area 1.
333 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 2, STI);
334 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
336 // Move SP to SP upon entry to the function.
337 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI);
338 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
341 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
342 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
343 // Tail call return: adjust the stack pointer and jump to callee.
344 MBBI = prior(MBB.end());
345 MachineOperand &JumpTarget = MBBI->getOperand(0);
347 // Jump to label or value in register.
348 if (RetOpcode == ARM::TCRETURNdi) {
349 BuildMI(MBB, MBBI, dl,
350 TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
351 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
352 JumpTarget.getTargetFlags());
353 } else if (RetOpcode == ARM::TCRETURNdiND) {
354 BuildMI(MBB, MBBI, dl,
355 TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
356 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
357 JumpTarget.getTargetFlags());
358 } else if (RetOpcode == ARM::TCRETURNri) {
359 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
360 addReg(JumpTarget.getReg(), RegState::Kill);
361 } else if (RetOpcode == ARM::TCRETURNriND) {
362 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
363 addReg(JumpTarget.getReg(), RegState::Kill);
366 MachineInstr *NewMI = prior(MBBI);
367 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
368 NewMI->addOperand(MBBI->getOperand(i));
370 // Delete the pseudo instruction TCRETURN.
375 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);