1 //=======- ARMFrameInfo.cpp - ARM Frame Information ------------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameInfo.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
24 for (unsigned i = 0; CSRegs[i]; ++i)
30 static bool isCSRestore(MachineInstr *MI,
31 const ARMBaseInstrInfo &TII,
32 const unsigned *CSRegs) {
33 // Integer spill area is handled with "pop".
34 if (MI->getOpcode() == ARM::LDMIA_RET ||
35 MI->getOpcode() == ARM::t2LDMIA_RET ||
36 MI->getOpcode() == ARM::LDMIA_UPD ||
37 MI->getOpcode() == ARM::t2LDMIA_UPD ||
38 MI->getOpcode() == ARM::VLDMDIA_UPD) {
39 // The first two operands are predicates. The last two are
40 // imp-def and imp-use of SP. Check everything in between.
41 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
42 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
51 emitSPUpdate(bool isARM,
52 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
53 DebugLoc dl, const ARMBaseInstrInfo &TII,
55 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
57 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
60 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
64 void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
65 MachineBasicBlock &MBB = MF.front();
66 MachineBasicBlock::iterator MBBI = MBB.begin();
67 MachineFrameInfo *MFI = MF.getFrameInfo();
68 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
69 const ARMBaseRegisterInfo *RegInfo =
70 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
71 const ARMBaseInstrInfo &TII =
72 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
73 assert(!AFI->isThumb1OnlyFunction() &&
74 "This emitPrologue does not support Thumb1!");
75 bool isARM = !AFI->isThumbFunction();
76 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
77 unsigned NumBytes = MFI->getStackSize();
78 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
79 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
80 unsigned FramePtr = RegInfo->getFrameRegister(MF);
82 // Determine the sizes of each callee-save spill areas and record which frame
83 // belongs to which callee-save spill areas.
84 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
85 int FramePtrSpillFI = 0;
87 // Allocate the vararg register save area. This is not counted in NumBytes.
89 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
91 if (!AFI->hasStackFrame()) {
93 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
97 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
98 unsigned Reg = CSI[i].getReg();
99 int FI = CSI[i].getFrameIdx();
107 FramePtrSpillFI = FI;
108 AFI->addGPRCalleeSavedArea1Frame(FI);
116 FramePtrSpillFI = FI;
117 if (STI.isTargetDarwin()) {
118 AFI->addGPRCalleeSavedArea2Frame(FI);
121 AFI->addGPRCalleeSavedArea1Frame(FI);
126 AFI->addDPRCalleeSavedAreaFrame(FI);
132 if (GPRCS1Size > 0) MBBI++;
134 // Set FP to point to the stack slot that contains the previous FP.
135 // For Darwin, FP is R7, which has now been stored in spill area 1.
136 // Otherwise, if this is not Darwin, all the callee-saved registers go
137 // into spill area 1, including the FP in R11. In either case, it is
138 // now safe to emit this assignment.
139 bool HasFP = RegInfo->hasFP(MF);
141 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
142 MachineInstrBuilder MIB =
143 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
144 .addFrameIndex(FramePtrSpillFI).addImm(0);
145 AddDefaultCC(AddDefaultPred(MIB));
149 if (GPRCS2Size > 0) MBBI++;
151 // Determine starting offsets of spill areas.
152 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
153 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
154 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
156 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
158 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
159 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
160 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
163 if (DPRCSSize > 0) MBBI++;
165 NumBytes = DPRCSOffset;
167 // Adjust SP after all the callee-save spills.
168 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
170 AFI->setShouldRestoreSPFromFP(true);
173 if (STI.isTargetELF() && RegInfo->hasFP(MF)) {
174 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
175 AFI->getFramePtrSpillOffset());
176 AFI->setShouldRestoreSPFromFP(true);
179 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
180 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
181 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
183 // If we need dynamic stack realignment, do it here. Be paranoid and make
184 // sure if we also have VLAs, we have a base pointer for frame access.
185 if (RegInfo->needsStackRealignment(MF)) {
186 unsigned MaxAlign = MFI->getMaxAlignment();
187 assert (!AFI->isThumb1OnlyFunction());
188 if (!AFI->isThumbFunction()) {
189 // Emit bic sp, sp, MaxAlign
190 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
191 TII.get(ARM::BICri), ARM::SP)
192 .addReg(ARM::SP, RegState::Kill)
193 .addImm(MaxAlign-1)));
195 // We cannot use sp as source/dest register here, thus we're emitting the
196 // following sequence:
198 // bic r4, r4, MaxAlign
200 // FIXME: It will be better just to find spare register here.
201 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
202 .addReg(ARM::SP, RegState::Kill);
203 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
204 TII.get(ARM::t2BICri), ARM::R4)
205 .addReg(ARM::R4, RegState::Kill)
206 .addImm(MaxAlign-1)));
207 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
208 .addReg(ARM::R4, RegState::Kill);
211 AFI->setShouldRestoreSPFromFP(true);
214 // If we need a base pointer, set it up here. It's whatever the value
215 // of the stack pointer is at this point. Any variable size objects
216 // will be allocated after this, so we can still use the base pointer
217 // to reference locals.
218 if (RegInfo->hasBasePointer(MF)) {
220 BuildMI(MBB, MBBI, dl,
221 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
223 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
225 BuildMI(MBB, MBBI, dl,
226 TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister())
230 // If the frame has variable sized objects then the epilogue must restore
232 if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
233 AFI->setShouldRestoreSPFromFP(true);
236 void ARMFrameInfo::emitEpilogue(MachineFunction &MF,
237 MachineBasicBlock &MBB) const {
238 MachineBasicBlock::iterator MBBI = prior(MBB.end());
239 assert(MBBI->getDesc().isReturn() &&
240 "Can only insert epilog into returning blocks");
241 unsigned RetOpcode = MBBI->getOpcode();
242 DebugLoc dl = MBBI->getDebugLoc();
243 MachineFrameInfo *MFI = MF.getFrameInfo();
244 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
245 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
246 const ARMBaseInstrInfo &TII =
247 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
248 assert(!AFI->isThumb1OnlyFunction() &&
249 "This emitEpilogue does not support Thumb1!");
250 bool isARM = !AFI->isThumbFunction();
252 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
253 int NumBytes = (int)MFI->getStackSize();
254 unsigned FramePtr = RegInfo->getFrameRegister(MF);
256 if (!AFI->hasStackFrame()) {
258 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
260 // Unwind MBBI to point to first LDR / VLDRD.
261 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
262 if (MBBI != MBB.begin()) {
265 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
266 if (!isCSRestore(MBBI, TII, CSRegs))
270 // Move SP to start of FP callee save spill area.
271 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
272 AFI->getGPRCalleeSavedArea2Size() +
273 AFI->getDPRCalleeSavedAreaSize());
275 // Reset SP based on frame pointer only if the stack frame extends beyond
276 // frame pointer stack slot or target is ELF and the function has FP.
277 if (AFI->shouldRestoreSPFromFP()) {
278 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
281 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
284 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
289 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
290 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
292 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
296 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
298 // Increment past our save areas.
299 if (AFI->getDPRCalleeSavedAreaSize()) MBBI++;
300 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
301 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
304 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
305 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
306 // Tail call return: adjust the stack pointer and jump to callee.
307 MBBI = prior(MBB.end());
308 MachineOperand &JumpTarget = MBBI->getOperand(0);
310 // Jump to label or value in register.
311 if (RetOpcode == ARM::TCRETURNdi) {
312 BuildMI(MBB, MBBI, dl,
313 TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
314 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
315 JumpTarget.getTargetFlags());
316 } else if (RetOpcode == ARM::TCRETURNdiND) {
317 BuildMI(MBB, MBBI, dl,
318 TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
319 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
320 JumpTarget.getTargetFlags());
321 } else if (RetOpcode == ARM::TCRETURNri) {
322 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
323 addReg(JumpTarget.getReg(), RegState::Kill);
324 } else if (RetOpcode == ARM::TCRETURNriND) {
325 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
326 addReg(JumpTarget.getReg(), RegState::Kill);
329 MachineInstr *NewMI = prior(MBBI);
330 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
331 NewMI->addOperand(MBBI->getOperand(i));
333 // Delete the pseudo instruction TCRETURN.
338 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);