1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Target/TargetOptions.h"
35 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
36 cl::desc("Align ARM NEON spills in prolog and epilog"));
38 static MachineBasicBlock::iterator
39 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
40 unsigned NumAlignedDPRCS2Regs);
42 ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)
43 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
46 /// hasFP - Return true if the specified function should have a dedicated frame
47 /// pointer register. This is true if the function has variable sized allocas
48 /// or if frame pointer elimination is disabled.
49 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
50 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
52 // iOS requires FP not to be clobbered for backtracing purpose.
53 if (STI.isTargetIOS())
56 const MachineFrameInfo *MFI = MF.getFrameInfo();
57 // Always eliminate non-leaf frame pointers.
58 return ((MF.getTarget().Options.DisableFramePointerElim(MF) &&
60 RegInfo->needsStackRealignment(MF) ||
61 MFI->hasVarSizedObjects() ||
62 MFI->isFrameAddressTaken());
65 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
66 /// not required, we reserve argument space for call sites in the function
67 /// immediately on entry to the current function. This eliminates the need for
68 /// add/sub sp brackets around call sites. Returns true if the call frame is
69 /// included as part of the stack frame.
70 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
71 const MachineFrameInfo *FFI = MF.getFrameInfo();
72 unsigned CFSize = FFI->getMaxCallFrameSize();
73 // It's not always a good idea to include the call frame as part of the
74 // stack frame. ARM (especially Thumb) has small immediate offset to
75 // address the stack frame. So a large call frame can cause poor codegen
76 // and may even makes it impossible to scavenge a register.
77 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
80 return !MF.getFrameInfo()->hasVarSizedObjects();
83 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
84 /// call frame pseudos can be simplified. Unlike most targets, having a FP
85 /// is not sufficient here since we still may reference some objects via SP
86 /// even when FP is available in Thumb2 mode.
88 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
89 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
92 static bool isCSRestore(MachineInstr *MI,
93 const ARMBaseInstrInfo &TII,
94 const MCPhysReg *CSRegs) {
95 // Integer spill area is handled with "pop".
96 if (isPopOpcode(MI->getOpcode())) {
97 // The first two operands are predicates. The last two are
98 // imp-def and imp-use of SP. Check everything in between.
99 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
100 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
104 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
105 MI->getOpcode() == ARM::LDR_POST_REG ||
106 MI->getOpcode() == ARM::t2LDR_POST) &&
107 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
108 MI->getOperand(1).getReg() == ARM::SP)
114 static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
116 const ARMBaseInstrInfo &TII, unsigned DestReg,
117 unsigned SrcReg, int NumBytes,
118 unsigned MIFlags = MachineInstr::NoFlags,
119 ARMCC::CondCodes Pred = ARMCC::AL,
120 unsigned PredReg = 0) {
122 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
123 Pred, PredReg, TII, MIFlags);
125 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
126 Pred, PredReg, TII, MIFlags);
129 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
130 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
131 const ARMBaseInstrInfo &TII, int NumBytes,
132 unsigned MIFlags = MachineInstr::NoFlags,
133 ARMCC::CondCodes Pred = ARMCC::AL,
134 unsigned PredReg = 0) {
135 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
136 MIFlags, Pred, PredReg);
139 static int sizeOfSPAdjustment(const MachineInstr *MI) {
140 assert(MI->getOpcode() == ARM::VSTMDDB_UPD);
142 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
143 // pred) so the list starts at 4.
144 for (int i = MI->getNumOperands() - 1; i >= 4; --i)
149 static bool WindowsRequiresStackProbe(const MachineFunction &MF,
150 size_t StackSizeInBytes) {
151 const MachineFrameInfo *MFI = MF.getFrameInfo();
152 if (MFI->getStackProtectorIndex() > 0)
153 return StackSizeInBytes >= 4080;
154 return StackSizeInBytes >= 4096;
157 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
158 MachineBasicBlock &MBB = MF.front();
159 MachineBasicBlock::iterator MBBI = MBB.begin();
160 MachineFrameInfo *MFI = MF.getFrameInfo();
161 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
162 MachineModuleInfo &MMI = MF.getMMI();
163 MCContext &Context = MMI.getContext();
164 const TargetMachine &TM = MF.getTarget();
165 const MCRegisterInfo *MRI = Context.getRegisterInfo();
166 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
167 TM.getSubtargetImpl()->getRegisterInfo());
168 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
169 TM.getSubtargetImpl()->getInstrInfo());
170 assert(!AFI->isThumb1OnlyFunction() &&
171 "This emitPrologue does not support Thumb1!");
172 bool isARM = !AFI->isThumbFunction();
174 TM.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
175 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
176 unsigned NumBytes = MFI->getStackSize();
177 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
178 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
179 unsigned FramePtr = RegInfo->getFrameRegister(MF);
182 // Determine the sizes of each callee-save spill areas and record which frame
183 // belongs to which callee-save spill areas.
184 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
185 int FramePtrSpillFI = 0;
188 // All calls are tail calls in GHC calling conv, and functions have no
189 // prologue/epilogue.
190 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
193 // Allocate the vararg register save area.
194 if (ArgRegsSaveSize) {
195 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
196 MachineInstr::FrameSetup);
197 CFAOffset -= ArgRegsSaveSize;
198 unsigned CFIIndex = MMI.addFrameInst(
199 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
200 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
201 .addCFIIndex(CFIIndex);
204 if (!AFI->hasStackFrame() &&
205 (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {
206 if (NumBytes - ArgRegsSaveSize != 0) {
207 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
208 MachineInstr::FrameSetup);
209 CFAOffset -= NumBytes - ArgRegsSaveSize;
210 unsigned CFIIndex = MMI.addFrameInst(
211 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
212 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
213 .addCFIIndex(CFIIndex);
218 // Determine spill area sizes.
219 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
220 unsigned Reg = CSI[i].getReg();
221 int FI = CSI[i].getFrameIdx();
228 if (STI.isTargetDarwin()) {
243 FramePtrSpillFI = FI;
247 // This is a DPR. Exclude the aligned DPRCS2 spills.
250 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
256 MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push,
259 GPRCS1Push = LastPush = MBBI++;
261 // Determine starting offsets of spill areas.
262 bool HasFP = hasFP(MF);
263 unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size;
264 unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
265 unsigned DPRAlign = DPRCSSize ? std::min(8U, Align) : 4U;
266 unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign;
267 unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;
268 int FramePtrOffsetInPush = 0;
270 FramePtrOffsetInPush = MFI->getObjectOffset(FramePtrSpillFI)
271 + GPRCS1Size + ArgRegsSaveSize;
272 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
275 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
276 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
277 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
281 GPRCS2Push = LastPush = MBBI++;
283 // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our
284 // .cfi_offset operations will reflect that.
286 assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs");
287 if (!tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, DPRGapSize))
288 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize,
289 MachineInstr::FrameSetup);
295 // Since vpush register list cannot have gaps, there may be multiple vpush
296 // instructions in the prologue.
297 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD)
301 // Move past the aligned DPRCS2 area.
302 if (AFI->getNumAlignedDPRCS2Regs() > 0) {
303 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
304 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
305 // leaves the stack pointer pointing to the DPRCS2 area.
307 // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
308 NumBytes += MFI->getObjectOffset(D8SpillFI);
310 NumBytes = DPRCSOffset;
312 if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
313 uint32_t NumWords = NumBytes >> 2;
315 if (NumWords < 65536)
316 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
318 .setMIFlags(MachineInstr::FrameSetup));
320 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
322 .setMIFlags(MachineInstr::FrameSetup);
324 switch (TM.getCodeModel()) {
325 case CodeModel::Small:
326 case CodeModel::Medium:
327 case CodeModel::Default:
328 case CodeModel::Kernel:
329 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
330 .addImm((unsigned)ARMCC::AL).addReg(0)
331 .addExternalSymbol("__chkstk")
332 .addReg(ARM::R4, RegState::Implicit)
333 .setMIFlags(MachineInstr::FrameSetup);
335 case CodeModel::Large:
336 case CodeModel::JITDefault:
337 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
338 .addExternalSymbol("__chkstk")
339 .setMIFlags(MachineInstr::FrameSetup);
341 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
342 .addImm((unsigned)ARMCC::AL).addReg(0)
343 .addReg(ARM::R12, RegState::Kill)
344 .addReg(ARM::R4, RegState::Implicit)
345 .setMIFlags(MachineInstr::FrameSetup);
349 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr),
351 .addReg(ARM::SP, RegState::Define)
352 .addReg(ARM::R4, RegState::Kill)
353 .setMIFlags(MachineInstr::FrameSetup)));
357 unsigned adjustedGPRCS1Size = GPRCS1Size;
359 // Adjust SP after all the callee-save spills.
360 if (tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, NumBytes)) {
361 if (LastPush == GPRCS1Push) {
362 FramePtrOffsetInPush += NumBytes;
363 adjustedGPRCS1Size += NumBytes;
367 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
368 MachineInstr::FrameSetup);
371 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
372 // Note it's not safe to do this in Thumb2 mode because it would have
373 // taken two instructions:
376 // If an interrupt is taken between the two instructions, then sp is in
377 // an inconsistent state (pointing to the middle of callee-saved area).
378 // The interrupt handler can end up clobbering the registers.
379 AFI->setShouldRestoreSPFromFP(true);
382 if (adjustedGPRCS1Size > 0) {
383 CFAOffset -= adjustedGPRCS1Size;
384 unsigned CFIIndex = MMI.addFrameInst(
385 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
386 MachineBasicBlock::iterator Pos = ++GPRCS1Push;
387 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
388 .addCFIIndex(CFIIndex);
389 for (const auto &Entry : CSI) {
390 unsigned Reg = Entry.getReg();
391 int FI = Entry.getFrameIdx();
398 if (STI.isTargetDarwin())
410 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
411 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
412 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
413 .addCFIIndex(CFIIndex);
419 // Set FP to point to the stack slot that contains the previous FP.
420 // For iOS, FP is R7, which has now been stored in spill area 1.
421 // Otherwise, if this is not iOS, all the callee-saved registers go
422 // into spill area 1, including the FP in R11. In either case, it
423 // is in area one and the adjustment needs to take place just after
426 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, GPRCS1Push, dl, TII,
427 FramePtr, ARM::SP, FramePtrOffsetInPush,
428 MachineInstr::FrameSetup);
429 if (FramePtrOffsetInPush) {
430 CFAOffset += FramePtrOffsetInPush;
431 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
432 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
433 BuildMI(MBB, GPRCS1Push, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
434 .addCFIIndex(CFIIndex);
438 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
439 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
440 BuildMI(MBB, GPRCS1Push, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
441 .addCFIIndex(CFIIndex);
445 if (GPRCS2Size > 0) {
446 MachineBasicBlock::iterator Pos = ++GPRCS2Push;
448 CFAOffset -= GPRCS2Size;
449 unsigned CFIIndex = MMI.addFrameInst(
450 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
451 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
452 .addCFIIndex(CFIIndex);
454 for (const auto &Entry : CSI) {
455 unsigned Reg = Entry.getReg();
456 int FI = Entry.getFrameIdx();
463 if (STI.isTargetDarwin()) {
464 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
465 unsigned Offset = MFI->getObjectOffset(FI);
466 unsigned CFIIndex = MMI.addFrameInst(
467 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
468 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
469 .addCFIIndex(CFIIndex);
477 // Since vpush register list cannot have gaps, there may be multiple vpush
478 // instructions in the prologue.
480 MachineBasicBlock::iterator Push = DPRCSPush++;
482 CFAOffset -= sizeOfSPAdjustment(Push);
483 unsigned CFIIndex = MMI.addFrameInst(
484 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
485 BuildMI(MBB, DPRCSPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
486 .addCFIIndex(CFIIndex);
488 } while (DPRCSPush->getOpcode() == ARM::VSTMDDB_UPD);
490 for (const auto &Entry : CSI) {
491 unsigned Reg = Entry.getReg();
492 int FI = Entry.getFrameIdx();
493 if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
494 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
495 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
496 unsigned Offset = MFI->getObjectOffset(FI);
497 unsigned CFIIndex = MMI.addFrameInst(
498 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
499 BuildMI(MBB, DPRCSPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
500 .addCFIIndex(CFIIndex);
507 CFAOffset -= NumBytes;
508 unsigned CFIIndex = MMI.addFrameInst(
509 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
510 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
511 .addCFIIndex(CFIIndex);
515 if (STI.isTargetELF() && hasFP(MF))
516 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
517 AFI->getFramePtrSpillOffset());
519 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
520 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
521 AFI->setDPRCalleeSavedGapSize(DPRGapSize);
522 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
524 // If we need dynamic stack realignment, do it here. Be paranoid and make
525 // sure if we also have VLAs, we have a base pointer for frame access.
526 // If aligned NEON registers were spilled, the stack has already been
528 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
529 unsigned MaxAlign = MFI->getMaxAlignment();
530 assert (!AFI->isThumb1OnlyFunction());
531 if (!AFI->isThumbFunction()) {
532 // Emit bic sp, sp, MaxAlign
533 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
534 TII.get(ARM::BICri), ARM::SP)
535 .addReg(ARM::SP, RegState::Kill)
536 .addImm(MaxAlign-1)));
538 // We cannot use sp as source/dest register here, thus we're emitting the
539 // following sequence:
541 // bic r4, r4, MaxAlign
543 // FIXME: It will be better just to find spare register here.
544 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
545 .addReg(ARM::SP, RegState::Kill));
546 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
547 TII.get(ARM::t2BICri), ARM::R4)
548 .addReg(ARM::R4, RegState::Kill)
549 .addImm(MaxAlign-1)));
550 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
551 .addReg(ARM::R4, RegState::Kill));
554 AFI->setShouldRestoreSPFromFP(true);
557 // If we need a base pointer, set it up here. It's whatever the value
558 // of the stack pointer is at this point. Any variable size objects
559 // will be allocated after this, so we can still use the base pointer
560 // to reference locals.
561 // FIXME: Clarify FrameSetup flags here.
562 if (RegInfo->hasBasePointer(MF)) {
564 BuildMI(MBB, MBBI, dl,
565 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
567 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
569 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
570 RegInfo->getBaseRegister())
574 // If the frame has variable sized objects then the epilogue must restore
575 // the sp from fp. We can assume there's an FP here since hasFP already
576 // checks for hasVarSizedObjects.
577 if (MFI->hasVarSizedObjects())
578 AFI->setShouldRestoreSPFromFP(true);
581 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
582 MachineBasicBlock &MBB) const {
583 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
584 assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
585 unsigned RetOpcode = MBBI->getOpcode();
586 DebugLoc dl = MBBI->getDebugLoc();
587 MachineFrameInfo *MFI = MF.getFrameInfo();
588 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
589 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
590 const ARMBaseInstrInfo &TII =
591 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
592 assert(!AFI->isThumb1OnlyFunction() &&
593 "This emitEpilogue does not support Thumb1!");
594 bool isARM = !AFI->isThumbFunction();
596 unsigned Align = MF.getTarget()
599 ->getStackAlignment();
600 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
601 int NumBytes = (int)MFI->getStackSize();
602 unsigned FramePtr = RegInfo->getFrameRegister(MF);
604 // All calls are tail calls in GHC calling conv, and functions have no
605 // prologue/epilogue.
606 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
609 if (!AFI->hasStackFrame()) {
610 if (NumBytes - ArgRegsSaveSize != 0)
611 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
613 // Unwind MBBI to point to first LDR / VLDRD.
614 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
615 if (MBBI != MBB.begin()) {
618 } while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
619 if (!isCSRestore(MBBI, TII, CSRegs))
623 // Move SP to start of FP callee save spill area.
624 NumBytes -= (ArgRegsSaveSize +
625 AFI->getGPRCalleeSavedArea1Size() +
626 AFI->getGPRCalleeSavedArea2Size() +
627 AFI->getDPRCalleeSavedGapSize() +
628 AFI->getDPRCalleeSavedAreaSize());
630 // Reset SP based on frame pointer only if the stack frame extends beyond
631 // frame pointer stack slot or target is ELF and the function has FP.
632 if (AFI->shouldRestoreSPFromFP()) {
633 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
636 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
639 // It's not possible to restore SP from FP in a single instruction.
640 // For iOS, this looks like:
643 // This is bad, if an interrupt is taken after the mov, sp is in an
644 // inconsistent state.
645 // Use the first callee-saved register as a scratch register.
646 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
647 "No scratch register to restore SP from FP!");
648 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
650 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
657 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
658 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
660 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
664 } else if (NumBytes &&
665 !tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
666 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
668 // Increment past our save areas.
669 if (AFI->getDPRCalleeSavedAreaSize()) {
671 // Since vpop register list cannot have gaps, there may be multiple vpop
672 // instructions in the epilogue.
673 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
676 if (AFI->getDPRCalleeSavedGapSize()) {
677 assert(AFI->getDPRCalleeSavedGapSize() == 4 &&
678 "unexpected DPR alignment gap");
679 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize());
682 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
683 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
686 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri) {
687 // Tail call return: adjust the stack pointer and jump to callee.
688 MBBI = MBB.getLastNonDebugInstr();
689 MachineOperand &JumpTarget = MBBI->getOperand(0);
691 // Jump to label or value in register.
692 if (RetOpcode == ARM::TCRETURNdi) {
693 unsigned TCOpcode = STI.isThumb() ?
694 (STI.isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
696 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
697 if (JumpTarget.isGlobal())
698 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
699 JumpTarget.getTargetFlags());
701 assert(JumpTarget.isSymbol());
702 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
703 JumpTarget.getTargetFlags());
706 // Add the default predicate in Thumb mode.
707 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
708 } else if (RetOpcode == ARM::TCRETURNri) {
709 BuildMI(MBB, MBBI, dl,
710 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
711 addReg(JumpTarget.getReg(), RegState::Kill);
714 MachineInstr *NewMI = std::prev(MBBI);
715 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
716 NewMI->addOperand(MBBI->getOperand(i));
718 // Delete the pseudo instruction TCRETURN.
724 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
727 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
728 /// debug info. It's the same as what we use for resolving the code-gen
729 /// references for now. FIXME: This can go wrong when references are
730 /// SP-relative and simple call frames aren't used.
732 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
733 unsigned &FrameReg) const {
734 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
738 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
739 int FI, unsigned &FrameReg,
741 const MachineFrameInfo *MFI = MF.getFrameInfo();
742 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
743 MF.getSubtarget().getRegisterInfo());
744 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
745 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
746 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
747 bool isFixed = MFI->isFixedObjectIndex(FI);
752 // SP can move around if there are allocas. We may also lose track of SP
753 // when emergency spilling inside a non-reserved call frame setup.
754 bool hasMovingSP = !hasReservedCallFrame(MF);
756 // When dynamically realigning the stack, use the frame pointer for
757 // parameters, and the stack/base pointer for locals.
758 if (RegInfo->needsStackRealignment(MF)) {
759 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
761 FrameReg = RegInfo->getFrameRegister(MF);
763 } else if (hasMovingSP) {
764 assert(RegInfo->hasBasePointer(MF) &&
765 "VLAs and dynamic stack alignment, but missing base pointer!");
766 FrameReg = RegInfo->getBaseRegister();
771 // If there is a frame pointer, use it when we can.
772 if (hasFP(MF) && AFI->hasStackFrame()) {
773 // Use frame pointer to reference fixed objects. Use it for locals if
774 // there are VLAs (and thus the SP isn't reliable as a base).
775 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {
776 FrameReg = RegInfo->getFrameRegister(MF);
778 } else if (hasMovingSP) {
779 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
780 if (AFI->isThumb2Function()) {
781 // Try to use the frame pointer if we can, else use the base pointer
782 // since it's available. This is handy for the emergency spill slot, in
784 if (FPOffset >= -255 && FPOffset < 0) {
785 FrameReg = RegInfo->getFrameRegister(MF);
789 } else if (AFI->isThumb2Function()) {
790 // Use add <rd>, sp, #<imm8>
791 // ldr <rd>, [sp, #<imm8>]
792 // if at all possible to save space.
793 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
795 // In Thumb2 mode, the negative offset is very limited. Try to avoid
796 // out of range references. ldr <rt>,[<rn>, #-<imm8>]
797 if (FPOffset >= -255 && FPOffset < 0) {
798 FrameReg = RegInfo->getFrameRegister(MF);
801 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
802 // Otherwise, use SP or FP, whichever is closer to the stack slot.
803 FrameReg = RegInfo->getFrameRegister(MF);
807 // Use the base pointer if we have one.
808 if (RegInfo->hasBasePointer(MF))
809 FrameReg = RegInfo->getBaseRegister();
813 int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
816 return getFrameIndexReference(MF, FI, FrameReg);
819 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
820 MachineBasicBlock::iterator MI,
821 const std::vector<CalleeSavedInfo> &CSI,
822 unsigned StmOpc, unsigned StrOpc,
824 bool(*Func)(unsigned, bool),
825 unsigned NumAlignedDPRCS2Regs,
826 unsigned MIFlags) const {
827 MachineFunction &MF = *MBB.getParent();
828 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
831 if (MI != MBB.end()) DL = MI->getDebugLoc();
833 SmallVector<std::pair<unsigned,bool>, 4> Regs;
834 unsigned i = CSI.size();
836 unsigned LastReg = 0;
837 for (; i != 0; --i) {
838 unsigned Reg = CSI[i-1].getReg();
839 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
841 // D-registers in the aligned area DPRCS2 are NOT spilled here.
842 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
845 // Add the callee-saved register as live-in unless it's LR and
846 // @llvm.returnaddress is called. If LR is returned for
847 // @llvm.returnaddress then it's already added to the function and
848 // entry block live-in sets.
850 if (Reg == ARM::LR) {
851 if (MF.getFrameInfo()->isReturnAddressTaken() &&
852 MF.getRegInfo().isLiveIn(Reg))
859 // If NoGap is true, push consecutive registers and then leave the rest
860 // for other instructions. e.g.
861 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
862 if (NoGap && LastReg && LastReg != Reg-1)
865 Regs.push_back(std::make_pair(Reg, isKill));
870 if (Regs.size() > 1 || StrOpc== 0) {
871 MachineInstrBuilder MIB =
872 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
873 .addReg(ARM::SP).setMIFlags(MIFlags));
874 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
875 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
876 } else if (Regs.size() == 1) {
877 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
879 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
880 .addReg(ARM::SP).setMIFlags(MIFlags)
886 // Put any subsequent vpush instructions before this one: they will refer to
887 // higher register numbers so need to be pushed first in order to preserve
893 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
894 MachineBasicBlock::iterator MI,
895 const std::vector<CalleeSavedInfo> &CSI,
896 unsigned LdmOpc, unsigned LdrOpc,
897 bool isVarArg, bool NoGap,
898 bool(*Func)(unsigned, bool),
899 unsigned NumAlignedDPRCS2Regs) const {
900 MachineFunction &MF = *MBB.getParent();
901 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
902 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
903 DebugLoc DL = MI->getDebugLoc();
904 unsigned RetOpcode = MI->getOpcode();
905 bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||
906 RetOpcode == ARM::TCRETURNri);
908 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
910 SmallVector<unsigned, 4> Regs;
911 unsigned i = CSI.size();
913 unsigned LastReg = 0;
914 bool DeleteRet = false;
915 for (; i != 0; --i) {
916 unsigned Reg = CSI[i-1].getReg();
917 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
919 // The aligned reloads from area DPRCS2 are not inserted here.
920 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
923 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
926 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
927 // Fold the return instruction into the LDM.
931 // If NoGap is true, pop consecutive registers and then leave the rest
932 // for other instructions. e.g.
933 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
934 if (NoGap && LastReg && LastReg != Reg-1)
943 if (Regs.size() > 1 || LdrOpc == 0) {
944 MachineInstrBuilder MIB =
945 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
947 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
948 MIB.addReg(Regs[i], getDefRegState(true));
950 MIB.copyImplicitOps(&*MI);
951 MI->eraseFromParent();
954 } else if (Regs.size() == 1) {
955 // If we adjusted the reg to PC from LR above, switch it back here. We
956 // only do that for LDM.
957 if (Regs[0] == ARM::PC)
959 MachineInstrBuilder MIB =
960 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
961 .addReg(ARM::SP, RegState::Define)
963 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
964 // that refactoring is complete (eventually).
965 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
967 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
974 // Put any subsequent vpop instructions after this one: they will refer to
975 // higher register numbers so need to be popped afterwards.
980 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
981 /// starting from d8. Also insert stack realignment code and leave the stack
982 /// pointer pointing to the d8 spill slot.
983 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
984 MachineBasicBlock::iterator MI,
985 unsigned NumAlignedDPRCS2Regs,
986 const std::vector<CalleeSavedInfo> &CSI,
987 const TargetRegisterInfo *TRI) {
988 MachineFunction &MF = *MBB.getParent();
989 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
990 DebugLoc DL = MI->getDebugLoc();
991 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
992 MachineFrameInfo &MFI = *MF.getFrameInfo();
994 // Mark the D-register spill slots as properly aligned. Since MFI computes
995 // stack slot layout backwards, this can actually mean that the d-reg stack
996 // slot offsets can be wrong. The offset for d8 will always be correct.
997 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
998 unsigned DNum = CSI[i].getReg() - ARM::D8;
1001 int FI = CSI[i].getFrameIdx();
1002 // The even-numbered registers will be 16-byte aligned, the odd-numbered
1003 // registers will be 8-byte aligned.
1004 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
1006 // The stack slot for D8 needs to be maximally aligned because this is
1007 // actually the point where we align the stack pointer. MachineFrameInfo
1008 // computes all offsets relative to the incoming stack pointer which is a
1009 // bit weird when realigning the stack. Any extra padding for this
1010 // over-alignment is not realized because the code inserted below adjusts
1011 // the stack pointer by numregs * 8 before aligning the stack pointer.
1013 MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
1016 // Move the stack pointer to the d8 spill slot, and align it at the same
1017 // time. Leave the stack slot address in the scratch register r4.
1019 // sub r4, sp, #numregs * 8
1020 // bic r4, r4, #align - 1
1023 bool isThumb = AFI->isThumbFunction();
1024 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1025 AFI->setShouldRestoreSPFromFP(true);
1027 // sub r4, sp, #numregs * 8
1028 // The immediate is <= 64, so it doesn't need any special encoding.
1029 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
1030 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1032 .addImm(8 * NumAlignedDPRCS2Regs)));
1034 // bic r4, r4, #align-1
1035 Opc = isThumb ? ARM::t2BICri : ARM::BICri;
1036 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment();
1037 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1038 .addReg(ARM::R4, RegState::Kill)
1039 .addImm(MaxAlign - 1)));
1042 // The stack pointer must be adjusted before spilling anything, otherwise
1043 // the stack slots could be clobbered by an interrupt handler.
1044 // Leave r4 live, it is used below.
1045 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
1046 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1048 MIB = AddDefaultPred(MIB);
1052 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1053 // r4 holds the stack slot address.
1054 unsigned NextReg = ARM::D8;
1056 // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
1057 // The writeback is only needed when emitting two vst1.64 instructions.
1058 if (NumAlignedDPRCS2Regs >= 6) {
1059 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1060 &ARM::QQPRRegClass);
1061 MBB.addLiveIn(SupReg);
1062 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
1064 .addReg(ARM::R4, RegState::Kill).addImm(16)
1066 .addReg(SupReg, RegState::ImplicitKill));
1068 NumAlignedDPRCS2Regs -= 4;
1071 // We won't modify r4 beyond this point. It currently points to the next
1072 // register to be spilled.
1073 unsigned R4BaseReg = NextReg;
1075 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
1076 if (NumAlignedDPRCS2Regs >= 4) {
1077 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1078 &ARM::QQPRRegClass);
1079 MBB.addLiveIn(SupReg);
1080 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1081 .addReg(ARM::R4).addImm(16).addReg(NextReg)
1082 .addReg(SupReg, RegState::ImplicitKill));
1084 NumAlignedDPRCS2Regs -= 4;
1087 // 16-byte aligned vst1.64 with 2 d-regs.
1088 if (NumAlignedDPRCS2Regs >= 2) {
1089 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1091 MBB.addLiveIn(SupReg);
1092 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1093 .addReg(ARM::R4).addImm(16).addReg(SupReg));
1095 NumAlignedDPRCS2Regs -= 2;
1098 // Finally, use a vanilla vstr.64 for the odd last register.
1099 if (NumAlignedDPRCS2Regs) {
1100 MBB.addLiveIn(NextReg);
1101 // vstr.64 uses addrmode5 which has an offset scale of 4.
1102 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1104 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
1107 // The last spill instruction inserted should kill the scratch register r4.
1108 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1111 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
1112 /// iterator to the following instruction.
1113 static MachineBasicBlock::iterator
1114 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
1115 unsigned NumAlignedDPRCS2Regs) {
1116 // sub r4, sp, #numregs * 8
1117 // bic r4, r4, #align - 1
1120 assert(MI->mayStore() && "Expecting spill instruction");
1122 // These switches all fall through.
1123 switch(NumAlignedDPRCS2Regs) {
1126 assert(MI->mayStore() && "Expecting spill instruction");
1129 assert(MI->mayStore() && "Expecting spill instruction");
1133 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1139 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1140 /// starting from d8. These instructions are assumed to execute while the
1141 /// stack is still aligned, unlike the code inserted by emitPopInst.
1142 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
1143 MachineBasicBlock::iterator MI,
1144 unsigned NumAlignedDPRCS2Regs,
1145 const std::vector<CalleeSavedInfo> &CSI,
1146 const TargetRegisterInfo *TRI) {
1147 MachineFunction &MF = *MBB.getParent();
1148 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1149 DebugLoc DL = MI->getDebugLoc();
1150 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1152 // Find the frame index assigned to d8.
1154 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
1155 if (CSI[i].getReg() == ARM::D8) {
1156 D8SpillFI = CSI[i].getFrameIdx();
1160 // Materialize the address of the d8 spill slot into the scratch register r4.
1161 // This can be fairly complicated if the stack frame is large, so just use
1162 // the normal frame index elimination mechanism to do it. This code runs as
1163 // the initial part of the epilog where the stack and base pointers haven't
1164 // been changed yet.
1165 bool isThumb = AFI->isThumbFunction();
1166 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1168 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
1169 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1170 .addFrameIndex(D8SpillFI).addImm(0)));
1172 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1173 unsigned NextReg = ARM::D8;
1175 // 16-byte aligned vld1.64 with 4 d-regs and writeback.
1176 if (NumAlignedDPRCS2Regs >= 6) {
1177 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1178 &ARM::QQPRRegClass);
1179 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1180 .addReg(ARM::R4, RegState::Define)
1181 .addReg(ARM::R4, RegState::Kill).addImm(16)
1182 .addReg(SupReg, RegState::ImplicitDefine));
1184 NumAlignedDPRCS2Regs -= 4;
1187 // We won't modify r4 beyond this point. It currently points to the next
1188 // register to be spilled.
1189 unsigned R4BaseReg = NextReg;
1191 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
1192 if (NumAlignedDPRCS2Regs >= 4) {
1193 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1194 &ARM::QQPRRegClass);
1195 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1196 .addReg(ARM::R4).addImm(16)
1197 .addReg(SupReg, RegState::ImplicitDefine));
1199 NumAlignedDPRCS2Regs -= 4;
1202 // 16-byte aligned vld1.64 with 2 d-regs.
1203 if (NumAlignedDPRCS2Regs >= 2) {
1204 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1206 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1207 .addReg(ARM::R4).addImm(16));
1209 NumAlignedDPRCS2Regs -= 2;
1212 // Finally, use a vanilla vldr.64 for the remaining odd register.
1213 if (NumAlignedDPRCS2Regs)
1214 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1215 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
1217 // Last store kills r4.
1218 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1221 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1222 MachineBasicBlock::iterator MI,
1223 const std::vector<CalleeSavedInfo> &CSI,
1224 const TargetRegisterInfo *TRI) const {
1228 MachineFunction &MF = *MBB.getParent();
1229 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1231 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
1232 unsigned PushOneOpc = AFI->isThumbFunction() ?
1233 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
1234 unsigned FltOpc = ARM::VSTMDDB_UPD;
1235 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1236 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
1237 MachineInstr::FrameSetup);
1238 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
1239 MachineInstr::FrameSetup);
1240 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1241 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1243 // The code above does not insert spill code for the aligned DPRCS2 registers.
1244 // The stack realignment code will be inserted between the push instructions
1245 // and these spills.
1246 if (NumAlignedDPRCS2Regs)
1247 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1252 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1253 MachineBasicBlock::iterator MI,
1254 const std::vector<CalleeSavedInfo> &CSI,
1255 const TargetRegisterInfo *TRI) const {
1259 MachineFunction &MF = *MBB.getParent();
1260 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1261 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
1262 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1264 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
1265 // registers. Do that here instead.
1266 if (NumAlignedDPRCS2Regs)
1267 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1269 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1270 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1271 unsigned FltOpc = ARM::VLDMDIA_UPD;
1272 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1273 NumAlignedDPRCS2Regs);
1274 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1275 &isARMArea2Register, 0);
1276 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1277 &isARMArea1Register, 0);
1282 // FIXME: Make generic?
1283 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
1284 const ARMBaseInstrInfo &TII) {
1285 unsigned FnSize = 0;
1286 for (auto &MBB : MF) {
1287 for (auto &MI : MBB)
1288 FnSize += TII.GetInstSizeInBytes(&MI);
1293 /// estimateRSStackSizeLimit - Look at each instruction that references stack
1294 /// frames and return the stack size limit beyond which some of these
1295 /// instructions will require a scratch register during their expansion later.
1296 // FIXME: Move to TII?
1297 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
1298 const TargetFrameLowering *TFI) {
1299 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1300 unsigned Limit = (1 << 12) - 1;
1301 for (auto &MBB : MF) {
1302 for (auto &MI : MBB) {
1303 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1304 if (!MI.getOperand(i).isFI())
1307 // When using ADDri to get the address of a stack object, 255 is the
1308 // largest offset guaranteed to fit in the immediate offset.
1309 if (MI.getOpcode() == ARM::ADDri) {
1310 Limit = std::min(Limit, (1U << 8) - 1);
1314 // Otherwise check the addressing mode.
1315 switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
1316 case ARMII::AddrMode3:
1317 case ARMII::AddrModeT2_i8:
1318 Limit = std::min(Limit, (1U << 8) - 1);
1320 case ARMII::AddrMode5:
1321 case ARMII::AddrModeT2_i8s4:
1322 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
1324 case ARMII::AddrModeT2_i12:
1325 // i12 supports only positive offset so these will be converted to
1326 // i8 opcodes. See llvm::rewriteT2FrameIndex.
1327 if (TFI->hasFP(MF) && AFI->hasStackFrame())
1328 Limit = std::min(Limit, (1U << 8) - 1);
1330 case ARMII::AddrMode4:
1331 case ARMII::AddrMode6:
1332 // Addressing modes 4 & 6 (load/store) instructions can't encode an
1333 // immediate offset for stack references.
1338 break; // At most one FI per instruction
1346 // In functions that realign the stack, it can be an advantage to spill the
1347 // callee-saved vector registers after realigning the stack. The vst1 and vld1
1348 // instructions take alignment hints that can improve performance.
1350 static void checkNumAlignedDPRCS2Regs(MachineFunction &MF) {
1351 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
1352 if (!SpillAlignedNEONRegs)
1355 // Naked functions don't spill callee-saved registers.
1356 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1360 // We are planning to use NEON instructions vst1 / vld1.
1361 if (!MF.getTarget().getSubtarget<ARMSubtarget>().hasNEON())
1364 // Don't bother if the default stack alignment is sufficiently high.
1367 ->getFrameLowering()
1368 ->getStackAlignment() >= 8)
1371 // Aligned spills require stack realignment.
1372 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1373 MF.getSubtarget().getRegisterInfo());
1374 if (!RegInfo->canRealignStack(MF))
1377 // We always spill contiguous d-registers starting from d8. Count how many
1378 // needs spilling. The register allocator will almost always use the
1379 // callee-saved registers in order, but it can happen that there are holes in
1380 // the range. Registers above the hole will be spilled to the standard DPRCS
1382 MachineRegisterInfo &MRI = MF.getRegInfo();
1383 unsigned NumSpills = 0;
1384 for (; NumSpills < 8; ++NumSpills)
1385 if (!MRI.isPhysRegUsed(ARM::D8 + NumSpills))
1388 // Don't do this for just one d-register. It's not worth it.
1392 // Spill the first NumSpills D-registers after realigning the stack.
1393 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
1395 // A scratch register is required for the vst1 / vld1 instructions.
1396 MF.getRegInfo().setPhysRegUsed(ARM::R4);
1400 ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1401 RegScavenger *RS) const {
1402 // This tells PEI to spill the FP as if it is any other callee-save register
1403 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1404 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1405 // to combine multiple loads / stores.
1406 bool CanEliminateFrame = true;
1407 bool CS1Spilled = false;
1408 bool LRSpilled = false;
1409 unsigned NumGPRSpills = 0;
1410 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1411 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1412 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1413 MF.getSubtarget().getRegisterInfo());
1414 const ARMBaseInstrInfo &TII =
1415 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1416 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1417 MachineFrameInfo *MFI = MF.getFrameInfo();
1418 MachineRegisterInfo &MRI = MF.getRegInfo();
1419 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1421 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1422 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1423 // since it's not always possible to restore sp from fp in a single
1425 // FIXME: It will be better just to find spare register here.
1426 if (AFI->isThumb2Function() &&
1427 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
1428 MRI.setPhysRegUsed(ARM::R4);
1430 if (AFI->isThumb1OnlyFunction()) {
1431 // Spill LR if Thumb1 function uses variable length argument lists.
1432 if (AFI->getArgRegsSaveSize() > 0)
1433 MRI.setPhysRegUsed(ARM::LR);
1435 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know
1436 // for sure what the stack size will be, but for this, an estimate is good
1437 // enough. If there anything changes it, it'll be a spill, which implies
1438 // we've used all the registers and so R4 is already used, so not marking
1439 // it here will be OK.
1440 // FIXME: It will be better just to find spare register here.
1441 unsigned StackSize = MFI->estimateStackSize(MF);
1442 if (MFI->hasVarSizedObjects() || StackSize > 508)
1443 MRI.setPhysRegUsed(ARM::R4);
1446 // See if we can spill vector registers to aligned stack.
1447 checkNumAlignedDPRCS2Regs(MF);
1449 // Spill the BasePtr if it's used.
1450 if (RegInfo->hasBasePointer(MF))
1451 MRI.setPhysRegUsed(RegInfo->getBaseRegister());
1453 // Don't spill FP if the frame can be eliminated. This is determined
1454 // by scanning the callee-save registers to see if any is used.
1455 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1456 for (unsigned i = 0; CSRegs[i]; ++i) {
1457 unsigned Reg = CSRegs[i];
1458 bool Spilled = false;
1459 if (MRI.isPhysRegUsed(Reg)) {
1461 CanEliminateFrame = false;
1464 if (!ARM::GPRRegClass.contains(Reg))
1470 if (!STI.isTargetDarwin()) {
1477 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1482 case ARM::R0: case ARM::R1:
1483 case ARM::R2: case ARM::R3:
1484 case ARM::R4: case ARM::R5:
1485 case ARM::R6: case ARM::R7:
1492 if (!STI.isTargetDarwin()) {
1493 UnspilledCS1GPRs.push_back(Reg);
1498 case ARM::R0: case ARM::R1:
1499 case ARM::R2: case ARM::R3:
1500 case ARM::R4: case ARM::R5:
1501 case ARM::R6: case ARM::R7:
1503 UnspilledCS1GPRs.push_back(Reg);
1506 UnspilledCS2GPRs.push_back(Reg);
1512 bool ForceLRSpill = false;
1513 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
1514 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
1515 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1516 // use of BL to implement far jump. If it turns out that it's not needed
1517 // then the branch fix up path will undo it.
1518 if (FnSize >= (1 << 11)) {
1519 CanEliminateFrame = false;
1520 ForceLRSpill = true;
1524 // If any of the stack slot references may be out of range of an immediate
1525 // offset, make sure a register (or a spill slot) is available for the
1526 // register scavenger. Note that if we're indexing off the frame pointer, the
1527 // effective stack size is 4 bytes larger since the FP points to the stack
1528 // slot of the previous FP. Also, if we have variable sized objects in the
1529 // function, stack slot references will often be negative, and some of
1530 // our instructions are positive-offset only, so conservatively consider
1531 // that case to want a spill slot (or register) as well. Similarly, if
1532 // the function adjusts the stack pointer during execution and the
1533 // adjustments aren't already part of our stack size estimate, our offset
1534 // calculations may be off, so be conservative.
1535 // FIXME: We could add logic to be more precise about negative offsets
1536 // and which instructions will need a scratch register for them. Is it
1537 // worth the effort and added fragility?
1540 (MFI->estimateStackSize(MF) +
1541 ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
1542 estimateRSStackSizeLimit(MF, this)))
1543 || MFI->hasVarSizedObjects()
1544 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
1546 bool ExtraCSSpill = false;
1547 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
1548 AFI->setHasStackFrame(true);
1550 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1551 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1552 if (!LRSpilled && CS1Spilled) {
1553 MRI.setPhysRegUsed(ARM::LR);
1555 SmallVectorImpl<unsigned>::iterator LRPos;
1556 LRPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
1558 if (LRPos != UnspilledCS1GPRs.end())
1559 UnspilledCS1GPRs.erase(LRPos);
1561 ForceLRSpill = false;
1562 ExtraCSSpill = true;
1566 MRI.setPhysRegUsed(FramePtr);
1567 auto FPPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
1569 if (FPPos != UnspilledCS1GPRs.end())
1570 UnspilledCS1GPRs.erase(FPPos);
1574 // If stack and double are 8-byte aligned and we are spilling an odd number
1575 // of GPRs, spill one extra callee save GPR so we won't have to pad between
1576 // the integer and double callee save areas.
1577 unsigned TargetAlign = getStackAlignment();
1578 if (TargetAlign >= 8 && (NumGPRSpills & 1)) {
1579 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1580 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1581 unsigned Reg = UnspilledCS1GPRs[i];
1582 // Don't spill high register if the function is thumb1
1583 if (!AFI->isThumb1OnlyFunction() ||
1584 isARMLowRegister(Reg) || Reg == ARM::LR) {
1585 MRI.setPhysRegUsed(Reg);
1586 if (!MRI.isReserved(Reg))
1587 ExtraCSSpill = true;
1591 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
1592 unsigned Reg = UnspilledCS2GPRs.front();
1593 MRI.setPhysRegUsed(Reg);
1594 if (!MRI.isReserved(Reg))
1595 ExtraCSSpill = true;
1599 // Estimate if we might need to scavenge a register at some point in order
1600 // to materialize a stack offset. If so, either spill one additional
1601 // callee-saved register or reserve a special spill slot to facilitate
1602 // register scavenging. Thumb1 needs a spill slot for stack pointer
1603 // adjustments also, even when the frame itself is small.
1604 if (BigStack && !ExtraCSSpill) {
1605 // If any non-reserved CS register isn't spilled, just spill one or two
1606 // extra. That should take care of it!
1607 unsigned NumExtras = TargetAlign / 4;
1608 SmallVector<unsigned, 2> Extras;
1609 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1610 unsigned Reg = UnspilledCS1GPRs.back();
1611 UnspilledCS1GPRs.pop_back();
1612 if (!MRI.isReserved(Reg) &&
1613 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1615 Extras.push_back(Reg);
1619 // For non-Thumb1 functions, also check for hi-reg CS registers
1620 if (!AFI->isThumb1OnlyFunction()) {
1621 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1622 unsigned Reg = UnspilledCS2GPRs.back();
1623 UnspilledCS2GPRs.pop_back();
1624 if (!MRI.isReserved(Reg)) {
1625 Extras.push_back(Reg);
1630 if (Extras.size() && NumExtras == 0) {
1631 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1632 MRI.setPhysRegUsed(Extras[i]);
1634 } else if (!AFI->isThumb1OnlyFunction()) {
1635 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1636 // closest to SP or frame pointer.
1637 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1638 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1646 MRI.setPhysRegUsed(ARM::LR);
1647 AFI->setLRIsSpilledForFarJump(true);
1652 void ARMFrameLowering::
1653 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1654 MachineBasicBlock::iterator I) const {
1655 const ARMBaseInstrInfo &TII =
1656 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1657 if (!hasReservedCallFrame(MF)) {
1658 // If we have alloca, convert as follows:
1659 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1660 // ADJCALLSTACKUP -> add, sp, sp, amount
1661 MachineInstr *Old = I;
1662 DebugLoc dl = Old->getDebugLoc();
1663 unsigned Amount = Old->getOperand(0).getImm();
1665 // We need to keep the stack aligned properly. To do this, we round the
1666 // amount of space needed for the outgoing arguments up to the next
1667 // alignment boundary.
1668 unsigned Align = getStackAlignment();
1669 Amount = (Amount+Align-1)/Align*Align;
1671 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1672 assert(!AFI->isThumb1OnlyFunction() &&
1673 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1674 bool isARM = !AFI->isThumbFunction();
1676 // Replace the pseudo instruction with a new instruction...
1677 unsigned Opc = Old->getOpcode();
1678 int PIdx = Old->findFirstPredOperandIdx();
1679 ARMCC::CondCodes Pred = (PIdx == -1)
1680 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1681 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1682 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1683 unsigned PredReg = Old->getOperand(2).getReg();
1684 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
1687 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1688 unsigned PredReg = Old->getOperand(3).getReg();
1689 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1690 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
1698 /// Get the minimum constant for ARM that is greater than or equal to the
1699 /// argument. In ARM, constants can have any value that can be produced by
1700 /// rotating an 8-bit value to the right by an even number of bits within a
1702 static uint32_t alignToARMConstant(uint32_t Value) {
1703 unsigned Shifted = 0;
1708 while (!(Value & 0xC0000000)) {
1713 bool Carry = (Value & 0x00FFFFFF);
1714 Value = ((Value & 0xFF000000) >> 24) + Carry;
1716 if (Value & 0x0000100)
1717 Value = Value & 0x000001FC;
1720 Value = Value >> (Shifted - 24);
1722 Value = Value << (24 - Shifted);
1727 // The stack limit in the TCB is set to this many bytes above the actual
1729 static const uint64_t kSplitStackAvailable = 256;
1731 // Adjust the function prologue to enable split stacks. This currently only
1732 // supports android and linux.
1734 // The ABI of the segmented stack prologue is a little arbitrarily chosen, but
1735 // must be well defined in order to allow for consistent implementations of the
1736 // __morestack helper function. The ABI is also not a normal ABI in that it
1737 // doesn't follow the normal calling conventions because this allows the
1738 // prologue of each function to be optimized further.
1740 // Currently, the ABI looks like (when calling __morestack)
1742 // * r4 holds the minimum stack size requested for this function call
1743 // * r5 holds the stack size of the arguments to the function
1744 // * the beginning of the function is 3 instructions after the call to
1747 // Implementations of __morestack should use r4 to allocate a new stack, r5 to
1748 // place the arguments on to the new stack, and the 3-instruction knowledge to
1749 // jump directly to the body of the function when working on the new stack.
1751 // An old (and possibly no longer compatible) implementation of __morestack for
1752 // ARM can be found at [1].
1754 // [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S
1755 void ARMFrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1758 const ARMSubtarget *ST = &MF.getTarget().getSubtarget<ARMSubtarget>();
1759 bool Thumb = ST->isThumb();
1761 // Sadly, this currently doesn't support varargs, platforms other than
1762 // android/linux. Note that thumb1/thumb2 are support for android/linux.
1763 if (MF.getFunction()->isVarArg())
1764 report_fatal_error("Segmented stacks do not support vararg functions.");
1765 if (!ST->isTargetAndroid() && !ST->isTargetLinux())
1766 report_fatal_error("Segmented stacks not supported on this platform.");
1768 MachineBasicBlock &prologueMBB = MF.front();
1769 MachineFrameInfo *MFI = MF.getFrameInfo();
1770 MachineModuleInfo &MMI = MF.getMMI();
1771 MCContext &Context = MMI.getContext();
1772 const MCRegisterInfo *MRI = Context.getRegisterInfo();
1773 const ARMBaseInstrInfo &TII =
1774 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1775 ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();
1778 uint64_t StackSize = MFI->getStackSize();
1780 // Do not generate a prologue for functions with a stack of size zero
1784 // Use R4 and R5 as scratch registers.
1785 // We save R4 and R5 before use and restore them before leaving the function.
1786 unsigned ScratchReg0 = ARM::R4;
1787 unsigned ScratchReg1 = ARM::R5;
1788 uint64_t AlignedStackSize;
1790 MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();
1791 MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();
1792 MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();
1793 MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock();
1794 MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock();
1796 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1797 e = prologueMBB.livein_end();
1799 AllocMBB->addLiveIn(*i);
1800 GetMBB->addLiveIn(*i);
1801 McrMBB->addLiveIn(*i);
1802 PrevStackMBB->addLiveIn(*i);
1803 PostStackMBB->addLiveIn(*i);
1806 MF.push_front(PostStackMBB);
1807 MF.push_front(AllocMBB);
1808 MF.push_front(GetMBB);
1809 MF.push_front(McrMBB);
1810 MF.push_front(PrevStackMBB);
1812 // The required stack size that is aligned to ARM constant criterion.
1813 AlignedStackSize = alignToARMConstant(StackSize);
1815 // When the frame size is less than 256 we just compare the stack
1816 // boundary directly to the value of the stack pointer, per gcc.
1817 bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable;
1819 // We will use two of the callee save registers as scratch registers so we
1820 // need to save those registers onto the stack.
1821 // We will use SR0 to hold stack limit and SR1 to hold the stack size
1822 // requested and arguments for __morestack().
1823 // SR0: Scratch Register #0
1824 // SR1: Scratch Register #1
1827 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)))
1828 .addReg(ScratchReg0).addReg(ScratchReg1);
1830 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
1831 .addReg(ARM::SP, RegState::Define).addReg(ARM::SP))
1832 .addReg(ScratchReg0).addReg(ScratchReg1);
1835 // Emit the relevant DWARF information about the change in stack pointer as
1836 // well as where to find both r4 and r5 (the callee-save registers)
1838 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8));
1839 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1840 .addCFIIndex(CFIIndex);
1841 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1842 nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
1843 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1844 .addCFIIndex(CFIIndex);
1845 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1846 nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
1847 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1848 .addCFIIndex(CFIIndex);
1852 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
1854 } else if (CompareStackPointer) {
1855 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
1856 .addReg(ARM::SP)).addReg(0);
1859 // sub SR1, sp, #StackSize
1860 if (!CompareStackPointer && Thumb) {
1862 AddDefaultCC(BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1))
1863 .addReg(ScratchReg1).addImm(AlignedStackSize));
1864 } else if (!CompareStackPointer) {
1865 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
1866 .addReg(ARM::SP).addImm(AlignedStackSize)).addReg(0);
1869 if (Thumb && ST->isThumb1Only()) {
1870 unsigned PCLabelId = ARMFI->createPICLabelUId();
1871 ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create(
1872 MF.getFunction()->getContext(), "__STACK_LIMIT", PCLabelId, 0);
1873 MachineConstantPool *MCP = MF.getConstantPool();
1874 unsigned CPI = MCP->getConstantPoolIndex(NewCPV, MF.getAlignment());
1876 // ldr SR0, [pc, offset(STACK_LIMIT)]
1877 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
1878 .addConstantPoolIndex(CPI));
1881 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
1882 .addReg(ScratchReg0).addImm(0));
1884 // Get TLS base address from the coprocessor
1885 // mrc p15, #0, SR0, c13, c0, #3
1886 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0)
1893 // Use the last tls slot on android and a private field of the TCP on linux.
1894 assert(ST->isTargetAndroid() || ST->isTargetLinux());
1895 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;
1897 // Get the stack limit from the right offset
1898 // ldr SR0, [sr0, #4 * TlsOffset]
1899 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)
1900 .addReg(ScratchReg0).addImm(4 * TlsOffset));
1903 // Compare stack limit with stack size requested.
1905 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr;
1906 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(Opcode))
1907 .addReg(ScratchReg0)
1908 .addReg(ScratchReg1));
1910 // This jump is taken if StackLimit < SP - stack required.
1911 Opcode = Thumb ? ARM::tBcc : ARM::Bcc;
1912 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
1917 // Calling __morestack(StackSize, Size of stack arguments).
1918 // __morestack knows that the stack size requested is in SR0(r4)
1919 // and amount size of stack arguments is in SR1(r5).
1921 // Pass first argument for the __morestack by Scratch Register #0.
1922 // The amount size of stack required
1924 AddDefaultPred(AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8),
1925 ScratchReg0)).addImm(AlignedStackSize));
1927 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
1928 .addImm(AlignedStackSize)).addReg(0);
1930 // Pass second argument for the __morestack by Scratch Register #1.
1931 // The amount size of stack consumed to save function arguments.
1934 AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1))
1935 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())));
1937 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
1938 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())))
1942 // push {lr} - Save return address of this function.
1944 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)))
1947 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
1948 .addReg(ARM::SP, RegState::Define)
1953 // Emit the DWARF info about the change in stack as well as where to find the
1954 // previous link register
1956 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12));
1957 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1958 .addCFIIndex(CFIIndex);
1959 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1960 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
1961 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1962 .addCFIIndex(CFIIndex);
1964 // Call __morestack().
1966 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tBL)))
1967 .addExternalSymbol("__morestack");
1969 BuildMI(AllocMBB, DL, TII.get(ARM::BL))
1970 .addExternalSymbol("__morestack");
1973 // pop {lr} - Restore return address of this original function.
1975 if (ST->isThumb1Only()) {
1976 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)))
1977 .addReg(ScratchReg0);
1978 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
1979 .addReg(ScratchReg0));
1981 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
1982 .addReg(ARM::LR, RegState::Define)
1983 .addReg(ARM::SP, RegState::Define)
1988 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
1989 .addReg(ARM::SP, RegState::Define)
1994 // Restore SR0 and SR1 in case of __morestack() was called.
1995 // __morestack() will skip PostStackMBB block so we need to restore
1996 // scratch registers from here.
1999 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)))
2000 .addReg(ScratchReg0)
2001 .addReg(ScratchReg1);
2003 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2004 .addReg(ARM::SP, RegState::Define)
2006 .addReg(ScratchReg0)
2007 .addReg(ScratchReg1);
2010 // Update the CFA offset now that we've popped
2011 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2012 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2013 .addCFIIndex(CFIIndex);
2015 // bx lr - Return from this function.
2016 Opcode = Thumb ? ARM::tBX_RET : ARM::BX_RET;
2017 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(Opcode)));
2019 // Restore SR0 and SR1 in case of __morestack() was not called.
2022 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)))
2023 .addReg(ScratchReg0)
2024 .addReg(ScratchReg1);
2026 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
2027 .addReg(ARM::SP, RegState::Define)
2029 .addReg(ScratchReg0)
2030 .addReg(ScratchReg1);
2033 // Update the CFA offset now that we've popped
2034 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2035 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2036 .addCFIIndex(CFIIndex);
2038 // Tell debuggers that r4 and r5 are now the same as they were in the
2039 // previous function, that they're the "Same Value".
2040 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue(
2041 nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
2042 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2043 .addCFIIndex(CFIIndex);
2044 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue(
2045 nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
2046 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2047 .addCFIIndex(CFIIndex);
2049 // Organizing MBB lists
2050 PostStackMBB->addSuccessor(&prologueMBB);
2052 AllocMBB->addSuccessor(PostStackMBB);
2054 GetMBB->addSuccessor(PostStackMBB);
2055 GetMBB->addSuccessor(AllocMBB);
2057 McrMBB->addSuccessor(GetMBB);
2059 PrevStackMBB->addSuccessor(McrMBB);