1 //=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetOptions.h"
28 /// hasFP - Return true if the specified function should have a dedicated frame
29 /// pointer register. This is true if the function has variable sized allocas
30 /// or if frame pointer elimination is disabled.
31 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
32 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
34 // Mac OS X requires FP not to be clobbered for backtracing purpose.
35 if (STI.isTargetDarwin())
38 const MachineFrameInfo *MFI = MF.getFrameInfo();
39 // Always eliminate non-leaf frame pointers.
40 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
41 RegInfo->needsStackRealignment(MF) ||
42 MFI->hasVarSizedObjects() ||
43 MFI->isFrameAddressTaken());
46 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
47 /// not required, we reserve argument space for call sites in the function
48 /// immediately on entry to the current function. This eliminates the need for
49 /// add/sub sp brackets around call sites. Returns true if the call frame is
50 /// included as part of the stack frame.
51 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
52 const MachineFrameInfo *FFI = MF.getFrameInfo();
53 unsigned CFSize = FFI->getMaxCallFrameSize();
54 // It's not always a good idea to include the call frame as part of the
55 // stack frame. ARM (especially Thumb) has small immediate offset to
56 // address the stack frame. So a large call frame can cause poor codegen
57 // and may even makes it impossible to scavenge a register.
58 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
61 return !MF.getFrameInfo()->hasVarSizedObjects();
64 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
65 /// call frame pseudos can be simplified. Unlike most targets, having a FP
66 /// is not sufficient here since we still may reference some objects via SP
67 /// even when FP is available in Thumb2 mode.
69 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
70 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
73 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
74 for (unsigned i = 0; CSRegs[i]; ++i)
80 static bool isCSRestore(MachineInstr *MI,
81 const ARMBaseInstrInfo &TII,
82 const unsigned *CSRegs) {
83 // Integer spill area is handled with "pop".
84 if (MI->getOpcode() == ARM::LDMIA_RET ||
85 MI->getOpcode() == ARM::t2LDMIA_RET ||
86 MI->getOpcode() == ARM::LDMIA_UPD ||
87 MI->getOpcode() == ARM::t2LDMIA_UPD ||
88 MI->getOpcode() == ARM::VLDMDIA_UPD) {
89 // The first two operands are predicates. The last two are
90 // imp-def and imp-use of SP. Check everything in between.
91 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
92 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
96 if ((MI->getOpcode() == ARM::LDR_POST ||
97 MI->getOpcode() == ARM::t2LDR_POST) &&
98 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
99 MI->getOperand(1).getReg() == ARM::SP)
106 emitSPUpdate(bool isARM,
107 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
108 DebugLoc dl, const ARMBaseInstrInfo &TII,
109 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
111 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
112 ARMCC::AL, 0, TII, MIFlags);
114 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
115 ARMCC::AL, 0, TII, MIFlags);
118 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
119 MachineBasicBlock &MBB = MF.front();
120 MachineBasicBlock::iterator MBBI = MBB.begin();
121 MachineFrameInfo *MFI = MF.getFrameInfo();
122 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
123 const ARMBaseRegisterInfo *RegInfo =
124 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
125 const ARMBaseInstrInfo &TII =
126 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
127 assert(!AFI->isThumb1OnlyFunction() &&
128 "This emitPrologue does not support Thumb1!");
129 bool isARM = !AFI->isThumbFunction();
130 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
131 unsigned NumBytes = MFI->getStackSize();
132 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
133 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
134 unsigned FramePtr = RegInfo->getFrameRegister(MF);
136 // Determine the sizes of each callee-save spill areas and record which frame
137 // belongs to which callee-save spill areas.
138 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
139 int FramePtrSpillFI = 0;
141 // Allocate the vararg register save area. This is not counted in NumBytes.
143 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize,
144 MachineInstr::FrameSetup);
146 if (!AFI->hasStackFrame()) {
148 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
149 MachineInstr::FrameSetup);
153 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
154 unsigned Reg = CSI[i].getReg();
155 int FI = CSI[i].getFrameIdx();
163 FramePtrSpillFI = FI;
164 AFI->addGPRCalleeSavedArea1Frame(FI);
172 FramePtrSpillFI = FI;
173 if (STI.isTargetDarwin()) {
174 AFI->addGPRCalleeSavedArea2Frame(FI);
177 AFI->addGPRCalleeSavedArea1Frame(FI);
182 AFI->addDPRCalleeSavedAreaFrame(FI);
188 if (GPRCS1Size > 0) MBBI++;
190 // Set FP to point to the stack slot that contains the previous FP.
191 // For Darwin, FP is R7, which has now been stored in spill area 1.
192 // Otherwise, if this is not Darwin, all the callee-saved registers go
193 // into spill area 1, including the FP in R11. In either case, it is
194 // now safe to emit this assignment.
195 bool HasFP = hasFP(MF);
197 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
198 MachineInstrBuilder MIB =
199 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
200 .addFrameIndex(FramePtrSpillFI).addImm(0)
201 .setMIFlag(MachineInstr::FrameSetup);
202 AddDefaultCC(AddDefaultPred(MIB));
206 if (GPRCS2Size > 0) MBBI++;
208 // Determine starting offsets of spill areas.
209 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
210 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
211 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
213 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
215 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
216 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
217 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
222 // Since vpush register list cannot have gaps, there may be multiple vpush
223 // instructions in the prologue.
224 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD)
228 NumBytes = DPRCSOffset;
230 // Adjust SP after all the callee-save spills.
231 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
232 MachineInstr::FrameSetup);
234 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
235 // Note it's not safe to do this in Thumb2 mode because it would have
236 // taken two instructions:
239 // If an interrupt is taken between the two instructions, then sp is in
240 // an inconsistent state (pointing to the middle of callee-saved area).
241 // The interrupt handler can end up clobbering the registers.
242 AFI->setShouldRestoreSPFromFP(true);
245 if (STI.isTargetELF() && hasFP(MF))
246 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
247 AFI->getFramePtrSpillOffset());
249 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
250 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
251 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
253 // If we need dynamic stack realignment, do it here. Be paranoid and make
254 // sure if we also have VLAs, we have a base pointer for frame access.
255 if (RegInfo->needsStackRealignment(MF)) {
256 unsigned MaxAlign = MFI->getMaxAlignment();
257 assert (!AFI->isThumb1OnlyFunction());
258 if (!AFI->isThumbFunction()) {
259 // Emit bic sp, sp, MaxAlign
260 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
261 TII.get(ARM::BICri), ARM::SP)
262 .addReg(ARM::SP, RegState::Kill)
263 .addImm(MaxAlign-1)));
265 // We cannot use sp as source/dest register here, thus we're emitting the
266 // following sequence:
268 // bic r4, r4, MaxAlign
270 // FIXME: It will be better just to find spare register here.
271 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
272 .addReg(ARM::SP, RegState::Kill);
273 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
274 TII.get(ARM::t2BICri), ARM::R4)
275 .addReg(ARM::R4, RegState::Kill)
276 .addImm(MaxAlign-1)));
277 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
278 .addReg(ARM::R4, RegState::Kill);
281 AFI->setShouldRestoreSPFromFP(true);
284 // If we need a base pointer, set it up here. It's whatever the value
285 // of the stack pointer is at this point. Any variable size objects
286 // will be allocated after this, so we can still use the base pointer
287 // to reference locals.
288 // FIXME: Clarify FrameSetup flags here.
289 if (RegInfo->hasBasePointer(MF)) {
291 BuildMI(MBB, MBBI, dl,
292 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
294 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
296 BuildMI(MBB, MBBI, dl,
297 TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister())
301 // If the frame has variable sized objects then the epilogue must restore
302 // the sp from fp. We can assume there's an FP here since hasFP already
303 // checks for hasVarSizedObjects.
304 if (MFI->hasVarSizedObjects())
305 AFI->setShouldRestoreSPFromFP(true);
308 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
309 MachineBasicBlock &MBB) const {
310 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
311 assert(MBBI->getDesc().isReturn() &&
312 "Can only insert epilog into returning blocks");
313 unsigned RetOpcode = MBBI->getOpcode();
314 DebugLoc dl = MBBI->getDebugLoc();
315 MachineFrameInfo *MFI = MF.getFrameInfo();
316 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
317 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
318 const ARMBaseInstrInfo &TII =
319 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
320 assert(!AFI->isThumb1OnlyFunction() &&
321 "This emitEpilogue does not support Thumb1!");
322 bool isARM = !AFI->isThumbFunction();
324 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
325 int NumBytes = (int)MFI->getStackSize();
326 unsigned FramePtr = RegInfo->getFrameRegister(MF);
328 if (!AFI->hasStackFrame()) {
330 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
332 // Unwind MBBI to point to first LDR / VLDRD.
333 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
334 if (MBBI != MBB.begin()) {
337 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
338 if (!isCSRestore(MBBI, TII, CSRegs))
342 // Move SP to start of FP callee save spill area.
343 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
344 AFI->getGPRCalleeSavedArea2Size() +
345 AFI->getDPRCalleeSavedAreaSize());
347 // Reset SP based on frame pointer only if the stack frame extends beyond
348 // frame pointer stack slot or target is ELF and the function has FP.
349 if (AFI->shouldRestoreSPFromFP()) {
350 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
353 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
356 // It's not possible to restore SP from FP in a single instruction.
357 // For Darwin, this looks like:
360 // This is bad, if an interrupt is taken after the mov, sp is in an
361 // inconsistent state.
362 // Use the first callee-saved register as a scratch register.
363 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
364 "No scratch register to restore SP from FP!");
365 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
367 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
373 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
374 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
376 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
380 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
382 // Increment past our save areas.
383 if (AFI->getDPRCalleeSavedAreaSize()) {
385 // Since vpop register list cannot have gaps, there may be multiple vpop
386 // instructions in the epilogue.
387 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
390 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
391 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
394 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
395 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
396 // Tail call return: adjust the stack pointer and jump to callee.
397 MBBI = MBB.getLastNonDebugInstr();
398 MachineOperand &JumpTarget = MBBI->getOperand(0);
400 // Jump to label or value in register.
401 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND) {
402 unsigned TCOpcode = (RetOpcode == ARM::TCRETURNdi)
403 ? (STI.isThumb() ? ARM::tTAILJMPd : ARM::TAILJMPd)
404 : (STI.isThumb() ? ARM::tTAILJMPdND : ARM::TAILJMPdND);
405 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
406 if (JumpTarget.isGlobal())
407 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
408 JumpTarget.getTargetFlags());
410 assert(JumpTarget.isSymbol());
411 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
412 JumpTarget.getTargetFlags());
414 } else if (RetOpcode == ARM::TCRETURNri) {
415 BuildMI(MBB, MBBI, dl,
416 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
417 addReg(JumpTarget.getReg(), RegState::Kill);
418 } else if (RetOpcode == ARM::TCRETURNriND) {
419 BuildMI(MBB, MBBI, dl,
420 TII.get(STI.isThumb() ? ARM::tTAILJMPrND : ARM::TAILJMPrND)).
421 addReg(JumpTarget.getReg(), RegState::Kill);
424 MachineInstr *NewMI = prior(MBBI);
425 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
426 NewMI->addOperand(MBBI->getOperand(i));
428 // Delete the pseudo instruction TCRETURN.
433 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
436 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
437 /// debug info. It's the same as what we use for resolving the code-gen
438 /// references for now. FIXME: This can go wrong when references are
439 /// SP-relative and simple call frames aren't used.
441 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
442 unsigned &FrameReg) const {
443 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
447 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
448 int FI, unsigned &FrameReg,
450 const MachineFrameInfo *MFI = MF.getFrameInfo();
451 const ARMBaseRegisterInfo *RegInfo =
452 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
453 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
454 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
455 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
456 bool isFixed = MFI->isFixedObjectIndex(FI);
460 if (AFI->isGPRCalleeSavedArea1Frame(FI))
461 return Offset - AFI->getGPRCalleeSavedArea1Offset();
462 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
463 return Offset - AFI->getGPRCalleeSavedArea2Offset();
464 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
465 return Offset - AFI->getDPRCalleeSavedAreaOffset();
467 // When dynamically realigning the stack, use the frame pointer for
468 // parameters, and the stack/base pointer for locals.
469 if (RegInfo->needsStackRealignment(MF)) {
470 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
472 FrameReg = RegInfo->getFrameRegister(MF);
474 } else if (MFI->hasVarSizedObjects()) {
475 assert(RegInfo->hasBasePointer(MF) &&
476 "VLAs and dynamic stack alignment, but missing base pointer!");
477 FrameReg = RegInfo->getBaseRegister();
482 // If there is a frame pointer, use it when we can.
483 if (hasFP(MF) && AFI->hasStackFrame()) {
484 // Use frame pointer to reference fixed objects. Use it for locals if
485 // there are VLAs (and thus the SP isn't reliable as a base).
486 if (isFixed || (MFI->hasVarSizedObjects() &&
487 !RegInfo->hasBasePointer(MF))) {
488 FrameReg = RegInfo->getFrameRegister(MF);
490 } else if (MFI->hasVarSizedObjects()) {
491 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
492 if (AFI->isThumb2Function()) {
493 // Try to use the frame pointer if we can, else use the base pointer
494 // since it's available. This is handy for the emergency spill slot, in
496 if (FPOffset >= -255 && FPOffset < 0) {
497 FrameReg = RegInfo->getFrameRegister(MF);
501 } else if (AFI->isThumb2Function()) {
502 // Use add <rd>, sp, #<imm8>
503 // ldr <rd>, [sp, #<imm8>]
504 // if at all possible to save space.
505 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
507 // In Thumb2 mode, the negative offset is very limited. Try to avoid
508 // out of range references. ldr <rt>,[<rn>, #-<imm8>]
509 if (FPOffset >= -255 && FPOffset < 0) {
510 FrameReg = RegInfo->getFrameRegister(MF);
513 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
514 // Otherwise, use SP or FP, whichever is closer to the stack slot.
515 FrameReg = RegInfo->getFrameRegister(MF);
519 // Use the base pointer if we have one.
520 if (RegInfo->hasBasePointer(MF))
521 FrameReg = RegInfo->getBaseRegister();
525 int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
528 return getFrameIndexReference(MF, FI, FrameReg);
531 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
532 MachineBasicBlock::iterator MI,
533 const std::vector<CalleeSavedInfo> &CSI,
534 unsigned StmOpc, unsigned StrOpc,
536 bool(*Func)(unsigned, bool),
537 unsigned MIFlags) const {
538 MachineFunction &MF = *MBB.getParent();
539 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
542 if (MI != MBB.end()) DL = MI->getDebugLoc();
544 SmallVector<std::pair<unsigned,bool>, 4> Regs;
545 unsigned i = CSI.size();
547 unsigned LastReg = 0;
548 for (; i != 0; --i) {
549 unsigned Reg = CSI[i-1].getReg();
550 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
552 // Add the callee-saved register as live-in unless it's LR and
553 // @llvm.returnaddress is called. If LR is returned for
554 // @llvm.returnaddress then it's already added to the function and
555 // entry block live-in sets.
557 if (Reg == ARM::LR) {
558 if (MF.getFrameInfo()->isReturnAddressTaken() &&
559 MF.getRegInfo().isLiveIn(Reg))
566 // If NoGap is true, push consecutive registers and then leave the rest
567 // for other instructions. e.g.
568 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
569 if (NoGap && LastReg && LastReg != Reg-1)
572 Regs.push_back(std::make_pair(Reg, isKill));
577 if (Regs.size() > 1 || StrOpc== 0) {
578 MachineInstrBuilder MIB =
579 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
580 .addReg(ARM::SP).setMIFlags(MIFlags));
581 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
582 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
583 } else if (Regs.size() == 1) {
584 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
586 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
587 .addReg(ARM::SP).setMIFlags(MIFlags);
588 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
589 // that refactoring is complete (eventually).
590 if (StrOpc == ARM::STR_PRE) {
592 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::sub, 4, ARM_AM::no_shift));
601 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
602 MachineBasicBlock::iterator MI,
603 const std::vector<CalleeSavedInfo> &CSI,
604 unsigned LdmOpc, unsigned LdrOpc,
605 bool isVarArg, bool NoGap,
606 bool(*Func)(unsigned, bool)) const {
607 MachineFunction &MF = *MBB.getParent();
608 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
609 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
610 DebugLoc DL = MI->getDebugLoc();
611 unsigned RetOpcode = MI->getOpcode();
612 bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||
613 RetOpcode == ARM::TCRETURNdiND ||
614 RetOpcode == ARM::TCRETURNri ||
615 RetOpcode == ARM::TCRETURNriND);
617 SmallVector<unsigned, 4> Regs;
618 unsigned i = CSI.size();
620 unsigned LastReg = 0;
621 bool DeleteRet = false;
622 for (; i != 0; --i) {
623 unsigned Reg = CSI[i-1].getReg();
624 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
626 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) {
628 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
629 // Fold the return instruction into the LDM.
633 // If NoGap is true, pop consecutive registers and then leave the rest
634 // for other instructions. e.g.
635 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
636 if (NoGap && LastReg && LastReg != Reg-1)
645 if (Regs.size() > 1 || LdrOpc == 0) {
646 MachineInstrBuilder MIB =
647 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
649 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
650 MIB.addReg(Regs[i], getDefRegState(true));
652 MI->eraseFromParent();
654 } else if (Regs.size() == 1) {
655 // If we adjusted the reg to PC from LR above, switch it back here. We
656 // only do that for LDM.
657 if (Regs[0] == ARM::PC)
659 MachineInstrBuilder MIB =
660 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
661 .addReg(ARM::SP, RegState::Define)
663 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
664 // that refactoring is complete (eventually).
665 if (LdrOpc == ARM::LDR_POST) {
667 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
676 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
677 MachineBasicBlock::iterator MI,
678 const std::vector<CalleeSavedInfo> &CSI,
679 const TargetRegisterInfo *TRI) const {
683 MachineFunction &MF = *MBB.getParent();
684 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
686 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
687 unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE;
688 unsigned FltOpc = ARM::VSTMDDB_UPD;
689 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register,
690 MachineInstr::FrameSetup);
691 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register,
692 MachineInstr::FrameSetup);
693 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
694 MachineInstr::FrameSetup);
699 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
700 MachineBasicBlock::iterator MI,
701 const std::vector<CalleeSavedInfo> &CSI,
702 const TargetRegisterInfo *TRI) const {
706 MachineFunction &MF = *MBB.getParent();
707 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
708 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
710 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
711 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST;
712 unsigned FltOpc = ARM::VLDMDIA_UPD;
713 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register);
714 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
715 &isARMArea2Register);
716 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
717 &isARMArea1Register);
722 // FIXME: Make generic?
723 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
724 const ARMBaseInstrInfo &TII) {
726 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
728 const MachineBasicBlock &MBB = *MBBI;
729 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
731 FnSize += TII.GetInstSizeInBytes(I);
736 /// estimateStackSize - Estimate and return the size of the frame.
737 /// FIXME: Make generic?
738 static unsigned estimateStackSize(MachineFunction &MF) {
739 const MachineFrameInfo *FFI = MF.getFrameInfo();
741 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
742 int FixedOff = -FFI->getObjectOffset(i);
743 if (FixedOff > Offset) Offset = FixedOff;
745 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
746 if (FFI->isDeadObjectIndex(i))
748 Offset += FFI->getObjectSize(i);
749 unsigned Align = FFI->getObjectAlignment(i);
750 // Adjust to alignment boundary
751 Offset = (Offset+Align-1)/Align*Align;
753 return (unsigned)Offset;
756 /// estimateRSStackSizeLimit - Look at each instruction that references stack
757 /// frames and return the stack size limit beyond which some of these
758 /// instructions will require a scratch register during their expansion later.
759 // FIXME: Move to TII?
760 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
761 const TargetFrameLowering *TFI) {
762 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
763 unsigned Limit = (1 << 12) - 1;
764 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
765 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
767 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
768 if (!I->getOperand(i).isFI()) continue;
770 // When using ADDri to get the address of a stack object, 255 is the
771 // largest offset guaranteed to fit in the immediate offset.
772 if (I->getOpcode() == ARM::ADDri) {
773 Limit = std::min(Limit, (1U << 8) - 1);
777 // Otherwise check the addressing mode.
778 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
779 case ARMII::AddrMode3:
780 case ARMII::AddrModeT2_i8:
781 Limit = std::min(Limit, (1U << 8) - 1);
783 case ARMII::AddrMode5:
784 case ARMII::AddrModeT2_i8s4:
785 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
787 case ARMII::AddrModeT2_i12:
788 // i12 supports only positive offset so these will be converted to
789 // i8 opcodes. See llvm::rewriteT2FrameIndex.
790 if (TFI->hasFP(MF) && AFI->hasStackFrame())
791 Limit = std::min(Limit, (1U << 8) - 1);
793 case ARMII::AddrMode4:
794 case ARMII::AddrMode6:
795 // Addressing modes 4 & 6 (load/store) instructions can't encode an
796 // immediate offset for stack references.
801 break; // At most one FI per instruction
810 ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
811 RegScavenger *RS) const {
812 // This tells PEI to spill the FP as if it is any other callee-save register
813 // to take advantage the eliminateFrameIndex machinery. This also ensures it
814 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
815 // to combine multiple loads / stores.
816 bool CanEliminateFrame = true;
817 bool CS1Spilled = false;
818 bool LRSpilled = false;
819 unsigned NumGPRSpills = 0;
820 SmallVector<unsigned, 4> UnspilledCS1GPRs;
821 SmallVector<unsigned, 4> UnspilledCS2GPRs;
822 const ARMBaseRegisterInfo *RegInfo =
823 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
824 const ARMBaseInstrInfo &TII =
825 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
826 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
827 MachineFrameInfo *MFI = MF.getFrameInfo();
828 unsigned FramePtr = RegInfo->getFrameRegister(MF);
830 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
831 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
832 // since it's not always possible to restore sp from fp in a single
834 // FIXME: It will be better just to find spare register here.
835 if (AFI->isThumb2Function() &&
836 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
837 MF.getRegInfo().setPhysRegUsed(ARM::R4);
839 if (AFI->isThumb1OnlyFunction()) {
840 // Spill LR if Thumb1 function uses variable length argument lists.
841 if (AFI->getVarArgsRegSaveSize() > 0)
842 MF.getRegInfo().setPhysRegUsed(ARM::LR);
844 // Spill R4 if Thumb1 epilogue has to restore SP from FP since
845 // FIXME: It will be better just to find spare register here.
846 if (MFI->hasVarSizedObjects())
847 MF.getRegInfo().setPhysRegUsed(ARM::R4);
850 // Spill the BasePtr if it's used.
851 if (RegInfo->hasBasePointer(MF))
852 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
854 // Don't spill FP if the frame can be eliminated. This is determined
855 // by scanning the callee-save registers to see if any is used.
856 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
857 for (unsigned i = 0; CSRegs[i]; ++i) {
858 unsigned Reg = CSRegs[i];
859 bool Spilled = false;
860 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
862 CanEliminateFrame = false;
864 // Check alias registers too.
865 for (const unsigned *Aliases =
866 RegInfo->getAliasSet(Reg); *Aliases; ++Aliases) {
867 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
869 CanEliminateFrame = false;
874 if (!ARM::GPRRegisterClass->contains(Reg))
880 if (!STI.isTargetDarwin()) {
887 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
892 case ARM::R4: case ARM::R5:
893 case ARM::R6: case ARM::R7:
900 if (!STI.isTargetDarwin()) {
901 UnspilledCS1GPRs.push_back(Reg);
906 case ARM::R4: case ARM::R5:
907 case ARM::R6: case ARM::R7:
909 UnspilledCS1GPRs.push_back(Reg);
912 UnspilledCS2GPRs.push_back(Reg);
918 bool ForceLRSpill = false;
919 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
920 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
921 // Force LR to be spilled if the Thumb function size is > 2048. This enables
922 // use of BL to implement far jump. If it turns out that it's not needed
923 // then the branch fix up path will undo it.
924 if (FnSize >= (1 << 11)) {
925 CanEliminateFrame = false;
930 // If any of the stack slot references may be out of range of an immediate
931 // offset, make sure a register (or a spill slot) is available for the
932 // register scavenger. Note that if we're indexing off the frame pointer, the
933 // effective stack size is 4 bytes larger since the FP points to the stack
934 // slot of the previous FP. Also, if we have variable sized objects in the
935 // function, stack slot references will often be negative, and some of
936 // our instructions are positive-offset only, so conservatively consider
937 // that case to want a spill slot (or register) as well. Similarly, if
938 // the function adjusts the stack pointer during execution and the
939 // adjustments aren't already part of our stack size estimate, our offset
940 // calculations may be off, so be conservative.
941 // FIXME: We could add logic to be more precise about negative offsets
942 // and which instructions will need a scratch register for them. Is it
943 // worth the effort and added fragility?
946 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
947 estimateRSStackSizeLimit(MF, this)))
948 || MFI->hasVarSizedObjects()
949 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
951 bool ExtraCSSpill = false;
952 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
953 AFI->setHasStackFrame(true);
955 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
956 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
957 if (!LRSpilled && CS1Spilled) {
958 MF.getRegInfo().setPhysRegUsed(ARM::LR);
960 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
961 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
962 ForceLRSpill = false;
967 MF.getRegInfo().setPhysRegUsed(FramePtr);
971 // If stack and double are 8-byte aligned and we are spilling an odd number
972 // of GPRs, spill one extra callee save GPR so we won't have to pad between
973 // the integer and double callee save areas.
974 unsigned TargetAlign = getStackAlignment();
975 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
976 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
977 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
978 unsigned Reg = UnspilledCS1GPRs[i];
979 // Don't spill high register if the function is thumb1
980 if (!AFI->isThumb1OnlyFunction() ||
981 isARMLowRegister(Reg) || Reg == ARM::LR) {
982 MF.getRegInfo().setPhysRegUsed(Reg);
983 if (!RegInfo->isReservedReg(MF, Reg))
988 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
989 unsigned Reg = UnspilledCS2GPRs.front();
990 MF.getRegInfo().setPhysRegUsed(Reg);
991 if (!RegInfo->isReservedReg(MF, Reg))
996 // Estimate if we might need to scavenge a register at some point in order
997 // to materialize a stack offset. If so, either spill one additional
998 // callee-saved register or reserve a special spill slot to facilitate
999 // register scavenging. Thumb1 needs a spill slot for stack pointer
1000 // adjustments also, even when the frame itself is small.
1001 if (BigStack && !ExtraCSSpill) {
1002 // If any non-reserved CS register isn't spilled, just spill one or two
1003 // extra. That should take care of it!
1004 unsigned NumExtras = TargetAlign / 4;
1005 SmallVector<unsigned, 2> Extras;
1006 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1007 unsigned Reg = UnspilledCS1GPRs.back();
1008 UnspilledCS1GPRs.pop_back();
1009 if (!RegInfo->isReservedReg(MF, Reg) &&
1010 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1012 Extras.push_back(Reg);
1016 // For non-Thumb1 functions, also check for hi-reg CS registers
1017 if (!AFI->isThumb1OnlyFunction()) {
1018 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1019 unsigned Reg = UnspilledCS2GPRs.back();
1020 UnspilledCS2GPRs.pop_back();
1021 if (!RegInfo->isReservedReg(MF, Reg)) {
1022 Extras.push_back(Reg);
1027 if (Extras.size() && NumExtras == 0) {
1028 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1029 MF.getRegInfo().setPhysRegUsed(Extras[i]);
1031 } else if (!AFI->isThumb1OnlyFunction()) {
1032 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1033 // closest to SP or frame pointer.
1034 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
1035 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1043 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1044 AFI->setLRIsSpilledForFarJump(true);