1 //===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMHazardRecognizer.h"
11 #include "ARMBaseInstrInfo.h"
12 #include "ARMBaseRegisterInfo.h"
13 #include "ARMSubtarget.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/ScheduleDAG.h"
16 #include "llvm/Target/TargetRegisterInfo.h"
19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
20 const TargetRegisterInfo &TRI) {
21 // FIXME: Detect integer instructions properly.
22 const TargetInstrDesc &TID = MI->getDesc();
23 unsigned Domain = TID.TSFlags & ARMII::DomainMask;
24 if (Domain == ARMII::DomainVFP) {
25 unsigned Opcode = MI->getOpcode();
26 if (Opcode == ARM::VSTRS || Opcode == ARM::VSTRD ||
27 Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
29 } else if (Domain == ARMII::DomainNEON) {
30 if (MI->getDesc().mayStore() || MI->getDesc().mayLoad())
34 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
37 ScheduleHazardRecognizer::HazardType
38 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
39 assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
41 MachineInstr *MI = SU->getInstr();
43 if (!MI->isDebugValue()) {
44 if (ITBlockSize && MI != ITBlockMIs[ITBlockSize-1])
47 // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
48 // a VMLA / VMLS will cause 4 cycle stall.
49 const TargetInstrDesc &TID = MI->getDesc();
50 if (LastMI && (TID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
51 MachineInstr *DefMI = LastMI;
52 const TargetInstrDesc &LastTID = LastMI->getDesc();
53 // Skip over one non-VFP / NEON instruction.
54 if (!LastTID.isBarrier() &&
55 (LastTID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
56 MachineBasicBlock::iterator I = LastMI;
57 if (I != LastMI->getParent()->begin()) {
63 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
64 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
65 hasRAWHazard(DefMI, MI, TRI))) {
66 // Try to schedule another instruction for the next 4 cycles.
74 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
77 void ARMHazardRecognizer::Reset() {
81 ScoreboardHazardRecognizer::Reset();
84 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
85 MachineInstr *MI = SU->getInstr();
86 unsigned Opcode = MI->getOpcode();
89 } else if (Opcode == ARM::t2IT) {
90 unsigned Mask = MI->getOperand(1).getImm();
91 unsigned NumTZ = CountTrailingZeros_32(Mask);
92 assert(NumTZ <= 3 && "Invalid IT mask!");
93 ITBlockSize = 4 - NumTZ;
94 MachineBasicBlock::iterator I = MI;
95 for (unsigned i = 0; i < ITBlockSize; ++i) {
96 // Advance to the next instruction, skipping any dbg_value instructions.
99 } while (I->isDebugValue());
100 ITBlockMIs[ITBlockSize-1-i] = &*I;
104 if (!MI->isDebugValue()) {
109 ScoreboardHazardRecognizer::EmitInstruction(SU);
112 void ARMHazardRecognizer::AdvanceCycle() {
113 if (FpMLxStalls && --FpMLxStalls == 0)
114 // Stalled for 4 cycles but still can't schedule any other instructions.
116 ScoreboardHazardRecognizer::AdvanceCycle();
119 void ARMHazardRecognizer::RecedeCycle() {
120 llvm_unreachable("reverse ARM hazard checking unsupported");