1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
39 static const unsigned arm_dsubreg_0 = 5;
40 static const unsigned arm_dsubreg_1 = 6;
42 //===--------------------------------------------------------------------===//
43 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
44 /// instructions for SelectionDAG operations.
47 class ARMDAGToDAGISel : public SelectionDAGISel {
48 ARMBaseTargetMachine &TM;
50 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
51 /// make the right decision when generating code for different targets.
52 const ARMSubtarget *Subtarget;
55 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm)
56 : SelectionDAGISel(tm), TM(tm),
57 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
60 virtual const char *getPassName() const {
61 return "ARM Instruction Selection";
64 /// getI32Imm - Return a target constant with the specified value, of type i32.
65 inline SDValue getI32Imm(unsigned Imm) {
66 return CurDAG->getTargetConstant(Imm, MVT::i32);
69 SDNode *Select(SDValue Op);
70 virtual void InstructionSelect();
71 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
72 SDValue &B, SDValue &C);
73 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
74 SDValue &Offset, SDValue &Opc);
75 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
76 SDValue &Offset, SDValue &Opc);
77 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
78 SDValue &Offset, SDValue &Opc);
79 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
80 SDValue &Offset, SDValue &Opc);
81 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
83 bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
86 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
89 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
91 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
92 SDValue &Base, SDValue &OffImm,
94 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
95 SDValue &OffImm, SDValue &Offset);
96 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
97 SDValue &OffImm, SDValue &Offset);
98 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
99 SDValue &OffImm, SDValue &Offset);
100 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
103 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
104 SDValue &BaseReg, SDValue &Opc);
105 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
107 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
109 bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
111 bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
113 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
114 SDValue &OffReg, SDValue &ShImm);
116 // Include the pieces autogenerated from the target description.
117 #include "ARMGenDAGISel.inc"
120 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
122 SDNode *SelectARMIndexedLoad(SDValue Op);
123 SDNode *SelectT2IndexedLoad(SDValue Op);
125 /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
126 SDNode *SelectDYN_ALLOC(SDValue Op);
128 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
129 /// inline asm expressions.
130 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
132 std::vector<SDValue> &OutOps);
136 void ARMDAGToDAGISel::InstructionSelect() {
140 CurDAG->RemoveDeadNodes();
143 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
148 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
150 // Don't match base register only case. That is matched to a separate
151 // lower complexity pattern with explicit register operand.
152 if (ShOpcVal == ARM_AM::no_shift) return false;
154 BaseReg = N.getOperand(0);
155 unsigned ShImmVal = 0;
156 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
157 ShReg = CurDAG->getRegister(0, MVT::i32);
158 ShImmVal = RHS->getZExtValue() & 31;
160 ShReg = N.getOperand(1);
162 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
167 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
168 SDValue &Base, SDValue &Offset,
170 if (N.getOpcode() == ISD::MUL) {
171 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
172 // X * [3,5,9] -> X + X * [2,4,8] etc.
173 int RHSC = (int)RHS->getZExtValue();
176 ARM_AM::AddrOpc AddSub = ARM_AM::add;
178 AddSub = ARM_AM::sub;
181 if (isPowerOf2_32(RHSC)) {
182 unsigned ShAmt = Log2_32(RHSC);
183 Base = Offset = N.getOperand(0);
184 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
193 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
195 if (N.getOpcode() == ISD::FrameIndex) {
196 int FI = cast<FrameIndexSDNode>(N)->getIndex();
197 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
198 } else if (N.getOpcode() == ARMISD::Wrapper) {
199 Base = N.getOperand(0);
201 Offset = CurDAG->getRegister(0, MVT::i32);
202 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
208 // Match simple R +/- imm12 operands.
209 if (N.getOpcode() == ISD::ADD)
210 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
211 int RHSC = (int)RHS->getZExtValue();
212 if ((RHSC >= 0 && RHSC < 0x1000) ||
213 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
214 Base = N.getOperand(0);
215 if (Base.getOpcode() == ISD::FrameIndex) {
216 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
217 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
219 Offset = CurDAG->getRegister(0, MVT::i32);
221 ARM_AM::AddrOpc AddSub = ARM_AM::add;
223 AddSub = ARM_AM::sub;
226 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
233 // Otherwise this is R +/- [possibly shifted] R
234 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
235 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
238 Base = N.getOperand(0);
239 Offset = N.getOperand(1);
241 if (ShOpcVal != ARM_AM::no_shift) {
242 // Check to see if the RHS of the shift is a constant, if not, we can't fold
244 if (ConstantSDNode *Sh =
245 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
246 ShAmt = Sh->getZExtValue();
247 Offset = N.getOperand(1).getOperand(0);
249 ShOpcVal = ARM_AM::no_shift;
253 // Try matching (R shl C) + (R).
254 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
255 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
256 if (ShOpcVal != ARM_AM::no_shift) {
257 // Check to see if the RHS of the shift is a constant, if not, we can't
259 if (ConstantSDNode *Sh =
260 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
261 ShAmt = Sh->getZExtValue();
262 Offset = N.getOperand(0).getOperand(0);
263 Base = N.getOperand(1);
265 ShOpcVal = ARM_AM::no_shift;
270 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
275 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
276 SDValue &Offset, SDValue &Opc) {
277 unsigned Opcode = Op.getOpcode();
278 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
279 ? cast<LoadSDNode>(Op)->getAddressingMode()
280 : cast<StoreSDNode>(Op)->getAddressingMode();
281 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
282 ? ARM_AM::add : ARM_AM::sub;
283 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
284 int Val = (int)C->getZExtValue();
285 if (Val >= 0 && Val < 0x1000) { // 12 bits.
286 Offset = CurDAG->getRegister(0, MVT::i32);
287 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
295 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
297 if (ShOpcVal != ARM_AM::no_shift) {
298 // Check to see if the RHS of the shift is a constant, if not, we can't fold
300 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
301 ShAmt = Sh->getZExtValue();
302 Offset = N.getOperand(0);
304 ShOpcVal = ARM_AM::no_shift;
308 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
314 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
315 SDValue &Base, SDValue &Offset,
317 if (N.getOpcode() == ISD::SUB) {
318 // X - C is canonicalize to X + -C, no need to handle it here.
319 Base = N.getOperand(0);
320 Offset = N.getOperand(1);
321 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
325 if (N.getOpcode() != ISD::ADD) {
327 if (N.getOpcode() == ISD::FrameIndex) {
328 int FI = cast<FrameIndexSDNode>(N)->getIndex();
329 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
331 Offset = CurDAG->getRegister(0, MVT::i32);
332 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
336 // If the RHS is +/- imm8, fold into addr mode.
337 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
338 int RHSC = (int)RHS->getZExtValue();
339 if ((RHSC >= 0 && RHSC < 256) ||
340 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
341 Base = N.getOperand(0);
342 if (Base.getOpcode() == ISD::FrameIndex) {
343 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
344 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
346 Offset = CurDAG->getRegister(0, MVT::i32);
348 ARM_AM::AddrOpc AddSub = ARM_AM::add;
350 AddSub = ARM_AM::sub;
353 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
358 Base = N.getOperand(0);
359 Offset = N.getOperand(1);
360 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
364 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
365 SDValue &Offset, SDValue &Opc) {
366 unsigned Opcode = Op.getOpcode();
367 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
368 ? cast<LoadSDNode>(Op)->getAddressingMode()
369 : cast<StoreSDNode>(Op)->getAddressingMode();
370 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
371 ? ARM_AM::add : ARM_AM::sub;
372 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
373 int Val = (int)C->getZExtValue();
374 if (Val >= 0 && Val < 256) {
375 Offset = CurDAG->getRegister(0, MVT::i32);
376 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
382 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
387 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
388 SDValue &Base, SDValue &Offset) {
389 if (N.getOpcode() != ISD::ADD) {
391 if (N.getOpcode() == ISD::FrameIndex) {
392 int FI = cast<FrameIndexSDNode>(N)->getIndex();
393 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
394 } else if (N.getOpcode() == ARMISD::Wrapper) {
395 Base = N.getOperand(0);
397 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
402 // If the RHS is +/- imm8, fold into addr mode.
403 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
404 int RHSC = (int)RHS->getZExtValue();
405 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
407 if ((RHSC >= 0 && RHSC < 256) ||
408 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
409 Base = N.getOperand(0);
410 if (Base.getOpcode() == ISD::FrameIndex) {
411 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
412 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
415 ARM_AM::AddrOpc AddSub = ARM_AM::add;
417 AddSub = ARM_AM::sub;
420 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
428 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
433 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
434 SDValue &Addr, SDValue &Update,
437 // The optional writeback is handled in ARMLoadStoreOpt.
438 Update = CurDAG->getRegister(0, MVT::i32);
439 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
443 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
444 SDValue &Offset, SDValue &Label) {
445 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
446 Offset = N.getOperand(0);
447 SDValue N1 = N.getOperand(1);
448 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
455 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
456 SDValue &Base, SDValue &Offset){
457 // FIXME dl should come from the parent load or store, not the address
458 DebugLoc dl = Op.getDebugLoc();
459 if (N.getOpcode() != ISD::ADD) {
460 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
461 if (!NC || NC->getZExtValue() != 0)
468 Base = N.getOperand(0);
469 Offset = N.getOperand(1);
474 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
475 unsigned Scale, SDValue &Base,
476 SDValue &OffImm, SDValue &Offset) {
478 SDValue TmpBase, TmpOffImm;
479 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
480 return false; // We want to select tLDRspi / tSTRspi instead.
481 if (N.getOpcode() == ARMISD::Wrapper &&
482 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
483 return false; // We want to select tLDRpci instead.
486 if (N.getOpcode() != ISD::ADD) {
487 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
488 Offset = CurDAG->getRegister(0, MVT::i32);
489 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
493 // Thumb does not have [sp, r] address mode.
494 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
495 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
496 if ((LHSR && LHSR->getReg() == ARM::SP) ||
497 (RHSR && RHSR->getReg() == ARM::SP)) {
499 Offset = CurDAG->getRegister(0, MVT::i32);
500 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
504 // If the RHS is + imm5 * scale, fold into addr mode.
505 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
506 int RHSC = (int)RHS->getZExtValue();
507 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
509 if (RHSC >= 0 && RHSC < 32) {
510 Base = N.getOperand(0);
511 Offset = CurDAG->getRegister(0, MVT::i32);
512 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
518 Base = N.getOperand(0);
519 Offset = N.getOperand(1);
520 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
524 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
525 SDValue &Base, SDValue &OffImm,
527 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
530 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
531 SDValue &Base, SDValue &OffImm,
533 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
536 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
537 SDValue &Base, SDValue &OffImm,
539 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
542 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
543 SDValue &Base, SDValue &OffImm) {
544 if (N.getOpcode() == ISD::FrameIndex) {
545 int FI = cast<FrameIndexSDNode>(N)->getIndex();
546 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
547 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
551 if (N.getOpcode() != ISD::ADD)
554 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
555 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
556 (LHSR && LHSR->getReg() == ARM::SP)) {
557 // If the RHS is + imm8 * scale, fold into addr mode.
558 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
559 int RHSC = (int)RHS->getZExtValue();
560 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
562 if (RHSC >= 0 && RHSC < 256) {
563 Base = N.getOperand(0);
564 if (Base.getOpcode() == ISD::FrameIndex) {
565 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
566 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
568 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
578 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
581 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
583 // Don't match base register only case. That is matched to a separate
584 // lower complexity pattern with explicit register operand.
585 if (ShOpcVal == ARM_AM::no_shift) return false;
587 BaseReg = N.getOperand(0);
588 unsigned ShImmVal = 0;
589 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
590 ShImmVal = RHS->getZExtValue() & 31;
591 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
598 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
599 SDValue &Base, SDValue &OffImm) {
600 // Match simple R + imm12 operands.
602 // Match frame index...
603 if ((N.getOpcode() != ISD::ADD) && (N.getOpcode() != ISD::SUB)) {
604 if (N.getOpcode() == ISD::FrameIndex) {
605 int FI = cast<FrameIndexSDNode>(N)->getIndex();
606 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
607 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
613 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
614 int RHSC = (int)RHS->getZExtValue();
615 if (N.getOpcode() == ISD::SUB)
618 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
619 Base = N.getOperand(0);
620 if (Base.getOpcode() == ISD::FrameIndex) {
621 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
622 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
624 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
632 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
633 SDValue &Base, SDValue &OffImm) {
634 // Match simple R - imm8 operands.
635 if ((N.getOpcode() == ISD::ADD) || (N.getOpcode() == ISD::SUB)) {
636 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
637 int RHSC = (int)RHS->getSExtValue();
638 if (N.getOpcode() == ISD::SUB)
641 if ((RHSC >= -255) && (RHSC <= 0)) { // 8 bits (always negative)
642 Base = N.getOperand(0);
643 if (Base.getOpcode() == ISD::FrameIndex) {
644 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
645 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
647 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
656 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
658 unsigned Opcode = Op.getOpcode();
659 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
660 ? cast<LoadSDNode>(Op)->getAddressingMode()
661 : cast<StoreSDNode>(Op)->getAddressingMode();
662 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
663 int RHSC = (int)RHS->getZExtValue();
664 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
665 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
666 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
667 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
675 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
676 SDValue &Base, SDValue &OffImm) {
677 if (N.getOpcode() == ISD::ADD) {
678 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
679 int RHSC = (int)RHS->getZExtValue();
680 if (((RHSC & 0x3) == 0) &&
681 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
682 Base = N.getOperand(0);
683 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
687 } else if (N.getOpcode() == ISD::SUB) {
688 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
689 int RHSC = (int)RHS->getZExtValue();
690 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
691 Base = N.getOperand(0);
692 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
701 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
703 SDValue &OffReg, SDValue &ShImm) {
705 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
707 if (N.getOpcode() == ISD::FrameIndex) {
708 return false; // we want to select t2LDRri12 instead
709 } else if (N.getOpcode() == ARMISD::Wrapper) {
710 Base = N.getOperand(0);
711 if (Base.getOpcode() == ISD::TargetConstantPool)
712 return false; // We want to select t2LDRpci instead.
714 OffReg = CurDAG->getRegister(0, MVT::i32);
715 ShImm = CurDAG->getTargetConstant(0, MVT::i32);
719 // Leave (R +/- imm) for other address modes... unless they can't
721 if (dyn_cast<ConstantSDNode>(N.getOperand(1)) != NULL) {
723 if (SelectT2AddrModeImm12(Op, N, Base, OffImm) ||
724 SelectT2AddrModeImm8 (Op, N, Base, OffImm))
728 // Thumb2 does not support (R - R) or (R - (R << [1,2,3])).
729 if (N.getOpcode() == ISD::SUB) {
731 OffReg = CurDAG->getRegister(0, MVT::i32);
732 ShImm = CurDAG->getTargetConstant(0, MVT::i32);
736 assert(N.getOpcode() == ISD::ADD);
738 // Look for (R + R) or (R + (R << [1,2,3])).
740 Base = N.getOperand(0);
741 OffReg = N.getOperand(1);
743 // Swap if it is ((R << c) + R).
744 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
745 if (ShOpcVal != ARM_AM::lsl) {
746 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
747 if (ShOpcVal == ARM_AM::lsl)
748 std::swap(Base, OffReg);
751 if (ShOpcVal == ARM_AM::lsl) {
752 // Check to see if the RHS of the shift is a constant, if not, we can't fold
754 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
755 ShAmt = Sh->getZExtValue();
758 ShOpcVal = ARM_AM::no_shift;
760 OffReg = OffReg.getOperand(0);
762 ShOpcVal = ARM_AM::no_shift;
766 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
771 //===--------------------------------------------------------------------===//
773 /// getAL - Returns a ARMCC::AL immediate node.
774 static inline SDValue getAL(SelectionDAG *CurDAG) {
775 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
778 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
779 LoadSDNode *LD = cast<LoadSDNode>(Op);
780 ISD::MemIndexedMode AM = LD->getAddressingMode();
781 if (AM == ISD::UNINDEXED)
784 MVT LoadedVT = LD->getMemoryVT();
785 SDValue Offset, AMOpc;
786 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
789 if (LoadedVT == MVT::i32 &&
790 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
791 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
793 } else if (LoadedVT == MVT::i16 &&
794 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
796 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
797 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
798 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
799 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
800 if (LD->getExtensionType() == ISD::SEXTLOAD) {
801 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
803 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
806 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
808 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
814 SDValue Chain = LD->getChain();
815 SDValue Base = LD->getBasePtr();
816 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
817 CurDAG->getRegister(0, MVT::i32), Chain };
818 return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
825 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
826 LoadSDNode *LD = cast<LoadSDNode>(Op);
827 ISD::MemIndexedMode AM = LD->getAddressingMode();
828 if (AM == ISD::UNINDEXED)
831 MVT LoadedVT = LD->getMemoryVT();
832 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
834 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
837 if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
838 switch (LoadedVT.getSimpleVT()) {
840 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
844 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
846 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
851 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
853 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
862 SDValue Chain = LD->getChain();
863 SDValue Base = LD->getBasePtr();
864 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
865 CurDAG->getRegister(0, MVT::i32), Chain };
866 return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
873 SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
874 SDNode *N = Op.getNode();
875 DebugLoc dl = N->getDebugLoc();
876 MVT VT = Op.getValueType();
877 SDValue Chain = Op.getOperand(0);
878 SDValue Size = Op.getOperand(1);
879 SDValue Align = Op.getOperand(2);
880 SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
881 int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
883 // We need to align the stack. Use Thumb1 tAND which is the only thumb
884 // instruction that can read and write SP. This matches to a pseudo
885 // instruction that has a chain to ensure the result is written back to
886 // the stack pointer.
887 SP = SDValue(CurDAG->getTargetNode(ARM::tANDsp, dl, VT, SP, Align), 0);
889 bool isC = isa<ConstantSDNode>(Size);
890 uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
891 // Handle the most common case for both Thumb1 and Thumb2:
892 // tSUBspi - immediate is between 0 ... 508 inclusive.
893 if (C <= 508 && ((C & 3) == 0))
894 // FIXME: tSUBspi encode scale 4 implicitly.
895 return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
896 CurDAG->getTargetConstant(C/4, MVT::i32),
899 if (Subtarget->isThumb1Only()) {
900 // Use tADDrSPr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
901 // should have negated the size operand already. FIXME: We can't insert
902 // new target independent node at this stage so we are forced to negate
903 // it earlier. Is there a better solution?
904 return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
906 } else if (Subtarget->isThumb2()) {
907 if (isC && Predicate_t2_so_imm(Size.getNode())) {
909 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
910 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
911 } else if (isC && Predicate_imm0_4095(Size.getNode())) {
913 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
914 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
917 SDValue Ops[] = { SP, Size,
918 getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
919 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
923 // FIXME: Add ADD / SUB sp instructions for ARM.
927 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
928 SDNode *N = Op.getNode();
929 DebugLoc dl = N->getDebugLoc();
931 if (N->isMachineOpcode())
932 return NULL; // Already selected.
934 switch (N->getOpcode()) {
936 case ISD::Constant: {
937 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
939 if (Subtarget->isThumb()) {
940 if (Subtarget->hasThumb2())
941 // Thumb2 has the MOVT instruction, so all immediates can
942 // be done with MOV + MOVT, at worst.
945 UseCP = (Val > 255 && // MOV
946 ~Val > 255 && // MOV + MVN
947 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
949 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
950 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
951 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
954 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
958 if (Subtarget->isThumb1Only()) {
959 SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
960 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
961 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
962 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
967 CurDAG->getRegister(0, MVT::i32),
968 CurDAG->getTargetConstant(0, MVT::i32),
970 CurDAG->getRegister(0, MVT::i32),
971 CurDAG->getEntryNode()
973 ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
976 ReplaceUses(Op, SDValue(ResNode, 0));
980 // Other cases are autogenerated.
983 case ISD::FrameIndex: {
984 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
985 int FI = cast<FrameIndexSDNode>(N)->getIndex();
986 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
987 if (Subtarget->isThumb1Only()) {
988 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
989 CurDAG->getTargetConstant(0, MVT::i32));
991 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
992 ARM::t2ADDri : ARM::ADDri);
993 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
994 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
995 CurDAG->getRegister(0, MVT::i32) };
996 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
999 case ARMISD::DYN_ALLOC:
1000 return SelectDYN_ALLOC(Op);
1002 if (Subtarget->isThumb1Only())
1004 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1005 unsigned RHSV = C->getZExtValue();
1007 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1008 unsigned ShImm = Log2_32(RHSV-1);
1011 SDValue V = Op.getOperand(0);
1012 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1013 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1014 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1015 if (Subtarget->isThumb()) {
1016 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1017 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1019 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1020 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1023 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1024 unsigned ShImm = Log2_32(RHSV+1);
1027 SDValue V = Op.getOperand(0);
1028 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1029 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1030 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1031 if (Subtarget->isThumb()) {
1032 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1033 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1035 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1036 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1042 return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
1043 Op.getOperand(0), getAL(CurDAG),
1044 CurDAG->getRegister(0, MVT::i32));
1045 case ISD::UMUL_LOHI: {
1046 if (Subtarget->isThumb1Only())
1048 if (Subtarget->isThumb()) {
1049 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1050 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1051 CurDAG->getRegister(0, MVT::i32) };
1052 return CurDAG->getTargetNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1054 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1055 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1056 CurDAG->getRegister(0, MVT::i32) };
1057 return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1060 case ISD::SMUL_LOHI: {
1061 if (Subtarget->isThumb1Only())
1063 if (Subtarget->isThumb()) {
1064 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1065 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1066 return CurDAG->getTargetNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1068 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1069 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1070 CurDAG->getRegister(0, MVT::i32) };
1071 return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1075 SDNode *ResNode = 0;
1076 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1077 ResNode = SelectT2IndexedLoad(Op);
1079 ResNode = SelectARMIndexedLoad(Op);
1082 // Other cases are autogenerated.
1085 case ARMISD::BRCOND: {
1086 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1087 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1088 // Pattern complexity = 6 cost = 1 size = 0
1090 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1091 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1092 // Pattern complexity = 6 cost = 1 size = 0
1094 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1095 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1096 // Pattern complexity = 6 cost = 1 size = 0
1098 unsigned Opc = Subtarget->isThumb() ?
1099 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1100 SDValue Chain = Op.getOperand(0);
1101 SDValue N1 = Op.getOperand(1);
1102 SDValue N2 = Op.getOperand(2);
1103 SDValue N3 = Op.getOperand(3);
1104 SDValue InFlag = Op.getOperand(4);
1105 assert(N1.getOpcode() == ISD::BasicBlock);
1106 assert(N2.getOpcode() == ISD::Constant);
1107 assert(N3.getOpcode() == ISD::Register);
1109 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1110 cast<ConstantSDNode>(N2)->getZExtValue()),
1112 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1113 SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
1115 Chain = SDValue(ResNode, 0);
1116 if (Op.getNode()->getNumValues() == 2) {
1117 InFlag = SDValue(ResNode, 1);
1118 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1120 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
1123 case ARMISD::CMOV: {
1124 MVT VT = Op.getValueType();
1125 SDValue N0 = Op.getOperand(0);
1126 SDValue N1 = Op.getOperand(1);
1127 SDValue N2 = Op.getOperand(2);
1128 SDValue N3 = Op.getOperand(3);
1129 SDValue InFlag = Op.getOperand(4);
1130 assert(N2.getOpcode() == ISD::Constant);
1131 assert(N3.getOpcode() == ISD::Register);
1133 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1134 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1135 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1136 // Pattern complexity = 18 cost = 1 size = 0
1140 if (Subtarget->isThumb()) {
1141 if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
1142 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1143 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1146 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1147 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1148 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1149 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1151 llvm_unreachable("Unknown so_reg opcode!");
1155 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1156 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1157 cast<ConstantSDNode>(N2)->getZExtValue()),
1159 SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
1160 return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
1163 if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
1164 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1165 cast<ConstantSDNode>(N2)->getZExtValue()),
1167 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
1168 return CurDAG->SelectNodeTo(Op.getNode(),
1169 ARM::MOVCCs, MVT::i32, Ops, 7);
1173 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1174 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1176 // Emits: (MOVCCi:i32 GPR:i32:$false,
1177 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1178 // Pattern complexity = 10 cost = 1 size = 0
1179 if (N3.getOpcode() == ISD::Constant) {
1180 if (Subtarget->isThumb()) {
1181 if (Predicate_t2_so_imm(N3.getNode())) {
1182 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1183 cast<ConstantSDNode>(N1)->getZExtValue()),
1185 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1186 cast<ConstantSDNode>(N2)->getZExtValue()),
1188 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1189 return CurDAG->SelectNodeTo(Op.getNode(),
1190 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1193 if (Predicate_so_imm(N3.getNode())) {
1194 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1195 cast<ConstantSDNode>(N1)->getZExtValue()),
1197 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1198 cast<ConstantSDNode>(N2)->getZExtValue()),
1200 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1201 return CurDAG->SelectNodeTo(Op.getNode(),
1202 ARM::MOVCCi, MVT::i32, Ops, 5);
1208 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1209 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1210 // Pattern complexity = 6 cost = 1 size = 0
1212 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1213 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1214 // Pattern complexity = 6 cost = 11 size = 0
1216 // Also FCPYScc and FCPYDcc.
1217 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1218 cast<ConstantSDNode>(N2)->getZExtValue()),
1220 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1222 switch (VT.getSimpleVT()) {
1223 default: assert(false && "Illegal conditional move type!");
1226 Opc = Subtarget->isThumb()
1227 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr)
1237 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1239 case ARMISD::CNEG: {
1240 MVT VT = Op.getValueType();
1241 SDValue N0 = Op.getOperand(0);
1242 SDValue N1 = Op.getOperand(1);
1243 SDValue N2 = Op.getOperand(2);
1244 SDValue N3 = Op.getOperand(3);
1245 SDValue InFlag = Op.getOperand(4);
1246 assert(N2.getOpcode() == ISD::Constant);
1247 assert(N3.getOpcode() == ISD::Register);
1249 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1250 cast<ConstantSDNode>(N2)->getZExtValue()),
1252 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1254 switch (VT.getSimpleVT()) {
1255 default: assert(false && "Illegal conditional move type!");
1264 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1267 case ISD::DECLARE: {
1268 SDValue Chain = Op.getOperand(0);
1269 SDValue N1 = Op.getOperand(1);
1270 SDValue N2 = Op.getOperand(2);
1271 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
1272 // FIXME: handle VLAs.
1274 ReplaceUses(Op.getValue(0), Chain);
1277 if (N2.getOpcode() == ARMISD::PIC_ADD && isa<LoadSDNode>(N2.getOperand(0)))
1278 N2 = N2.getOperand(0);
1279 LoadSDNode *Ld = dyn_cast<LoadSDNode>(N2);
1281 ReplaceUses(Op.getValue(0), Chain);
1284 SDValue BasePtr = Ld->getBasePtr();
1285 assert(BasePtr.getOpcode() == ARMISD::Wrapper &&
1286 isa<ConstantPoolSDNode>(BasePtr.getOperand(0)) &&
1287 "llvm.dbg.variable should be a constantpool node");
1288 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(BasePtr.getOperand(0));
1289 GlobalValue *GV = 0;
1290 if (CP->isMachineConstantPoolEntry()) {
1291 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal();
1294 GV = dyn_cast<GlobalValue>(CP->getConstVal());
1296 ReplaceUses(Op.getValue(0), Chain);
1300 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
1301 TLI.getPointerTy());
1302 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
1303 SDValue Ops[] = { Tmp1, Tmp2, Chain };
1304 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
1305 MVT::Other, Ops, 3);
1308 case ISD::VECTOR_SHUFFLE: {
1309 MVT VT = Op.getValueType();
1311 // Match 128-bit splat to VDUPLANEQ. (This could be done with a Pat in
1312 // ARMInstrNEON.td but it is awkward because the shuffle mask needs to be
1313 // transformed first into a lane number and then to both a subregister
1314 // index and an adjusted lane number.) If the source operand is a
1315 // SCALAR_TO_VECTOR, leave it so it will be matched later as a VDUP.
1316 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1317 if (VT.is128BitVector() && SVOp->isSplat() &&
1318 Op.getOperand(0).getOpcode() != ISD::SCALAR_TO_VECTOR &&
1319 Op.getOperand(1).getOpcode() == ISD::UNDEF) {
1320 unsigned LaneVal = SVOp->getSplatIndex();
1324 switch (VT.getVectorElementType().getSimpleVT()) {
1325 default: llvm_unreachable("unhandled VDUP splat type");
1326 case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break;
1327 case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
1328 case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
1329 case MVT::f32: Opc = ARM::VDUPLNfq; HalfVT = MVT::v2f32; break;
1332 // The source operand needs to be changed to a subreg of the original
1333 // 128-bit operand, and the lane number needs to be adjusted accordingly.
1334 unsigned NumElts = VT.getVectorNumElements() / 2;
1335 unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1);
1336 SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32);
1337 SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32);
1338 SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
1339 dl, HalfVT, N->getOperand(0), SR);
1340 return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane);
1346 case ARMISD::VLD2D: {
1347 SDValue MemAddr, MemUpdate, MemOpc;
1348 if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
1351 MVT VT = Op.getValueType();
1352 switch (VT.getSimpleVT()) {
1353 default: llvm_unreachable("unhandled VLD2D type");
1354 case MVT::v8i8: Opc = ARM::VLD2d8; break;
1355 case MVT::v4i16: Opc = ARM::VLD2d16; break;
1357 case MVT::v2i32: Opc = ARM::VLD2d32; break;
1359 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
1360 return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3);
1363 case ARMISD::VLD3D: {
1364 SDValue MemAddr, MemUpdate, MemOpc;
1365 if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
1368 MVT VT = Op.getValueType();
1369 switch (VT.getSimpleVT()) {
1370 default: llvm_unreachable("unhandled VLD3D type");
1371 case MVT::v8i8: Opc = ARM::VLD3d8; break;
1372 case MVT::v4i16: Opc = ARM::VLD3d16; break;
1374 case MVT::v2i32: Opc = ARM::VLD3d32; break;
1376 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
1377 return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3);
1380 case ARMISD::VLD4D: {
1381 SDValue MemAddr, MemUpdate, MemOpc;
1382 if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
1385 MVT VT = Op.getValueType();
1386 switch (VT.getSimpleVT()) {
1387 default: llvm_unreachable("unhandled VLD4D type");
1388 case MVT::v8i8: Opc = ARM::VLD4d8; break;
1389 case MVT::v4i16: Opc = ARM::VLD4d16; break;
1391 case MVT::v2i32: Opc = ARM::VLD4d32; break;
1393 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
1394 std::vector<MVT> ResTys(4, VT);
1395 ResTys.push_back(MVT::Other);
1396 return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3);
1399 case ARMISD::VST2D: {
1400 SDValue MemAddr, MemUpdate, MemOpc;
1401 if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
1404 switch (N->getOperand(2).getValueType().getSimpleVT()) {
1405 default: llvm_unreachable("unhandled VST2D type");
1406 case MVT::v8i8: Opc = ARM::VST2d8; break;
1407 case MVT::v4i16: Opc = ARM::VST2d16; break;
1409 case MVT::v2i32: Opc = ARM::VST2d32; break;
1411 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1412 N->getOperand(2), N->getOperand(3) };
1413 return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 5);
1416 case ARMISD::VST3D: {
1417 SDValue MemAddr, MemUpdate, MemOpc;
1418 if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
1421 switch (N->getOperand(2).getValueType().getSimpleVT()) {
1422 default: llvm_unreachable("unhandled VST3D type");
1423 case MVT::v8i8: Opc = ARM::VST3d8; break;
1424 case MVT::v4i16: Opc = ARM::VST3d16; break;
1426 case MVT::v2i32: Opc = ARM::VST3d32; break;
1428 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1429 N->getOperand(2), N->getOperand(3),
1431 return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
1434 case ARMISD::VST4D: {
1435 SDValue MemAddr, MemUpdate, MemOpc;
1436 if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
1439 switch (N->getOperand(2).getValueType().getSimpleVT()) {
1440 default: llvm_unreachable("unhandled VST4D type");
1441 case MVT::v8i8: Opc = ARM::VST4d8; break;
1442 case MVT::v4i16: Opc = ARM::VST4d16; break;
1444 case MVT::v2i32: Opc = ARM::VST4d32; break;
1446 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1447 N->getOperand(2), N->getOperand(3),
1448 N->getOperand(4), N->getOperand(5) };
1449 return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
1453 return SelectCode(Op);
1456 bool ARMDAGToDAGISel::
1457 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1458 std::vector<SDValue> &OutOps) {
1459 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1461 SDValue Base, Offset, Opc;
1462 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
1465 OutOps.push_back(Base);
1466 OutOps.push_back(Offset);
1467 OutOps.push_back(Opc);
1471 /// createARMISelDag - This pass converts a legalized DAG into a
1472 /// ARM-specific DAG, ready for instruction scheduling.
1474 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM) {
1475 return new ARMDAGToDAGISel(TM);