1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
41 DisableShifterOp("disable-shifter-op", cl::Hidden,
42 cl::desc("Disable isel of shifter-op"),
46 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47 cl::desc("Check fp vmla / vmls hazard at isel time"),
50 //===--------------------------------------------------------------------===//
51 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
52 /// instructions for SelectionDAG operations.
57 AM2_BASE, // Simple AM2 (+-imm12)
58 AM2_SHOP // Shifter-op AM2
61 class ARMDAGToDAGISel : public SelectionDAGISel {
62 ARMBaseTargetMachine &TM;
63 const ARMBaseInstrInfo *TII;
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when generating code for different targets.
67 const ARMSubtarget *Subtarget;
70 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
71 CodeGenOpt::Level OptLevel)
72 : SelectionDAGISel(tm, OptLevel), TM(tm),
73 TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
74 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
77 virtual const char *getPassName() const {
78 return "ARM Instruction Selection";
81 /// getI32Imm - Return a target constant of type i32 with the specified
83 inline SDValue getI32Imm(unsigned Imm) {
84 return CurDAG->getTargetConstant(Imm, MVT::i32);
87 SDNode *Select(SDNode *N);
90 bool hasNoVMLxHazardUse(SDNode *N) const;
91 bool isShifterOpProfitable(const SDValue &Shift,
92 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
93 bool SelectShifterOperandReg(SDValue N, SDValue &A,
94 SDValue &B, SDValue &C,
95 bool CheckProfitability = true);
96 bool SelectShiftShifterOperandReg(SDValue N, SDValue &A,
97 SDValue &B, SDValue &C) {
98 // Don't apply the profitability check
99 return SelectShifterOperandReg(N, A, B, C, false);
102 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
103 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
105 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
106 SDValue &Offset, SDValue &Opc);
107 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
109 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
112 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
114 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
117 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
119 SelectAddrMode2Worker(N, Base, Offset, Opc);
120 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
121 // This always matches one way or another.
125 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
126 SDValue &Offset, SDValue &Opc);
127 bool SelectAddrMode3(SDValue N, SDValue &Base,
128 SDValue &Offset, SDValue &Opc);
129 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
130 SDValue &Offset, SDValue &Opc);
131 bool SelectAddrMode5(SDValue N, SDValue &Base,
133 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
134 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
136 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
138 // Thumb Addressing Modes:
139 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
140 bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
142 bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
143 bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
144 bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
145 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
147 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
149 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
151 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
153 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
155 // Thumb 2 Addressing Modes:
156 bool SelectT2ShifterOperandReg(SDValue N,
157 SDValue &BaseReg, SDValue &Opc);
158 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
159 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
161 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
163 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
164 SDValue &OffReg, SDValue &ShImm);
166 inline bool is_so_imm(unsigned Imm) const {
167 return ARM_AM::getSOImmVal(Imm) != -1;
170 inline bool is_so_imm_not(unsigned Imm) const {
171 return ARM_AM::getSOImmVal(~Imm) != -1;
174 inline bool is_t2_so_imm(unsigned Imm) const {
175 return ARM_AM::getT2SOImmVal(Imm) != -1;
178 inline bool is_t2_so_imm_not(unsigned Imm) const {
179 return ARM_AM::getT2SOImmVal(~Imm) != -1;
182 inline bool Pred_so_imm(SDNode *inN) const {
183 ConstantSDNode *N = cast<ConstantSDNode>(inN);
184 return is_so_imm(N->getZExtValue());
187 inline bool Pred_t2_so_imm(SDNode *inN) const {
188 ConstantSDNode *N = cast<ConstantSDNode>(inN);
189 return is_t2_so_imm(N->getZExtValue());
192 // Include the pieces autogenerated from the target description.
193 #include "ARMGenDAGISel.inc"
196 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
198 SDNode *SelectARMIndexedLoad(SDNode *N);
199 SDNode *SelectT2IndexedLoad(SDNode *N);
201 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
202 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
203 /// loads of D registers and even subregs and odd subregs of Q registers.
204 /// For NumVecs <= 2, QOpcodes1 is not used.
205 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
207 unsigned *QOpcodes0, unsigned *QOpcodes1);
209 /// SelectVST - Select NEON store intrinsics. NumVecs should
210 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
211 /// stores of D registers and even subregs and odd subregs of Q registers.
212 /// For NumVecs <= 2, QOpcodes1 is not used.
213 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
215 unsigned *QOpcodes0, unsigned *QOpcodes1);
217 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
218 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
219 /// load/store of D registers and Q registers.
220 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
221 bool isUpdating, unsigned NumVecs,
222 unsigned *DOpcodes, unsigned *QOpcodes);
224 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
225 /// should be 2, 3 or 4. The opcode array specifies the instructions used
226 /// for loading D registers. (Q registers are not supported.)
227 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
230 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
231 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
232 /// generated to force the table registers to be consecutive.
233 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
235 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
236 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
238 /// SelectCMOVOp - Select CMOV instructions for ARM.
239 SDNode *SelectCMOVOp(SDNode *N);
240 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
241 ARMCC::CondCodes CCVal, SDValue CCR,
243 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
244 ARMCC::CondCodes CCVal, SDValue CCR,
246 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
247 ARMCC::CondCodes CCVal, SDValue CCR,
249 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
250 ARMCC::CondCodes CCVal, SDValue CCR,
253 SDNode *SelectConcatVector(SDNode *N);
255 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
256 /// inline asm expressions.
257 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
259 std::vector<SDValue> &OutOps);
261 // Form pairs of consecutive S, D, or Q registers.
262 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
263 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
264 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
266 // Form sequences of 4 consecutive S, D, or Q registers.
267 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
268 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
269 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
271 // Get the alignment operand for a NEON VLD or VST instruction.
272 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
276 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
277 /// operand. If so Imm will receive the 32-bit value.
278 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
279 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
280 Imm = cast<ConstantSDNode>(N)->getZExtValue();
286 // isInt32Immediate - This method tests to see if a constant operand.
287 // If so Imm will receive the 32 bit value.
288 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
289 return isInt32Immediate(N.getNode(), Imm);
292 // isOpcWithIntImmediate - This method tests to see if the node is a specific
293 // opcode and that it has a immediate integer right operand.
294 // If so Imm will receive the 32 bit value.
295 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
296 return N->getOpcode() == Opc &&
297 isInt32Immediate(N->getOperand(1).getNode(), Imm);
300 /// \brief Check whether a particular node is a constant value representable as
301 /// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
303 /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
304 static bool isScaledConstantInRange(SDValue Node, unsigned Scale,
305 int RangeMin, int RangeMax,
306 int &ScaledConstant) {
307 assert(Scale && "Invalid scale!");
309 // Check that this is a constant.
310 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
314 ScaledConstant = (int) C->getZExtValue();
315 if ((ScaledConstant % Scale) != 0)
318 ScaledConstant /= Scale;
319 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
322 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
323 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
324 /// least on current ARM implementations) which should be avoidded.
325 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
326 if (OptLevel == CodeGenOpt::None)
329 if (!CheckVMLxHazard)
332 if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
338 SDNode *Use = *N->use_begin();
339 if (Use->getOpcode() == ISD::CopyToReg)
341 if (Use->isMachineOpcode()) {
342 const TargetInstrDesc &TID = TII->get(Use->getMachineOpcode());
345 unsigned Opcode = TID.getOpcode();
346 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
348 // vmlx feeding into another vmlx. We actually want to unfold
349 // the use later in the MLxExpansion pass. e.g.
351 // vmla (stall 8 cycles)
356 // This adds up to about 18 - 19 cycles.
359 // vmul (stall 4 cycles)
360 // vadd adds up to about 14 cycles.
361 return TII->isFpMLxInstruction(Opcode);
367 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
368 ARM_AM::ShiftOpc ShOpcVal,
370 if (!Subtarget->isCortexA9())
372 if (Shift.hasOneUse())
375 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
378 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
382 bool CheckProfitability) {
383 if (DisableShifterOp)
386 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
388 // Don't match base register only case. That is matched to a separate
389 // lower complexity pattern with explicit register operand.
390 if (ShOpcVal == ARM_AM::no_shift) return false;
392 BaseReg = N.getOperand(0);
393 unsigned ShImmVal = 0;
394 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
395 ShReg = CurDAG->getRegister(0, MVT::i32);
396 ShImmVal = RHS->getZExtValue() & 31;
398 ShReg = N.getOperand(1);
399 if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
402 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
407 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
410 // Match simple R + imm12 operands.
413 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
414 !CurDAG->isBaseWithConstantOffset(N)) {
415 if (N.getOpcode() == ISD::FrameIndex) {
416 // Match frame index.
417 int FI = cast<FrameIndexSDNode>(N)->getIndex();
418 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
419 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
423 if (N.getOpcode() == ARMISD::Wrapper &&
424 !(Subtarget->useMovt() &&
425 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
426 Base = N.getOperand(0);
429 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
433 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
434 int RHSC = (int)RHS->getZExtValue();
435 if (N.getOpcode() == ISD::SUB)
438 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
439 Base = N.getOperand(0);
440 if (Base.getOpcode() == ISD::FrameIndex) {
441 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
442 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
444 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
451 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
457 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
459 if (N.getOpcode() == ISD::MUL &&
460 (!Subtarget->isCortexA9() || N.hasOneUse())) {
461 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
462 // X * [3,5,9] -> X + X * [2,4,8] etc.
463 int RHSC = (int)RHS->getZExtValue();
466 ARM_AM::AddrOpc AddSub = ARM_AM::add;
468 AddSub = ARM_AM::sub;
471 if (isPowerOf2_32(RHSC)) {
472 unsigned ShAmt = Log2_32(RHSC);
473 Base = Offset = N.getOperand(0);
474 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
483 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
484 // ISD::OR that is equivalent to an ISD::ADD.
485 !CurDAG->isBaseWithConstantOffset(N))
488 // Leave simple R +/- imm12 operands for LDRi12
489 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
491 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
492 -0x1000+1, 0x1000, RHSC)) // 12 bits.
496 if (Subtarget->isCortexA9() && !N.hasOneUse())
497 // Compute R +/- (R << N) and reuse it.
500 // Otherwise this is R +/- [possibly shifted] R.
501 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
502 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
505 Base = N.getOperand(0);
506 Offset = N.getOperand(1);
508 if (ShOpcVal != ARM_AM::no_shift) {
509 // Check to see if the RHS of the shift is a constant, if not, we can't fold
511 if (ConstantSDNode *Sh =
512 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
513 ShAmt = Sh->getZExtValue();
514 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
515 Offset = N.getOperand(1).getOperand(0);
518 ShOpcVal = ARM_AM::no_shift;
521 ShOpcVal = ARM_AM::no_shift;
525 // Try matching (R shl C) + (R).
526 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
527 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
528 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
529 if (ShOpcVal != ARM_AM::no_shift) {
530 // Check to see if the RHS of the shift is a constant, if not, we can't
532 if (ConstantSDNode *Sh =
533 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
534 ShAmt = Sh->getZExtValue();
535 if (!Subtarget->isCortexA9() ||
537 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
538 Offset = N.getOperand(0).getOperand(0);
539 Base = N.getOperand(1);
542 ShOpcVal = ARM_AM::no_shift;
545 ShOpcVal = ARM_AM::no_shift;
550 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
560 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
564 if (N.getOpcode() == ISD::MUL &&
565 (!Subtarget->isCortexA9() || N.hasOneUse())) {
566 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
567 // X * [3,5,9] -> X + X * [2,4,8] etc.
568 int RHSC = (int)RHS->getZExtValue();
571 ARM_AM::AddrOpc AddSub = ARM_AM::add;
573 AddSub = ARM_AM::sub;
576 if (isPowerOf2_32(RHSC)) {
577 unsigned ShAmt = Log2_32(RHSC);
578 Base = Offset = N.getOperand(0);
579 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
588 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
589 // ISD::OR that is equivalent to an ADD.
590 !CurDAG->isBaseWithConstantOffset(N)) {
592 if (N.getOpcode() == ISD::FrameIndex) {
593 int FI = cast<FrameIndexSDNode>(N)->getIndex();
594 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
595 } else if (N.getOpcode() == ARMISD::Wrapper &&
596 !(Subtarget->useMovt() &&
597 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
598 Base = N.getOperand(0);
600 Offset = CurDAG->getRegister(0, MVT::i32);
601 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
607 // Match simple R +/- imm12 operands.
608 if (N.getOpcode() != ISD::SUB) {
610 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
611 -0x1000+1, 0x1000, RHSC)) { // 12 bits.
612 Base = N.getOperand(0);
613 if (Base.getOpcode() == ISD::FrameIndex) {
614 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
615 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
617 Offset = CurDAG->getRegister(0, MVT::i32);
619 ARM_AM::AddrOpc AddSub = ARM_AM::add;
621 AddSub = ARM_AM::sub;
624 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
631 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
632 // Compute R +/- (R << N) and reuse it.
634 Offset = CurDAG->getRegister(0, MVT::i32);
635 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
641 // Otherwise this is R +/- [possibly shifted] R.
642 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
643 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
646 Base = N.getOperand(0);
647 Offset = N.getOperand(1);
649 if (ShOpcVal != ARM_AM::no_shift) {
650 // Check to see if the RHS of the shift is a constant, if not, we can't fold
652 if (ConstantSDNode *Sh =
653 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
654 ShAmt = Sh->getZExtValue();
655 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
656 Offset = N.getOperand(1).getOperand(0);
659 ShOpcVal = ARM_AM::no_shift;
662 ShOpcVal = ARM_AM::no_shift;
666 // Try matching (R shl C) + (R).
667 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
668 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
669 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
670 if (ShOpcVal != ARM_AM::no_shift) {
671 // Check to see if the RHS of the shift is a constant, if not, we can't
673 if (ConstantSDNode *Sh =
674 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
675 ShAmt = Sh->getZExtValue();
676 if (!Subtarget->isCortexA9() ||
678 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
679 Offset = N.getOperand(0).getOperand(0);
680 Base = N.getOperand(1);
683 ShOpcVal = ARM_AM::no_shift;
686 ShOpcVal = ARM_AM::no_shift;
691 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
696 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
697 SDValue &Offset, SDValue &Opc) {
698 unsigned Opcode = Op->getOpcode();
699 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
700 ? cast<LoadSDNode>(Op)->getAddressingMode()
701 : cast<StoreSDNode>(Op)->getAddressingMode();
702 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
703 ? ARM_AM::add : ARM_AM::sub;
705 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
706 Offset = CurDAG->getRegister(0, MVT::i32);
707 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
714 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
716 if (ShOpcVal != ARM_AM::no_shift) {
717 // Check to see if the RHS of the shift is a constant, if not, we can't fold
719 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
720 ShAmt = Sh->getZExtValue();
721 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
722 Offset = N.getOperand(0);
725 ShOpcVal = ARM_AM::no_shift;
728 ShOpcVal = ARM_AM::no_shift;
732 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
738 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
739 SDValue &Base, SDValue &Offset,
741 if (N.getOpcode() == ISD::SUB) {
742 // X - C is canonicalize to X + -C, no need to handle it here.
743 Base = N.getOperand(0);
744 Offset = N.getOperand(1);
745 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
749 if (!CurDAG->isBaseWithConstantOffset(N)) {
751 if (N.getOpcode() == ISD::FrameIndex) {
752 int FI = cast<FrameIndexSDNode>(N)->getIndex();
753 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
755 Offset = CurDAG->getRegister(0, MVT::i32);
756 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
760 // If the RHS is +/- imm8, fold into addr mode.
762 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
763 -256 + 1, 256, RHSC)) { // 8 bits.
764 Base = N.getOperand(0);
765 if (Base.getOpcode() == ISD::FrameIndex) {
766 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
767 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
769 Offset = CurDAG->getRegister(0, MVT::i32);
771 ARM_AM::AddrOpc AddSub = ARM_AM::add;
773 AddSub = ARM_AM::sub;
776 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
780 Base = N.getOperand(0);
781 Offset = N.getOperand(1);
782 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
786 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
787 SDValue &Offset, SDValue &Opc) {
788 unsigned Opcode = Op->getOpcode();
789 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
790 ? cast<LoadSDNode>(Op)->getAddressingMode()
791 : cast<StoreSDNode>(Op)->getAddressingMode();
792 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
793 ? ARM_AM::add : ARM_AM::sub;
795 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
796 Offset = CurDAG->getRegister(0, MVT::i32);
797 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
802 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
806 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
807 SDValue &Base, SDValue &Offset) {
808 if (!CurDAG->isBaseWithConstantOffset(N)) {
810 if (N.getOpcode() == ISD::FrameIndex) {
811 int FI = cast<FrameIndexSDNode>(N)->getIndex();
812 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
813 } else if (N.getOpcode() == ARMISD::Wrapper &&
814 !(Subtarget->useMovt() &&
815 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
816 Base = N.getOperand(0);
818 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
823 // If the RHS is +/- imm8, fold into addr mode.
825 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
826 -256 + 1, 256, RHSC)) {
827 Base = N.getOperand(0);
828 if (Base.getOpcode() == ISD::FrameIndex) {
829 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
830 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
833 ARM_AM::AddrOpc AddSub = ARM_AM::add;
835 AddSub = ARM_AM::sub;
838 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
844 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
849 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
853 unsigned Alignment = 0;
854 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
855 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
856 // The maximum alignment is equal to the memory size being referenced.
857 unsigned LSNAlign = LSN->getAlignment();
858 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
859 if (LSNAlign > MemSize && MemSize > 1)
862 // All other uses of addrmode6 are for intrinsics. For now just record
863 // the raw alignment value; it will be refined later based on the legal
864 // alignment operands for the intrinsic.
865 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
868 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
872 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
874 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
875 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
876 if (AM != ISD::POST_INC)
879 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
880 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
881 Offset = CurDAG->getRegister(0, MVT::i32);
886 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
887 SDValue &Offset, SDValue &Label) {
888 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
889 Offset = N.getOperand(0);
890 SDValue N1 = N.getOperand(1);
891 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
900 //===----------------------------------------------------------------------===//
901 // Thumb Addressing Modes
902 //===----------------------------------------------------------------------===//
904 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
905 SDValue &Base, SDValue &Offset){
906 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
907 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
908 if (!NC || !NC->isNullValue())
915 Base = N.getOperand(0);
916 Offset = N.getOperand(1);
921 ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
922 SDValue &Offset, unsigned Scale) {
924 SDValue TmpBase, TmpOffImm;
925 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
926 return false; // We want to select tLDRspi / tSTRspi instead.
928 if (N.getOpcode() == ARMISD::Wrapper &&
929 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
930 return false; // We want to select tLDRpci instead.
933 if (!CurDAG->isBaseWithConstantOffset(N))
936 // Thumb does not have [sp, r] address mode.
937 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
938 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
939 if ((LHSR && LHSR->getReg() == ARM::SP) ||
940 (RHSR && RHSR->getReg() == ARM::SP))
943 // FIXME: Why do we explicitly check for a match here and then return false?
944 // Presumably to allow something else to match, but shouldn't this be
947 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
950 Base = N.getOperand(0);
951 Offset = N.getOperand(1);
956 ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
959 return SelectThumbAddrModeRI(N, Base, Offset, 1);
963 ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
966 return SelectThumbAddrModeRI(N, Base, Offset, 2);
970 ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
973 return SelectThumbAddrModeRI(N, Base, Offset, 4);
977 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
978 SDValue &Base, SDValue &OffImm) {
980 SDValue TmpBase, TmpOffImm;
981 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
982 return false; // We want to select tLDRspi / tSTRspi instead.
984 if (N.getOpcode() == ARMISD::Wrapper &&
985 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
986 return false; // We want to select tLDRpci instead.
989 if (!CurDAG->isBaseWithConstantOffset(N)) {
990 if (N.getOpcode() == ARMISD::Wrapper &&
991 !(Subtarget->useMovt() &&
992 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
993 Base = N.getOperand(0);
998 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1002 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1003 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1004 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1005 (RHSR && RHSR->getReg() == ARM::SP)) {
1006 ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1007 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1008 unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1009 unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1011 // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1012 if (LHSC != 0 || RHSC != 0) return false;
1015 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1019 // If the RHS is + imm5 * scale, fold into addr mode.
1021 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1022 Base = N.getOperand(0);
1023 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1027 Base = N.getOperand(0);
1028 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1033 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1035 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1039 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1041 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1045 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1047 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1050 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1051 SDValue &Base, SDValue &OffImm) {
1052 if (N.getOpcode() == ISD::FrameIndex) {
1053 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1054 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1055 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1059 if (!CurDAG->isBaseWithConstantOffset(N))
1062 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1063 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1064 (LHSR && LHSR->getReg() == ARM::SP)) {
1065 // If the RHS is + imm8 * scale, fold into addr mode.
1067 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1068 Base = N.getOperand(0);
1069 if (Base.getOpcode() == ISD::FrameIndex) {
1070 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1071 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1073 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1082 //===----------------------------------------------------------------------===//
1083 // Thumb 2 Addressing Modes
1084 //===----------------------------------------------------------------------===//
1087 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1089 if (DisableShifterOp)
1092 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
1094 // Don't match base register only case. That is matched to a separate
1095 // lower complexity pattern with explicit register operand.
1096 if (ShOpcVal == ARM_AM::no_shift) return false;
1098 BaseReg = N.getOperand(0);
1099 unsigned ShImmVal = 0;
1100 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1101 ShImmVal = RHS->getZExtValue() & 31;
1102 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1109 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1110 SDValue &Base, SDValue &OffImm) {
1111 // Match simple R + imm12 operands.
1114 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1115 !CurDAG->isBaseWithConstantOffset(N)) {
1116 if (N.getOpcode() == ISD::FrameIndex) {
1117 // Match frame index.
1118 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1119 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1120 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1124 if (N.getOpcode() == ARMISD::Wrapper &&
1125 !(Subtarget->useMovt() &&
1126 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1127 Base = N.getOperand(0);
1128 if (Base.getOpcode() == ISD::TargetConstantPool)
1129 return false; // We want to select t2LDRpci instead.
1132 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1136 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1137 if (SelectT2AddrModeImm8(N, Base, OffImm))
1138 // Let t2LDRi8 handle (R - imm8).
1141 int RHSC = (int)RHS->getZExtValue();
1142 if (N.getOpcode() == ISD::SUB)
1145 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1146 Base = N.getOperand(0);
1147 if (Base.getOpcode() == ISD::FrameIndex) {
1148 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1149 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1151 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1158 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1162 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1163 SDValue &Base, SDValue &OffImm) {
1164 // Match simple R - imm8 operands.
1165 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1166 !CurDAG->isBaseWithConstantOffset(N))
1169 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1170 int RHSC = (int)RHS->getSExtValue();
1171 if (N.getOpcode() == ISD::SUB)
1174 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1175 Base = N.getOperand(0);
1176 if (Base.getOpcode() == ISD::FrameIndex) {
1177 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1178 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1180 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1188 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1190 unsigned Opcode = Op->getOpcode();
1191 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1192 ? cast<LoadSDNode>(Op)->getAddressingMode()
1193 : cast<StoreSDNode>(Op)->getAddressingMode();
1195 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1196 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1197 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1198 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1205 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1207 SDValue &OffReg, SDValue &ShImm) {
1208 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1209 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1212 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1213 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1214 int RHSC = (int)RHS->getZExtValue();
1215 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1217 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1221 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1222 // Compute R + (R << [1,2,3]) and reuse it.
1227 // Look for (R + R) or (R + (R << [1,2,3])).
1229 Base = N.getOperand(0);
1230 OffReg = N.getOperand(1);
1232 // Swap if it is ((R << c) + R).
1233 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
1234 if (ShOpcVal != ARM_AM::lsl) {
1235 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
1236 if (ShOpcVal == ARM_AM::lsl)
1237 std::swap(Base, OffReg);
1240 if (ShOpcVal == ARM_AM::lsl) {
1241 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1243 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1244 ShAmt = Sh->getZExtValue();
1245 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1246 OffReg = OffReg.getOperand(0);
1249 ShOpcVal = ARM_AM::no_shift;
1252 ShOpcVal = ARM_AM::no_shift;
1256 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1261 //===--------------------------------------------------------------------===//
1263 /// getAL - Returns a ARMCC::AL immediate node.
1264 static inline SDValue getAL(SelectionDAG *CurDAG) {
1265 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1268 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1269 LoadSDNode *LD = cast<LoadSDNode>(N);
1270 ISD::MemIndexedMode AM = LD->getAddressingMode();
1271 if (AM == ISD::UNINDEXED)
1274 EVT LoadedVT = LD->getMemoryVT();
1275 SDValue Offset, AMOpc;
1276 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1277 unsigned Opcode = 0;
1279 if (LoadedVT == MVT::i32 &&
1280 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1281 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
1283 } else if (LoadedVT == MVT::i16 &&
1284 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1286 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1287 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1288 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1289 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1290 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1291 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1293 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1296 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1298 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
1304 SDValue Chain = LD->getChain();
1305 SDValue Base = LD->getBasePtr();
1306 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1307 CurDAG->getRegister(0, MVT::i32), Chain };
1308 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1309 MVT::Other, Ops, 6);
1315 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1316 LoadSDNode *LD = cast<LoadSDNode>(N);
1317 ISD::MemIndexedMode AM = LD->getAddressingMode();
1318 if (AM == ISD::UNINDEXED)
1321 EVT LoadedVT = LD->getMemoryVT();
1322 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1324 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1325 unsigned Opcode = 0;
1327 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1328 switch (LoadedVT.getSimpleVT().SimpleTy) {
1330 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1334 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1336 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1341 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1343 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1352 SDValue Chain = LD->getChain();
1353 SDValue Base = LD->getBasePtr();
1354 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1355 CurDAG->getRegister(0, MVT::i32), Chain };
1356 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1357 MVT::Other, Ops, 5);
1363 /// PairSRegs - Form a D register from a pair of S registers.
1365 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1366 DebugLoc dl = V0.getNode()->getDebugLoc();
1367 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1368 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1369 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1370 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1373 /// PairDRegs - Form a quad register from a pair of D registers.
1375 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1376 DebugLoc dl = V0.getNode()->getDebugLoc();
1377 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1378 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1379 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1380 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1383 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1385 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1386 DebugLoc dl = V0.getNode()->getDebugLoc();
1387 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1388 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1389 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1390 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1393 /// QuadSRegs - Form 4 consecutive S registers.
1395 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1396 SDValue V2, SDValue V3) {
1397 DebugLoc dl = V0.getNode()->getDebugLoc();
1398 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1399 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1400 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1401 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1402 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1403 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1406 /// QuadDRegs - Form 4 consecutive D registers.
1408 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1409 SDValue V2, SDValue V3) {
1410 DebugLoc dl = V0.getNode()->getDebugLoc();
1411 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1412 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1413 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1414 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1415 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1416 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1419 /// QuadQRegs - Form 4 consecutive Q registers.
1421 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1422 SDValue V2, SDValue V3) {
1423 DebugLoc dl = V0.getNode()->getDebugLoc();
1424 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1425 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1426 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1427 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1428 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1429 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1432 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1433 /// of a NEON VLD or VST instruction. The supported values depend on the
1434 /// number of registers being loaded.
1435 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1436 bool is64BitVector) {
1437 unsigned NumRegs = NumVecs;
1438 if (!is64BitVector && NumVecs < 3)
1441 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1442 if (Alignment >= 32 && NumRegs == 4)
1444 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1446 else if (Alignment >= 8)
1451 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1454 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1455 unsigned *DOpcodes, unsigned *QOpcodes0,
1456 unsigned *QOpcodes1) {
1457 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1458 DebugLoc dl = N->getDebugLoc();
1460 SDValue MemAddr, Align;
1461 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1462 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1465 SDValue Chain = N->getOperand(0);
1466 EVT VT = N->getValueType(0);
1467 bool is64BitVector = VT.is64BitVector();
1468 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1470 unsigned OpcodeIndex;
1471 switch (VT.getSimpleVT().SimpleTy) {
1472 default: llvm_unreachable("unhandled vld type");
1473 // Double-register operations:
1474 case MVT::v8i8: OpcodeIndex = 0; break;
1475 case MVT::v4i16: OpcodeIndex = 1; break;
1477 case MVT::v2i32: OpcodeIndex = 2; break;
1478 case MVT::v1i64: OpcodeIndex = 3; break;
1479 // Quad-register operations:
1480 case MVT::v16i8: OpcodeIndex = 0; break;
1481 case MVT::v8i16: OpcodeIndex = 1; break;
1483 case MVT::v4i32: OpcodeIndex = 2; break;
1484 case MVT::v2i64: OpcodeIndex = 3;
1485 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1493 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1496 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1498 std::vector<EVT> ResTys;
1499 ResTys.push_back(ResTy);
1501 ResTys.push_back(MVT::i32);
1502 ResTys.push_back(MVT::Other);
1504 SDValue Pred = getAL(CurDAG);
1505 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1507 SmallVector<SDValue, 7> Ops;
1509 // Double registers and VLD1/VLD2 quad registers are directly supported.
1510 if (is64BitVector || NumVecs <= 2) {
1511 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1512 QOpcodes0[OpcodeIndex]);
1513 Ops.push_back(MemAddr);
1514 Ops.push_back(Align);
1516 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1517 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1519 Ops.push_back(Pred);
1520 Ops.push_back(Reg0);
1521 Ops.push_back(Chain);
1522 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1525 // Otherwise, quad registers are loaded with two separate instructions,
1526 // where one loads the even registers and the other loads the odd registers.
1527 EVT AddrTy = MemAddr.getValueType();
1529 // Load the even subregs. This is always an updating load, so that it
1530 // provides the address to the second load for the odd subregs.
1532 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1533 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1534 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1535 ResTy, AddrTy, MVT::Other, OpsA, 7);
1536 Chain = SDValue(VLdA, 2);
1538 // Load the odd subregs.
1539 Ops.push_back(SDValue(VLdA, 1));
1540 Ops.push_back(Align);
1542 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1543 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1544 "only constant post-increment update allowed for VLD3/4");
1546 Ops.push_back(Reg0);
1548 Ops.push_back(SDValue(VLdA, 0));
1549 Ops.push_back(Pred);
1550 Ops.push_back(Reg0);
1551 Ops.push_back(Chain);
1552 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1553 Ops.data(), Ops.size());
1559 // Extract out the subregisters.
1560 SDValue SuperReg = SDValue(VLd, 0);
1561 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1562 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1563 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1564 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1565 ReplaceUses(SDValue(N, Vec),
1566 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1567 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1569 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1573 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1574 unsigned *DOpcodes, unsigned *QOpcodes0,
1575 unsigned *QOpcodes1) {
1576 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1577 DebugLoc dl = N->getDebugLoc();
1579 SDValue MemAddr, Align;
1580 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1581 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1582 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1585 SDValue Chain = N->getOperand(0);
1586 EVT VT = N->getOperand(Vec0Idx).getValueType();
1587 bool is64BitVector = VT.is64BitVector();
1588 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1590 unsigned OpcodeIndex;
1591 switch (VT.getSimpleVT().SimpleTy) {
1592 default: llvm_unreachable("unhandled vst type");
1593 // Double-register operations:
1594 case MVT::v8i8: OpcodeIndex = 0; break;
1595 case MVT::v4i16: OpcodeIndex = 1; break;
1597 case MVT::v2i32: OpcodeIndex = 2; break;
1598 case MVT::v1i64: OpcodeIndex = 3; break;
1599 // Quad-register operations:
1600 case MVT::v16i8: OpcodeIndex = 0; break;
1601 case MVT::v8i16: OpcodeIndex = 1; break;
1603 case MVT::v4i32: OpcodeIndex = 2; break;
1604 case MVT::v2i64: OpcodeIndex = 3;
1605 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1609 std::vector<EVT> ResTys;
1611 ResTys.push_back(MVT::i32);
1612 ResTys.push_back(MVT::Other);
1614 SDValue Pred = getAL(CurDAG);
1615 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1616 SmallVector<SDValue, 7> Ops;
1618 // Double registers and VST1/VST2 quad registers are directly supported.
1619 if (is64BitVector || NumVecs <= 2) {
1622 SrcReg = N->getOperand(Vec0Idx);
1623 } else if (is64BitVector) {
1624 // Form a REG_SEQUENCE to force register allocation.
1625 SDValue V0 = N->getOperand(Vec0Idx + 0);
1626 SDValue V1 = N->getOperand(Vec0Idx + 1);
1628 SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1630 SDValue V2 = N->getOperand(Vec0Idx + 2);
1631 // If it's a vst3, form a quad D-register and leave the last part as
1633 SDValue V3 = (NumVecs == 3)
1634 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1635 : N->getOperand(Vec0Idx + 3);
1636 SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1639 // Form a QQ register.
1640 SDValue Q0 = N->getOperand(Vec0Idx);
1641 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1642 SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1645 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1646 QOpcodes0[OpcodeIndex]);
1647 Ops.push_back(MemAddr);
1648 Ops.push_back(Align);
1650 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1651 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1653 Ops.push_back(SrcReg);
1654 Ops.push_back(Pred);
1655 Ops.push_back(Reg0);
1656 Ops.push_back(Chain);
1657 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1660 // Otherwise, quad registers are stored with two separate instructions,
1661 // where one stores the even registers and the other stores the odd registers.
1663 // Form the QQQQ REG_SEQUENCE.
1664 SDValue V0 = N->getOperand(Vec0Idx + 0);
1665 SDValue V1 = N->getOperand(Vec0Idx + 1);
1666 SDValue V2 = N->getOperand(Vec0Idx + 2);
1667 SDValue V3 = (NumVecs == 3)
1668 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1669 : N->getOperand(Vec0Idx + 3);
1670 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1672 // Store the even D registers. This is always an updating store, so that it
1673 // provides the address to the second store for the odd subregs.
1674 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1675 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1676 MemAddr.getValueType(),
1677 MVT::Other, OpsA, 7);
1678 Chain = SDValue(VStA, 1);
1680 // Store the odd D registers.
1681 Ops.push_back(SDValue(VStA, 0));
1682 Ops.push_back(Align);
1684 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1685 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1686 "only constant post-increment update allowed for VST3/4");
1688 Ops.push_back(Reg0);
1690 Ops.push_back(RegSeq);
1691 Ops.push_back(Pred);
1692 Ops.push_back(Reg0);
1693 Ops.push_back(Chain);
1694 return CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1695 Ops.data(), Ops.size());
1698 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1699 bool isUpdating, unsigned NumVecs,
1701 unsigned *QOpcodes) {
1702 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1703 DebugLoc dl = N->getDebugLoc();
1705 SDValue MemAddr, Align;
1706 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1707 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1708 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1711 SDValue Chain = N->getOperand(0);
1713 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1714 EVT VT = N->getOperand(Vec0Idx).getValueType();
1715 bool is64BitVector = VT.is64BitVector();
1717 unsigned Alignment = 0;
1719 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1720 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1721 if (Alignment > NumBytes)
1722 Alignment = NumBytes;
1723 if (Alignment < 8 && Alignment < NumBytes)
1725 // Alignment must be a power of two; make sure of that.
1726 Alignment = (Alignment & -Alignment);
1730 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1732 unsigned OpcodeIndex;
1733 switch (VT.getSimpleVT().SimpleTy) {
1734 default: llvm_unreachable("unhandled vld/vst lane type");
1735 // Double-register operations:
1736 case MVT::v8i8: OpcodeIndex = 0; break;
1737 case MVT::v4i16: OpcodeIndex = 1; break;
1739 case MVT::v2i32: OpcodeIndex = 2; break;
1740 // Quad-register operations:
1741 case MVT::v8i16: OpcodeIndex = 0; break;
1743 case MVT::v4i32: OpcodeIndex = 1; break;
1746 std::vector<EVT> ResTys;
1748 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1751 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1752 MVT::i64, ResTyElts));
1755 ResTys.push_back(MVT::i32);
1756 ResTys.push_back(MVT::Other);
1758 SDValue Pred = getAL(CurDAG);
1759 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1761 SmallVector<SDValue, 8> Ops;
1762 Ops.push_back(MemAddr);
1763 Ops.push_back(Align);
1765 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1766 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1770 SDValue V0 = N->getOperand(Vec0Idx + 0);
1771 SDValue V1 = N->getOperand(Vec0Idx + 1);
1774 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1776 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1778 SDValue V2 = N->getOperand(Vec0Idx + 2);
1779 SDValue V3 = (NumVecs == 3)
1780 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1781 : N->getOperand(Vec0Idx + 3);
1783 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1785 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1787 Ops.push_back(SuperReg);
1788 Ops.push_back(getI32Imm(Lane));
1789 Ops.push_back(Pred);
1790 Ops.push_back(Reg0);
1791 Ops.push_back(Chain);
1793 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1794 QOpcodes[OpcodeIndex]);
1795 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1796 Ops.data(), Ops.size());
1800 // Extract the subregisters.
1801 SuperReg = SDValue(VLdLn, 0);
1802 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1803 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1804 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1805 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1806 ReplaceUses(SDValue(N, Vec),
1807 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1808 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1810 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1814 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
1815 unsigned NumVecs, unsigned *Opcodes) {
1816 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1817 DebugLoc dl = N->getDebugLoc();
1819 SDValue MemAddr, Align;
1820 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
1823 SDValue Chain = N->getOperand(0);
1824 EVT VT = N->getValueType(0);
1826 unsigned Alignment = 0;
1828 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1829 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1830 if (Alignment > NumBytes)
1831 Alignment = NumBytes;
1832 if (Alignment < 8 && Alignment < NumBytes)
1834 // Alignment must be a power of two; make sure of that.
1835 Alignment = (Alignment & -Alignment);
1839 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1841 unsigned OpcodeIndex;
1842 switch (VT.getSimpleVT().SimpleTy) {
1843 default: llvm_unreachable("unhandled vld-dup type");
1844 case MVT::v8i8: OpcodeIndex = 0; break;
1845 case MVT::v4i16: OpcodeIndex = 1; break;
1847 case MVT::v2i32: OpcodeIndex = 2; break;
1850 SDValue Pred = getAL(CurDAG);
1851 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1853 unsigned Opc = Opcodes[OpcodeIndex];
1854 SmallVector<SDValue, 6> Ops;
1855 Ops.push_back(MemAddr);
1856 Ops.push_back(Align);
1858 SDValue Inc = N->getOperand(2);
1859 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1861 Ops.push_back(Pred);
1862 Ops.push_back(Reg0);
1863 Ops.push_back(Chain);
1865 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1866 std::vector<EVT> ResTys;
1867 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts));
1869 ResTys.push_back(MVT::i32);
1870 ResTys.push_back(MVT::Other);
1872 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1873 SuperReg = SDValue(VLdDup, 0);
1875 // Extract the subregisters.
1876 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1877 unsigned SubIdx = ARM::dsub_0;
1878 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1879 ReplaceUses(SDValue(N, Vec),
1880 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1881 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
1883 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
1887 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1889 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1890 DebugLoc dl = N->getDebugLoc();
1891 EVT VT = N->getValueType(0);
1892 unsigned FirstTblReg = IsExt ? 2 : 1;
1894 // Form a REG_SEQUENCE to force register allocation.
1896 SDValue V0 = N->getOperand(FirstTblReg + 0);
1897 SDValue V1 = N->getOperand(FirstTblReg + 1);
1899 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1901 SDValue V2 = N->getOperand(FirstTblReg + 2);
1902 // If it's a vtbl3, form a quad D-register and leave the last part as
1904 SDValue V3 = (NumVecs == 3)
1905 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1906 : N->getOperand(FirstTblReg + 3);
1907 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1910 SmallVector<SDValue, 6> Ops;
1912 Ops.push_back(N->getOperand(1));
1913 Ops.push_back(RegSeq);
1914 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1915 Ops.push_back(getAL(CurDAG)); // predicate
1916 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1917 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1920 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1922 if (!Subtarget->hasV6T2Ops())
1925 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1926 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1929 // For unsigned extracts, check for a shift right and mask
1930 unsigned And_imm = 0;
1931 if (N->getOpcode() == ISD::AND) {
1932 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1934 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1935 if (And_imm & (And_imm + 1))
1938 unsigned Srl_imm = 0;
1939 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1941 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1943 unsigned Width = CountTrailingOnes_32(And_imm);
1944 unsigned LSB = Srl_imm;
1945 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1946 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1947 CurDAG->getTargetConstant(LSB, MVT::i32),
1948 CurDAG->getTargetConstant(Width, MVT::i32),
1949 getAL(CurDAG), Reg0 };
1950 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1956 // Otherwise, we're looking for a shift of a shift
1957 unsigned Shl_imm = 0;
1958 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1959 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1960 unsigned Srl_imm = 0;
1961 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1962 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1963 unsigned Width = 32 - Srl_imm;
1964 int LSB = Srl_imm - Shl_imm;
1967 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1968 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1969 CurDAG->getTargetConstant(LSB, MVT::i32),
1970 CurDAG->getTargetConstant(Width, MVT::i32),
1971 getAL(CurDAG), Reg0 };
1972 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1978 SDNode *ARMDAGToDAGISel::
1979 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1980 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1983 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
1984 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1985 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1988 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1989 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1990 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1991 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1993 llvm_unreachable("Unknown so_reg opcode!");
1997 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1998 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1999 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2000 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2005 SDNode *ARMDAGToDAGISel::
2006 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2007 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2011 if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2012 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2013 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2014 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
2019 SDNode *ARMDAGToDAGISel::
2020 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2021 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2022 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2027 unsigned TrueImm = T->getZExtValue();
2028 if (is_t2_so_imm(TrueImm)) {
2029 Opc = ARM::t2MOVCCi;
2030 } else if (TrueImm <= 0xffff) {
2031 Opc = ARM::t2MOVCCi16;
2032 } else if (is_t2_so_imm_not(TrueImm)) {
2034 Opc = ARM::t2MVNCCi;
2035 } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2037 Opc = ARM::t2MOVCCi32imm;
2041 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2042 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2043 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2044 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2050 SDNode *ARMDAGToDAGISel::
2051 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2052 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2053 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2058 unsigned TrueImm = T->getZExtValue();
2059 bool isSoImm = is_so_imm(TrueImm);
2062 } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2063 Opc = ARM::MOVCCi16;
2064 } else if (is_so_imm_not(TrueImm)) {
2067 } else if (TrueVal.getNode()->hasOneUse() &&
2068 (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2070 Opc = ARM::MOVCCi32imm;
2074 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2075 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2076 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2077 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2083 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2084 EVT VT = N->getValueType(0);
2085 SDValue FalseVal = N->getOperand(0);
2086 SDValue TrueVal = N->getOperand(1);
2087 SDValue CC = N->getOperand(2);
2088 SDValue CCR = N->getOperand(3);
2089 SDValue InFlag = N->getOperand(4);
2090 assert(CC.getOpcode() == ISD::Constant);
2091 assert(CCR.getOpcode() == ISD::Register);
2092 ARMCC::CondCodes CCVal =
2093 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2095 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2096 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2097 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2098 // Pattern complexity = 18 cost = 1 size = 0
2102 if (Subtarget->isThumb()) {
2103 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2104 CCVal, CCR, InFlag);
2106 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2107 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2111 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2112 CCVal, CCR, InFlag);
2114 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2115 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2120 // Pattern: (ARMcmov:i32 GPR:i32:$false,
2121 // (imm:i32)<<P:Pred_so_imm>>:$true,
2123 // Emits: (MOVCCi:i32 GPR:i32:$false,
2124 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2125 // Pattern complexity = 10 cost = 1 size = 0
2126 if (Subtarget->isThumb()) {
2127 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2128 CCVal, CCR, InFlag);
2130 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2131 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2135 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2136 CCVal, CCR, InFlag);
2138 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2139 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2145 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2146 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2147 // Pattern complexity = 6 cost = 1 size = 0
2149 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2150 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2151 // Pattern complexity = 6 cost = 11 size = 0
2153 // Also VMOVScc and VMOVDcc.
2154 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2155 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2157 switch (VT.getSimpleVT().SimpleTy) {
2158 default: assert(false && "Illegal conditional move type!");
2161 Opc = Subtarget->isThumb()
2162 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2172 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2175 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2176 // The only time a CONCAT_VECTORS operation can have legal types is when
2177 // two 64-bit vectors are concatenated to a 128-bit vector.
2178 EVT VT = N->getValueType(0);
2179 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2180 llvm_unreachable("unexpected CONCAT_VECTORS");
2181 return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2184 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2185 DebugLoc dl = N->getDebugLoc();
2187 if (N->isMachineOpcode())
2188 return NULL; // Already selected.
2190 switch (N->getOpcode()) {
2192 case ISD::Constant: {
2193 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2195 if (Subtarget->hasThumb2())
2196 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2197 // be done with MOV + MOVT, at worst.
2200 if (Subtarget->isThumb()) {
2201 UseCP = (Val > 255 && // MOV
2202 ~Val > 255 && // MOV + MVN
2203 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
2205 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2206 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2207 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
2212 CurDAG->getTargetConstantPool(ConstantInt::get(
2213 Type::getInt32Ty(*CurDAG->getContext()), Val),
2214 TLI.getPointerTy());
2217 if (Subtarget->isThumb1Only()) {
2218 SDValue Pred = getAL(CurDAG);
2219 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2220 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2221 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2226 CurDAG->getTargetConstant(0, MVT::i32),
2228 CurDAG->getRegister(0, MVT::i32),
2229 CurDAG->getEntryNode()
2231 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2234 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2238 // Other cases are autogenerated.
2241 case ISD::FrameIndex: {
2242 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2243 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2244 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2245 if (Subtarget->isThumb1Only()) {
2246 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
2247 CurDAG->getTargetConstant(0, MVT::i32));
2249 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2250 ARM::t2ADDri : ARM::ADDri);
2251 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2252 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2253 CurDAG->getRegister(0, MVT::i32) };
2254 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2258 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2262 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2266 if (Subtarget->isThumb1Only())
2268 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2269 unsigned RHSV = C->getZExtValue();
2271 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2272 unsigned ShImm = Log2_32(RHSV-1);
2275 SDValue V = N->getOperand(0);
2276 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2277 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2278 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2279 if (Subtarget->isThumb()) {
2280 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2281 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2283 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2284 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
2287 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2288 unsigned ShImm = Log2_32(RHSV+1);
2291 SDValue V = N->getOperand(0);
2292 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2293 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2294 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2295 if (Subtarget->isThumb()) {
2296 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2297 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2299 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2300 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
2306 // Check for unsigned bitfield extract
2307 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2310 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2311 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2312 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2313 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2314 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2315 EVT VT = N->getValueType(0);
2318 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2320 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2323 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2324 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2327 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2328 SDValue N2 = N0.getOperand(1);
2329 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2332 unsigned N1CVal = N1C->getZExtValue();
2333 unsigned N2CVal = N2C->getZExtValue();
2334 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2335 (N1CVal & 0xffffU) == 0xffffU &&
2336 (N2CVal & 0xffffU) == 0x0U) {
2337 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2339 SDValue Ops[] = { N0.getOperand(0), Imm16,
2340 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2341 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2346 case ARMISD::VMOVRRD:
2347 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2348 N->getOperand(0), getAL(CurDAG),
2349 CurDAG->getRegister(0, MVT::i32));
2350 case ISD::UMUL_LOHI: {
2351 if (Subtarget->isThumb1Only())
2353 if (Subtarget->isThumb()) {
2354 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2355 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2356 CurDAG->getRegister(0, MVT::i32) };
2357 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2359 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2360 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2361 CurDAG->getRegister(0, MVT::i32) };
2362 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2363 ARM::UMULL : ARM::UMULLv5,
2364 dl, MVT::i32, MVT::i32, Ops, 5);
2367 case ISD::SMUL_LOHI: {
2368 if (Subtarget->isThumb1Only())
2370 if (Subtarget->isThumb()) {
2371 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2372 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2373 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2375 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2376 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2377 CurDAG->getRegister(0, MVT::i32) };
2378 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2379 ARM::SMULL : ARM::SMULLv5,
2380 dl, MVT::i32, MVT::i32, Ops, 5);
2384 SDNode *ResNode = 0;
2385 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2386 ResNode = SelectT2IndexedLoad(N);
2388 ResNode = SelectARMIndexedLoad(N);
2391 // Other cases are autogenerated.
2394 case ARMISD::BRCOND: {
2395 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2396 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2397 // Pattern complexity = 6 cost = 1 size = 0
2399 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2400 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2401 // Pattern complexity = 6 cost = 1 size = 0
2403 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2404 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2405 // Pattern complexity = 6 cost = 1 size = 0
2407 unsigned Opc = Subtarget->isThumb() ?
2408 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2409 SDValue Chain = N->getOperand(0);
2410 SDValue N1 = N->getOperand(1);
2411 SDValue N2 = N->getOperand(2);
2412 SDValue N3 = N->getOperand(3);
2413 SDValue InFlag = N->getOperand(4);
2414 assert(N1.getOpcode() == ISD::BasicBlock);
2415 assert(N2.getOpcode() == ISD::Constant);
2416 assert(N3.getOpcode() == ISD::Register);
2418 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2419 cast<ConstantSDNode>(N2)->getZExtValue()),
2421 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2422 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2424 Chain = SDValue(ResNode, 0);
2425 if (N->getNumValues() == 2) {
2426 InFlag = SDValue(ResNode, 1);
2427 ReplaceUses(SDValue(N, 1), InFlag);
2429 ReplaceUses(SDValue(N, 0),
2430 SDValue(Chain.getNode(), Chain.getResNo()));
2434 return SelectCMOVOp(N);
2435 case ARMISD::VZIP: {
2437 EVT VT = N->getValueType(0);
2438 switch (VT.getSimpleVT().SimpleTy) {
2439 default: return NULL;
2440 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2441 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2443 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2444 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2445 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2447 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2449 SDValue Pred = getAL(CurDAG);
2450 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2451 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2452 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2454 case ARMISD::VUZP: {
2456 EVT VT = N->getValueType(0);
2457 switch (VT.getSimpleVT().SimpleTy) {
2458 default: return NULL;
2459 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2460 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2462 case MVT::v2i32: Opc = ARM::VUZPd32; break;
2463 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2464 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2466 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2468 SDValue Pred = getAL(CurDAG);
2469 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2470 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2471 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2473 case ARMISD::VTRN: {
2475 EVT VT = N->getValueType(0);
2476 switch (VT.getSimpleVT().SimpleTy) {
2477 default: return NULL;
2478 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2479 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2481 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2482 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2483 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2485 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2487 SDValue Pred = getAL(CurDAG);
2488 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2489 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2490 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2492 case ARMISD::BUILD_VECTOR: {
2493 EVT VecVT = N->getValueType(0);
2494 EVT EltVT = VecVT.getVectorElementType();
2495 unsigned NumElts = VecVT.getVectorNumElements();
2496 if (EltVT == MVT::f64) {
2497 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2498 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2500 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2502 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2503 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2504 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2505 N->getOperand(2), N->getOperand(3));
2508 case ARMISD::VLD2DUP: {
2509 unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2510 ARM::VLD2DUPd32Pseudo };
2511 return SelectVLDDup(N, false, 2, Opcodes);
2514 case ARMISD::VLD3DUP: {
2515 unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2516 ARM::VLD3DUPd32Pseudo };
2517 return SelectVLDDup(N, false, 3, Opcodes);
2520 case ARMISD::VLD4DUP: {
2521 unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2522 ARM::VLD4DUPd32Pseudo };
2523 return SelectVLDDup(N, false, 4, Opcodes);
2526 case ARMISD::VLD2DUP_UPD: {
2527 unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd16Pseudo_UPD,
2528 ARM::VLD2DUPd32Pseudo_UPD };
2529 return SelectVLDDup(N, true, 2, Opcodes);
2532 case ARMISD::VLD3DUP_UPD: {
2533 unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd16Pseudo_UPD,
2534 ARM::VLD3DUPd32Pseudo_UPD };
2535 return SelectVLDDup(N, true, 3, Opcodes);
2538 case ARMISD::VLD4DUP_UPD: {
2539 unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd16Pseudo_UPD,
2540 ARM::VLD4DUPd32Pseudo_UPD };
2541 return SelectVLDDup(N, true, 4, Opcodes);
2544 case ARMISD::VLD1_UPD: {
2545 unsigned DOpcodes[] = { ARM::VLD1d8_UPD, ARM::VLD1d16_UPD,
2546 ARM::VLD1d32_UPD, ARM::VLD1d64_UPD };
2547 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q16Pseudo_UPD,
2548 ARM::VLD1q32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2549 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2552 case ARMISD::VLD2_UPD: {
2553 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d16Pseudo_UPD,
2554 ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2555 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q16Pseudo_UPD,
2556 ARM::VLD2q32Pseudo_UPD };
2557 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2560 case ARMISD::VLD3_UPD: {
2561 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2562 ARM::VLD3d32Pseudo_UPD, ARM::VLD1d64TPseudo_UPD };
2563 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2564 ARM::VLD3q16Pseudo_UPD,
2565 ARM::VLD3q32Pseudo_UPD };
2566 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2567 ARM::VLD3q16oddPseudo_UPD,
2568 ARM::VLD3q32oddPseudo_UPD };
2569 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2572 case ARMISD::VLD4_UPD: {
2573 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2574 ARM::VLD4d32Pseudo_UPD, ARM::VLD1d64QPseudo_UPD };
2575 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2576 ARM::VLD4q16Pseudo_UPD,
2577 ARM::VLD4q32Pseudo_UPD };
2578 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2579 ARM::VLD4q16oddPseudo_UPD,
2580 ARM::VLD4q32oddPseudo_UPD };
2581 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2584 case ARMISD::VLD2LN_UPD: {
2585 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd16Pseudo_UPD,
2586 ARM::VLD2LNd32Pseudo_UPD };
2587 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2588 ARM::VLD2LNq32Pseudo_UPD };
2589 return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2592 case ARMISD::VLD3LN_UPD: {
2593 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd16Pseudo_UPD,
2594 ARM::VLD3LNd32Pseudo_UPD };
2595 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2596 ARM::VLD3LNq32Pseudo_UPD };
2597 return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2600 case ARMISD::VLD4LN_UPD: {
2601 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd16Pseudo_UPD,
2602 ARM::VLD4LNd32Pseudo_UPD };
2603 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2604 ARM::VLD4LNq32Pseudo_UPD };
2605 return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2608 case ARMISD::VST1_UPD: {
2609 unsigned DOpcodes[] = { ARM::VST1d8_UPD, ARM::VST1d16_UPD,
2610 ARM::VST1d32_UPD, ARM::VST1d64_UPD };
2611 unsigned QOpcodes[] = { ARM::VST1q8Pseudo_UPD, ARM::VST1q16Pseudo_UPD,
2612 ARM::VST1q32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2613 return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2616 case ARMISD::VST2_UPD: {
2617 unsigned DOpcodes[] = { ARM::VST2d8Pseudo_UPD, ARM::VST2d16Pseudo_UPD,
2618 ARM::VST2d32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2619 unsigned QOpcodes[] = { ARM::VST2q8Pseudo_UPD, ARM::VST2q16Pseudo_UPD,
2620 ARM::VST2q32Pseudo_UPD };
2621 return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2624 case ARMISD::VST3_UPD: {
2625 unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
2626 ARM::VST3d32Pseudo_UPD, ARM::VST1d64TPseudo_UPD };
2627 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2628 ARM::VST3q16Pseudo_UPD,
2629 ARM::VST3q32Pseudo_UPD };
2630 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2631 ARM::VST3q16oddPseudo_UPD,
2632 ARM::VST3q32oddPseudo_UPD };
2633 return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2636 case ARMISD::VST4_UPD: {
2637 unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
2638 ARM::VST4d32Pseudo_UPD, ARM::VST1d64QPseudo_UPD };
2639 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2640 ARM::VST4q16Pseudo_UPD,
2641 ARM::VST4q32Pseudo_UPD };
2642 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2643 ARM::VST4q16oddPseudo_UPD,
2644 ARM::VST4q32oddPseudo_UPD };
2645 return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2648 case ARMISD::VST2LN_UPD: {
2649 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd16Pseudo_UPD,
2650 ARM::VST2LNd32Pseudo_UPD };
2651 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2652 ARM::VST2LNq32Pseudo_UPD };
2653 return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2656 case ARMISD::VST3LN_UPD: {
2657 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd16Pseudo_UPD,
2658 ARM::VST3LNd32Pseudo_UPD };
2659 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2660 ARM::VST3LNq32Pseudo_UPD };
2661 return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2664 case ARMISD::VST4LN_UPD: {
2665 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd16Pseudo_UPD,
2666 ARM::VST4LNd32Pseudo_UPD };
2667 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2668 ARM::VST4LNq32Pseudo_UPD };
2669 return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2672 case ISD::INTRINSIC_VOID:
2673 case ISD::INTRINSIC_W_CHAIN: {
2674 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2679 case Intrinsic::arm_neon_vld1: {
2680 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2681 ARM::VLD1d32, ARM::VLD1d64 };
2682 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2683 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2684 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
2687 case Intrinsic::arm_neon_vld2: {
2688 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2689 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2690 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2691 ARM::VLD2q32Pseudo };
2692 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
2695 case Intrinsic::arm_neon_vld3: {
2696 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2697 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2698 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2699 ARM::VLD3q16Pseudo_UPD,
2700 ARM::VLD3q32Pseudo_UPD };
2701 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo,
2702 ARM::VLD3q16oddPseudo,
2703 ARM::VLD3q32oddPseudo };
2704 return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2707 case Intrinsic::arm_neon_vld4: {
2708 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2709 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2710 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2711 ARM::VLD4q16Pseudo_UPD,
2712 ARM::VLD4q32Pseudo_UPD };
2713 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo,
2714 ARM::VLD4q16oddPseudo,
2715 ARM::VLD4q32oddPseudo };
2716 return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2719 case Intrinsic::arm_neon_vld2lane: {
2720 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2721 ARM::VLD2LNd32Pseudo };
2722 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2723 return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
2726 case Intrinsic::arm_neon_vld3lane: {
2727 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2728 ARM::VLD3LNd32Pseudo };
2729 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2730 return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
2733 case Intrinsic::arm_neon_vld4lane: {
2734 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2735 ARM::VLD4LNd32Pseudo };
2736 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2737 return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
2740 case Intrinsic::arm_neon_vst1: {
2741 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2742 ARM::VST1d32, ARM::VST1d64 };
2743 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2744 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2745 return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
2748 case Intrinsic::arm_neon_vst2: {
2749 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
2750 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
2751 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
2752 ARM::VST2q32Pseudo };
2753 return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
2756 case Intrinsic::arm_neon_vst3: {
2757 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
2758 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
2759 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2760 ARM::VST3q16Pseudo_UPD,
2761 ARM::VST3q32Pseudo_UPD };
2762 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo,
2763 ARM::VST3q16oddPseudo,
2764 ARM::VST3q32oddPseudo };
2765 return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2768 case Intrinsic::arm_neon_vst4: {
2769 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
2770 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
2771 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2772 ARM::VST4q16Pseudo_UPD,
2773 ARM::VST4q32Pseudo_UPD };
2774 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo,
2775 ARM::VST4q16oddPseudo,
2776 ARM::VST4q32oddPseudo };
2777 return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2780 case Intrinsic::arm_neon_vst2lane: {
2781 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
2782 ARM::VST2LNd32Pseudo };
2783 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
2784 return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
2787 case Intrinsic::arm_neon_vst3lane: {
2788 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
2789 ARM::VST3LNd32Pseudo };
2790 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
2791 return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
2794 case Intrinsic::arm_neon_vst4lane: {
2795 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
2796 ARM::VST4LNd32Pseudo };
2797 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
2798 return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
2804 case ISD::INTRINSIC_WO_CHAIN: {
2805 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2810 case Intrinsic::arm_neon_vtbl2:
2811 return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
2812 case Intrinsic::arm_neon_vtbl3:
2813 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
2814 case Intrinsic::arm_neon_vtbl4:
2815 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
2817 case Intrinsic::arm_neon_vtbx2:
2818 return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
2819 case Intrinsic::arm_neon_vtbx3:
2820 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
2821 case Intrinsic::arm_neon_vtbx4:
2822 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
2827 case ARMISD::VTBL1: {
2828 DebugLoc dl = N->getDebugLoc();
2829 EVT VT = N->getValueType(0);
2830 SmallVector<SDValue, 6> Ops;
2832 Ops.push_back(N->getOperand(0));
2833 Ops.push_back(N->getOperand(1));
2834 Ops.push_back(getAL(CurDAG)); // Predicate
2835 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
2836 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
2838 case ARMISD::VTBL2: {
2839 DebugLoc dl = N->getDebugLoc();
2840 EVT VT = N->getValueType(0);
2842 // Form a REG_SEQUENCE to force register allocation.
2843 SDValue V0 = N->getOperand(0);
2844 SDValue V1 = N->getOperand(1);
2845 SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2847 SmallVector<SDValue, 6> Ops;
2848 Ops.push_back(RegSeq);
2849 Ops.push_back(N->getOperand(2));
2850 Ops.push_back(getAL(CurDAG)); // Predicate
2851 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
2852 return CurDAG->getMachineNode(ARM::VTBL2Pseudo, dl, VT,
2853 Ops.data(), Ops.size());
2856 case ISD::CONCAT_VECTORS:
2857 return SelectConcatVector(N);
2860 return SelectCode(N);
2863 bool ARMDAGToDAGISel::
2864 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2865 std::vector<SDValue> &OutOps) {
2866 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2867 // Require the address to be in a register. That is safe for all ARM
2868 // variants and it is hard to do anything much smarter without knowing
2869 // how the operand is used.
2870 OutOps.push_back(Op);
2874 /// createARMISelDag - This pass converts a legalized DAG into a
2875 /// ARM-specific DAG, ready for instruction scheduling.
2877 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2878 CodeGenOpt::Level OptLevel) {
2879 return new ARMDAGToDAGISel(TM, OptLevel);