1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMTargetMachine.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Constants.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/Function.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
37 //===--------------------------------------------------------------------===//
38 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
39 /// instructions for SelectionDAG operations.
42 class ARMDAGToDAGISel : public SelectionDAGISel {
43 ARMBaseTargetMachine &TM;
45 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
46 /// make the right decision when generating code for different targets.
47 const ARMSubtarget *Subtarget;
50 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
51 CodeGenOpt::Level OptLevel)
52 : SelectionDAGISel(tm, OptLevel), TM(tm),
53 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
56 virtual const char *getPassName() const {
57 return "ARM Instruction Selection";
60 /// getI32Imm - Return a target constant of type i32 with the specified
62 inline SDValue getI32Imm(unsigned Imm) {
63 return CurDAG->getTargetConstant(Imm, MVT::i32);
66 SDNode *Select(SDNode *N);
68 bool SelectShifterOperandReg(SDNode *Op, SDValue N, SDValue &A,
69 SDValue &B, SDValue &C);
70 bool SelectAddrMode2(SDNode *Op, SDValue N, SDValue &Base,
71 SDValue &Offset, SDValue &Opc);
72 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
73 SDValue &Offset, SDValue &Opc);
74 bool SelectAddrMode3(SDNode *Op, SDValue N, SDValue &Base,
75 SDValue &Offset, SDValue &Opc);
76 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
77 SDValue &Offset, SDValue &Opc);
78 bool SelectAddrMode4(SDNode *Op, SDValue N, SDValue &Addr,
80 bool SelectAddrMode5(SDNode *Op, SDValue N, SDValue &Base,
82 bool SelectAddrMode6(SDNode *Op, SDValue N, SDValue &Addr, SDValue &Align);
84 bool SelectAddrModePC(SDNode *Op, SDValue N, SDValue &Offset,
87 bool SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base,
89 bool SelectThumbAddrModeRI5(SDNode *Op, SDValue N, unsigned Scale,
90 SDValue &Base, SDValue &OffImm,
92 bool SelectThumbAddrModeS1(SDNode *Op, SDValue N, SDValue &Base,
93 SDValue &OffImm, SDValue &Offset);
94 bool SelectThumbAddrModeS2(SDNode *Op, SDValue N, SDValue &Base,
95 SDValue &OffImm, SDValue &Offset);
96 bool SelectThumbAddrModeS4(SDNode *Op, SDValue N, SDValue &Base,
97 SDValue &OffImm, SDValue &Offset);
98 bool SelectThumbAddrModeSP(SDNode *Op, SDValue N, SDValue &Base,
101 bool SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
102 SDValue &BaseReg, SDValue &Opc);
103 bool SelectT2AddrModeImm12(SDNode *Op, SDValue N, SDValue &Base,
105 bool SelectT2AddrModeImm8(SDNode *Op, SDValue N, SDValue &Base,
107 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
109 bool SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, SDValue &Base,
111 bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base,
112 SDValue &OffReg, SDValue &ShImm);
114 // Include the pieces autogenerated from the target description.
115 #include "ARMGenDAGISel.inc"
118 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
120 SDNode *SelectARMIndexedLoad(SDNode *N);
121 SDNode *SelectT2IndexedLoad(SDNode *N);
123 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
124 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
125 /// loads of D registers and even subregs and odd subregs of Q registers.
126 /// For NumVecs <= 2, QOpcodes1 is not used.
127 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
128 unsigned *QOpcodes0, unsigned *QOpcodes1);
130 /// SelectVST - Select NEON store intrinsics. NumVecs should
131 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
132 /// stores of D registers and even subregs and odd subregs of Q registers.
133 /// For NumVecs <= 2, QOpcodes1 is not used.
134 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
135 unsigned *QOpcodes0, unsigned *QOpcodes1);
137 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
138 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
139 /// load/store of D registers and even subregs and odd subregs of Q registers.
140 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
141 unsigned *DOpcodes, unsigned *QOpcodes0,
142 unsigned *QOpcodes1);
144 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
145 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
147 /// SelectCMOVOp - Select CMOV instructions for ARM.
148 SDNode *SelectCMOVOp(SDNode *N);
149 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
150 ARMCC::CondCodes CCVal, SDValue CCR,
152 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
153 ARMCC::CondCodes CCVal, SDValue CCR,
155 SDNode *SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
156 ARMCC::CondCodes CCVal, SDValue CCR,
158 SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
159 ARMCC::CondCodes CCVal, SDValue CCR,
162 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
163 /// inline asm expressions.
164 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
166 std::vector<SDValue> &OutOps);
168 /// PairDRegs - Insert a pair of double registers into an implicit def to
169 /// form a quad register.
170 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
174 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
175 /// operand. If so Imm will receive the 32-bit value.
176 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
177 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
178 Imm = cast<ConstantSDNode>(N)->getZExtValue();
184 // isInt32Immediate - This method tests to see if a constant operand.
185 // If so Imm will receive the 32 bit value.
186 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
187 return isInt32Immediate(N.getNode(), Imm);
190 // isOpcWithIntImmediate - This method tests to see if the node is a specific
191 // opcode and that it has a immediate integer right operand.
192 // If so Imm will receive the 32 bit value.
193 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
194 return N->getOpcode() == Opc &&
195 isInt32Immediate(N->getOperand(1).getNode(), Imm);
199 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op,
204 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
206 // Don't match base register only case. That is matched to a separate
207 // lower complexity pattern with explicit register operand.
208 if (ShOpcVal == ARM_AM::no_shift) return false;
210 BaseReg = N.getOperand(0);
211 unsigned ShImmVal = 0;
212 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
213 ShReg = CurDAG->getRegister(0, MVT::i32);
214 ShImmVal = RHS->getZExtValue() & 31;
216 ShReg = N.getOperand(1);
218 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
223 bool ARMDAGToDAGISel::SelectAddrMode2(SDNode *Op, SDValue N,
224 SDValue &Base, SDValue &Offset,
226 if (N.getOpcode() == ISD::MUL) {
227 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
228 // X * [3,5,9] -> X + X * [2,4,8] etc.
229 int RHSC = (int)RHS->getZExtValue();
232 ARM_AM::AddrOpc AddSub = ARM_AM::add;
234 AddSub = ARM_AM::sub;
237 if (isPowerOf2_32(RHSC)) {
238 unsigned ShAmt = Log2_32(RHSC);
239 Base = Offset = N.getOperand(0);
240 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
249 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
251 if (N.getOpcode() == ISD::FrameIndex) {
252 int FI = cast<FrameIndexSDNode>(N)->getIndex();
253 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
254 } else if (N.getOpcode() == ARMISD::Wrapper &&
255 !(Subtarget->useMovt() &&
256 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
257 Base = N.getOperand(0);
259 Offset = CurDAG->getRegister(0, MVT::i32);
260 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
266 // Match simple R +/- imm12 operands.
267 if (N.getOpcode() == ISD::ADD)
268 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
269 int RHSC = (int)RHS->getZExtValue();
270 if ((RHSC >= 0 && RHSC < 0x1000) ||
271 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
272 Base = N.getOperand(0);
273 if (Base.getOpcode() == ISD::FrameIndex) {
274 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
275 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
277 Offset = CurDAG->getRegister(0, MVT::i32);
279 ARM_AM::AddrOpc AddSub = ARM_AM::add;
281 AddSub = ARM_AM::sub;
284 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
291 // Otherwise this is R +/- [possibly shifted] R.
292 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
293 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
296 Base = N.getOperand(0);
297 Offset = N.getOperand(1);
299 if (ShOpcVal != ARM_AM::no_shift) {
300 // Check to see if the RHS of the shift is a constant, if not, we can't fold
302 if (ConstantSDNode *Sh =
303 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
304 ShAmt = Sh->getZExtValue();
305 Offset = N.getOperand(1).getOperand(0);
307 ShOpcVal = ARM_AM::no_shift;
311 // Try matching (R shl C) + (R).
312 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
313 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
314 if (ShOpcVal != ARM_AM::no_shift) {
315 // Check to see if the RHS of the shift is a constant, if not, we can't
317 if (ConstantSDNode *Sh =
318 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
319 ShAmt = Sh->getZExtValue();
320 Offset = N.getOperand(0).getOperand(0);
321 Base = N.getOperand(1);
323 ShOpcVal = ARM_AM::no_shift;
328 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
333 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
334 SDValue &Offset, SDValue &Opc) {
335 unsigned Opcode = Op->getOpcode();
336 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
337 ? cast<LoadSDNode>(Op)->getAddressingMode()
338 : cast<StoreSDNode>(Op)->getAddressingMode();
339 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
340 ? ARM_AM::add : ARM_AM::sub;
341 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
342 int Val = (int)C->getZExtValue();
343 if (Val >= 0 && Val < 0x1000) { // 12 bits.
344 Offset = CurDAG->getRegister(0, MVT::i32);
345 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
353 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
355 if (ShOpcVal != ARM_AM::no_shift) {
356 // Check to see if the RHS of the shift is a constant, if not, we can't fold
358 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
359 ShAmt = Sh->getZExtValue();
360 Offset = N.getOperand(0);
362 ShOpcVal = ARM_AM::no_shift;
366 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
372 bool ARMDAGToDAGISel::SelectAddrMode3(SDNode *Op, SDValue N,
373 SDValue &Base, SDValue &Offset,
375 if (N.getOpcode() == ISD::SUB) {
376 // X - C is canonicalize to X + -C, no need to handle it here.
377 Base = N.getOperand(0);
378 Offset = N.getOperand(1);
379 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
383 if (N.getOpcode() != ISD::ADD) {
385 if (N.getOpcode() == ISD::FrameIndex) {
386 int FI = cast<FrameIndexSDNode>(N)->getIndex();
387 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
389 Offset = CurDAG->getRegister(0, MVT::i32);
390 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
394 // If the RHS is +/- imm8, fold into addr mode.
395 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
396 int RHSC = (int)RHS->getZExtValue();
397 if ((RHSC >= 0 && RHSC < 256) ||
398 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
399 Base = N.getOperand(0);
400 if (Base.getOpcode() == ISD::FrameIndex) {
401 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
402 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
404 Offset = CurDAG->getRegister(0, MVT::i32);
406 ARM_AM::AddrOpc AddSub = ARM_AM::add;
408 AddSub = ARM_AM::sub;
411 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
416 Base = N.getOperand(0);
417 Offset = N.getOperand(1);
418 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
422 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
423 SDValue &Offset, SDValue &Opc) {
424 unsigned Opcode = Op->getOpcode();
425 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
426 ? cast<LoadSDNode>(Op)->getAddressingMode()
427 : cast<StoreSDNode>(Op)->getAddressingMode();
428 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
429 ? ARM_AM::add : ARM_AM::sub;
430 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
431 int Val = (int)C->getZExtValue();
432 if (Val >= 0 && Val < 256) {
433 Offset = CurDAG->getRegister(0, MVT::i32);
434 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
440 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
444 bool ARMDAGToDAGISel::SelectAddrMode4(SDNode *Op, SDValue N,
445 SDValue &Addr, SDValue &Mode) {
447 Mode = CurDAG->getTargetConstant(0, MVT::i32);
451 bool ARMDAGToDAGISel::SelectAddrMode5(SDNode *Op, SDValue N,
452 SDValue &Base, SDValue &Offset) {
453 if (N.getOpcode() != ISD::ADD) {
455 if (N.getOpcode() == ISD::FrameIndex) {
456 int FI = cast<FrameIndexSDNode>(N)->getIndex();
457 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
458 } else if (N.getOpcode() == ARMISD::Wrapper &&
459 !(Subtarget->useMovt() &&
460 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
461 Base = N.getOperand(0);
463 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
468 // If the RHS is +/- imm8, fold into addr mode.
469 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
470 int RHSC = (int)RHS->getZExtValue();
471 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
473 if ((RHSC >= 0 && RHSC < 256) ||
474 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
475 Base = N.getOperand(0);
476 if (Base.getOpcode() == ISD::FrameIndex) {
477 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
478 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
481 ARM_AM::AddrOpc AddSub = ARM_AM::add;
483 AddSub = ARM_AM::sub;
486 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
494 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
499 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Op, SDValue N,
500 SDValue &Addr, SDValue &Align) {
502 // Default to no alignment.
503 Align = CurDAG->getTargetConstant(0, MVT::i32);
507 bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N,
508 SDValue &Offset, SDValue &Label) {
509 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
510 Offset = N.getOperand(0);
511 SDValue N1 = N.getOperand(1);
512 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
519 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N,
520 SDValue &Base, SDValue &Offset){
521 // FIXME dl should come from the parent load or store, not the address
522 DebugLoc dl = Op->getDebugLoc();
523 if (N.getOpcode() != ISD::ADD) {
524 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
525 if (!NC || NC->getZExtValue() != 0)
532 Base = N.getOperand(0);
533 Offset = N.getOperand(1);
538 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDNode *Op, SDValue N,
539 unsigned Scale, SDValue &Base,
540 SDValue &OffImm, SDValue &Offset) {
542 SDValue TmpBase, TmpOffImm;
543 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
544 return false; // We want to select tLDRspi / tSTRspi instead.
545 if (N.getOpcode() == ARMISD::Wrapper &&
546 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
547 return false; // We want to select tLDRpci instead.
550 if (N.getOpcode() != ISD::ADD) {
551 if (N.getOpcode() == ARMISD::Wrapper &&
552 !(Subtarget->useMovt() &&
553 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
554 Base = N.getOperand(0);
558 Offset = CurDAG->getRegister(0, MVT::i32);
559 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
563 // Thumb does not have [sp, r] address mode.
564 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
565 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
566 if ((LHSR && LHSR->getReg() == ARM::SP) ||
567 (RHSR && RHSR->getReg() == ARM::SP)) {
569 Offset = CurDAG->getRegister(0, MVT::i32);
570 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
574 // If the RHS is + imm5 * scale, fold into addr mode.
575 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
576 int RHSC = (int)RHS->getZExtValue();
577 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
579 if (RHSC >= 0 && RHSC < 32) {
580 Base = N.getOperand(0);
581 Offset = CurDAG->getRegister(0, MVT::i32);
582 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
588 Base = N.getOperand(0);
589 Offset = N.getOperand(1);
590 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
594 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDNode *Op, SDValue N,
595 SDValue &Base, SDValue &OffImm,
597 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
600 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDNode *Op, SDValue N,
601 SDValue &Base, SDValue &OffImm,
603 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
606 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDNode *Op, SDValue N,
607 SDValue &Base, SDValue &OffImm,
609 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
612 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDNode *Op, SDValue N,
613 SDValue &Base, SDValue &OffImm) {
614 if (N.getOpcode() == ISD::FrameIndex) {
615 int FI = cast<FrameIndexSDNode>(N)->getIndex();
616 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
617 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
621 if (N.getOpcode() != ISD::ADD)
624 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
625 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
626 (LHSR && LHSR->getReg() == ARM::SP)) {
627 // If the RHS is + imm8 * scale, fold into addr mode.
628 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
629 int RHSC = (int)RHS->getZExtValue();
630 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
632 if (RHSC >= 0 && RHSC < 256) {
633 Base = N.getOperand(0);
634 if (Base.getOpcode() == ISD::FrameIndex) {
635 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
636 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
638 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
648 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
651 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
653 // Don't match base register only case. That is matched to a separate
654 // lower complexity pattern with explicit register operand.
655 if (ShOpcVal == ARM_AM::no_shift) return false;
657 BaseReg = N.getOperand(0);
658 unsigned ShImmVal = 0;
659 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
660 ShImmVal = RHS->getZExtValue() & 31;
661 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
668 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDNode *Op, SDValue N,
669 SDValue &Base, SDValue &OffImm) {
670 // Match simple R + imm12 operands.
673 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
674 if (N.getOpcode() == ISD::FrameIndex) {
675 // Match frame index...
676 int FI = cast<FrameIndexSDNode>(N)->getIndex();
677 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
678 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
680 } else if (N.getOpcode() == ARMISD::Wrapper &&
681 !(Subtarget->useMovt() &&
682 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
683 Base = N.getOperand(0);
684 if (Base.getOpcode() == ISD::TargetConstantPool)
685 return false; // We want to select t2LDRpci instead.
688 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
692 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
693 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
694 // Let t2LDRi8 handle (R - imm8).
697 int RHSC = (int)RHS->getZExtValue();
698 if (N.getOpcode() == ISD::SUB)
701 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
702 Base = N.getOperand(0);
703 if (Base.getOpcode() == ISD::FrameIndex) {
704 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
705 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
707 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
714 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
718 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDNode *Op, SDValue N,
719 SDValue &Base, SDValue &OffImm) {
720 // Match simple R - imm8 operands.
721 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
722 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
723 int RHSC = (int)RHS->getSExtValue();
724 if (N.getOpcode() == ISD::SUB)
727 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
728 Base = N.getOperand(0);
729 if (Base.getOpcode() == ISD::FrameIndex) {
730 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
731 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
733 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
742 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
744 unsigned Opcode = Op->getOpcode();
745 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
746 ? cast<LoadSDNode>(Op)->getAddressingMode()
747 : cast<StoreSDNode>(Op)->getAddressingMode();
748 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
749 int RHSC = (int)RHS->getZExtValue();
750 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
751 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
752 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
753 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
761 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDNode *Op, SDValue N,
762 SDValue &Base, SDValue &OffImm) {
763 if (N.getOpcode() == ISD::ADD) {
764 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
765 int RHSC = (int)RHS->getZExtValue();
766 if (((RHSC & 0x3) == 0) &&
767 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
768 Base = N.getOperand(0);
769 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
773 } else if (N.getOpcode() == ISD::SUB) {
774 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
775 int RHSC = (int)RHS->getZExtValue();
776 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
777 Base = N.getOperand(0);
778 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
787 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDNode *Op, SDValue N,
789 SDValue &OffReg, SDValue &ShImm) {
790 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
791 if (N.getOpcode() != ISD::ADD)
794 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
795 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
796 int RHSC = (int)RHS->getZExtValue();
797 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
799 else if (RHSC < 0 && RHSC >= -255) // 8 bits
803 // Look for (R + R) or (R + (R << [1,2,3])).
805 Base = N.getOperand(0);
806 OffReg = N.getOperand(1);
808 // Swap if it is ((R << c) + R).
809 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
810 if (ShOpcVal != ARM_AM::lsl) {
811 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
812 if (ShOpcVal == ARM_AM::lsl)
813 std::swap(Base, OffReg);
816 if (ShOpcVal == ARM_AM::lsl) {
817 // Check to see if the RHS of the shift is a constant, if not, we can't fold
819 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
820 ShAmt = Sh->getZExtValue();
823 ShOpcVal = ARM_AM::no_shift;
825 OffReg = OffReg.getOperand(0);
827 ShOpcVal = ARM_AM::no_shift;
831 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
836 //===--------------------------------------------------------------------===//
838 /// getAL - Returns a ARMCC::AL immediate node.
839 static inline SDValue getAL(SelectionDAG *CurDAG) {
840 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
843 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
844 LoadSDNode *LD = cast<LoadSDNode>(N);
845 ISD::MemIndexedMode AM = LD->getAddressingMode();
846 if (AM == ISD::UNINDEXED)
849 EVT LoadedVT = LD->getMemoryVT();
850 SDValue Offset, AMOpc;
851 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
854 if (LoadedVT == MVT::i32 &&
855 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
856 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
858 } else if (LoadedVT == MVT::i16 &&
859 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
861 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
862 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
863 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
864 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
865 if (LD->getExtensionType() == ISD::SEXTLOAD) {
866 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
868 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
871 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
873 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
879 SDValue Chain = LD->getChain();
880 SDValue Base = LD->getBasePtr();
881 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
882 CurDAG->getRegister(0, MVT::i32), Chain };
883 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
890 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
891 LoadSDNode *LD = cast<LoadSDNode>(N);
892 ISD::MemIndexedMode AM = LD->getAddressingMode();
893 if (AM == ISD::UNINDEXED)
896 EVT LoadedVT = LD->getMemoryVT();
897 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
899 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
902 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
903 switch (LoadedVT.getSimpleVT().SimpleTy) {
905 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
909 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
911 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
916 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
918 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
927 SDValue Chain = LD->getChain();
928 SDValue Base = LD->getBasePtr();
929 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
930 CurDAG->getRegister(0, MVT::i32), Chain };
931 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
938 /// PairDRegs - Insert a pair of double registers into an implicit def to
939 /// form a quad register.
940 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
941 DebugLoc dl = V0.getNode()->getDebugLoc();
943 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0);
944 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
945 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
946 SDNode *Pair = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
947 VT, Undef, V0, SubReg0);
948 return CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
949 VT, SDValue(Pair, 0), V1, SubReg1);
952 /// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type
953 /// for a 64-bit subregister of the vector.
954 static EVT GetNEONSubregVT(EVT VT) {
955 switch (VT.getSimpleVT().SimpleTy) {
956 default: llvm_unreachable("unhandled NEON type");
957 case MVT::v16i8: return MVT::v8i8;
958 case MVT::v8i16: return MVT::v4i16;
959 case MVT::v4f32: return MVT::v2f32;
960 case MVT::v4i32: return MVT::v2i32;
961 case MVT::v2i64: return MVT::v1i64;
965 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
966 unsigned *DOpcodes, unsigned *QOpcodes0,
967 unsigned *QOpcodes1) {
968 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
969 DebugLoc dl = N->getDebugLoc();
971 SDValue MemAddr, Align;
972 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
975 SDValue Chain = N->getOperand(0);
976 EVT VT = N->getValueType(0);
977 bool is64BitVector = VT.is64BitVector();
979 unsigned OpcodeIndex;
980 switch (VT.getSimpleVT().SimpleTy) {
981 default: llvm_unreachable("unhandled vld type");
982 // Double-register operations:
983 case MVT::v8i8: OpcodeIndex = 0; break;
984 case MVT::v4i16: OpcodeIndex = 1; break;
986 case MVT::v2i32: OpcodeIndex = 2; break;
987 case MVT::v1i64: OpcodeIndex = 3; break;
988 // Quad-register operations:
989 case MVT::v16i8: OpcodeIndex = 0; break;
990 case MVT::v8i16: OpcodeIndex = 1; break;
992 case MVT::v4i32: OpcodeIndex = 2; break;
993 case MVT::v2i64: OpcodeIndex = 3;
994 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
998 SDValue Pred = getAL(CurDAG);
999 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1000 if (is64BitVector) {
1001 unsigned Opc = DOpcodes[OpcodeIndex];
1002 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1003 std::vector<EVT> ResTys(NumVecs, VT);
1004 ResTys.push_back(MVT::Other);
1005 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1008 EVT RegVT = GetNEONSubregVT(VT);
1010 // Quad registers are directly supported for VLD1 and VLD2,
1011 // loading pairs of D regs.
1012 unsigned Opc = QOpcodes0[OpcodeIndex];
1013 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1014 std::vector<EVT> ResTys(2 * NumVecs, RegVT);
1015 ResTys.push_back(MVT::Other);
1016 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1017 Chain = SDValue(VLd, 2 * NumVecs);
1019 // Combine the even and odd subregs to produce the result.
1020 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1021 SDNode *Q = PairDRegs(VT, SDValue(VLd, 2*Vec), SDValue(VLd, 2*Vec+1));
1022 ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1025 // Otherwise, quad registers are loaded with two separate instructions,
1026 // where one loads the even registers and the other loads the odd registers.
1028 std::vector<EVT> ResTys(NumVecs, RegVT);
1029 ResTys.push_back(MemAddr.getValueType());
1030 ResTys.push_back(MVT::Other);
1032 // Load the even subregs.
1033 unsigned Opc = QOpcodes0[OpcodeIndex];
1034 const SDValue OpsA[] = { MemAddr, Align, Reg0, Pred, Reg0, Chain };
1035 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 6);
1036 Chain = SDValue(VLdA, NumVecs+1);
1038 // Load the odd subregs.
1039 Opc = QOpcodes1[OpcodeIndex];
1040 const SDValue OpsB[] = { SDValue(VLdA, NumVecs),
1041 Align, Reg0, Pred, Reg0, Chain };
1042 SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 6);
1043 Chain = SDValue(VLdB, NumVecs+1);
1045 // Combine the even and odd subregs to produce the result.
1046 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1047 SDNode *Q = PairDRegs(VT, SDValue(VLdA, Vec), SDValue(VLdB, Vec));
1048 ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1051 ReplaceUses(SDValue(N, NumVecs), Chain);
1055 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1056 unsigned *DOpcodes, unsigned *QOpcodes0,
1057 unsigned *QOpcodes1) {
1058 assert(NumVecs >=1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1059 DebugLoc dl = N->getDebugLoc();
1061 SDValue MemAddr, Align;
1062 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1065 SDValue Chain = N->getOperand(0);
1066 EVT VT = N->getOperand(3).getValueType();
1067 bool is64BitVector = VT.is64BitVector();
1069 unsigned OpcodeIndex;
1070 switch (VT.getSimpleVT().SimpleTy) {
1071 default: llvm_unreachable("unhandled vst type");
1072 // Double-register operations:
1073 case MVT::v8i8: OpcodeIndex = 0; break;
1074 case MVT::v4i16: OpcodeIndex = 1; break;
1076 case MVT::v2i32: OpcodeIndex = 2; break;
1077 case MVT::v1i64: OpcodeIndex = 3; break;
1078 // Quad-register operations:
1079 case MVT::v16i8: OpcodeIndex = 0; break;
1080 case MVT::v8i16: OpcodeIndex = 1; break;
1082 case MVT::v4i32: OpcodeIndex = 2; break;
1083 case MVT::v2i64: OpcodeIndex = 3;
1084 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1088 SDValue Pred = getAL(CurDAG);
1089 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1091 SmallVector<SDValue, 10> Ops;
1092 Ops.push_back(MemAddr);
1093 Ops.push_back(Align);
1095 if (is64BitVector) {
1096 unsigned Opc = DOpcodes[OpcodeIndex];
1097 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1098 Ops.push_back(N->getOperand(Vec+3));
1099 Ops.push_back(Pred);
1100 Ops.push_back(Reg0); // predicate register
1101 Ops.push_back(Chain);
1102 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5);
1105 EVT RegVT = GetNEONSubregVT(VT);
1107 // Quad registers are directly supported for VST1 and VST2,
1108 // storing pairs of D regs.
1109 unsigned Opc = QOpcodes0[OpcodeIndex];
1110 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1111 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1112 N->getOperand(Vec+3)));
1113 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1114 N->getOperand(Vec+3)));
1116 Ops.push_back(Pred);
1117 Ops.push_back(Reg0); // predicate register
1118 Ops.push_back(Chain);
1119 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(),
1123 // Otherwise, quad registers are stored with two separate instructions,
1124 // where one stores the even registers and the other stores the odd registers.
1126 Ops.push_back(Reg0); // post-access address offset
1128 // Store the even subregs.
1129 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1130 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1131 N->getOperand(Vec+3)));
1132 Ops.push_back(Pred);
1133 Ops.push_back(Reg0); // predicate register
1134 Ops.push_back(Chain);
1135 unsigned Opc = QOpcodes0[OpcodeIndex];
1136 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1137 MVT::Other, Ops.data(), NumVecs+6);
1138 Chain = SDValue(VStA, 1);
1140 // Store the odd subregs.
1141 Ops[0] = SDValue(VStA, 0); // MemAddr
1142 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1143 Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1144 N->getOperand(Vec+3));
1145 Ops[NumVecs+5] = Chain;
1146 Opc = QOpcodes1[OpcodeIndex];
1147 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1148 MVT::Other, Ops.data(), NumVecs+6);
1149 Chain = SDValue(VStB, 1);
1150 ReplaceUses(SDValue(N, 0), Chain);
1154 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1155 unsigned NumVecs, unsigned *DOpcodes,
1156 unsigned *QOpcodes0,
1157 unsigned *QOpcodes1) {
1158 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1159 DebugLoc dl = N->getDebugLoc();
1161 SDValue MemAddr, Align;
1162 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1165 SDValue Chain = N->getOperand(0);
1167 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1168 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1169 bool is64BitVector = VT.is64BitVector();
1171 // Quad registers are handled by load/store of subregs. Find the subreg info.
1172 unsigned NumElts = 0;
1175 if (!is64BitVector) {
1176 RegVT = GetNEONSubregVT(VT);
1177 NumElts = RegVT.getVectorNumElements();
1178 SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1181 unsigned OpcodeIndex;
1182 switch (VT.getSimpleVT().SimpleTy) {
1183 default: llvm_unreachable("unhandled vld/vst lane type");
1184 // Double-register operations:
1185 case MVT::v8i8: OpcodeIndex = 0; break;
1186 case MVT::v4i16: OpcodeIndex = 1; break;
1188 case MVT::v2i32: OpcodeIndex = 2; break;
1189 // Quad-register operations:
1190 case MVT::v8i16: OpcodeIndex = 0; break;
1192 case MVT::v4i32: OpcodeIndex = 1; break;
1195 SDValue Pred = getAL(CurDAG);
1196 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1198 SmallVector<SDValue, 10> Ops;
1199 Ops.push_back(MemAddr);
1200 Ops.push_back(Align);
1203 if (is64BitVector) {
1204 Opc = DOpcodes[OpcodeIndex];
1205 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1206 Ops.push_back(N->getOperand(Vec+3));
1208 // Check if this is loading the even or odd subreg of a Q register.
1209 if (Lane < NumElts) {
1210 Opc = QOpcodes0[OpcodeIndex];
1213 Opc = QOpcodes1[OpcodeIndex];
1215 // Extract the subregs of the input vector.
1216 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1217 Ops.push_back(CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1218 N->getOperand(Vec+3)));
1220 Ops.push_back(getI32Imm(Lane));
1221 Ops.push_back(Pred);
1222 Ops.push_back(Reg0);
1223 Ops.push_back(Chain);
1226 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+6);
1228 std::vector<EVT> ResTys(NumVecs, RegVT);
1229 ResTys.push_back(MVT::Other);
1231 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+6);
1232 // For a 64-bit vector load to D registers, nothing more needs to be done.
1236 // For 128-bit vectors, take the 64-bit results of the load and insert them
1237 // as subregs into the result.
1238 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1239 SDValue QuadVec = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1240 N->getOperand(Vec+3),
1241 SDValue(VLdLn, Vec));
1242 ReplaceUses(SDValue(N, Vec), QuadVec);
1245 Chain = SDValue(VLdLn, NumVecs);
1246 ReplaceUses(SDValue(N, NumVecs), Chain);
1250 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1252 if (!Subtarget->hasV6T2Ops())
1255 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1256 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1259 // For unsigned extracts, check for a shift right and mask
1260 unsigned And_imm = 0;
1261 if (N->getOpcode() == ISD::AND) {
1262 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1264 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1265 if (And_imm & (And_imm + 1))
1268 unsigned Srl_imm = 0;
1269 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1271 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1273 unsigned Width = CountTrailingOnes_32(And_imm);
1274 unsigned LSB = Srl_imm;
1275 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1276 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1277 CurDAG->getTargetConstant(LSB, MVT::i32),
1278 CurDAG->getTargetConstant(Width, MVT::i32),
1279 getAL(CurDAG), Reg0 };
1280 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1286 // Otherwise, we're looking for a shift of a shift
1287 unsigned Shl_imm = 0;
1288 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1289 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1290 unsigned Srl_imm = 0;
1291 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1292 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1293 unsigned Width = 32 - Srl_imm;
1294 int LSB = Srl_imm - Shl_imm;
1297 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1298 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1299 CurDAG->getTargetConstant(LSB, MVT::i32),
1300 CurDAG->getTargetConstant(Width, MVT::i32),
1301 getAL(CurDAG), Reg0 };
1302 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1308 SDNode *ARMDAGToDAGISel::
1309 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1310 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1313 if (SelectT2ShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1)) {
1314 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1315 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1318 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1319 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1320 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1321 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1323 llvm_unreachable("Unknown so_reg opcode!");
1327 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1328 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1329 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1330 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1335 SDNode *ARMDAGToDAGISel::
1336 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1337 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1341 if (SelectShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1342 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1343 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1344 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1349 SDNode *ARMDAGToDAGISel::
1350 SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1351 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1352 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1356 if (Predicate_t2_so_imm(TrueVal.getNode())) {
1357 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1358 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1359 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1360 return CurDAG->SelectNodeTo(N,
1361 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1366 SDNode *ARMDAGToDAGISel::
1367 SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1368 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1369 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1373 if (Predicate_so_imm(TrueVal.getNode())) {
1374 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1375 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1376 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1377 return CurDAG->SelectNodeTo(N,
1378 ARM::MOVCCi, MVT::i32, Ops, 5);
1383 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1384 EVT VT = N->getValueType(0);
1385 SDValue FalseVal = N->getOperand(0);
1386 SDValue TrueVal = N->getOperand(1);
1387 SDValue CC = N->getOperand(2);
1388 SDValue CCR = N->getOperand(3);
1389 SDValue InFlag = N->getOperand(4);
1390 assert(CC.getOpcode() == ISD::Constant);
1391 assert(CCR.getOpcode() == ISD::Register);
1392 ARMCC::CondCodes CCVal =
1393 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1395 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1396 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1397 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1398 // Pattern complexity = 18 cost = 1 size = 0
1402 if (Subtarget->isThumb()) {
1403 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1404 CCVal, CCR, InFlag);
1406 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1407 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1411 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1412 CCVal, CCR, InFlag);
1414 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1415 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1420 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1421 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1423 // Emits: (MOVCCi:i32 GPR:i32:$false,
1424 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1425 // Pattern complexity = 10 cost = 1 size = 0
1426 if (Subtarget->isThumb()) {
1427 SDNode *Res = SelectT2CMOVSoImmOp(N, FalseVal, TrueVal,
1428 CCVal, CCR, InFlag);
1430 Res = SelectT2CMOVSoImmOp(N, TrueVal, FalseVal,
1431 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1435 SDNode *Res = SelectARMCMOVSoImmOp(N, FalseVal, TrueVal,
1436 CCVal, CCR, InFlag);
1438 Res = SelectARMCMOVSoImmOp(N, TrueVal, FalseVal,
1439 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1445 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1446 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1447 // Pattern complexity = 6 cost = 1 size = 0
1449 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1450 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1451 // Pattern complexity = 6 cost = 11 size = 0
1453 // Also FCPYScc and FCPYDcc.
1454 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1455 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1457 switch (VT.getSimpleVT().SimpleTy) {
1458 default: assert(false && "Illegal conditional move type!");
1461 Opc = Subtarget->isThumb()
1462 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1472 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1475 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
1476 DebugLoc dl = N->getDebugLoc();
1478 if (N->isMachineOpcode())
1479 return NULL; // Already selected.
1481 switch (N->getOpcode()) {
1483 case ISD::Constant: {
1484 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1486 if (Subtarget->hasThumb2())
1487 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1488 // be done with MOV + MOVT, at worst.
1491 if (Subtarget->isThumb()) {
1492 UseCP = (Val > 255 && // MOV
1493 ~Val > 255 && // MOV + MVN
1494 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1496 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1497 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1498 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1503 CurDAG->getTargetConstantPool(ConstantInt::get(
1504 Type::getInt32Ty(*CurDAG->getContext()), Val),
1505 TLI.getPointerTy());
1508 if (Subtarget->isThumb1Only()) {
1509 SDValue Pred = getAL(CurDAG);
1510 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1511 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1512 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1517 CurDAG->getRegister(0, MVT::i32),
1518 CurDAG->getTargetConstant(0, MVT::i32),
1520 CurDAG->getRegister(0, MVT::i32),
1521 CurDAG->getEntryNode()
1523 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1526 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
1530 // Other cases are autogenerated.
1533 case ISD::FrameIndex: {
1534 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1535 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1536 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1537 if (Subtarget->isThumb1Only()) {
1538 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1539 CurDAG->getTargetConstant(0, MVT::i32));
1541 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1542 ARM::t2ADDri : ARM::ADDri);
1543 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1544 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1545 CurDAG->getRegister(0, MVT::i32) };
1546 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1550 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
1554 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
1558 if (Subtarget->isThumb1Only())
1560 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1561 unsigned RHSV = C->getZExtValue();
1563 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1564 unsigned ShImm = Log2_32(RHSV-1);
1567 SDValue V = N->getOperand(0);
1568 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1569 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1570 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1571 if (Subtarget->isThumb()) {
1572 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1573 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1575 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1576 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1579 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1580 unsigned ShImm = Log2_32(RHSV+1);
1583 SDValue V = N->getOperand(0);
1584 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1585 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1586 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1587 if (Subtarget->isThumb()) {
1588 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1589 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1591 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1592 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1598 // Check for unsigned bitfield extract
1599 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
1602 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
1603 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
1604 // are entirely contributed by c2 and lower 16-bits are entirely contributed
1605 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
1606 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
1607 EVT VT = N->getValueType(0);
1610 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
1612 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
1615 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1616 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1619 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
1620 SDValue N2 = N0.getOperand(1);
1621 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1624 unsigned N1CVal = N1C->getZExtValue();
1625 unsigned N2CVal = N2C->getZExtValue();
1626 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
1627 (N1CVal & 0xffffU) == 0xffffU &&
1628 (N2CVal & 0xffffU) == 0x0U) {
1629 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
1631 SDValue Ops[] = { N0.getOperand(0), Imm16,
1632 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1633 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
1638 case ARMISD::VMOVRRD:
1639 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
1640 N->getOperand(0), getAL(CurDAG),
1641 CurDAG->getRegister(0, MVT::i32));
1642 case ISD::UMUL_LOHI: {
1643 if (Subtarget->isThumb1Only())
1645 if (Subtarget->isThumb()) {
1646 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1647 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1648 CurDAG->getRegister(0, MVT::i32) };
1649 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1651 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1652 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1653 CurDAG->getRegister(0, MVT::i32) };
1654 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1657 case ISD::SMUL_LOHI: {
1658 if (Subtarget->isThumb1Only())
1660 if (Subtarget->isThumb()) {
1661 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1662 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1663 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1665 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1666 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1667 CurDAG->getRegister(0, MVT::i32) };
1668 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1672 SDNode *ResNode = 0;
1673 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1674 ResNode = SelectT2IndexedLoad(N);
1676 ResNode = SelectARMIndexedLoad(N);
1680 // VLDMQ must be custom-selected for "v2f64 load" to set the AM5Opc value.
1681 if (Subtarget->hasVFP2() &&
1682 N->getValueType(0).getSimpleVT().SimpleTy == MVT::v2f64) {
1683 SDValue Chain = N->getOperand(0);
1685 CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32);
1686 SDValue Pred = getAL(CurDAG);
1687 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1688 SDValue Ops[] = { N->getOperand(1), AM5Opc, Pred, PredReg, Chain };
1689 return CurDAG->getMachineNode(ARM::VLDMQ, dl, MVT::v2f64, MVT::Other,
1692 // Other cases are autogenerated.
1696 // VSTMQ must be custom-selected for "v2f64 store" to set the AM5Opc value.
1697 if (Subtarget->hasVFP2() &&
1698 N->getOperand(1).getValueType().getSimpleVT().SimpleTy == MVT::v2f64) {
1699 SDValue Chain = N->getOperand(0);
1701 CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32);
1702 SDValue Pred = getAL(CurDAG);
1703 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1704 SDValue Ops[] = { N->getOperand(1), N->getOperand(2),
1705 AM5Opc, Pred, PredReg, Chain };
1706 return CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6);
1708 // Other cases are autogenerated.
1711 case ARMISD::BRCOND: {
1712 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1713 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1714 // Pattern complexity = 6 cost = 1 size = 0
1716 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1717 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1718 // Pattern complexity = 6 cost = 1 size = 0
1720 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1721 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1722 // Pattern complexity = 6 cost = 1 size = 0
1724 unsigned Opc = Subtarget->isThumb() ?
1725 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1726 SDValue Chain = N->getOperand(0);
1727 SDValue N1 = N->getOperand(1);
1728 SDValue N2 = N->getOperand(2);
1729 SDValue N3 = N->getOperand(3);
1730 SDValue InFlag = N->getOperand(4);
1731 assert(N1.getOpcode() == ISD::BasicBlock);
1732 assert(N2.getOpcode() == ISD::Constant);
1733 assert(N3.getOpcode() == ISD::Register);
1735 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1736 cast<ConstantSDNode>(N2)->getZExtValue()),
1738 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1739 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1741 Chain = SDValue(ResNode, 0);
1742 if (N->getNumValues() == 2) {
1743 InFlag = SDValue(ResNode, 1);
1744 ReplaceUses(SDValue(N, 1), InFlag);
1746 ReplaceUses(SDValue(N, 0),
1747 SDValue(Chain.getNode(), Chain.getResNo()));
1751 return SelectCMOVOp(N);
1752 case ARMISD::CNEG: {
1753 EVT VT = N->getValueType(0);
1754 SDValue N0 = N->getOperand(0);
1755 SDValue N1 = N->getOperand(1);
1756 SDValue N2 = N->getOperand(2);
1757 SDValue N3 = N->getOperand(3);
1758 SDValue InFlag = N->getOperand(4);
1759 assert(N2.getOpcode() == ISD::Constant);
1760 assert(N3.getOpcode() == ISD::Register);
1762 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1763 cast<ConstantSDNode>(N2)->getZExtValue()),
1765 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1767 switch (VT.getSimpleVT().SimpleTy) {
1768 default: assert(false && "Illegal conditional move type!");
1777 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1780 case ARMISD::VZIP: {
1782 EVT VT = N->getValueType(0);
1783 switch (VT.getSimpleVT().SimpleTy) {
1784 default: return NULL;
1785 case MVT::v8i8: Opc = ARM::VZIPd8; break;
1786 case MVT::v4i16: Opc = ARM::VZIPd16; break;
1788 case MVT::v2i32: Opc = ARM::VZIPd32; break;
1789 case MVT::v16i8: Opc = ARM::VZIPq8; break;
1790 case MVT::v8i16: Opc = ARM::VZIPq16; break;
1792 case MVT::v4i32: Opc = ARM::VZIPq32; break;
1794 SDValue Pred = getAL(CurDAG);
1795 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1796 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1797 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1799 case ARMISD::VUZP: {
1801 EVT VT = N->getValueType(0);
1802 switch (VT.getSimpleVT().SimpleTy) {
1803 default: return NULL;
1804 case MVT::v8i8: Opc = ARM::VUZPd8; break;
1805 case MVT::v4i16: Opc = ARM::VUZPd16; break;
1807 case MVT::v2i32: Opc = ARM::VUZPd32; break;
1808 case MVT::v16i8: Opc = ARM::VUZPq8; break;
1809 case MVT::v8i16: Opc = ARM::VUZPq16; break;
1811 case MVT::v4i32: Opc = ARM::VUZPq32; break;
1813 SDValue Pred = getAL(CurDAG);
1814 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1815 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1816 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1818 case ARMISD::VTRN: {
1820 EVT VT = N->getValueType(0);
1821 switch (VT.getSimpleVT().SimpleTy) {
1822 default: return NULL;
1823 case MVT::v8i8: Opc = ARM::VTRNd8; break;
1824 case MVT::v4i16: Opc = ARM::VTRNd16; break;
1826 case MVT::v2i32: Opc = ARM::VTRNd32; break;
1827 case MVT::v16i8: Opc = ARM::VTRNq8; break;
1828 case MVT::v8i16: Opc = ARM::VTRNq16; break;
1830 case MVT::v4i32: Opc = ARM::VTRNq32; break;
1832 SDValue Pred = getAL(CurDAG);
1833 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1834 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1835 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1838 case ISD::INTRINSIC_VOID:
1839 case ISD::INTRINSIC_W_CHAIN: {
1840 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1845 case Intrinsic::arm_neon_vld1: {
1846 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
1847 ARM::VLD1d32, ARM::VLD1d64 };
1848 unsigned QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
1849 ARM::VLD1q32, ARM::VLD1q64 };
1850 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0);
1853 case Intrinsic::arm_neon_vld2: {
1854 unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
1855 ARM::VLD2d32, ARM::VLD1q64 };
1856 unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 };
1857 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
1860 case Intrinsic::arm_neon_vld3: {
1861 unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
1862 ARM::VLD3d32, ARM::VLD1d64T };
1863 unsigned QOpcodes0[] = { ARM::VLD3q8_UPD,
1866 unsigned QOpcodes1[] = { ARM::VLD3q8odd_UPD,
1867 ARM::VLD3q16odd_UPD,
1868 ARM::VLD3q32odd_UPD };
1869 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
1872 case Intrinsic::arm_neon_vld4: {
1873 unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
1874 ARM::VLD4d32, ARM::VLD1d64Q };
1875 unsigned QOpcodes0[] = { ARM::VLD4q8_UPD,
1878 unsigned QOpcodes1[] = { ARM::VLD4q8odd_UPD,
1879 ARM::VLD4q16odd_UPD,
1880 ARM::VLD4q32odd_UPD };
1881 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
1884 case Intrinsic::arm_neon_vld2lane: {
1885 unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 };
1886 unsigned QOpcodes0[] = { ARM::VLD2LNq16, ARM::VLD2LNq32 };
1887 unsigned QOpcodes1[] = { ARM::VLD2LNq16odd, ARM::VLD2LNq32odd };
1888 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
1891 case Intrinsic::arm_neon_vld3lane: {
1892 unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 };
1893 unsigned QOpcodes0[] = { ARM::VLD3LNq16, ARM::VLD3LNq32 };
1894 unsigned QOpcodes1[] = { ARM::VLD3LNq16odd, ARM::VLD3LNq32odd };
1895 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
1898 case Intrinsic::arm_neon_vld4lane: {
1899 unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 };
1900 unsigned QOpcodes0[] = { ARM::VLD4LNq16, ARM::VLD4LNq32 };
1901 unsigned QOpcodes1[] = { ARM::VLD4LNq16odd, ARM::VLD4LNq32odd };
1902 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
1905 case Intrinsic::arm_neon_vst1: {
1906 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
1907 ARM::VST1d32, ARM::VST1d64 };
1908 unsigned QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
1909 ARM::VST1q32, ARM::VST1q64 };
1910 return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
1913 case Intrinsic::arm_neon_vst2: {
1914 unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
1915 ARM::VST2d32, ARM::VST1q64 };
1916 unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
1917 return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
1920 case Intrinsic::arm_neon_vst3: {
1921 unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
1922 ARM::VST3d32, ARM::VST1d64T };
1923 unsigned QOpcodes0[] = { ARM::VST3q8_UPD,
1926 unsigned QOpcodes1[] = { ARM::VST3q8odd_UPD,
1927 ARM::VST3q16odd_UPD,
1928 ARM::VST3q32odd_UPD };
1929 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
1932 case Intrinsic::arm_neon_vst4: {
1933 unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
1934 ARM::VST4d32, ARM::VST1d64Q };
1935 unsigned QOpcodes0[] = { ARM::VST4q8_UPD,
1938 unsigned QOpcodes1[] = { ARM::VST4q8odd_UPD,
1939 ARM::VST4q16odd_UPD,
1940 ARM::VST4q32odd_UPD };
1941 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
1944 case Intrinsic::arm_neon_vst2lane: {
1945 unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 };
1946 unsigned QOpcodes0[] = { ARM::VST2LNq16, ARM::VST2LNq32 };
1947 unsigned QOpcodes1[] = { ARM::VST2LNq16odd, ARM::VST2LNq32odd };
1948 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
1951 case Intrinsic::arm_neon_vst3lane: {
1952 unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 };
1953 unsigned QOpcodes0[] = { ARM::VST3LNq16, ARM::VST3LNq32 };
1954 unsigned QOpcodes1[] = { ARM::VST3LNq16odd, ARM::VST3LNq32odd };
1955 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
1958 case Intrinsic::arm_neon_vst4lane: {
1959 unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 };
1960 unsigned QOpcodes0[] = { ARM::VST4LNq16, ARM::VST4LNq32 };
1961 unsigned QOpcodes1[] = { ARM::VST4LNq16odd, ARM::VST4LNq32odd };
1962 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
1968 return SelectCode(N);
1971 bool ARMDAGToDAGISel::
1972 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1973 std::vector<SDValue> &OutOps) {
1974 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1975 // Require the address to be in a register. That is safe for all ARM
1976 // variants and it is hard to do anything much smarter without knowing
1977 // how the operand is used.
1978 OutOps.push_back(Op);
1982 /// createARMISelDag - This pass converts a legalized DAG into a
1983 /// ARM-specific DAG, ready for instruction scheduling.
1985 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
1986 CodeGenOpt::Level OptLevel) {
1987 return new ARMDAGToDAGISel(TM, OptLevel);