1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMTargetMachine.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/IR/CallingConv.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Target/TargetOptions.h"
42 DisableShifterOp("disable-shifter-op", cl::Hidden,
43 cl::desc("Disable isel of shifter-op"),
47 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
48 cl::desc("Check fp vmla / vmls hazard at isel time"),
51 //===--------------------------------------------------------------------===//
52 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
53 /// instructions for SelectionDAG operations.
58 AM2_BASE, // Simple AM2 (+-imm12)
59 AM2_SHOP // Shifter-op AM2
62 class ARMDAGToDAGISel : public SelectionDAGISel {
63 ARMBaseTargetMachine &TM;
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when generating code for different targets.
67 const ARMSubtarget *Subtarget;
70 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
71 CodeGenOpt::Level OptLevel)
72 : SelectionDAGISel(tm, OptLevel), TM(tm),
73 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
76 virtual const char *getPassName() const {
77 return "ARM Instruction Selection";
80 virtual void PreprocessISelDAG();
82 /// getI32Imm - Return a target constant of type i32 with the specified
84 inline SDValue getI32Imm(unsigned Imm) {
85 return CurDAG->getTargetConstant(Imm, MVT::i32);
88 SDNode *Select(SDNode *N);
91 bool hasNoVMLxHazardUse(SDNode *N) const;
92 bool isShifterOpProfitable(const SDValue &Shift,
93 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
94 bool SelectRegShifterOperand(SDValue N, SDValue &A,
95 SDValue &B, SDValue &C,
96 bool CheckProfitability = true);
97 bool SelectImmShifterOperand(SDValue N, SDValue &A,
98 SDValue &B, bool CheckProfitability = true);
99 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
100 SDValue &B, SDValue &C) {
101 // Don't apply the profitability check
102 return SelectRegShifterOperand(N, A, B, C, false);
104 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
106 // Don't apply the profitability check
107 return SelectImmShifterOperand(N, A, B, false);
110 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
111 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
113 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
114 SDValue &Offset, SDValue &Opc);
115 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
117 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
120 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
122 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
125 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
127 SelectAddrMode2Worker(N, Base, Offset, Opc);
128 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
129 // This always matches one way or another.
133 bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
134 const ConstantSDNode *CN = cast<ConstantSDNode>(N);
135 Pred = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
136 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
140 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
141 SDValue &Offset, SDValue &Opc);
142 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
143 SDValue &Offset, SDValue &Opc);
144 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
145 SDValue &Offset, SDValue &Opc);
146 bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
147 bool SelectAddrMode3(SDValue N, SDValue &Base,
148 SDValue &Offset, SDValue &Opc);
149 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
150 SDValue &Offset, SDValue &Opc);
151 bool SelectAddrMode5(SDValue N, SDValue &Base,
153 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
154 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
156 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
158 // Thumb Addressing Modes:
159 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
160 bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
162 bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
163 bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
164 bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
165 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
167 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
169 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
171 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
173 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
175 // Thumb 2 Addressing Modes:
176 bool SelectT2ShifterOperandReg(SDValue N,
177 SDValue &BaseReg, SDValue &Opc);
178 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
179 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
181 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
183 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
184 SDValue &OffReg, SDValue &ShImm);
185 bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
187 inline bool is_so_imm(unsigned Imm) const {
188 return ARM_AM::getSOImmVal(Imm) != -1;
191 inline bool is_so_imm_not(unsigned Imm) const {
192 return ARM_AM::getSOImmVal(~Imm) != -1;
195 inline bool is_t2_so_imm(unsigned Imm) const {
196 return ARM_AM::getT2SOImmVal(Imm) != -1;
199 inline bool is_t2_so_imm_not(unsigned Imm) const {
200 return ARM_AM::getT2SOImmVal(~Imm) != -1;
203 // Include the pieces autogenerated from the target description.
204 #include "ARMGenDAGISel.inc"
207 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
209 SDNode *SelectARMIndexedLoad(SDNode *N);
210 SDNode *SelectT2IndexedLoad(SDNode *N);
212 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
213 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
214 /// loads of D registers and even subregs and odd subregs of Q registers.
215 /// For NumVecs <= 2, QOpcodes1 is not used.
216 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
217 const uint16_t *DOpcodes,
218 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
220 /// SelectVST - Select NEON store intrinsics. NumVecs should
221 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
222 /// stores of D registers and even subregs and odd subregs of Q registers.
223 /// For NumVecs <= 2, QOpcodes1 is not used.
224 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
225 const uint16_t *DOpcodes,
226 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
228 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
229 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
230 /// load/store of D registers and Q registers.
231 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
232 bool isUpdating, unsigned NumVecs,
233 const uint16_t *DOpcodes, const uint16_t *QOpcodes);
235 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
236 /// should be 2, 3 or 4. The opcode array specifies the instructions used
237 /// for loading D registers. (Q registers are not supported.)
238 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
239 const uint16_t *Opcodes);
241 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
242 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
243 /// generated to force the table registers to be consecutive.
244 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
246 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
247 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
249 // Select special operations if node forms integer ABS pattern
250 SDNode *SelectABSOp(SDNode *N);
252 SDNode *SelectInlineAsm(SDNode *N);
254 SDNode *SelectConcatVector(SDNode *N);
256 SDNode *SelectAtomic(SDNode *N, unsigned Op8, unsigned Op16, unsigned Op32, unsigned Op64);
258 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
259 /// inline asm expressions.
260 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
262 std::vector<SDValue> &OutOps);
264 // Form pairs of consecutive R, S, D, or Q registers.
265 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
266 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
267 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
268 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
270 // Form sequences of 4 consecutive S, D, or Q registers.
271 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
272 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
273 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
275 // Get the alignment operand for a NEON VLD or VST instruction.
276 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
280 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
281 /// operand. If so Imm will receive the 32-bit value.
282 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
283 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
284 Imm = cast<ConstantSDNode>(N)->getZExtValue();
290 // isInt32Immediate - This method tests to see if a constant operand.
291 // If so Imm will receive the 32 bit value.
292 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
293 return isInt32Immediate(N.getNode(), Imm);
296 // isOpcWithIntImmediate - This method tests to see if the node is a specific
297 // opcode and that it has a immediate integer right operand.
298 // If so Imm will receive the 32 bit value.
299 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
300 return N->getOpcode() == Opc &&
301 isInt32Immediate(N->getOperand(1).getNode(), Imm);
304 /// \brief Check whether a particular node is a constant value representable as
305 /// (N * Scale) where (N in [\p RangeMin, \p RangeMax).
307 /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
308 static bool isScaledConstantInRange(SDValue Node, int Scale,
309 int RangeMin, int RangeMax,
310 int &ScaledConstant) {
311 assert(Scale > 0 && "Invalid scale!");
313 // Check that this is a constant.
314 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
318 ScaledConstant = (int) C->getZExtValue();
319 if ((ScaledConstant % Scale) != 0)
322 ScaledConstant /= Scale;
323 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
326 void ARMDAGToDAGISel::PreprocessISelDAG() {
327 if (!Subtarget->hasV6T2Ops())
330 bool isThumb2 = Subtarget->isThumb();
331 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
332 E = CurDAG->allnodes_end(); I != E; ) {
333 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
335 if (N->getOpcode() != ISD::ADD)
338 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
339 // leading zeros, followed by consecutive set bits, followed by 1 or 2
340 // trailing zeros, e.g. 1020.
341 // Transform the expression to
342 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
343 // of trailing zeros of c2. The left shift would be folded as an shifter
344 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
347 SDValue N0 = N->getOperand(0);
348 SDValue N1 = N->getOperand(1);
349 unsigned And_imm = 0;
350 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
351 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
357 // Check if the AND mask is an immediate of the form: 000.....1111111100
358 unsigned TZ = countTrailingZeros(And_imm);
359 if (TZ != 1 && TZ != 2)
360 // Be conservative here. Shifter operands aren't always free. e.g. On
361 // Swift, left shifter operand of 1 / 2 for free but others are not.
363 // ubfx r3, r1, #16, #8
364 // ldr.w r3, [r0, r3, lsl #2]
367 // and.w r2, r9, r1, lsr #14
371 if (And_imm & (And_imm + 1))
374 // Look for (and (srl X, c1), c2).
375 SDValue Srl = N1.getOperand(0);
376 unsigned Srl_imm = 0;
377 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
381 // Make sure first operand is not a shifter operand which would prevent
382 // folding of the left shift.
387 if (SelectT2ShifterOperandReg(N0, CPTmp0, CPTmp1))
390 if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1) ||
391 SelectRegShifterOperand(N0, CPTmp0, CPTmp1, CPTmp2))
395 // Now make the transformation.
396 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
398 CurDAG->getConstant(Srl_imm+TZ, MVT::i32));
399 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
400 Srl, CurDAG->getConstant(And_imm, MVT::i32));
401 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
402 N1, CurDAG->getConstant(TZ, MVT::i32));
403 CurDAG->UpdateNodeOperands(N, N0, N1);
407 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
408 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
409 /// least on current ARM implementations) which should be avoidded.
410 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
411 if (OptLevel == CodeGenOpt::None)
414 if (!CheckVMLxHazard)
417 if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9() &&
418 !Subtarget->isSwift())
424 SDNode *Use = *N->use_begin();
425 if (Use->getOpcode() == ISD::CopyToReg)
427 if (Use->isMachineOpcode()) {
428 const ARMBaseInstrInfo *TII =
429 static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
431 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
434 unsigned Opcode = MCID.getOpcode();
435 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
437 // vmlx feeding into another vmlx. We actually want to unfold
438 // the use later in the MLxExpansion pass. e.g.
440 // vmla (stall 8 cycles)
445 // This adds up to about 18 - 19 cycles.
448 // vmul (stall 4 cycles)
449 // vadd adds up to about 14 cycles.
450 return TII->isFpMLxInstruction(Opcode);
456 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
457 ARM_AM::ShiftOpc ShOpcVal,
459 if (!Subtarget->isLikeA9() && !Subtarget->isSwift())
461 if (Shift.hasOneUse())
464 return ShOpcVal == ARM_AM::lsl &&
465 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
468 bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
471 bool CheckProfitability) {
472 if (DisableShifterOp)
475 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
477 // Don't match base register only case. That is matched to a separate
478 // lower complexity pattern with explicit register operand.
479 if (ShOpcVal == ARM_AM::no_shift) return false;
481 BaseReg = N.getOperand(0);
482 unsigned ShImmVal = 0;
483 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
484 if (!RHS) return false;
485 ShImmVal = RHS->getZExtValue() & 31;
486 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
491 bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
495 bool CheckProfitability) {
496 if (DisableShifterOp)
499 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
501 // Don't match base register only case. That is matched to a separate
502 // lower complexity pattern with explicit register operand.
503 if (ShOpcVal == ARM_AM::no_shift) return false;
505 BaseReg = N.getOperand(0);
506 unsigned ShImmVal = 0;
507 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
508 if (RHS) return false;
510 ShReg = N.getOperand(1);
511 if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
513 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
519 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
522 // Match simple R + imm12 operands.
525 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
526 !CurDAG->isBaseWithConstantOffset(N)) {
527 if (N.getOpcode() == ISD::FrameIndex) {
528 // Match frame index.
529 int FI = cast<FrameIndexSDNode>(N)->getIndex();
530 Base = CurDAG->getTargetFrameIndex(FI,
531 getTargetLowering()->getPointerTy());
532 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
536 if (N.getOpcode() == ARMISD::Wrapper &&
537 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
538 Base = N.getOperand(0);
541 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
545 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
546 int RHSC = (int)RHS->getZExtValue();
547 if (N.getOpcode() == ISD::SUB)
550 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
551 Base = N.getOperand(0);
552 if (Base.getOpcode() == ISD::FrameIndex) {
553 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
554 Base = CurDAG->getTargetFrameIndex(FI,
555 getTargetLowering()->getPointerTy());
557 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
564 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
570 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
572 if (N.getOpcode() == ISD::MUL &&
573 ((!Subtarget->isLikeA9() && !Subtarget->isSwift()) || N.hasOneUse())) {
574 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
575 // X * [3,5,9] -> X + X * [2,4,8] etc.
576 int RHSC = (int)RHS->getZExtValue();
579 ARM_AM::AddrOpc AddSub = ARM_AM::add;
581 AddSub = ARM_AM::sub;
584 if (isPowerOf2_32(RHSC)) {
585 unsigned ShAmt = Log2_32(RHSC);
586 Base = Offset = N.getOperand(0);
587 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
596 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
597 // ISD::OR that is equivalent to an ISD::ADD.
598 !CurDAG->isBaseWithConstantOffset(N))
601 // Leave simple R +/- imm12 operands for LDRi12
602 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
604 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
605 -0x1000+1, 0x1000, RHSC)) // 12 bits.
609 // Otherwise this is R +/- [possibly shifted] R.
610 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
611 ARM_AM::ShiftOpc ShOpcVal =
612 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
615 Base = N.getOperand(0);
616 Offset = N.getOperand(1);
618 if (ShOpcVal != ARM_AM::no_shift) {
619 // Check to see if the RHS of the shift is a constant, if not, we can't fold
621 if (ConstantSDNode *Sh =
622 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
623 ShAmt = Sh->getZExtValue();
624 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
625 Offset = N.getOperand(1).getOperand(0);
628 ShOpcVal = ARM_AM::no_shift;
631 ShOpcVal = ARM_AM::no_shift;
635 // Try matching (R shl C) + (R).
636 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
637 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
638 N.getOperand(0).hasOneUse())) {
639 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
640 if (ShOpcVal != ARM_AM::no_shift) {
641 // Check to see if the RHS of the shift is a constant, if not, we can't
643 if (ConstantSDNode *Sh =
644 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
645 ShAmt = Sh->getZExtValue();
646 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
647 Offset = N.getOperand(0).getOperand(0);
648 Base = N.getOperand(1);
651 ShOpcVal = ARM_AM::no_shift;
654 ShOpcVal = ARM_AM::no_shift;
659 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
667 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
671 if (N.getOpcode() == ISD::MUL &&
672 (!(Subtarget->isLikeA9() || Subtarget->isSwift()) || N.hasOneUse())) {
673 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
674 // X * [3,5,9] -> X + X * [2,4,8] etc.
675 int RHSC = (int)RHS->getZExtValue();
678 ARM_AM::AddrOpc AddSub = ARM_AM::add;
680 AddSub = ARM_AM::sub;
683 if (isPowerOf2_32(RHSC)) {
684 unsigned ShAmt = Log2_32(RHSC);
685 Base = Offset = N.getOperand(0);
686 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
695 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
696 // ISD::OR that is equivalent to an ADD.
697 !CurDAG->isBaseWithConstantOffset(N)) {
699 if (N.getOpcode() == ISD::FrameIndex) {
700 int FI = cast<FrameIndexSDNode>(N)->getIndex();
701 Base = CurDAG->getTargetFrameIndex(FI,
702 getTargetLowering()->getPointerTy());
703 } else if (N.getOpcode() == ARMISD::Wrapper &&
704 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
705 Base = N.getOperand(0);
707 Offset = CurDAG->getRegister(0, MVT::i32);
708 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
714 // Match simple R +/- imm12 operands.
715 if (N.getOpcode() != ISD::SUB) {
717 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
718 -0x1000+1, 0x1000, RHSC)) { // 12 bits.
719 Base = N.getOperand(0);
720 if (Base.getOpcode() == ISD::FrameIndex) {
721 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
722 Base = CurDAG->getTargetFrameIndex(FI,
723 getTargetLowering()->getPointerTy());
725 Offset = CurDAG->getRegister(0, MVT::i32);
727 ARM_AM::AddrOpc AddSub = ARM_AM::add;
729 AddSub = ARM_AM::sub;
732 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
739 if ((Subtarget->isLikeA9() || Subtarget->isSwift()) && !N.hasOneUse()) {
740 // Compute R +/- (R << N) and reuse it.
742 Offset = CurDAG->getRegister(0, MVT::i32);
743 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
749 // Otherwise this is R +/- [possibly shifted] R.
750 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
751 ARM_AM::ShiftOpc ShOpcVal =
752 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
755 Base = N.getOperand(0);
756 Offset = N.getOperand(1);
758 if (ShOpcVal != ARM_AM::no_shift) {
759 // Check to see if the RHS of the shift is a constant, if not, we can't fold
761 if (ConstantSDNode *Sh =
762 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
763 ShAmt = Sh->getZExtValue();
764 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
765 Offset = N.getOperand(1).getOperand(0);
768 ShOpcVal = ARM_AM::no_shift;
771 ShOpcVal = ARM_AM::no_shift;
775 // Try matching (R shl C) + (R).
776 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
777 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
778 N.getOperand(0).hasOneUse())) {
779 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
780 if (ShOpcVal != ARM_AM::no_shift) {
781 // Check to see if the RHS of the shift is a constant, if not, we can't
783 if (ConstantSDNode *Sh =
784 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
785 ShAmt = Sh->getZExtValue();
786 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
787 Offset = N.getOperand(0).getOperand(0);
788 Base = N.getOperand(1);
791 ShOpcVal = ARM_AM::no_shift;
794 ShOpcVal = ARM_AM::no_shift;
799 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
804 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
805 SDValue &Offset, SDValue &Opc) {
806 unsigned Opcode = Op->getOpcode();
807 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
808 ? cast<LoadSDNode>(Op)->getAddressingMode()
809 : cast<StoreSDNode>(Op)->getAddressingMode();
810 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
811 ? ARM_AM::add : ARM_AM::sub;
813 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
817 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
819 if (ShOpcVal != ARM_AM::no_shift) {
820 // Check to see if the RHS of the shift is a constant, if not, we can't fold
822 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
823 ShAmt = Sh->getZExtValue();
824 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
825 Offset = N.getOperand(0);
828 ShOpcVal = ARM_AM::no_shift;
831 ShOpcVal = ARM_AM::no_shift;
835 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
840 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
841 SDValue &Offset, SDValue &Opc) {
842 unsigned Opcode = Op->getOpcode();
843 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
844 ? cast<LoadSDNode>(Op)->getAddressingMode()
845 : cast<StoreSDNode>(Op)->getAddressingMode();
846 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
847 ? ARM_AM::add : ARM_AM::sub;
849 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
850 if (AddSub == ARM_AM::sub) Val *= -1;
851 Offset = CurDAG->getRegister(0, MVT::i32);
852 Opc = CurDAG->getTargetConstant(Val, MVT::i32);
860 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
861 SDValue &Offset, SDValue &Opc) {
862 unsigned Opcode = Op->getOpcode();
863 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
864 ? cast<LoadSDNode>(Op)->getAddressingMode()
865 : cast<StoreSDNode>(Op)->getAddressingMode();
866 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
867 ? ARM_AM::add : ARM_AM::sub;
869 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
870 Offset = CurDAG->getRegister(0, MVT::i32);
871 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
880 bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
885 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
886 SDValue &Base, SDValue &Offset,
888 if (N.getOpcode() == ISD::SUB) {
889 // X - C is canonicalize to X + -C, no need to handle it here.
890 Base = N.getOperand(0);
891 Offset = N.getOperand(1);
892 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
896 if (!CurDAG->isBaseWithConstantOffset(N)) {
898 if (N.getOpcode() == ISD::FrameIndex) {
899 int FI = cast<FrameIndexSDNode>(N)->getIndex();
900 Base = CurDAG->getTargetFrameIndex(FI,
901 getTargetLowering()->getPointerTy());
903 Offset = CurDAG->getRegister(0, MVT::i32);
904 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
908 // If the RHS is +/- imm8, fold into addr mode.
910 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
911 -256 + 1, 256, RHSC)) { // 8 bits.
912 Base = N.getOperand(0);
913 if (Base.getOpcode() == ISD::FrameIndex) {
914 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
915 Base = CurDAG->getTargetFrameIndex(FI,
916 getTargetLowering()->getPointerTy());
918 Offset = CurDAG->getRegister(0, MVT::i32);
920 ARM_AM::AddrOpc AddSub = ARM_AM::add;
922 AddSub = ARM_AM::sub;
925 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
929 Base = N.getOperand(0);
930 Offset = N.getOperand(1);
931 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
935 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
936 SDValue &Offset, SDValue &Opc) {
937 unsigned Opcode = Op->getOpcode();
938 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
939 ? cast<LoadSDNode>(Op)->getAddressingMode()
940 : cast<StoreSDNode>(Op)->getAddressingMode();
941 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
942 ? ARM_AM::add : ARM_AM::sub;
944 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
945 Offset = CurDAG->getRegister(0, MVT::i32);
946 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
951 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
955 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
956 SDValue &Base, SDValue &Offset) {
957 if (!CurDAG->isBaseWithConstantOffset(N)) {
959 if (N.getOpcode() == ISD::FrameIndex) {
960 int FI = cast<FrameIndexSDNode>(N)->getIndex();
961 Base = CurDAG->getTargetFrameIndex(FI,
962 getTargetLowering()->getPointerTy());
963 } else if (N.getOpcode() == ARMISD::Wrapper &&
964 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
965 Base = N.getOperand(0);
967 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
972 // If the RHS is +/- imm8, fold into addr mode.
974 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
975 -256 + 1, 256, RHSC)) {
976 Base = N.getOperand(0);
977 if (Base.getOpcode() == ISD::FrameIndex) {
978 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
979 Base = CurDAG->getTargetFrameIndex(FI,
980 getTargetLowering()->getPointerTy());
983 ARM_AM::AddrOpc AddSub = ARM_AM::add;
985 AddSub = ARM_AM::sub;
988 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
994 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
999 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
1003 unsigned Alignment = 0;
1004 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
1005 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
1006 // The maximum alignment is equal to the memory size being referenced.
1007 unsigned LSNAlign = LSN->getAlignment();
1008 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
1009 if (LSNAlign >= MemSize && MemSize > 1)
1010 Alignment = MemSize;
1012 // All other uses of addrmode6 are for intrinsics. For now just record
1013 // the raw alignment value; it will be refined later based on the legal
1014 // alignment operands for the intrinsic.
1015 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
1018 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1022 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
1024 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
1025 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
1026 if (AM != ISD::POST_INC)
1029 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
1030 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
1031 Offset = CurDAG->getRegister(0, MVT::i32);
1036 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
1037 SDValue &Offset, SDValue &Label) {
1038 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
1039 Offset = N.getOperand(0);
1040 SDValue N1 = N.getOperand(1);
1041 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
1050 //===----------------------------------------------------------------------===//
1051 // Thumb Addressing Modes
1052 //===----------------------------------------------------------------------===//
1054 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
1055 SDValue &Base, SDValue &Offset){
1056 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1057 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
1058 if (!NC || !NC->isNullValue())
1065 Base = N.getOperand(0);
1066 Offset = N.getOperand(1);
1071 ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
1072 SDValue &Offset, unsigned Scale) {
1074 SDValue TmpBase, TmpOffImm;
1075 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1076 return false; // We want to select tLDRspi / tSTRspi instead.
1078 if (N.getOpcode() == ARMISD::Wrapper &&
1079 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1080 return false; // We want to select tLDRpci instead.
1083 if (!CurDAG->isBaseWithConstantOffset(N))
1086 // Thumb does not have [sp, r] address mode.
1087 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1088 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1089 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1090 (RHSR && RHSR->getReg() == ARM::SP))
1093 // FIXME: Why do we explicitly check for a match here and then return false?
1094 // Presumably to allow something else to match, but shouldn't this be
1097 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1100 Base = N.getOperand(0);
1101 Offset = N.getOperand(1);
1106 ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1109 return SelectThumbAddrModeRI(N, Base, Offset, 1);
1113 ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1116 return SelectThumbAddrModeRI(N, Base, Offset, 2);
1120 ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1123 return SelectThumbAddrModeRI(N, Base, Offset, 4);
1127 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1128 SDValue &Base, SDValue &OffImm) {
1130 SDValue TmpBase, TmpOffImm;
1131 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1132 return false; // We want to select tLDRspi / tSTRspi instead.
1134 if (N.getOpcode() == ARMISD::Wrapper &&
1135 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1136 return false; // We want to select tLDRpci instead.
1139 if (!CurDAG->isBaseWithConstantOffset(N)) {
1140 if (N.getOpcode() == ARMISD::Wrapper &&
1141 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
1142 Base = N.getOperand(0);
1147 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1151 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1152 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1153 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1154 (RHSR && RHSR->getReg() == ARM::SP)) {
1155 ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1156 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1157 unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1158 unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1160 // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1161 if (LHSC != 0 || RHSC != 0) return false;
1164 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1168 // If the RHS is + imm5 * scale, fold into addr mode.
1170 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1171 Base = N.getOperand(0);
1172 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1176 Base = N.getOperand(0);
1177 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1182 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1184 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1188 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1190 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1194 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1196 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1199 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1200 SDValue &Base, SDValue &OffImm) {
1201 if (N.getOpcode() == ISD::FrameIndex) {
1202 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1203 Base = CurDAG->getTargetFrameIndex(FI,
1204 getTargetLowering()->getPointerTy());
1205 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1209 if (!CurDAG->isBaseWithConstantOffset(N))
1212 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1213 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1214 (LHSR && LHSR->getReg() == ARM::SP)) {
1215 // If the RHS is + imm8 * scale, fold into addr mode.
1217 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1218 Base = N.getOperand(0);
1219 if (Base.getOpcode() == ISD::FrameIndex) {
1220 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1221 Base = CurDAG->getTargetFrameIndex(FI,
1222 getTargetLowering()->getPointerTy());
1224 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1233 //===----------------------------------------------------------------------===//
1234 // Thumb 2 Addressing Modes
1235 //===----------------------------------------------------------------------===//
1238 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1240 if (DisableShifterOp)
1243 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1245 // Don't match base register only case. That is matched to a separate
1246 // lower complexity pattern with explicit register operand.
1247 if (ShOpcVal == ARM_AM::no_shift) return false;
1249 BaseReg = N.getOperand(0);
1250 unsigned ShImmVal = 0;
1251 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1252 ShImmVal = RHS->getZExtValue() & 31;
1253 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1260 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1261 SDValue &Base, SDValue &OffImm) {
1262 // Match simple R + imm12 operands.
1265 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1266 !CurDAG->isBaseWithConstantOffset(N)) {
1267 if (N.getOpcode() == ISD::FrameIndex) {
1268 // Match frame index.
1269 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1270 Base = CurDAG->getTargetFrameIndex(FI,
1271 getTargetLowering()->getPointerTy());
1272 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1276 if (N.getOpcode() == ARMISD::Wrapper &&
1277 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
1278 Base = N.getOperand(0);
1279 if (Base.getOpcode() == ISD::TargetConstantPool)
1280 return false; // We want to select t2LDRpci instead.
1283 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1287 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1288 if (SelectT2AddrModeImm8(N, Base, OffImm))
1289 // Let t2LDRi8 handle (R - imm8).
1292 int RHSC = (int)RHS->getZExtValue();
1293 if (N.getOpcode() == ISD::SUB)
1296 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1297 Base = N.getOperand(0);
1298 if (Base.getOpcode() == ISD::FrameIndex) {
1299 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1300 Base = CurDAG->getTargetFrameIndex(FI,
1301 getTargetLowering()->getPointerTy());
1303 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1310 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1314 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1315 SDValue &Base, SDValue &OffImm) {
1316 // Match simple R - imm8 operands.
1317 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1318 !CurDAG->isBaseWithConstantOffset(N))
1321 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1322 int RHSC = (int)RHS->getSExtValue();
1323 if (N.getOpcode() == ISD::SUB)
1326 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1327 Base = N.getOperand(0);
1328 if (Base.getOpcode() == ISD::FrameIndex) {
1329 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1330 Base = CurDAG->getTargetFrameIndex(FI,
1331 getTargetLowering()->getPointerTy());
1333 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1341 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1343 unsigned Opcode = Op->getOpcode();
1344 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1345 ? cast<LoadSDNode>(Op)->getAddressingMode()
1346 : cast<StoreSDNode>(Op)->getAddressingMode();
1348 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1349 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1350 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1351 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1358 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1360 SDValue &OffReg, SDValue &ShImm) {
1361 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1362 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1365 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1366 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1367 int RHSC = (int)RHS->getZExtValue();
1368 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1370 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1374 // Look for (R + R) or (R + (R << [1,2,3])).
1376 Base = N.getOperand(0);
1377 OffReg = N.getOperand(1);
1379 // Swap if it is ((R << c) + R).
1380 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1381 if (ShOpcVal != ARM_AM::lsl) {
1382 ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1383 if (ShOpcVal == ARM_AM::lsl)
1384 std::swap(Base, OffReg);
1387 if (ShOpcVal == ARM_AM::lsl) {
1388 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1390 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1391 ShAmt = Sh->getZExtValue();
1392 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1393 OffReg = OffReg.getOperand(0);
1396 ShOpcVal = ARM_AM::no_shift;
1399 ShOpcVal = ARM_AM::no_shift;
1403 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1408 bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
1410 // This *must* succeed since it's used for the irreplacable ldrex and strex
1413 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1415 if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
1418 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1422 uint32_t RHSC = (int)RHS->getZExtValue();
1423 if (RHSC > 1020 || RHSC % 4 != 0)
1426 Base = N.getOperand(0);
1427 if (Base.getOpcode() == ISD::FrameIndex) {
1428 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1429 Base = CurDAG->getTargetFrameIndex(FI, getTargetLowering()->getPointerTy());
1432 OffImm = CurDAG->getTargetConstant(RHSC / 4, MVT::i32);
1436 //===--------------------------------------------------------------------===//
1438 /// getAL - Returns a ARMCC::AL immediate node.
1439 static inline SDValue getAL(SelectionDAG *CurDAG) {
1440 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1443 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1444 LoadSDNode *LD = cast<LoadSDNode>(N);
1445 ISD::MemIndexedMode AM = LD->getAddressingMode();
1446 if (AM == ISD::UNINDEXED)
1449 EVT LoadedVT = LD->getMemoryVT();
1450 SDValue Offset, AMOpc;
1451 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1452 unsigned Opcode = 0;
1454 if (LoadedVT == MVT::i32 && isPre &&
1455 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1456 Opcode = ARM::LDR_PRE_IMM;
1458 } else if (LoadedVT == MVT::i32 && !isPre &&
1459 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1460 Opcode = ARM::LDR_POST_IMM;
1462 } else if (LoadedVT == MVT::i32 &&
1463 SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1464 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1467 } else if (LoadedVT == MVT::i16 &&
1468 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1470 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1471 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1472 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1473 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1474 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1475 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1477 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1481 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1483 Opcode = ARM::LDRB_PRE_IMM;
1484 } else if (!isPre &&
1485 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1487 Opcode = ARM::LDRB_POST_IMM;
1488 } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1490 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1496 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1497 SDValue Chain = LD->getChain();
1498 SDValue Base = LD->getBasePtr();
1499 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1500 CurDAG->getRegister(0, MVT::i32), Chain };
1501 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1502 MVT::i32, MVT::Other, Ops);
1504 SDValue Chain = LD->getChain();
1505 SDValue Base = LD->getBasePtr();
1506 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1507 CurDAG->getRegister(0, MVT::i32), Chain };
1508 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1509 MVT::i32, MVT::Other, Ops);
1516 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1517 LoadSDNode *LD = cast<LoadSDNode>(N);
1518 ISD::MemIndexedMode AM = LD->getAddressingMode();
1519 if (AM == ISD::UNINDEXED)
1522 EVT LoadedVT = LD->getMemoryVT();
1523 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1525 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1526 unsigned Opcode = 0;
1528 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1529 switch (LoadedVT.getSimpleVT().SimpleTy) {
1531 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1535 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1537 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1542 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1544 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1553 SDValue Chain = LD->getChain();
1554 SDValue Base = LD->getBasePtr();
1555 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1556 CurDAG->getRegister(0, MVT::i32), Chain };
1557 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
1564 /// \brief Form a GPRPair pseudo register from a pair of GPR regs.
1565 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1566 SDLoc dl(V0.getNode());
1568 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);
1569 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
1570 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
1571 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1572 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1575 /// \brief Form a D register from a pair of S registers.
1576 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1577 SDLoc dl(V0.getNode());
1579 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1580 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1581 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1582 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1583 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1586 /// \brief Form a quad register from a pair of D registers.
1587 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1588 SDLoc dl(V0.getNode());
1589 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1590 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1591 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1592 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1593 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1596 /// \brief Form 4 consecutive D registers from a pair of Q registers.
1597 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1598 SDLoc dl(V0.getNode());
1599 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1600 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1601 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1602 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1603 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1606 /// \brief Form 4 consecutive S registers.
1607 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1608 SDValue V2, SDValue V3) {
1609 SDLoc dl(V0.getNode());
1611 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1612 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1613 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1614 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1615 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1616 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1617 V2, SubReg2, V3, SubReg3 };
1618 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1621 /// \brief Form 4 consecutive D registers.
1622 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1623 SDValue V2, SDValue V3) {
1624 SDLoc dl(V0.getNode());
1625 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1626 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1627 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1628 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1629 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1630 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1631 V2, SubReg2, V3, SubReg3 };
1632 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1635 /// \brief Form 4 consecutive Q registers.
1636 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1637 SDValue V2, SDValue V3) {
1638 SDLoc dl(V0.getNode());
1639 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1640 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1641 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1642 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1643 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1644 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1645 V2, SubReg2, V3, SubReg3 };
1646 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1649 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1650 /// of a NEON VLD or VST instruction. The supported values depend on the
1651 /// number of registers being loaded.
1652 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1653 bool is64BitVector) {
1654 unsigned NumRegs = NumVecs;
1655 if (!is64BitVector && NumVecs < 3)
1658 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1659 if (Alignment >= 32 && NumRegs == 4)
1661 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1663 else if (Alignment >= 8)
1668 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1671 // Get the register stride update opcode of a VLD/VST instruction that
1672 // is otherwise equivalent to the given fixed stride updating instruction.
1673 static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1676 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1677 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1678 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1679 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1680 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1681 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1682 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1683 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1685 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1686 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1687 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1688 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1689 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1690 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1691 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1692 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1693 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1694 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1696 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1697 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1698 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1699 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1700 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1701 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1703 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1704 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1705 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1706 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1707 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1708 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1710 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1711 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1712 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
1714 return Opc; // If not one we handle, return it unchanged.
1717 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1718 const uint16_t *DOpcodes,
1719 const uint16_t *QOpcodes0,
1720 const uint16_t *QOpcodes1) {
1721 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1724 SDValue MemAddr, Align;
1725 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1726 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1729 SDValue Chain = N->getOperand(0);
1730 EVT VT = N->getValueType(0);
1731 bool is64BitVector = VT.is64BitVector();
1732 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1734 unsigned OpcodeIndex;
1735 switch (VT.getSimpleVT().SimpleTy) {
1736 default: llvm_unreachable("unhandled vld type");
1737 // Double-register operations:
1738 case MVT::v8i8: OpcodeIndex = 0; break;
1739 case MVT::v4i16: OpcodeIndex = 1; break;
1741 case MVT::v2i32: OpcodeIndex = 2; break;
1742 case MVT::v1i64: OpcodeIndex = 3; break;
1743 // Quad-register operations:
1744 case MVT::v16i8: OpcodeIndex = 0; break;
1745 case MVT::v8i16: OpcodeIndex = 1; break;
1747 case MVT::v4i32: OpcodeIndex = 2; break;
1748 case MVT::v2i64: OpcodeIndex = 3;
1749 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1757 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1760 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1762 std::vector<EVT> ResTys;
1763 ResTys.push_back(ResTy);
1765 ResTys.push_back(MVT::i32);
1766 ResTys.push_back(MVT::Other);
1768 SDValue Pred = getAL(CurDAG);
1769 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1771 SmallVector<SDValue, 7> Ops;
1773 // Double registers and VLD1/VLD2 quad registers are directly supported.
1774 if (is64BitVector || NumVecs <= 2) {
1775 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1776 QOpcodes0[OpcodeIndex]);
1777 Ops.push_back(MemAddr);
1778 Ops.push_back(Align);
1780 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1781 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1782 // case entirely when the rest are updated to that form, too.
1783 if ((NumVecs == 1 || NumVecs == 2) && !isa<ConstantSDNode>(Inc.getNode()))
1784 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1785 // We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1786 // check for that explicitly too. Horribly hacky, but temporary.
1787 if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64wb_fixed) ||
1788 !isa<ConstantSDNode>(Inc.getNode()))
1789 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1791 Ops.push_back(Pred);
1792 Ops.push_back(Reg0);
1793 Ops.push_back(Chain);
1794 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1797 // Otherwise, quad registers are loaded with two separate instructions,
1798 // where one loads the even registers and the other loads the odd registers.
1799 EVT AddrTy = MemAddr.getValueType();
1801 // Load the even subregs. This is always an updating load, so that it
1802 // provides the address to the second load for the odd subregs.
1804 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1805 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1806 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1807 ResTy, AddrTy, MVT::Other, OpsA);
1808 Chain = SDValue(VLdA, 2);
1810 // Load the odd subregs.
1811 Ops.push_back(SDValue(VLdA, 1));
1812 Ops.push_back(Align);
1814 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1815 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1816 "only constant post-increment update allowed for VLD3/4");
1818 Ops.push_back(Reg0);
1820 Ops.push_back(SDValue(VLdA, 0));
1821 Ops.push_back(Pred);
1822 Ops.push_back(Reg0);
1823 Ops.push_back(Chain);
1824 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops);
1827 // Transfer memoperands.
1828 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1829 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1830 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1835 // Extract out the subregisters.
1836 SDValue SuperReg = SDValue(VLd, 0);
1837 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1838 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1839 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1840 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1841 ReplaceUses(SDValue(N, Vec),
1842 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1843 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1845 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1849 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1850 const uint16_t *DOpcodes,
1851 const uint16_t *QOpcodes0,
1852 const uint16_t *QOpcodes1) {
1853 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1856 SDValue MemAddr, Align;
1857 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1858 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1859 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1862 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1863 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1865 SDValue Chain = N->getOperand(0);
1866 EVT VT = N->getOperand(Vec0Idx).getValueType();
1867 bool is64BitVector = VT.is64BitVector();
1868 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1870 unsigned OpcodeIndex;
1871 switch (VT.getSimpleVT().SimpleTy) {
1872 default: llvm_unreachable("unhandled vst type");
1873 // Double-register operations:
1874 case MVT::v8i8: OpcodeIndex = 0; break;
1875 case MVT::v4i16: OpcodeIndex = 1; break;
1877 case MVT::v2i32: OpcodeIndex = 2; break;
1878 case MVT::v1i64: OpcodeIndex = 3; break;
1879 // Quad-register operations:
1880 case MVT::v16i8: OpcodeIndex = 0; break;
1881 case MVT::v8i16: OpcodeIndex = 1; break;
1883 case MVT::v4i32: OpcodeIndex = 2; break;
1884 case MVT::v2i64: OpcodeIndex = 3;
1885 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1889 std::vector<EVT> ResTys;
1891 ResTys.push_back(MVT::i32);
1892 ResTys.push_back(MVT::Other);
1894 SDValue Pred = getAL(CurDAG);
1895 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1896 SmallVector<SDValue, 7> Ops;
1898 // Double registers and VST1/VST2 quad registers are directly supported.
1899 if (is64BitVector || NumVecs <= 2) {
1902 SrcReg = N->getOperand(Vec0Idx);
1903 } else if (is64BitVector) {
1904 // Form a REG_SEQUENCE to force register allocation.
1905 SDValue V0 = N->getOperand(Vec0Idx + 0);
1906 SDValue V1 = N->getOperand(Vec0Idx + 1);
1908 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
1910 SDValue V2 = N->getOperand(Vec0Idx + 2);
1911 // If it's a vst3, form a quad D-register and leave the last part as
1913 SDValue V3 = (NumVecs == 3)
1914 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1915 : N->getOperand(Vec0Idx + 3);
1916 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
1919 // Form a QQ register.
1920 SDValue Q0 = N->getOperand(Vec0Idx);
1921 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1922 SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0);
1925 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1926 QOpcodes0[OpcodeIndex]);
1927 Ops.push_back(MemAddr);
1928 Ops.push_back(Align);
1930 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1931 // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
1932 // case entirely when the rest are updated to that form, too.
1933 if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1934 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1935 // We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
1936 // check for that explicitly too. Horribly hacky, but temporary.
1937 if ((NumVecs > 2 && Opc != ARM::VST1q64wb_fixed) ||
1938 !isa<ConstantSDNode>(Inc.getNode()))
1939 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1941 Ops.push_back(SrcReg);
1942 Ops.push_back(Pred);
1943 Ops.push_back(Reg0);
1944 Ops.push_back(Chain);
1945 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1947 // Transfer memoperands.
1948 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1953 // Otherwise, quad registers are stored with two separate instructions,
1954 // where one stores the even registers and the other stores the odd registers.
1956 // Form the QQQQ REG_SEQUENCE.
1957 SDValue V0 = N->getOperand(Vec0Idx + 0);
1958 SDValue V1 = N->getOperand(Vec0Idx + 1);
1959 SDValue V2 = N->getOperand(Vec0Idx + 2);
1960 SDValue V3 = (NumVecs == 3)
1961 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1962 : N->getOperand(Vec0Idx + 3);
1963 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
1965 // Store the even D registers. This is always an updating store, so that it
1966 // provides the address to the second store for the odd subregs.
1967 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1968 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1969 MemAddr.getValueType(),
1971 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
1972 Chain = SDValue(VStA, 1);
1974 // Store the odd D registers.
1975 Ops.push_back(SDValue(VStA, 0));
1976 Ops.push_back(Align);
1978 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1979 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1980 "only constant post-increment update allowed for VST3/4");
1982 Ops.push_back(Reg0);
1984 Ops.push_back(RegSeq);
1985 Ops.push_back(Pred);
1986 Ops.push_back(Reg0);
1987 Ops.push_back(Chain);
1988 SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1990 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
1994 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1995 bool isUpdating, unsigned NumVecs,
1996 const uint16_t *DOpcodes,
1997 const uint16_t *QOpcodes) {
1998 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
2001 SDValue MemAddr, Align;
2002 unsigned AddrOpIdx = isUpdating ? 1 : 2;
2003 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
2004 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
2007 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2008 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2010 SDValue Chain = N->getOperand(0);
2012 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
2013 EVT VT = N->getOperand(Vec0Idx).getValueType();
2014 bool is64BitVector = VT.is64BitVector();
2016 unsigned Alignment = 0;
2018 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2019 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2020 if (Alignment > NumBytes)
2021 Alignment = NumBytes;
2022 if (Alignment < 8 && Alignment < NumBytes)
2024 // Alignment must be a power of two; make sure of that.
2025 Alignment = (Alignment & -Alignment);
2029 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2031 unsigned OpcodeIndex;
2032 switch (VT.getSimpleVT().SimpleTy) {
2033 default: llvm_unreachable("unhandled vld/vst lane type");
2034 // Double-register operations:
2035 case MVT::v8i8: OpcodeIndex = 0; break;
2036 case MVT::v4i16: OpcodeIndex = 1; break;
2038 case MVT::v2i32: OpcodeIndex = 2; break;
2039 // Quad-register operations:
2040 case MVT::v8i16: OpcodeIndex = 0; break;
2042 case MVT::v4i32: OpcodeIndex = 1; break;
2045 std::vector<EVT> ResTys;
2047 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2050 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
2051 MVT::i64, ResTyElts));
2054 ResTys.push_back(MVT::i32);
2055 ResTys.push_back(MVT::Other);
2057 SDValue Pred = getAL(CurDAG);
2058 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2060 SmallVector<SDValue, 8> Ops;
2061 Ops.push_back(MemAddr);
2062 Ops.push_back(Align);
2064 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2065 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2069 SDValue V0 = N->getOperand(Vec0Idx + 0);
2070 SDValue V1 = N->getOperand(Vec0Idx + 1);
2073 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2075 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2077 SDValue V2 = N->getOperand(Vec0Idx + 2);
2078 SDValue V3 = (NumVecs == 3)
2079 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2080 : N->getOperand(Vec0Idx + 3);
2082 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2084 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2086 Ops.push_back(SuperReg);
2087 Ops.push_back(getI32Imm(Lane));
2088 Ops.push_back(Pred);
2089 Ops.push_back(Reg0);
2090 Ops.push_back(Chain);
2092 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
2093 QOpcodes[OpcodeIndex]);
2094 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2095 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
2099 // Extract the subregisters.
2100 SuperReg = SDValue(VLdLn, 0);
2101 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
2102 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
2103 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2104 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2105 ReplaceUses(SDValue(N, Vec),
2106 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2107 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2109 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2113 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
2115 const uint16_t *Opcodes) {
2116 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2119 SDValue MemAddr, Align;
2120 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
2123 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2124 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2126 SDValue Chain = N->getOperand(0);
2127 EVT VT = N->getValueType(0);
2129 unsigned Alignment = 0;
2131 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2132 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2133 if (Alignment > NumBytes)
2134 Alignment = NumBytes;
2135 if (Alignment < 8 && Alignment < NumBytes)
2137 // Alignment must be a power of two; make sure of that.
2138 Alignment = (Alignment & -Alignment);
2142 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2144 unsigned OpcodeIndex;
2145 switch (VT.getSimpleVT().SimpleTy) {
2146 default: llvm_unreachable("unhandled vld-dup type");
2147 case MVT::v8i8: OpcodeIndex = 0; break;
2148 case MVT::v4i16: OpcodeIndex = 1; break;
2150 case MVT::v2i32: OpcodeIndex = 2; break;
2153 SDValue Pred = getAL(CurDAG);
2154 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2156 unsigned Opc = Opcodes[OpcodeIndex];
2157 SmallVector<SDValue, 6> Ops;
2158 Ops.push_back(MemAddr);
2159 Ops.push_back(Align);
2161 // fixed-stride update instructions don't have an explicit writeback
2162 // operand. It's implicit in the opcode itself.
2163 SDValue Inc = N->getOperand(2);
2164 if (!isa<ConstantSDNode>(Inc.getNode()))
2166 // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
2167 else if (NumVecs > 2)
2168 Ops.push_back(Reg0);
2170 Ops.push_back(Pred);
2171 Ops.push_back(Reg0);
2172 Ops.push_back(Chain);
2174 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2175 std::vector<EVT> ResTys;
2176 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2178 ResTys.push_back(MVT::i32);
2179 ResTys.push_back(MVT::Other);
2180 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2181 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2182 SuperReg = SDValue(VLdDup, 0);
2184 // Extract the subregisters.
2185 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2186 unsigned SubIdx = ARM::dsub_0;
2187 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2188 ReplaceUses(SDValue(N, Vec),
2189 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2190 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2192 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2196 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2198 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2200 EVT VT = N->getValueType(0);
2201 unsigned FirstTblReg = IsExt ? 2 : 1;
2203 // Form a REG_SEQUENCE to force register allocation.
2205 SDValue V0 = N->getOperand(FirstTblReg + 0);
2206 SDValue V1 = N->getOperand(FirstTblReg + 1);
2208 RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
2210 SDValue V2 = N->getOperand(FirstTblReg + 2);
2211 // If it's a vtbl3, form a quad D-register and leave the last part as
2213 SDValue V3 = (NumVecs == 3)
2214 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2215 : N->getOperand(FirstTblReg + 3);
2216 RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2219 SmallVector<SDValue, 6> Ops;
2221 Ops.push_back(N->getOperand(1));
2222 Ops.push_back(RegSeq);
2223 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2224 Ops.push_back(getAL(CurDAG)); // predicate
2225 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2226 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2229 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2231 if (!Subtarget->hasV6T2Ops())
2234 unsigned Opc = isSigned
2235 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2236 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2238 // For unsigned extracts, check for a shift right and mask
2239 unsigned And_imm = 0;
2240 if (N->getOpcode() == ISD::AND) {
2241 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2243 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2244 if (And_imm & (And_imm + 1))
2247 unsigned Srl_imm = 0;
2248 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2250 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2252 // Note: The width operand is encoded as width-1.
2253 unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2254 unsigned LSB = Srl_imm;
2256 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2258 if ((LSB + Width + 1) == N->getValueType(0).getSizeInBits()) {
2259 // It's cheaper to use a right shift to extract the top bits.
2260 if (Subtarget->isThumb()) {
2261 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
2262 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2263 CurDAG->getTargetConstant(LSB, MVT::i32),
2264 getAL(CurDAG), Reg0, Reg0 };
2265 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2268 // ARM models shift instructions as MOVsi with shifter operand.
2269 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
2271 CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, LSB),
2273 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
2274 getAL(CurDAG), Reg0, Reg0 };
2275 return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops, 5);
2278 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2279 CurDAG->getTargetConstant(LSB, MVT::i32),
2280 CurDAG->getTargetConstant(Width, MVT::i32),
2281 getAL(CurDAG), Reg0 };
2282 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2288 // Otherwise, we're looking for a shift of a shift
2289 unsigned Shl_imm = 0;
2290 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2291 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2292 unsigned Srl_imm = 0;
2293 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2294 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2295 // Note: The width operand is encoded as width-1.
2296 unsigned Width = 32 - Srl_imm - 1;
2297 int LSB = Srl_imm - Shl_imm;
2300 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2301 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2302 CurDAG->getTargetConstant(LSB, MVT::i32),
2303 CurDAG->getTargetConstant(Width, MVT::i32),
2304 getAL(CurDAG), Reg0 };
2305 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2311 /// Target-specific DAG combining for ISD::XOR.
2312 /// Target-independent combining lowers SELECT_CC nodes of the form
2313 /// select_cc setg[ge] X, 0, X, -X
2314 /// select_cc setgt X, -1, X, -X
2315 /// select_cc setl[te] X, 0, -X, X
2316 /// select_cc setlt X, 1, -X, X
2317 /// which represent Integer ABS into:
2318 /// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2319 /// ARM instruction selection detects the latter and matches it to
2320 /// ARM::ABS or ARM::t2ABS machine node.
2321 SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2322 SDValue XORSrc0 = N->getOperand(0);
2323 SDValue XORSrc1 = N->getOperand(1);
2324 EVT VT = N->getValueType(0);
2326 if (Subtarget->isThumb1Only())
2329 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2332 SDValue ADDSrc0 = XORSrc0.getOperand(0);
2333 SDValue ADDSrc1 = XORSrc0.getOperand(1);
2334 SDValue SRASrc0 = XORSrc1.getOperand(0);
2335 SDValue SRASrc1 = XORSrc1.getOperand(1);
2336 ConstantSDNode *SRAConstant = dyn_cast<ConstantSDNode>(SRASrc1);
2337 EVT XType = SRASrc0.getValueType();
2338 unsigned Size = XType.getSizeInBits() - 1;
2340 if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
2341 XType.isInteger() && SRAConstant != NULL &&
2342 Size == SRAConstant->getZExtValue()) {
2343 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
2344 return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2350 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2351 // The only time a CONCAT_VECTORS operation can have legal types is when
2352 // two 64-bit vectors are concatenated to a 128-bit vector.
2353 EVT VT = N->getValueType(0);
2354 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2355 llvm_unreachable("unexpected CONCAT_VECTORS");
2356 return createDRegPairNode(VT, N->getOperand(0), N->getOperand(1));
2359 SDNode *ARMDAGToDAGISel::SelectAtomic(SDNode *Node, unsigned Op8,
2360 unsigned Op16,unsigned Op32,
2362 // Mostly direct translation to the given operations, except that we preserve
2363 // the AtomicOrdering for use later on.
2364 AtomicSDNode *AN = cast<AtomicSDNode>(Node);
2365 EVT VT = AN->getMemoryVT();
2368 SDVTList VTs = CurDAG->getVTList(AN->getValueType(0), MVT::Other);
2371 else if (VT == MVT::i16)
2373 else if (VT == MVT::i32)
2375 else if (VT == MVT::i64) {
2377 VTs = CurDAG->getVTList(MVT::i32, MVT::i32, MVT::Other);
2379 llvm_unreachable("Unexpected atomic operation");
2381 SmallVector<SDValue, 6> Ops;
2382 for (unsigned i = 1; i < AN->getNumOperands(); ++i)
2383 Ops.push_back(AN->getOperand(i));
2385 Ops.push_back(CurDAG->getTargetConstant(AN->getOrdering(), MVT::i32));
2386 Ops.push_back(AN->getOperand(0)); // Chain moves to the end
2388 return CurDAG->SelectNodeTo(Node, Op, VTs, &Ops[0], Ops.size());
2391 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2394 if (N->isMachineOpcode()) {
2396 return NULL; // Already selected.
2399 switch (N->getOpcode()) {
2401 case ISD::INLINEASM: {
2402 SDNode *ResNode = SelectInlineAsm(N);
2408 // Select special operations if XOR node forms integer ABS pattern
2409 SDNode *ResNode = SelectABSOp(N);
2412 // Other cases are autogenerated.
2415 case ISD::Constant: {
2416 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2418 if (Subtarget->hasThumb2())
2419 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2420 // be done with MOV + MOVT, at worst.
2423 if (Subtarget->isThumb()) {
2424 UseCP = (Val > 255 && // MOV
2425 ~Val > 255 && // MOV + MVN
2426 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
2428 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2429 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2430 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
2435 CurDAG->getTargetConstantPool(ConstantInt::get(
2436 Type::getInt32Ty(*CurDAG->getContext()), Val),
2437 getTargetLowering()->getPointerTy());
2440 if (Subtarget->isThumb1Only()) {
2441 SDValue Pred = getAL(CurDAG);
2442 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2443 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2444 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2449 CurDAG->getTargetConstant(0, MVT::i32),
2451 CurDAG->getRegister(0, MVT::i32),
2452 CurDAG->getEntryNode()
2454 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2457 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2461 // Other cases are autogenerated.
2464 case ISD::FrameIndex: {
2465 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2466 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2467 SDValue TFI = CurDAG->getTargetFrameIndex(FI,
2468 getTargetLowering()->getPointerTy());
2469 if (Subtarget->isThumb1Only()) {
2470 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2471 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2472 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2474 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2475 ARM::t2ADDri : ARM::ADDri);
2476 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2477 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2478 CurDAG->getRegister(0, MVT::i32) };
2479 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2483 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2487 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2491 if (Subtarget->isThumb1Only())
2493 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2494 unsigned RHSV = C->getZExtValue();
2496 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2497 unsigned ShImm = Log2_32(RHSV-1);
2500 SDValue V = N->getOperand(0);
2501 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2502 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2503 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2504 if (Subtarget->isThumb()) {
2505 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2506 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2508 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2509 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2512 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2513 unsigned ShImm = Log2_32(RHSV+1);
2516 SDValue V = N->getOperand(0);
2517 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2518 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2519 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2520 if (Subtarget->isThumb()) {
2521 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2522 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2524 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2525 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2531 // Check for unsigned bitfield extract
2532 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2535 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2536 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2537 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2538 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2539 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2540 EVT VT = N->getValueType(0);
2543 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2545 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2548 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2549 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2552 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2553 SDValue N2 = N0.getOperand(1);
2554 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2557 unsigned N1CVal = N1C->getZExtValue();
2558 unsigned N2CVal = N2C->getZExtValue();
2559 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2560 (N1CVal & 0xffffU) == 0xffffU &&
2561 (N2CVal & 0xffffU) == 0x0U) {
2562 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2564 SDValue Ops[] = { N0.getOperand(0), Imm16,
2565 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2566 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2571 case ARMISD::VMOVRRD:
2572 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2573 N->getOperand(0), getAL(CurDAG),
2574 CurDAG->getRegister(0, MVT::i32));
2575 case ISD::UMUL_LOHI: {
2576 if (Subtarget->isThumb1Only())
2578 if (Subtarget->isThumb()) {
2579 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2580 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2581 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops);
2583 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2584 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2585 CurDAG->getRegister(0, MVT::i32) };
2586 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2587 ARM::UMULL : ARM::UMULLv5,
2588 dl, MVT::i32, MVT::i32, Ops);
2591 case ISD::SMUL_LOHI: {
2592 if (Subtarget->isThumb1Only())
2594 if (Subtarget->isThumb()) {
2595 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2596 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2597 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops);
2599 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2600 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2601 CurDAG->getRegister(0, MVT::i32) };
2602 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2603 ARM::SMULL : ARM::SMULLv5,
2604 dl, MVT::i32, MVT::i32, Ops);
2607 case ARMISD::UMLAL:{
2608 if (Subtarget->isThumb()) {
2609 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2610 N->getOperand(3), getAL(CurDAG),
2611 CurDAG->getRegister(0, MVT::i32)};
2612 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops);
2614 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2615 N->getOperand(3), getAL(CurDAG),
2616 CurDAG->getRegister(0, MVT::i32),
2617 CurDAG->getRegister(0, MVT::i32) };
2618 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2619 ARM::UMLAL : ARM::UMLALv5,
2620 dl, MVT::i32, MVT::i32, Ops);
2623 case ARMISD::SMLAL:{
2624 if (Subtarget->isThumb()) {
2625 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2626 N->getOperand(3), getAL(CurDAG),
2627 CurDAG->getRegister(0, MVT::i32)};
2628 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops);
2630 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2631 N->getOperand(3), getAL(CurDAG),
2632 CurDAG->getRegister(0, MVT::i32),
2633 CurDAG->getRegister(0, MVT::i32) };
2634 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2635 ARM::SMLAL : ARM::SMLALv5,
2636 dl, MVT::i32, MVT::i32, Ops);
2640 SDNode *ResNode = 0;
2641 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2642 ResNode = SelectT2IndexedLoad(N);
2644 ResNode = SelectARMIndexedLoad(N);
2647 // Other cases are autogenerated.
2650 case ARMISD::BRCOND: {
2651 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2652 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2653 // Pattern complexity = 6 cost = 1 size = 0
2655 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2656 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2657 // Pattern complexity = 6 cost = 1 size = 0
2659 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2660 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2661 // Pattern complexity = 6 cost = 1 size = 0
2663 unsigned Opc = Subtarget->isThumb() ?
2664 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2665 SDValue Chain = N->getOperand(0);
2666 SDValue N1 = N->getOperand(1);
2667 SDValue N2 = N->getOperand(2);
2668 SDValue N3 = N->getOperand(3);
2669 SDValue InFlag = N->getOperand(4);
2670 assert(N1.getOpcode() == ISD::BasicBlock);
2671 assert(N2.getOpcode() == ISD::Constant);
2672 assert(N3.getOpcode() == ISD::Register);
2674 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2675 cast<ConstantSDNode>(N2)->getZExtValue()),
2677 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2678 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2680 Chain = SDValue(ResNode, 0);
2681 if (N->getNumValues() == 2) {
2682 InFlag = SDValue(ResNode, 1);
2683 ReplaceUses(SDValue(N, 1), InFlag);
2685 ReplaceUses(SDValue(N, 0),
2686 SDValue(Chain.getNode(), Chain.getResNo()));
2689 case ARMISD::VZIP: {
2691 EVT VT = N->getValueType(0);
2692 switch (VT.getSimpleVT().SimpleTy) {
2693 default: return NULL;
2694 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2695 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2697 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2698 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2699 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2700 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2702 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2704 SDValue Pred = getAL(CurDAG);
2705 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2706 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2707 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2709 case ARMISD::VUZP: {
2711 EVT VT = N->getValueType(0);
2712 switch (VT.getSimpleVT().SimpleTy) {
2713 default: return NULL;
2714 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2715 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2717 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2718 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2719 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2720 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2722 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2724 SDValue Pred = getAL(CurDAG);
2725 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2726 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2727 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2729 case ARMISD::VTRN: {
2731 EVT VT = N->getValueType(0);
2732 switch (VT.getSimpleVT().SimpleTy) {
2733 default: return NULL;
2734 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2735 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2737 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2738 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2739 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2741 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2743 SDValue Pred = getAL(CurDAG);
2744 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2745 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2746 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2748 case ARMISD::BUILD_VECTOR: {
2749 EVT VecVT = N->getValueType(0);
2750 EVT EltVT = VecVT.getVectorElementType();
2751 unsigned NumElts = VecVT.getVectorNumElements();
2752 if (EltVT == MVT::f64) {
2753 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2754 return createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2756 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2758 return createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2759 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2760 return createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
2761 N->getOperand(2), N->getOperand(3));
2764 case ARMISD::VLD2DUP: {
2765 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
2767 return SelectVLDDup(N, false, 2, Opcodes);
2770 case ARMISD::VLD3DUP: {
2771 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
2772 ARM::VLD3DUPd16Pseudo,
2773 ARM::VLD3DUPd32Pseudo };
2774 return SelectVLDDup(N, false, 3, Opcodes);
2777 case ARMISD::VLD4DUP: {
2778 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
2779 ARM::VLD4DUPd16Pseudo,
2780 ARM::VLD4DUPd32Pseudo };
2781 return SelectVLDDup(N, false, 4, Opcodes);
2784 case ARMISD::VLD2DUP_UPD: {
2785 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
2786 ARM::VLD2DUPd16wb_fixed,
2787 ARM::VLD2DUPd32wb_fixed };
2788 return SelectVLDDup(N, true, 2, Opcodes);
2791 case ARMISD::VLD3DUP_UPD: {
2792 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
2793 ARM::VLD3DUPd16Pseudo_UPD,
2794 ARM::VLD3DUPd32Pseudo_UPD };
2795 return SelectVLDDup(N, true, 3, Opcodes);
2798 case ARMISD::VLD4DUP_UPD: {
2799 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
2800 ARM::VLD4DUPd16Pseudo_UPD,
2801 ARM::VLD4DUPd32Pseudo_UPD };
2802 return SelectVLDDup(N, true, 4, Opcodes);
2805 case ARMISD::VLD1_UPD: {
2806 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
2807 ARM::VLD1d16wb_fixed,
2808 ARM::VLD1d32wb_fixed,
2809 ARM::VLD1d64wb_fixed };
2810 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
2811 ARM::VLD1q16wb_fixed,
2812 ARM::VLD1q32wb_fixed,
2813 ARM::VLD1q64wb_fixed };
2814 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2817 case ARMISD::VLD2_UPD: {
2818 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
2819 ARM::VLD2d16wb_fixed,
2820 ARM::VLD2d32wb_fixed,
2821 ARM::VLD1q64wb_fixed};
2822 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
2823 ARM::VLD2q16PseudoWB_fixed,
2824 ARM::VLD2q32PseudoWB_fixed };
2825 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2828 case ARMISD::VLD3_UPD: {
2829 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
2830 ARM::VLD3d16Pseudo_UPD,
2831 ARM::VLD3d32Pseudo_UPD,
2832 ARM::VLD1q64wb_fixed};
2833 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2834 ARM::VLD3q16Pseudo_UPD,
2835 ARM::VLD3q32Pseudo_UPD };
2836 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2837 ARM::VLD3q16oddPseudo_UPD,
2838 ARM::VLD3q32oddPseudo_UPD };
2839 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2842 case ARMISD::VLD4_UPD: {
2843 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
2844 ARM::VLD4d16Pseudo_UPD,
2845 ARM::VLD4d32Pseudo_UPD,
2846 ARM::VLD1q64wb_fixed};
2847 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2848 ARM::VLD4q16Pseudo_UPD,
2849 ARM::VLD4q32Pseudo_UPD };
2850 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2851 ARM::VLD4q16oddPseudo_UPD,
2852 ARM::VLD4q32oddPseudo_UPD };
2853 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2856 case ARMISD::VLD2LN_UPD: {
2857 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
2858 ARM::VLD2LNd16Pseudo_UPD,
2859 ARM::VLD2LNd32Pseudo_UPD };
2860 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2861 ARM::VLD2LNq32Pseudo_UPD };
2862 return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2865 case ARMISD::VLD3LN_UPD: {
2866 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
2867 ARM::VLD3LNd16Pseudo_UPD,
2868 ARM::VLD3LNd32Pseudo_UPD };
2869 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2870 ARM::VLD3LNq32Pseudo_UPD };
2871 return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2874 case ARMISD::VLD4LN_UPD: {
2875 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
2876 ARM::VLD4LNd16Pseudo_UPD,
2877 ARM::VLD4LNd32Pseudo_UPD };
2878 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2879 ARM::VLD4LNq32Pseudo_UPD };
2880 return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2883 case ARMISD::VST1_UPD: {
2884 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
2885 ARM::VST1d16wb_fixed,
2886 ARM::VST1d32wb_fixed,
2887 ARM::VST1d64wb_fixed };
2888 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
2889 ARM::VST1q16wb_fixed,
2890 ARM::VST1q32wb_fixed,
2891 ARM::VST1q64wb_fixed };
2892 return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2895 case ARMISD::VST2_UPD: {
2896 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
2897 ARM::VST2d16wb_fixed,
2898 ARM::VST2d32wb_fixed,
2899 ARM::VST1q64wb_fixed};
2900 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
2901 ARM::VST2q16PseudoWB_fixed,
2902 ARM::VST2q32PseudoWB_fixed };
2903 return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2906 case ARMISD::VST3_UPD: {
2907 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
2908 ARM::VST3d16Pseudo_UPD,
2909 ARM::VST3d32Pseudo_UPD,
2910 ARM::VST1d64TPseudoWB_fixed};
2911 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2912 ARM::VST3q16Pseudo_UPD,
2913 ARM::VST3q32Pseudo_UPD };
2914 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2915 ARM::VST3q16oddPseudo_UPD,
2916 ARM::VST3q32oddPseudo_UPD };
2917 return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2920 case ARMISD::VST4_UPD: {
2921 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
2922 ARM::VST4d16Pseudo_UPD,
2923 ARM::VST4d32Pseudo_UPD,
2924 ARM::VST1d64QPseudoWB_fixed};
2925 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2926 ARM::VST4q16Pseudo_UPD,
2927 ARM::VST4q32Pseudo_UPD };
2928 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2929 ARM::VST4q16oddPseudo_UPD,
2930 ARM::VST4q32oddPseudo_UPD };
2931 return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2934 case ARMISD::VST2LN_UPD: {
2935 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
2936 ARM::VST2LNd16Pseudo_UPD,
2937 ARM::VST2LNd32Pseudo_UPD };
2938 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2939 ARM::VST2LNq32Pseudo_UPD };
2940 return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2943 case ARMISD::VST3LN_UPD: {
2944 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
2945 ARM::VST3LNd16Pseudo_UPD,
2946 ARM::VST3LNd32Pseudo_UPD };
2947 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2948 ARM::VST3LNq32Pseudo_UPD };
2949 return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2952 case ARMISD::VST4LN_UPD: {
2953 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
2954 ARM::VST4LNd16Pseudo_UPD,
2955 ARM::VST4LNd32Pseudo_UPD };
2956 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2957 ARM::VST4LNq32Pseudo_UPD };
2958 return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2961 case ISD::INTRINSIC_VOID:
2962 case ISD::INTRINSIC_W_CHAIN: {
2963 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2968 case Intrinsic::arm_ldrexd: {
2969 SDValue MemAddr = N->getOperand(2);
2971 SDValue Chain = N->getOperand(0);
2973 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
2974 unsigned NewOpc = isThumb ? ARM::t2LDREXD :ARM::LDREXD;
2976 // arm_ldrexd returns a i64 value in {i32, i32}
2977 std::vector<EVT> ResTys;
2979 ResTys.push_back(MVT::i32);
2980 ResTys.push_back(MVT::i32);
2982 ResTys.push_back(MVT::Untyped);
2983 ResTys.push_back(MVT::Other);
2985 // Place arguments in the right order.
2986 SmallVector<SDValue, 7> Ops;
2987 Ops.push_back(MemAddr);
2988 Ops.push_back(getAL(CurDAG));
2989 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2990 Ops.push_back(Chain);
2991 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
2992 // Transfer memoperands.
2993 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2994 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2995 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
2998 SDValue OutChain = isThumb ? SDValue(Ld, 2) : SDValue(Ld, 1);
2999 if (!SDValue(N, 0).use_empty()) {
3002 Result = SDValue(Ld, 0);
3004 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
3005 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3006 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3007 Result = SDValue(ResNode,0);
3009 ReplaceUses(SDValue(N, 0), Result);
3011 if (!SDValue(N, 1).use_empty()) {
3014 Result = SDValue(Ld, 1);
3016 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
3017 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3018 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3019 Result = SDValue(ResNode,0);
3021 ReplaceUses(SDValue(N, 1), Result);
3023 ReplaceUses(SDValue(N, 2), OutChain);
3027 case Intrinsic::arm_strexd: {
3029 SDValue Chain = N->getOperand(0);
3030 SDValue Val0 = N->getOperand(2);
3031 SDValue Val1 = N->getOperand(3);
3032 SDValue MemAddr = N->getOperand(4);
3034 // Store exclusive double return a i32 value which is the return status
3035 // of the issued store.
3036 EVT ResTys[] = { MVT::i32, MVT::Other };
3038 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3039 // Place arguments in the right order.
3040 SmallVector<SDValue, 7> Ops;
3042 Ops.push_back(Val0);
3043 Ops.push_back(Val1);
3045 // arm_strexd uses GPRPair.
3046 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
3047 Ops.push_back(MemAddr);
3048 Ops.push_back(getAL(CurDAG));
3049 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3050 Ops.push_back(Chain);
3052 unsigned NewOpc = isThumb ? ARM::t2STREXD : ARM::STREXD;
3054 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3055 // Transfer memoperands.
3056 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3057 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3058 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3063 case Intrinsic::arm_neon_vld1: {
3064 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3065 ARM::VLD1d32, ARM::VLD1d64 };
3066 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3067 ARM::VLD1q32, ARM::VLD1q64};
3068 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
3071 case Intrinsic::arm_neon_vld2: {
3072 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3073 ARM::VLD2d32, ARM::VLD1q64 };
3074 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3075 ARM::VLD2q32Pseudo };
3076 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
3079 case Intrinsic::arm_neon_vld3: {
3080 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
3083 ARM::VLD1d64TPseudo };
3084 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3085 ARM::VLD3q16Pseudo_UPD,
3086 ARM::VLD3q32Pseudo_UPD };
3087 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3088 ARM::VLD3q16oddPseudo,
3089 ARM::VLD3q32oddPseudo };
3090 return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3093 case Intrinsic::arm_neon_vld4: {
3094 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
3097 ARM::VLD1d64QPseudo };
3098 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3099 ARM::VLD4q16Pseudo_UPD,
3100 ARM::VLD4q32Pseudo_UPD };
3101 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3102 ARM::VLD4q16oddPseudo,
3103 ARM::VLD4q32oddPseudo };
3104 return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3107 case Intrinsic::arm_neon_vld2lane: {
3108 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
3109 ARM::VLD2LNd16Pseudo,
3110 ARM::VLD2LNd32Pseudo };
3111 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
3112 ARM::VLD2LNq32Pseudo };
3113 return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3116 case Intrinsic::arm_neon_vld3lane: {
3117 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
3118 ARM::VLD3LNd16Pseudo,
3119 ARM::VLD3LNd32Pseudo };
3120 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
3121 ARM::VLD3LNq32Pseudo };
3122 return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3125 case Intrinsic::arm_neon_vld4lane: {
3126 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
3127 ARM::VLD4LNd16Pseudo,
3128 ARM::VLD4LNd32Pseudo };
3129 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
3130 ARM::VLD4LNq32Pseudo };
3131 return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3134 case Intrinsic::arm_neon_vst1: {
3135 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3136 ARM::VST1d32, ARM::VST1d64 };
3137 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3138 ARM::VST1q32, ARM::VST1q64 };
3139 return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
3142 case Intrinsic::arm_neon_vst2: {
3143 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3144 ARM::VST2d32, ARM::VST1q64 };
3145 static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3146 ARM::VST2q32Pseudo };
3147 return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3150 case Intrinsic::arm_neon_vst3: {
3151 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
3154 ARM::VST1d64TPseudo };
3155 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3156 ARM::VST3q16Pseudo_UPD,
3157 ARM::VST3q32Pseudo_UPD };
3158 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
3159 ARM::VST3q16oddPseudo,
3160 ARM::VST3q32oddPseudo };
3161 return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3164 case Intrinsic::arm_neon_vst4: {
3165 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
3168 ARM::VST1d64QPseudo };
3169 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3170 ARM::VST4q16Pseudo_UPD,
3171 ARM::VST4q32Pseudo_UPD };
3172 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
3173 ARM::VST4q16oddPseudo,
3174 ARM::VST4q32oddPseudo };
3175 return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3178 case Intrinsic::arm_neon_vst2lane: {
3179 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
3180 ARM::VST2LNd16Pseudo,
3181 ARM::VST2LNd32Pseudo };
3182 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
3183 ARM::VST2LNq32Pseudo };
3184 return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3187 case Intrinsic::arm_neon_vst3lane: {
3188 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
3189 ARM::VST3LNd16Pseudo,
3190 ARM::VST3LNd32Pseudo };
3191 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
3192 ARM::VST3LNq32Pseudo };
3193 return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3196 case Intrinsic::arm_neon_vst4lane: {
3197 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
3198 ARM::VST4LNd16Pseudo,
3199 ARM::VST4LNd32Pseudo };
3200 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
3201 ARM::VST4LNq32Pseudo };
3202 return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3208 case ISD::INTRINSIC_WO_CHAIN: {
3209 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3214 case Intrinsic::arm_neon_vtbl2:
3215 return SelectVTBL(N, false, 2, ARM::VTBL2);
3216 case Intrinsic::arm_neon_vtbl3:
3217 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3218 case Intrinsic::arm_neon_vtbl4:
3219 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3221 case Intrinsic::arm_neon_vtbx2:
3222 return SelectVTBL(N, true, 2, ARM::VTBX2);
3223 case Intrinsic::arm_neon_vtbx3:
3224 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3225 case Intrinsic::arm_neon_vtbx4:
3226 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3231 case ARMISD::VTBL1: {
3233 EVT VT = N->getValueType(0);
3234 SmallVector<SDValue, 6> Ops;
3236 Ops.push_back(N->getOperand(0));
3237 Ops.push_back(N->getOperand(1));
3238 Ops.push_back(getAL(CurDAG)); // Predicate
3239 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3240 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops);
3242 case ARMISD::VTBL2: {
3244 EVT VT = N->getValueType(0);
3246 // Form a REG_SEQUENCE to force register allocation.
3247 SDValue V0 = N->getOperand(0);
3248 SDValue V1 = N->getOperand(1);
3249 SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
3251 SmallVector<SDValue, 6> Ops;
3252 Ops.push_back(RegSeq);
3253 Ops.push_back(N->getOperand(2));
3254 Ops.push_back(getAL(CurDAG)); // Predicate
3255 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3256 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops);
3259 case ISD::CONCAT_VECTORS:
3260 return SelectConcatVector(N);
3262 case ISD::ATOMIC_LOAD:
3263 if (cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64)
3264 return SelectAtomic(N, 0, 0, 0, ARM::ATOMIC_LOAD_I64);
3268 case ISD::ATOMIC_STORE:
3269 if (cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64)
3270 return SelectAtomic(N, 0, 0, 0, ARM::ATOMIC_STORE_I64);
3274 case ISD::ATOMIC_LOAD_ADD:
3275 return SelectAtomic(N,
3276 ARM::ATOMIC_LOAD_ADD_I8,
3277 ARM::ATOMIC_LOAD_ADD_I16,
3278 ARM::ATOMIC_LOAD_ADD_I32,
3279 ARM::ATOMIC_LOAD_ADD_I64);
3280 case ISD::ATOMIC_LOAD_SUB:
3281 return SelectAtomic(N,
3282 ARM::ATOMIC_LOAD_SUB_I8,
3283 ARM::ATOMIC_LOAD_SUB_I16,
3284 ARM::ATOMIC_LOAD_SUB_I32,
3285 ARM::ATOMIC_LOAD_SUB_I64);
3286 case ISD::ATOMIC_LOAD_AND:
3287 return SelectAtomic(N,
3288 ARM::ATOMIC_LOAD_AND_I8,
3289 ARM::ATOMIC_LOAD_AND_I16,
3290 ARM::ATOMIC_LOAD_AND_I32,
3291 ARM::ATOMIC_LOAD_AND_I64);
3292 case ISD::ATOMIC_LOAD_OR:
3293 return SelectAtomic(N,
3294 ARM::ATOMIC_LOAD_OR_I8,
3295 ARM::ATOMIC_LOAD_OR_I16,
3296 ARM::ATOMIC_LOAD_OR_I32,
3297 ARM::ATOMIC_LOAD_OR_I64);
3298 case ISD::ATOMIC_LOAD_XOR:
3299 return SelectAtomic(N,
3300 ARM::ATOMIC_LOAD_XOR_I8,
3301 ARM::ATOMIC_LOAD_XOR_I16,
3302 ARM::ATOMIC_LOAD_XOR_I32,
3303 ARM::ATOMIC_LOAD_XOR_I64);
3304 case ISD::ATOMIC_LOAD_NAND:
3305 return SelectAtomic(N,
3306 ARM::ATOMIC_LOAD_NAND_I8,
3307 ARM::ATOMIC_LOAD_NAND_I16,
3308 ARM::ATOMIC_LOAD_NAND_I32,
3309 ARM::ATOMIC_LOAD_NAND_I64);
3310 case ISD::ATOMIC_LOAD_MIN:
3311 return SelectAtomic(N,
3312 ARM::ATOMIC_LOAD_MIN_I8,
3313 ARM::ATOMIC_LOAD_MIN_I16,
3314 ARM::ATOMIC_LOAD_MIN_I32,
3315 ARM::ATOMIC_LOAD_MIN_I64);
3316 case ISD::ATOMIC_LOAD_MAX:
3317 return SelectAtomic(N,
3318 ARM::ATOMIC_LOAD_MAX_I8,
3319 ARM::ATOMIC_LOAD_MAX_I16,
3320 ARM::ATOMIC_LOAD_MAX_I32,
3321 ARM::ATOMIC_LOAD_MAX_I64);
3322 case ISD::ATOMIC_LOAD_UMIN:
3323 return SelectAtomic(N,
3324 ARM::ATOMIC_LOAD_UMIN_I8,
3325 ARM::ATOMIC_LOAD_UMIN_I16,
3326 ARM::ATOMIC_LOAD_UMIN_I32,
3327 ARM::ATOMIC_LOAD_UMIN_I64);
3328 case ISD::ATOMIC_LOAD_UMAX:
3329 return SelectAtomic(N,
3330 ARM::ATOMIC_LOAD_UMAX_I8,
3331 ARM::ATOMIC_LOAD_UMAX_I16,
3332 ARM::ATOMIC_LOAD_UMAX_I32,
3333 ARM::ATOMIC_LOAD_UMAX_I64);
3334 case ISD::ATOMIC_SWAP:
3335 return SelectAtomic(N,
3336 ARM::ATOMIC_SWAP_I8,
3337 ARM::ATOMIC_SWAP_I16,
3338 ARM::ATOMIC_SWAP_I32,
3339 ARM::ATOMIC_SWAP_I64);
3340 case ISD::ATOMIC_CMP_SWAP:
3341 return SelectAtomic(N,
3342 ARM::ATOMIC_CMP_SWAP_I8,
3343 ARM::ATOMIC_CMP_SWAP_I16,
3344 ARM::ATOMIC_CMP_SWAP_I32,
3345 ARM::ATOMIC_CMP_SWAP_I64);
3348 return SelectCode(N);
3351 SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
3352 std::vector<SDValue> AsmNodeOperands;
3353 unsigned Flag, Kind;
3354 bool Changed = false;
3355 unsigned NumOps = N->getNumOperands();
3357 // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
3358 // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
3359 // (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
3360 // respectively. Since there is no constraint to explicitly specify a
3361 // reg pair, we use GPRPair reg class for "%r" for 64-bit data. For Thumb,
3362 // the 64-bit data may be referred by H, Q, R modifiers, so we still pack
3363 // them into a GPRPair.
3366 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1) : SDValue(0,0);
3368 SmallVector<bool, 8> OpChanged;
3369 // Glue node will be appended late.
3370 for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
3371 SDValue op = N->getOperand(i);
3372 AsmNodeOperands.push_back(op);
3374 if (i < InlineAsm::Op_FirstOperand)
3377 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
3378 Flag = C->getZExtValue();
3379 Kind = InlineAsm::getKind(Flag);
3384 // Immediate operands to inline asm in the SelectionDAG are modeled with
3385 // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
3386 // the second is a constant with the value of the immediate. If we get here
3387 // and we have a Kind_Imm, skip the next operand, and continue.
3388 if (Kind == InlineAsm::Kind_Imm) {
3389 SDValue op = N->getOperand(++i);
3390 AsmNodeOperands.push_back(op);
3394 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
3396 OpChanged.push_back(false);
3398 unsigned DefIdx = 0;
3399 bool IsTiedToChangedOp = false;
3400 // If it's a use that is tied with a previous def, it has no
3401 // reg class constraint.
3402 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
3403 IsTiedToChangedOp = OpChanged[DefIdx];
3405 if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
3406 && Kind != InlineAsm::Kind_RegDefEarlyClobber)
3410 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
3411 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
3415 assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
3416 SDValue V0 = N->getOperand(i+1);
3417 SDValue V1 = N->getOperand(i+2);
3418 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
3419 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
3421 MachineRegisterInfo &MRI = MF->getRegInfo();
3423 if (Kind == InlineAsm::Kind_RegDef ||
3424 Kind == InlineAsm::Kind_RegDefEarlyClobber) {
3425 // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
3426 // the original GPRs.
3428 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3429 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3430 SDValue Chain = SDValue(N,0);
3432 SDNode *GU = N->getGluedUser();
3433 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
3436 // Extract values from a GPRPair reg and copy to the original GPR reg.
3437 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
3439 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
3441 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
3442 RegCopy.getValue(1));
3443 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
3445 // Update the original glue user.
3446 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
3447 Ops.push_back(T1.getValue(1));
3448 CurDAG->UpdateNodeOperands(GU, &Ops[0], Ops.size());
3452 // For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
3453 // GPRPair and then pass the GPRPair to the inline asm.
3454 SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
3456 // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
3457 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
3459 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
3461 SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
3463 // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
3464 // i32 VRs of inline asm with it.
3465 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3466 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3467 Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
3469 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
3470 Glue = Chain.getValue(1);
3475 if(PairedReg.getNode()) {
3476 OpChanged[OpChanged.size() -1 ] = true;
3477 Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
3478 if (IsTiedToChangedOp)
3479 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
3481 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
3482 // Replace the current flag.
3483 AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
3485 // Add the new register node and skip the original two GPRs.
3486 AsmNodeOperands.push_back(PairedReg);
3487 // Skip the next two GPRs.
3493 AsmNodeOperands.push_back(Glue);
3497 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
3498 CurDAG->getVTList(MVT::Other, MVT::Glue), &AsmNodeOperands[0],
3499 AsmNodeOperands.size());
3501 return New.getNode();
3505 bool ARMDAGToDAGISel::
3506 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3507 std::vector<SDValue> &OutOps) {
3508 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3509 // Require the address to be in a register. That is safe for all ARM
3510 // variants and it is hard to do anything much smarter without knowing
3511 // how the operand is used.
3512 OutOps.push_back(Op);
3516 /// createARMISelDag - This pass converts a legalized DAG into a
3517 /// ARM-specific DAG, ready for instruction scheduling.
3519 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3520 CodeGenOpt::Level OptLevel) {
3521 return new ARMDAGToDAGISel(TM, OptLevel);