1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMTargetMachine.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
34 //===--------------------------------------------------------------------===//
35 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
36 /// instructions for SelectionDAG operations.
39 class ARMDAGToDAGISel : public SelectionDAGISel {
42 ARMTargetLowering ARMLowering;
44 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
45 /// make the right decision when generating code for different targets.
46 const ARMSubtarget *Subtarget;
49 explicit ARMDAGToDAGISel(ARMTargetMachine &tm)
50 : SelectionDAGISel(ARMLowering), TM(tm), ARMLowering(tm),
51 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
54 virtual const char *getPassName() const {
55 return "ARM Instruction Selection";
58 SDNode *Select(SDValue Op);
59 virtual void InstructionSelect();
60 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
61 SDValue &Offset, SDValue &Opc);
62 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
63 SDValue &Offset, SDValue &Opc);
64 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
65 SDValue &Offset, SDValue &Opc);
66 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
67 SDValue &Offset, SDValue &Opc);
68 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
71 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
74 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
76 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
77 SDValue &Base, SDValue &OffImm,
79 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
80 SDValue &OffImm, SDValue &Offset);
81 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
82 SDValue &OffImm, SDValue &Offset);
83 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
84 SDValue &OffImm, SDValue &Offset);
85 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
88 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
89 SDValue &B, SDValue &C);
91 // Include the pieces autogenerated from the target description.
92 #include "ARMGenDAGISel.inc"
96 void ARMDAGToDAGISel::InstructionSelect() {
100 CurDAG->RemoveDeadNodes();
103 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
104 SDValue &Base, SDValue &Offset,
106 if (N.getOpcode() == ISD::MUL) {
107 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
108 // X * [3,5,9] -> X + X * [2,4,8] etc.
109 int RHSC = (int)RHS->getZExtValue();
112 ARM_AM::AddrOpc AddSub = ARM_AM::add;
114 AddSub = ARM_AM::sub;
117 if (isPowerOf2_32(RHSC)) {
118 unsigned ShAmt = Log2_32(RHSC);
119 Base = Offset = N.getOperand(0);
120 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
129 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
131 if (N.getOpcode() == ISD::FrameIndex) {
132 int FI = cast<FrameIndexSDNode>(N)->getIndex();
133 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
134 } else if (N.getOpcode() == ARMISD::Wrapper) {
135 Base = N.getOperand(0);
137 Offset = CurDAG->getRegister(0, MVT::i32);
138 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
144 // Match simple R +/- imm12 operands.
145 if (N.getOpcode() == ISD::ADD)
146 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
147 int RHSC = (int)RHS->getZExtValue();
148 if ((RHSC >= 0 && RHSC < 0x1000) ||
149 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
150 Base = N.getOperand(0);
151 if (Base.getOpcode() == ISD::FrameIndex) {
152 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
153 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
155 Offset = CurDAG->getRegister(0, MVT::i32);
157 ARM_AM::AddrOpc AddSub = ARM_AM::add;
159 AddSub = ARM_AM::sub;
162 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
169 // Otherwise this is R +/- [possibly shifted] R
170 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
171 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
174 Base = N.getOperand(0);
175 Offset = N.getOperand(1);
177 if (ShOpcVal != ARM_AM::no_shift) {
178 // Check to see if the RHS of the shift is a constant, if not, we can't fold
180 if (ConstantSDNode *Sh =
181 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
182 ShAmt = Sh->getZExtValue();
183 Offset = N.getOperand(1).getOperand(0);
185 ShOpcVal = ARM_AM::no_shift;
189 // Try matching (R shl C) + (R).
190 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
191 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
192 if (ShOpcVal != ARM_AM::no_shift) {
193 // Check to see if the RHS of the shift is a constant, if not, we can't
195 if (ConstantSDNode *Sh =
196 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
197 ShAmt = Sh->getZExtValue();
198 Offset = N.getOperand(0).getOperand(0);
199 Base = N.getOperand(1);
201 ShOpcVal = ARM_AM::no_shift;
206 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
211 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
212 SDValue &Offset, SDValue &Opc) {
213 unsigned Opcode = Op.getOpcode();
214 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
215 ? cast<LoadSDNode>(Op)->getAddressingMode()
216 : cast<StoreSDNode>(Op)->getAddressingMode();
217 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
218 ? ARM_AM::add : ARM_AM::sub;
219 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
220 int Val = (int)C->getZExtValue();
221 if (Val >= 0 && Val < 0x1000) { // 12 bits.
222 Offset = CurDAG->getRegister(0, MVT::i32);
223 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
231 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
233 if (ShOpcVal != ARM_AM::no_shift) {
234 // Check to see if the RHS of the shift is a constant, if not, we can't fold
236 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
237 ShAmt = Sh->getZExtValue();
238 Offset = N.getOperand(0);
240 ShOpcVal = ARM_AM::no_shift;
244 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
250 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
251 SDValue &Base, SDValue &Offset,
253 if (N.getOpcode() == ISD::SUB) {
254 // X - C is canonicalize to X + -C, no need to handle it here.
255 Base = N.getOperand(0);
256 Offset = N.getOperand(1);
257 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
261 if (N.getOpcode() != ISD::ADD) {
263 if (N.getOpcode() == ISD::FrameIndex) {
264 int FI = cast<FrameIndexSDNode>(N)->getIndex();
265 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
267 Offset = CurDAG->getRegister(0, MVT::i32);
268 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
272 // If the RHS is +/- imm8, fold into addr mode.
273 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
274 int RHSC = (int)RHS->getZExtValue();
275 if ((RHSC >= 0 && RHSC < 256) ||
276 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
277 Base = N.getOperand(0);
278 if (Base.getOpcode() == ISD::FrameIndex) {
279 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
280 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
282 Offset = CurDAG->getRegister(0, MVT::i32);
284 ARM_AM::AddrOpc AddSub = ARM_AM::add;
286 AddSub = ARM_AM::sub;
289 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
294 Base = N.getOperand(0);
295 Offset = N.getOperand(1);
296 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
300 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
301 SDValue &Offset, SDValue &Opc) {
302 unsigned Opcode = Op.getOpcode();
303 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
304 ? cast<LoadSDNode>(Op)->getAddressingMode()
305 : cast<StoreSDNode>(Op)->getAddressingMode();
306 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
307 ? ARM_AM::add : ARM_AM::sub;
308 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
309 int Val = (int)C->getZExtValue();
310 if (Val >= 0 && Val < 256) {
311 Offset = CurDAG->getRegister(0, MVT::i32);
312 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
318 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
323 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
324 SDValue &Base, SDValue &Offset) {
325 if (N.getOpcode() != ISD::ADD) {
327 if (N.getOpcode() == ISD::FrameIndex) {
328 int FI = cast<FrameIndexSDNode>(N)->getIndex();
329 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
330 } else if (N.getOpcode() == ARMISD::Wrapper) {
331 Base = N.getOperand(0);
333 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
338 // If the RHS is +/- imm8, fold into addr mode.
339 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
340 int RHSC = (int)RHS->getZExtValue();
341 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
343 if ((RHSC >= 0 && RHSC < 256) ||
344 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
345 Base = N.getOperand(0);
346 if (Base.getOpcode() == ISD::FrameIndex) {
347 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
348 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
351 ARM_AM::AddrOpc AddSub = ARM_AM::add;
353 AddSub = ARM_AM::sub;
356 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
364 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
369 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
370 SDValue &Offset, SDValue &Label) {
371 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
372 Offset = N.getOperand(0);
373 SDValue N1 = N.getOperand(1);
374 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
381 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
382 SDValue &Base, SDValue &Offset){
383 if (N.getOpcode() != ISD::ADD) {
385 // We must materialize a zero in a reg! Returning an constant here won't
386 // work since its node is -1 so it won't get added to the selection queue.
387 // Explicitly issue a tMOVri8 node!
388 Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
389 CurDAG->getTargetConstant(0, MVT::i32)), 0);
393 Base = N.getOperand(0);
394 Offset = N.getOperand(1);
399 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
400 unsigned Scale, SDValue &Base,
401 SDValue &OffImm, SDValue &Offset) {
403 SDValue TmpBase, TmpOffImm;
404 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
405 return false; // We want to select tLDRspi / tSTRspi instead.
406 if (N.getOpcode() == ARMISD::Wrapper &&
407 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
408 return false; // We want to select tLDRpci instead.
411 if (N.getOpcode() != ISD::ADD) {
412 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
413 Offset = CurDAG->getRegister(0, MVT::i32);
414 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
418 // Thumb does not have [sp, r] address mode.
419 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
420 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
421 if ((LHSR && LHSR->getReg() == ARM::SP) ||
422 (RHSR && RHSR->getReg() == ARM::SP)) {
424 Offset = CurDAG->getRegister(0, MVT::i32);
425 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
429 // If the RHS is + imm5 * scale, fold into addr mode.
430 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
431 int RHSC = (int)RHS->getZExtValue();
432 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
434 if (RHSC >= 0 && RHSC < 32) {
435 Base = N.getOperand(0);
436 Offset = CurDAG->getRegister(0, MVT::i32);
437 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
443 Base = N.getOperand(0);
444 Offset = N.getOperand(1);
445 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
449 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
450 SDValue &Base, SDValue &OffImm,
452 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
455 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
456 SDValue &Base, SDValue &OffImm,
458 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
461 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
462 SDValue &Base, SDValue &OffImm,
464 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
467 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
468 SDValue &Base, SDValue &OffImm) {
469 if (N.getOpcode() == ISD::FrameIndex) {
470 int FI = cast<FrameIndexSDNode>(N)->getIndex();
471 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
472 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
476 if (N.getOpcode() != ISD::ADD)
479 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
480 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
481 (LHSR && LHSR->getReg() == ARM::SP)) {
482 // If the RHS is + imm8 * scale, fold into addr mode.
483 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
484 int RHSC = (int)RHS->getZExtValue();
485 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
487 if (RHSC >= 0 && RHSC < 256) {
488 Base = N.getOperand(0);
489 if (Base.getOpcode() == ISD::FrameIndex) {
490 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
491 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
493 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
503 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
508 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
510 // Don't match base register only case. That is matched to a separate
511 // lower complexity pattern with explicit register operand.
512 if (ShOpcVal == ARM_AM::no_shift) return false;
514 BaseReg = N.getOperand(0);
515 unsigned ShImmVal = 0;
516 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
517 ShReg = CurDAG->getRegister(0, MVT::i32);
518 ShImmVal = RHS->getZExtValue() & 31;
520 ShReg = N.getOperand(1);
522 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
527 /// getAL - Returns a ARMCC::AL immediate node.
528 static inline SDValue getAL(SelectionDAG *CurDAG) {
529 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
533 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
534 SDNode *N = Op.getNode();
536 if (N->isMachineOpcode())
537 return NULL; // Already selected.
539 switch (N->getOpcode()) {
541 case ISD::Constant: {
542 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
544 if (Subtarget->isThumb())
545 UseCP = (Val > 255 && // MOV
546 ~Val > 255 && // MOV + MVN
547 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
549 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
550 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
551 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
554 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
558 if (Subtarget->isThumb())
559 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other,
560 CPIdx, CurDAG->getEntryNode());
564 CurDAG->getRegister(0, MVT::i32),
565 CurDAG->getTargetConstant(0, MVT::i32),
567 CurDAG->getRegister(0, MVT::i32),
568 CurDAG->getEntryNode()
570 ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6);
572 ReplaceUses(Op, SDValue(ResNode, 0));
576 // Other cases are autogenerated.
579 case ISD::FrameIndex: {
580 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
581 int FI = cast<FrameIndexSDNode>(N)->getIndex();
582 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
583 if (Subtarget->isThumb())
584 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
585 CurDAG->getTargetConstant(0, MVT::i32));
587 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
588 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
589 CurDAG->getRegister(0, MVT::i32) };
590 return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
594 // Select add sp, c to tADDhirr.
595 SDValue N0 = Op.getOperand(0);
596 SDValue N1 = Op.getOperand(1);
597 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
598 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
599 if (LHSR && LHSR->getReg() == ARM::SP) {
601 std::swap(LHSR, RHSR);
603 if (RHSR && RHSR->getReg() == ARM::SP) {
606 return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), N0, N1);
611 if (Subtarget->isThumb())
613 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
614 unsigned RHSV = C->getZExtValue();
616 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
617 SDValue V = Op.getOperand(0);
619 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
620 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
621 CurDAG->getTargetConstant(ShImm, MVT::i32),
622 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
623 CurDAG->getRegister(0, MVT::i32) };
624 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
626 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
627 SDValue V = Op.getOperand(0);
629 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
630 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
631 CurDAG->getTargetConstant(ShImm, MVT::i32),
632 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
633 CurDAG->getRegister(0, MVT::i32) };
634 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
639 AddToISelQueue(Op.getOperand(0));
640 return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32,
641 Op.getOperand(0), getAL(CurDAG),
642 CurDAG->getRegister(0, MVT::i32));
643 case ISD::UMUL_LOHI: {
644 AddToISelQueue(Op.getOperand(0));
645 AddToISelQueue(Op.getOperand(1));
646 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
647 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
648 CurDAG->getRegister(0, MVT::i32) };
649 return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5);
651 case ISD::SMUL_LOHI: {
652 AddToISelQueue(Op.getOperand(0));
653 AddToISelQueue(Op.getOperand(1));
654 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
655 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
656 CurDAG->getRegister(0, MVT::i32) };
657 return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5);
660 LoadSDNode *LD = cast<LoadSDNode>(Op);
661 ISD::MemIndexedMode AM = LD->getAddressingMode();
662 MVT LoadedVT = LD->getMemoryVT();
663 if (AM != ISD::UNINDEXED) {
664 SDValue Offset, AMOpc;
665 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
668 if (LoadedVT == MVT::i32 &&
669 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
670 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
672 } else if (LoadedVT == MVT::i16 &&
673 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
675 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
676 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
677 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
678 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
679 if (LD->getExtensionType() == ISD::SEXTLOAD) {
680 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
682 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
685 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
687 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
693 SDValue Chain = LD->getChain();
694 SDValue Base = LD->getBasePtr();
695 AddToISelQueue(Chain);
696 AddToISelQueue(Base);
697 AddToISelQueue(Offset);
698 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
699 CurDAG->getRegister(0, MVT::i32), Chain };
700 return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
704 // Other cases are autogenerated.
707 case ARMISD::BRCOND: {
708 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
709 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
710 // Pattern complexity = 6 cost = 1 size = 0
712 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
713 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
714 // Pattern complexity = 6 cost = 1 size = 0
716 unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc;
717 SDValue Chain = Op.getOperand(0);
718 SDValue N1 = Op.getOperand(1);
719 SDValue N2 = Op.getOperand(2);
720 SDValue N3 = Op.getOperand(3);
721 SDValue InFlag = Op.getOperand(4);
722 assert(N1.getOpcode() == ISD::BasicBlock);
723 assert(N2.getOpcode() == ISD::Constant);
724 assert(N3.getOpcode() == ISD::Register);
726 AddToISelQueue(Chain);
728 AddToISelQueue(InFlag);
729 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
730 cast<ConstantSDNode>(N2)->getZExtValue()),
732 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
733 SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
734 Chain = SDValue(ResNode, 0);
735 if (Op.getNode()->getNumValues() == 2) {
736 InFlag = SDValue(ResNode, 1);
737 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
739 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
743 bool isThumb = Subtarget->isThumb();
744 MVT VT = Op.getValueType();
745 SDValue N0 = Op.getOperand(0);
746 SDValue N1 = Op.getOperand(1);
747 SDValue N2 = Op.getOperand(2);
748 SDValue N3 = Op.getOperand(3);
749 SDValue InFlag = Op.getOperand(4);
750 assert(N2.getOpcode() == ISD::Constant);
751 assert(N3.getOpcode() == ISD::Register);
753 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
754 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
755 // Pattern complexity = 18 cost = 1 size = 0
759 if (!isThumb && VT == MVT::i32 &&
760 SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
762 AddToISelQueue(CPTmp0);
763 AddToISelQueue(CPTmp1);
764 AddToISelQueue(CPTmp2);
765 AddToISelQueue(InFlag);
766 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
767 cast<ConstantSDNode>(N2)->getZExtValue()),
769 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
770 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
773 // Pattern: (ARMcmov:i32 GPR:i32:$false,
774 // (imm:i32)<<P:Predicate_so_imm>><<X:so_imm_XFORM>>:$true,
776 // Emits: (MOVCCi:i32 GPR:i32:$false,
777 // (so_imm_XFORM:i32 (imm:i32):$true), (imm:i32):$cc)
778 // Pattern complexity = 10 cost = 1 size = 0
779 if (VT == MVT::i32 &&
780 N3.getOpcode() == ISD::Constant &&
781 Predicate_so_imm(N3.getNode())) {
783 AddToISelQueue(InFlag);
784 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
785 cast<ConstantSDNode>(N1)->getZExtValue()),
787 Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
788 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
789 cast<ConstantSDNode>(N2)->getZExtValue()),
791 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
792 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5);
795 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
796 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
797 // Pattern complexity = 6 cost = 1 size = 0
799 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
800 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
801 // Pattern complexity = 6 cost = 11 size = 0
803 // Also FCPYScc and FCPYDcc.
806 AddToISelQueue(InFlag);
807 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
808 cast<ConstantSDNode>(N2)->getZExtValue()),
810 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
812 switch (VT.getSimpleVT()) {
813 default: assert(false && "Illegal conditional move type!");
816 Opc = isThumb ? ARM::tMOVCCr : ARM::MOVCCr;
825 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
828 MVT VT = Op.getValueType();
829 SDValue N0 = Op.getOperand(0);
830 SDValue N1 = Op.getOperand(1);
831 SDValue N2 = Op.getOperand(2);
832 SDValue N3 = Op.getOperand(3);
833 SDValue InFlag = Op.getOperand(4);
834 assert(N2.getOpcode() == ISD::Constant);
835 assert(N3.getOpcode() == ISD::Register);
839 AddToISelQueue(InFlag);
840 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
841 cast<ConstantSDNode>(N2)->getZExtValue()),
843 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
845 switch (VT.getSimpleVT()) {
846 default: assert(false && "Illegal conditional move type!");
855 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
858 return SelectCode(Op);
861 /// createARMISelDag - This pass converts a legalized DAG into a
862 /// ARM-specific DAG, ready for instruction scheduling.
864 FunctionPass *llvm::createARMISelDag(ARMTargetMachine &TM) {
865 return new ARMDAGToDAGISel(TM);