1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMTargetMachine.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/IR/CallingConv.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "arm-isel"
43 DisableShifterOp("disable-shifter-op", cl::Hidden,
44 cl::desc("Disable isel of shifter-op"),
48 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
49 cl::desc("Check fp vmla / vmls hazard at isel time"),
52 //===--------------------------------------------------------------------===//
53 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
54 /// instructions for SelectionDAG operations.
59 AM2_BASE, // Simple AM2 (+-imm12)
60 AM2_SHOP // Shifter-op AM2
63 class ARMDAGToDAGISel : public SelectionDAGISel {
64 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
65 /// make the right decision when generating code for different targets.
66 const ARMSubtarget *Subtarget;
69 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel)
70 : SelectionDAGISel(tm, OptLevel) {}
72 bool runOnMachineFunction(MachineFunction &MF) override {
73 // Reset the subtarget each time through.
74 Subtarget = &MF.getSubtarget<ARMSubtarget>();
75 SelectionDAGISel::runOnMachineFunction(MF);
79 const char *getPassName() const override {
80 return "ARM Instruction Selection";
83 void PreprocessISelDAG() override;
85 /// getI32Imm - Return a target constant of type i32 with the specified
87 inline SDValue getI32Imm(unsigned Imm, SDLoc dl) {
88 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
91 SDNode *Select(SDNode *N) override;
94 bool hasNoVMLxHazardUse(SDNode *N) const;
95 bool isShifterOpProfitable(const SDValue &Shift,
96 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
97 bool SelectRegShifterOperand(SDValue N, SDValue &A,
98 SDValue &B, SDValue &C,
99 bool CheckProfitability = true);
100 bool SelectImmShifterOperand(SDValue N, SDValue &A,
101 SDValue &B, bool CheckProfitability = true);
102 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
103 SDValue &B, SDValue &C) {
104 // Don't apply the profitability check
105 return SelectRegShifterOperand(N, A, B, C, false);
107 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
109 // Don't apply the profitability check
110 return SelectImmShifterOperand(N, A, B, false);
113 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
114 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
116 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
117 SDValue &Offset, SDValue &Opc);
118 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
120 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
123 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
125 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
128 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
130 SelectAddrMode2Worker(N, Base, Offset, Opc);
131 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
132 // This always matches one way or another.
136 bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
137 const ConstantSDNode *CN = cast<ConstantSDNode>(N);
138 Pred = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(N), MVT::i32);
139 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
143 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
144 SDValue &Offset, SDValue &Opc);
145 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
146 SDValue &Offset, SDValue &Opc);
147 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
148 SDValue &Offset, SDValue &Opc);
149 bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
150 bool SelectAddrMode3(SDValue N, SDValue &Base,
151 SDValue &Offset, SDValue &Opc);
152 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
153 SDValue &Offset, SDValue &Opc);
154 bool SelectAddrMode5(SDValue N, SDValue &Base,
156 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
157 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
159 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
161 // Thumb Addressing Modes:
162 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
163 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
165 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
167 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
169 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
171 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
173 // Thumb 2 Addressing Modes:
174 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
175 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
177 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
179 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
180 SDValue &OffReg, SDValue &ShImm);
181 bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
183 inline bool is_so_imm(unsigned Imm) const {
184 return ARM_AM::getSOImmVal(Imm) != -1;
187 inline bool is_so_imm_not(unsigned Imm) const {
188 return ARM_AM::getSOImmVal(~Imm) != -1;
191 inline bool is_t2_so_imm(unsigned Imm) const {
192 return ARM_AM::getT2SOImmVal(Imm) != -1;
195 inline bool is_t2_so_imm_not(unsigned Imm) const {
196 return ARM_AM::getT2SOImmVal(~Imm) != -1;
199 // Include the pieces autogenerated from the target description.
200 #include "ARMGenDAGISel.inc"
203 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
205 SDNode *SelectARMIndexedLoad(SDNode *N);
206 SDNode *SelectT2IndexedLoad(SDNode *N);
208 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
209 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
210 /// loads of D registers and even subregs and odd subregs of Q registers.
211 /// For NumVecs <= 2, QOpcodes1 is not used.
212 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
213 const uint16_t *DOpcodes,
214 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
216 /// SelectVST - Select NEON store intrinsics. NumVecs should
217 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
218 /// stores of D registers and even subregs and odd subregs of Q registers.
219 /// For NumVecs <= 2, QOpcodes1 is not used.
220 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
221 const uint16_t *DOpcodes,
222 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
224 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
225 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
226 /// load/store of D registers and Q registers.
227 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
228 bool isUpdating, unsigned NumVecs,
229 const uint16_t *DOpcodes, const uint16_t *QOpcodes);
231 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
232 /// should be 2, 3 or 4. The opcode array specifies the instructions used
233 /// for loading D registers. (Q registers are not supported.)
234 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
235 const uint16_t *Opcodes);
237 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
238 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
239 /// generated to force the table registers to be consecutive.
240 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
242 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
243 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
245 // Select special operations if node forms integer ABS pattern
246 SDNode *SelectABSOp(SDNode *N);
248 SDNode *SelectReadRegister(SDNode *N);
249 SDNode *SelectWriteRegister(SDNode *N);
251 SDNode *SelectInlineAsm(SDNode *N);
253 SDNode *SelectConcatVector(SDNode *N);
255 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
256 /// inline asm expressions.
257 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
258 std::vector<SDValue> &OutOps) override;
260 // Form pairs of consecutive R, S, D, or Q registers.
261 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
262 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
263 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
264 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
266 // Form sequences of 4 consecutive S, D, or Q registers.
267 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
268 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
269 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
271 // Get the alignment operand for a NEON VLD or VST instruction.
272 SDValue GetVLDSTAlign(SDValue Align, SDLoc dl, unsigned NumVecs,
277 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
278 /// operand. If so Imm will receive the 32-bit value.
279 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
280 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
281 Imm = cast<ConstantSDNode>(N)->getZExtValue();
287 // isInt32Immediate - This method tests to see if a constant operand.
288 // If so Imm will receive the 32 bit value.
289 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
290 return isInt32Immediate(N.getNode(), Imm);
293 // isOpcWithIntImmediate - This method tests to see if the node is a specific
294 // opcode and that it has a immediate integer right operand.
295 // If so Imm will receive the 32 bit value.
296 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
297 return N->getOpcode() == Opc &&
298 isInt32Immediate(N->getOperand(1).getNode(), Imm);
301 /// \brief Check whether a particular node is a constant value representable as
302 /// (N * Scale) where (N in [\p RangeMin, \p RangeMax).
304 /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
305 static bool isScaledConstantInRange(SDValue Node, int Scale,
306 int RangeMin, int RangeMax,
307 int &ScaledConstant) {
308 assert(Scale > 0 && "Invalid scale!");
310 // Check that this is a constant.
311 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
315 ScaledConstant = (int) C->getZExtValue();
316 if ((ScaledConstant % Scale) != 0)
319 ScaledConstant /= Scale;
320 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
323 void ARMDAGToDAGISel::PreprocessISelDAG() {
324 if (!Subtarget->hasV6T2Ops())
327 bool isThumb2 = Subtarget->isThumb();
328 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
329 E = CurDAG->allnodes_end(); I != E; ) {
330 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
332 if (N->getOpcode() != ISD::ADD)
335 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
336 // leading zeros, followed by consecutive set bits, followed by 1 or 2
337 // trailing zeros, e.g. 1020.
338 // Transform the expression to
339 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
340 // of trailing zeros of c2. The left shift would be folded as an shifter
341 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
344 SDValue N0 = N->getOperand(0);
345 SDValue N1 = N->getOperand(1);
346 unsigned And_imm = 0;
347 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
348 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
354 // Check if the AND mask is an immediate of the form: 000.....1111111100
355 unsigned TZ = countTrailingZeros(And_imm);
356 if (TZ != 1 && TZ != 2)
357 // Be conservative here. Shifter operands aren't always free. e.g. On
358 // Swift, left shifter operand of 1 / 2 for free but others are not.
360 // ubfx r3, r1, #16, #8
361 // ldr.w r3, [r0, r3, lsl #2]
364 // and.w r2, r9, r1, lsr #14
368 if (And_imm & (And_imm + 1))
371 // Look for (and (srl X, c1), c2).
372 SDValue Srl = N1.getOperand(0);
373 unsigned Srl_imm = 0;
374 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
378 // Make sure first operand is not a shifter operand which would prevent
379 // folding of the left shift.
384 if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1))
387 if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1) ||
388 SelectRegShifterOperand(N0, CPTmp0, CPTmp1, CPTmp2))
392 // Now make the transformation.
393 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
395 CurDAG->getConstant(Srl_imm + TZ, SDLoc(Srl),
397 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
399 CurDAG->getConstant(And_imm, SDLoc(Srl), MVT::i32));
400 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
401 N1, CurDAG->getConstant(TZ, SDLoc(Srl), MVT::i32));
402 CurDAG->UpdateNodeOperands(N, N0, N1);
406 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
407 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
408 /// least on current ARM implementations) which should be avoidded.
409 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
410 if (OptLevel == CodeGenOpt::None)
413 if (!CheckVMLxHazard)
416 if (!Subtarget->isCortexA7() && !Subtarget->isCortexA8() &&
417 !Subtarget->isCortexA9() && !Subtarget->isSwift())
423 SDNode *Use = *N->use_begin();
424 if (Use->getOpcode() == ISD::CopyToReg)
426 if (Use->isMachineOpcode()) {
427 const ARMBaseInstrInfo *TII = static_cast<const ARMBaseInstrInfo *>(
428 CurDAG->getSubtarget().getInstrInfo());
430 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
433 unsigned Opcode = MCID.getOpcode();
434 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
436 // vmlx feeding into another vmlx. We actually want to unfold
437 // the use later in the MLxExpansion pass. e.g.
439 // vmla (stall 8 cycles)
444 // This adds up to about 18 - 19 cycles.
447 // vmul (stall 4 cycles)
448 // vadd adds up to about 14 cycles.
449 return TII->isFpMLxInstruction(Opcode);
455 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
456 ARM_AM::ShiftOpc ShOpcVal,
458 if (!Subtarget->isLikeA9() && !Subtarget->isSwift())
460 if (Shift.hasOneUse())
463 return ShOpcVal == ARM_AM::lsl &&
464 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
467 bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
470 bool CheckProfitability) {
471 if (DisableShifterOp)
474 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
476 // Don't match base register only case. That is matched to a separate
477 // lower complexity pattern with explicit register operand.
478 if (ShOpcVal == ARM_AM::no_shift) return false;
480 BaseReg = N.getOperand(0);
481 unsigned ShImmVal = 0;
482 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
483 if (!RHS) return false;
484 ShImmVal = RHS->getZExtValue() & 31;
485 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
490 bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
494 bool CheckProfitability) {
495 if (DisableShifterOp)
498 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
500 // Don't match base register only case. That is matched to a separate
501 // lower complexity pattern with explicit register operand.
502 if (ShOpcVal == ARM_AM::no_shift) return false;
504 BaseReg = N.getOperand(0);
505 unsigned ShImmVal = 0;
506 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
507 if (RHS) return false;
509 ShReg = N.getOperand(1);
510 if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
512 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
518 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
521 // Match simple R + imm12 operands.
524 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
525 !CurDAG->isBaseWithConstantOffset(N)) {
526 if (N.getOpcode() == ISD::FrameIndex) {
527 // Match frame index.
528 int FI = cast<FrameIndexSDNode>(N)->getIndex();
529 Base = CurDAG->getTargetFrameIndex(
530 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
531 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
535 if (N.getOpcode() == ARMISD::Wrapper &&
536 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
537 Base = N.getOperand(0);
540 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
544 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
545 int RHSC = (int)RHS->getSExtValue();
546 if (N.getOpcode() == ISD::SUB)
549 if (RHSC > -0x1000 && RHSC < 0x1000) { // 12 bits
550 Base = N.getOperand(0);
551 if (Base.getOpcode() == ISD::FrameIndex) {
552 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
553 Base = CurDAG->getTargetFrameIndex(
554 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
556 OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
563 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
569 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
571 if (N.getOpcode() == ISD::MUL &&
572 ((!Subtarget->isLikeA9() && !Subtarget->isSwift()) || N.hasOneUse())) {
573 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
574 // X * [3,5,9] -> X + X * [2,4,8] etc.
575 int RHSC = (int)RHS->getZExtValue();
578 ARM_AM::AddrOpc AddSub = ARM_AM::add;
580 AddSub = ARM_AM::sub;
583 if (isPowerOf2_32(RHSC)) {
584 unsigned ShAmt = Log2_32(RHSC);
585 Base = Offset = N.getOperand(0);
586 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
595 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
596 // ISD::OR that is equivalent to an ISD::ADD.
597 !CurDAG->isBaseWithConstantOffset(N))
600 // Leave simple R +/- imm12 operands for LDRi12
601 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
603 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
604 -0x1000+1, 0x1000, RHSC)) // 12 bits.
608 // Otherwise this is R +/- [possibly shifted] R.
609 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
610 ARM_AM::ShiftOpc ShOpcVal =
611 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
614 Base = N.getOperand(0);
615 Offset = N.getOperand(1);
617 if (ShOpcVal != ARM_AM::no_shift) {
618 // Check to see if the RHS of the shift is a constant, if not, we can't fold
620 if (ConstantSDNode *Sh =
621 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
622 ShAmt = Sh->getZExtValue();
623 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
624 Offset = N.getOperand(1).getOperand(0);
627 ShOpcVal = ARM_AM::no_shift;
630 ShOpcVal = ARM_AM::no_shift;
634 // Try matching (R shl C) + (R).
635 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
636 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
637 N.getOperand(0).hasOneUse())) {
638 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
639 if (ShOpcVal != ARM_AM::no_shift) {
640 // Check to see if the RHS of the shift is a constant, if not, we can't
642 if (ConstantSDNode *Sh =
643 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
644 ShAmt = Sh->getZExtValue();
645 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
646 Offset = N.getOperand(0).getOperand(0);
647 Base = N.getOperand(1);
650 ShOpcVal = ARM_AM::no_shift;
653 ShOpcVal = ARM_AM::no_shift;
658 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
666 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
670 if (N.getOpcode() == ISD::MUL &&
671 (!(Subtarget->isLikeA9() || Subtarget->isSwift()) || N.hasOneUse())) {
672 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
673 // X * [3,5,9] -> X + X * [2,4,8] etc.
674 int RHSC = (int)RHS->getZExtValue();
677 ARM_AM::AddrOpc AddSub = ARM_AM::add;
679 AddSub = ARM_AM::sub;
682 if (isPowerOf2_32(RHSC)) {
683 unsigned ShAmt = Log2_32(RHSC);
684 Base = Offset = N.getOperand(0);
685 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
694 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
695 // ISD::OR that is equivalent to an ADD.
696 !CurDAG->isBaseWithConstantOffset(N)) {
698 if (N.getOpcode() == ISD::FrameIndex) {
699 int FI = cast<FrameIndexSDNode>(N)->getIndex();
700 Base = CurDAG->getTargetFrameIndex(
701 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
702 } else if (N.getOpcode() == ARMISD::Wrapper &&
703 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
704 Base = N.getOperand(0);
706 Offset = CurDAG->getRegister(0, MVT::i32);
707 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
713 // Match simple R +/- imm12 operands.
714 if (N.getOpcode() != ISD::SUB) {
716 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
717 -0x1000+1, 0x1000, RHSC)) { // 12 bits.
718 Base = N.getOperand(0);
719 if (Base.getOpcode() == ISD::FrameIndex) {
720 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
721 Base = CurDAG->getTargetFrameIndex(
722 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
724 Offset = CurDAG->getRegister(0, MVT::i32);
726 ARM_AM::AddrOpc AddSub = ARM_AM::add;
728 AddSub = ARM_AM::sub;
731 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
738 if ((Subtarget->isLikeA9() || Subtarget->isSwift()) && !N.hasOneUse()) {
739 // Compute R +/- (R << N) and reuse it.
741 Offset = CurDAG->getRegister(0, MVT::i32);
742 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
748 // Otherwise this is R +/- [possibly shifted] R.
749 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
750 ARM_AM::ShiftOpc ShOpcVal =
751 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
754 Base = N.getOperand(0);
755 Offset = N.getOperand(1);
757 if (ShOpcVal != ARM_AM::no_shift) {
758 // Check to see if the RHS of the shift is a constant, if not, we can't fold
760 if (ConstantSDNode *Sh =
761 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
762 ShAmt = Sh->getZExtValue();
763 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
764 Offset = N.getOperand(1).getOperand(0);
767 ShOpcVal = ARM_AM::no_shift;
770 ShOpcVal = ARM_AM::no_shift;
774 // Try matching (R shl C) + (R).
775 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
776 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
777 N.getOperand(0).hasOneUse())) {
778 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
779 if (ShOpcVal != ARM_AM::no_shift) {
780 // Check to see if the RHS of the shift is a constant, if not, we can't
782 if (ConstantSDNode *Sh =
783 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
784 ShAmt = Sh->getZExtValue();
785 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
786 Offset = N.getOperand(0).getOperand(0);
787 Base = N.getOperand(1);
790 ShOpcVal = ARM_AM::no_shift;
793 ShOpcVal = ARM_AM::no_shift;
798 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
803 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
804 SDValue &Offset, SDValue &Opc) {
805 unsigned Opcode = Op->getOpcode();
806 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
807 ? cast<LoadSDNode>(Op)->getAddressingMode()
808 : cast<StoreSDNode>(Op)->getAddressingMode();
809 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
810 ? ARM_AM::add : ARM_AM::sub;
812 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
816 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
818 if (ShOpcVal != ARM_AM::no_shift) {
819 // Check to see if the RHS of the shift is a constant, if not, we can't fold
821 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
822 ShAmt = Sh->getZExtValue();
823 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
824 Offset = N.getOperand(0);
827 ShOpcVal = ARM_AM::no_shift;
830 ShOpcVal = ARM_AM::no_shift;
834 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
839 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
840 SDValue &Offset, SDValue &Opc) {
841 unsigned Opcode = Op->getOpcode();
842 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
843 ? cast<LoadSDNode>(Op)->getAddressingMode()
844 : cast<StoreSDNode>(Op)->getAddressingMode();
845 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
846 ? ARM_AM::add : ARM_AM::sub;
848 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
849 if (AddSub == ARM_AM::sub) Val *= -1;
850 Offset = CurDAG->getRegister(0, MVT::i32);
851 Opc = CurDAG->getTargetConstant(Val, SDLoc(Op), MVT::i32);
859 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
860 SDValue &Offset, SDValue &Opc) {
861 unsigned Opcode = Op->getOpcode();
862 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
863 ? cast<LoadSDNode>(Op)->getAddressingMode()
864 : cast<StoreSDNode>(Op)->getAddressingMode();
865 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
866 ? ARM_AM::add : ARM_AM::sub;
868 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
869 Offset = CurDAG->getRegister(0, MVT::i32);
870 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
872 SDLoc(Op), MVT::i32);
879 bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
884 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
885 SDValue &Base, SDValue &Offset,
887 if (N.getOpcode() == ISD::SUB) {
888 // X - C is canonicalize to X + -C, no need to handle it here.
889 Base = N.getOperand(0);
890 Offset = N.getOperand(1);
891 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0), SDLoc(N),
896 if (!CurDAG->isBaseWithConstantOffset(N)) {
898 if (N.getOpcode() == ISD::FrameIndex) {
899 int FI = cast<FrameIndexSDNode>(N)->getIndex();
900 Base = CurDAG->getTargetFrameIndex(
901 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
903 Offset = CurDAG->getRegister(0, MVT::i32);
904 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), SDLoc(N),
909 // If the RHS is +/- imm8, fold into addr mode.
911 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
912 -256 + 1, 256, RHSC)) { // 8 bits.
913 Base = N.getOperand(0);
914 if (Base.getOpcode() == ISD::FrameIndex) {
915 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
916 Base = CurDAG->getTargetFrameIndex(
917 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
919 Offset = CurDAG->getRegister(0, MVT::i32);
921 ARM_AM::AddrOpc AddSub = ARM_AM::add;
923 AddSub = ARM_AM::sub;
926 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC), SDLoc(N),
931 Base = N.getOperand(0);
932 Offset = N.getOperand(1);
933 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), SDLoc(N),
938 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
939 SDValue &Offset, SDValue &Opc) {
940 unsigned Opcode = Op->getOpcode();
941 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
942 ? cast<LoadSDNode>(Op)->getAddressingMode()
943 : cast<StoreSDNode>(Op)->getAddressingMode();
944 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
945 ? ARM_AM::add : ARM_AM::sub;
947 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
948 Offset = CurDAG->getRegister(0, MVT::i32);
949 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), SDLoc(Op),
955 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), SDLoc(Op),
960 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
961 SDValue &Base, SDValue &Offset) {
962 if (!CurDAG->isBaseWithConstantOffset(N)) {
964 if (N.getOpcode() == ISD::FrameIndex) {
965 int FI = cast<FrameIndexSDNode>(N)->getIndex();
966 Base = CurDAG->getTargetFrameIndex(
967 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
968 } else if (N.getOpcode() == ARMISD::Wrapper &&
969 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
970 Base = N.getOperand(0);
972 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
977 // If the RHS is +/- imm8, fold into addr mode.
979 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
980 -256 + 1, 256, RHSC)) {
981 Base = N.getOperand(0);
982 if (Base.getOpcode() == ISD::FrameIndex) {
983 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
984 Base = CurDAG->getTargetFrameIndex(
985 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
988 ARM_AM::AddrOpc AddSub = ARM_AM::add;
990 AddSub = ARM_AM::sub;
993 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
999 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
1000 SDLoc(N), MVT::i32);
1004 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
1008 unsigned Alignment = 0;
1010 MemSDNode *MemN = cast<MemSDNode>(Parent);
1012 if (isa<LSBaseSDNode>(MemN) ||
1013 ((MemN->getOpcode() == ARMISD::VST1_UPD ||
1014 MemN->getOpcode() == ARMISD::VLD1_UPD) &&
1015 MemN->getConstantOperandVal(MemN->getNumOperands() - 1) == 1)) {
1016 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
1017 // The maximum alignment is equal to the memory size being referenced.
1018 unsigned MMOAlign = MemN->getAlignment();
1019 unsigned MemSize = MemN->getMemoryVT().getSizeInBits() / 8;
1020 if (MMOAlign >= MemSize && MemSize > 1)
1021 Alignment = MemSize;
1023 // All other uses of addrmode6 are for intrinsics. For now just record
1024 // the raw alignment value; it will be refined later based on the legal
1025 // alignment operands for the intrinsic.
1026 Alignment = MemN->getAlignment();
1029 Align = CurDAG->getTargetConstant(Alignment, SDLoc(N), MVT::i32);
1033 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
1035 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
1036 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
1037 if (AM != ISD::POST_INC)
1040 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
1041 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
1042 Offset = CurDAG->getRegister(0, MVT::i32);
1047 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
1048 SDValue &Offset, SDValue &Label) {
1049 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
1050 Offset = N.getOperand(0);
1051 SDValue N1 = N.getOperand(1);
1052 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
1053 SDLoc(N), MVT::i32);
1061 //===----------------------------------------------------------------------===//
1062 // Thumb Addressing Modes
1063 //===----------------------------------------------------------------------===//
1065 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
1066 SDValue &Base, SDValue &Offset){
1067 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1068 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
1069 if (!NC || !NC->isNullValue())
1076 Base = N.getOperand(0);
1077 Offset = N.getOperand(1);
1082 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1083 SDValue &Base, SDValue &OffImm) {
1084 if (!CurDAG->isBaseWithConstantOffset(N)) {
1085 if (N.getOpcode() == ISD::ADD) {
1086 return false; // We want to select register offset instead
1087 } else if (N.getOpcode() == ARMISD::Wrapper &&
1088 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
1089 Base = N.getOperand(0);
1094 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
1098 // If the RHS is + imm5 * scale, fold into addr mode.
1100 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1101 Base = N.getOperand(0);
1102 OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
1106 // Offset is too large, so use register offset instead.
1111 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1113 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1117 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1119 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1123 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1125 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1128 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1129 SDValue &Base, SDValue &OffImm) {
1130 if (N.getOpcode() == ISD::FrameIndex) {
1131 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1132 // Only multiples of 4 are allowed for the offset, so the frame object
1133 // alignment must be at least 4.
1134 MachineFrameInfo *MFI = MF->getFrameInfo();
1135 if (MFI->getObjectAlignment(FI) < 4)
1136 MFI->setObjectAlignment(FI, 4);
1137 Base = CurDAG->getTargetFrameIndex(
1138 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
1139 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
1143 if (!CurDAG->isBaseWithConstantOffset(N))
1146 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1147 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1148 (LHSR && LHSR->getReg() == ARM::SP)) {
1149 // If the RHS is + imm8 * scale, fold into addr mode.
1151 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1152 Base = N.getOperand(0);
1153 if (Base.getOpcode() == ISD::FrameIndex) {
1154 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1155 // For LHS+RHS to result in an offset that's a multiple of 4 the object
1156 // indexed by the LHS must be 4-byte aligned.
1157 MachineFrameInfo *MFI = MF->getFrameInfo();
1158 if (MFI->getObjectAlignment(FI) < 4)
1159 MFI->setObjectAlignment(FI, 4);
1160 Base = CurDAG->getTargetFrameIndex(
1161 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
1163 OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
1172 //===----------------------------------------------------------------------===//
1173 // Thumb 2 Addressing Modes
1174 //===----------------------------------------------------------------------===//
1177 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1178 SDValue &Base, SDValue &OffImm) {
1179 // Match simple R + imm12 operands.
1182 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1183 !CurDAG->isBaseWithConstantOffset(N)) {
1184 if (N.getOpcode() == ISD::FrameIndex) {
1185 // Match frame index.
1186 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1187 Base = CurDAG->getTargetFrameIndex(
1188 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
1189 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
1193 if (N.getOpcode() == ARMISD::Wrapper &&
1194 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
1195 Base = N.getOperand(0);
1196 if (Base.getOpcode() == ISD::TargetConstantPool)
1197 return false; // We want to select t2LDRpci instead.
1200 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
1204 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1205 if (SelectT2AddrModeImm8(N, Base, OffImm))
1206 // Let t2LDRi8 handle (R - imm8).
1209 int RHSC = (int)RHS->getZExtValue();
1210 if (N.getOpcode() == ISD::SUB)
1213 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1214 Base = N.getOperand(0);
1215 if (Base.getOpcode() == ISD::FrameIndex) {
1216 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1217 Base = CurDAG->getTargetFrameIndex(
1218 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
1220 OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
1227 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
1231 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1232 SDValue &Base, SDValue &OffImm) {
1233 // Match simple R - imm8 operands.
1234 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1235 !CurDAG->isBaseWithConstantOffset(N))
1238 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1239 int RHSC = (int)RHS->getSExtValue();
1240 if (N.getOpcode() == ISD::SUB)
1243 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1244 Base = N.getOperand(0);
1245 if (Base.getOpcode() == ISD::FrameIndex) {
1246 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1247 Base = CurDAG->getTargetFrameIndex(
1248 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
1250 OffImm = CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32);
1258 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1260 unsigned Opcode = Op->getOpcode();
1261 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1262 ? cast<LoadSDNode>(Op)->getAddressingMode()
1263 : cast<StoreSDNode>(Op)->getAddressingMode();
1265 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1266 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1267 ? CurDAG->getTargetConstant(RHSC, SDLoc(N), MVT::i32)
1268 : CurDAG->getTargetConstant(-RHSC, SDLoc(N), MVT::i32);
1275 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1277 SDValue &OffReg, SDValue &ShImm) {
1278 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1279 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1282 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1283 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1284 int RHSC = (int)RHS->getZExtValue();
1285 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1287 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1291 // Look for (R + R) or (R + (R << [1,2,3])).
1293 Base = N.getOperand(0);
1294 OffReg = N.getOperand(1);
1296 // Swap if it is ((R << c) + R).
1297 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1298 if (ShOpcVal != ARM_AM::lsl) {
1299 ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1300 if (ShOpcVal == ARM_AM::lsl)
1301 std::swap(Base, OffReg);
1304 if (ShOpcVal == ARM_AM::lsl) {
1305 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1307 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1308 ShAmt = Sh->getZExtValue();
1309 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1310 OffReg = OffReg.getOperand(0);
1317 ShImm = CurDAG->getTargetConstant(ShAmt, SDLoc(N), MVT::i32);
1322 bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
1324 // This *must* succeed since it's used for the irreplaceable ldrex and strex
1327 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
1329 if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
1332 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1336 uint32_t RHSC = (int)RHS->getZExtValue();
1337 if (RHSC > 1020 || RHSC % 4 != 0)
1340 Base = N.getOperand(0);
1341 if (Base.getOpcode() == ISD::FrameIndex) {
1342 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1343 Base = CurDAG->getTargetFrameIndex(
1344 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
1347 OffImm = CurDAG->getTargetConstant(RHSC/4, SDLoc(N), MVT::i32);
1351 //===--------------------------------------------------------------------===//
1353 /// getAL - Returns a ARMCC::AL immediate node.
1354 static inline SDValue getAL(SelectionDAG *CurDAG, SDLoc dl) {
1355 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, dl, MVT::i32);
1358 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1359 LoadSDNode *LD = cast<LoadSDNode>(N);
1360 ISD::MemIndexedMode AM = LD->getAddressingMode();
1361 if (AM == ISD::UNINDEXED)
1364 EVT LoadedVT = LD->getMemoryVT();
1365 SDValue Offset, AMOpc;
1366 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1367 unsigned Opcode = 0;
1369 if (LoadedVT == MVT::i32 && isPre &&
1370 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1371 Opcode = ARM::LDR_PRE_IMM;
1373 } else if (LoadedVT == MVT::i32 && !isPre &&
1374 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1375 Opcode = ARM::LDR_POST_IMM;
1377 } else if (LoadedVT == MVT::i32 &&
1378 SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1379 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1382 } else if (LoadedVT == MVT::i16 &&
1383 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1385 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1386 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1387 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1388 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1389 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1390 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1392 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1396 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1398 Opcode = ARM::LDRB_PRE_IMM;
1399 } else if (!isPre &&
1400 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1402 Opcode = ARM::LDRB_POST_IMM;
1403 } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1405 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1411 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1412 SDValue Chain = LD->getChain();
1413 SDValue Base = LD->getBasePtr();
1414 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)),
1415 CurDAG->getRegister(0, MVT::i32), Chain };
1416 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1417 MVT::i32, MVT::Other, Ops);
1419 SDValue Chain = LD->getChain();
1420 SDValue Base = LD->getBasePtr();
1421 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)),
1422 CurDAG->getRegister(0, MVT::i32), Chain };
1423 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1424 MVT::i32, MVT::Other, Ops);
1431 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1432 LoadSDNode *LD = cast<LoadSDNode>(N);
1433 ISD::MemIndexedMode AM = LD->getAddressingMode();
1434 if (AM == ISD::UNINDEXED)
1437 EVT LoadedVT = LD->getMemoryVT();
1438 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1440 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1441 unsigned Opcode = 0;
1443 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1444 switch (LoadedVT.getSimpleVT().SimpleTy) {
1446 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1450 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1452 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1457 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1459 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1468 SDValue Chain = LD->getChain();
1469 SDValue Base = LD->getBasePtr();
1470 SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)),
1471 CurDAG->getRegister(0, MVT::i32), Chain };
1472 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
1479 /// \brief Form a GPRPair pseudo register from a pair of GPR regs.
1480 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1481 SDLoc dl(V0.getNode());
1483 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32);
1484 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32);
1485 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32);
1486 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1487 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1490 /// \brief Form a D register from a pair of S registers.
1491 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1492 SDLoc dl(V0.getNode());
1494 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, dl, MVT::i32);
1495 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
1496 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32);
1497 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1498 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1501 /// \brief Form a quad register from a pair of D registers.
1502 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1503 SDLoc dl(V0.getNode());
1504 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl,
1506 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
1507 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
1508 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1509 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1512 /// \brief Form 4 consecutive D registers from a pair of Q registers.
1513 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1514 SDLoc dl(V0.getNode());
1515 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl,
1517 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
1518 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
1519 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1520 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1523 /// \brief Form 4 consecutive S registers.
1524 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1525 SDValue V2, SDValue V3) {
1526 SDLoc dl(V0.getNode());
1528 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, dl, MVT::i32);
1529 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32);
1530 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32);
1531 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32);
1532 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, dl, MVT::i32);
1533 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1534 V2, SubReg2, V3, SubReg3 };
1535 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1538 /// \brief Form 4 consecutive D registers.
1539 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1540 SDValue V2, SDValue V3) {
1541 SDLoc dl(V0.getNode());
1542 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl,
1544 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32);
1545 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32);
1546 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32);
1547 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, dl, MVT::i32);
1548 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1549 V2, SubReg2, V3, SubReg3 };
1550 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1553 /// \brief Form 4 consecutive Q registers.
1554 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1555 SDValue V2, SDValue V3) {
1556 SDLoc dl(V0.getNode());
1557 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl,
1559 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32);
1560 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32);
1561 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32);
1562 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, dl, MVT::i32);
1563 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1564 V2, SubReg2, V3, SubReg3 };
1565 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1568 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1569 /// of a NEON VLD or VST instruction. The supported values depend on the
1570 /// number of registers being loaded.
1571 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, SDLoc dl,
1572 unsigned NumVecs, bool is64BitVector) {
1573 unsigned NumRegs = NumVecs;
1574 if (!is64BitVector && NumVecs < 3)
1577 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1578 if (Alignment >= 32 && NumRegs == 4)
1580 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1582 else if (Alignment >= 8)
1587 return CurDAG->getTargetConstant(Alignment, dl, MVT::i32);
1590 static bool isVLDfixed(unsigned Opc)
1593 default: return false;
1594 case ARM::VLD1d8wb_fixed : return true;
1595 case ARM::VLD1d16wb_fixed : return true;
1596 case ARM::VLD1d64Qwb_fixed : return true;
1597 case ARM::VLD1d32wb_fixed : return true;
1598 case ARM::VLD1d64wb_fixed : return true;
1599 case ARM::VLD1d64TPseudoWB_fixed : return true;
1600 case ARM::VLD1d64QPseudoWB_fixed : return true;
1601 case ARM::VLD1q8wb_fixed : return true;
1602 case ARM::VLD1q16wb_fixed : return true;
1603 case ARM::VLD1q32wb_fixed : return true;
1604 case ARM::VLD1q64wb_fixed : return true;
1605 case ARM::VLD2d8wb_fixed : return true;
1606 case ARM::VLD2d16wb_fixed : return true;
1607 case ARM::VLD2d32wb_fixed : return true;
1608 case ARM::VLD2q8PseudoWB_fixed : return true;
1609 case ARM::VLD2q16PseudoWB_fixed : return true;
1610 case ARM::VLD2q32PseudoWB_fixed : return true;
1611 case ARM::VLD2DUPd8wb_fixed : return true;
1612 case ARM::VLD2DUPd16wb_fixed : return true;
1613 case ARM::VLD2DUPd32wb_fixed : return true;
1617 static bool isVSTfixed(unsigned Opc)
1620 default: return false;
1621 case ARM::VST1d8wb_fixed : return true;
1622 case ARM::VST1d16wb_fixed : return true;
1623 case ARM::VST1d32wb_fixed : return true;
1624 case ARM::VST1d64wb_fixed : return true;
1625 case ARM::VST1q8wb_fixed : return true;
1626 case ARM::VST1q16wb_fixed : return true;
1627 case ARM::VST1q32wb_fixed : return true;
1628 case ARM::VST1q64wb_fixed : return true;
1629 case ARM::VST1d64TPseudoWB_fixed : return true;
1630 case ARM::VST1d64QPseudoWB_fixed : return true;
1631 case ARM::VST2d8wb_fixed : return true;
1632 case ARM::VST2d16wb_fixed : return true;
1633 case ARM::VST2d32wb_fixed : return true;
1634 case ARM::VST2q8PseudoWB_fixed : return true;
1635 case ARM::VST2q16PseudoWB_fixed : return true;
1636 case ARM::VST2q32PseudoWB_fixed : return true;
1640 // Get the register stride update opcode of a VLD/VST instruction that
1641 // is otherwise equivalent to the given fixed stride updating instruction.
1642 static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1643 assert((isVLDfixed(Opc) || isVSTfixed(Opc))
1644 && "Incorrect fixed stride updating instruction.");
1647 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1648 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1649 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1650 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1651 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1652 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1653 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1654 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1655 case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register;
1656 case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register;
1657 case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register;
1658 case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register;
1660 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1661 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1662 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1663 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1664 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1665 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1666 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1667 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1668 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1669 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1671 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1672 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1673 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1674 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1675 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1676 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1678 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1679 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1680 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1681 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1682 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1683 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1685 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1686 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1687 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
1689 return Opc; // If not one we handle, return it unchanged.
1692 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1693 const uint16_t *DOpcodes,
1694 const uint16_t *QOpcodes0,
1695 const uint16_t *QOpcodes1) {
1696 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1699 SDValue MemAddr, Align;
1700 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1701 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1704 SDValue Chain = N->getOperand(0);
1705 EVT VT = N->getValueType(0);
1706 bool is64BitVector = VT.is64BitVector();
1707 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
1709 unsigned OpcodeIndex;
1710 switch (VT.getSimpleVT().SimpleTy) {
1711 default: llvm_unreachable("unhandled vld type");
1712 // Double-register operations:
1713 case MVT::v8i8: OpcodeIndex = 0; break;
1714 case MVT::v4i16: OpcodeIndex = 1; break;
1716 case MVT::v2i32: OpcodeIndex = 2; break;
1717 case MVT::v1i64: OpcodeIndex = 3; break;
1718 // Quad-register operations:
1719 case MVT::v16i8: OpcodeIndex = 0; break;
1720 case MVT::v8i16: OpcodeIndex = 1; break;
1722 case MVT::v4i32: OpcodeIndex = 2; break;
1724 case MVT::v2i64: OpcodeIndex = 3;
1725 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1733 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1736 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1738 std::vector<EVT> ResTys;
1739 ResTys.push_back(ResTy);
1741 ResTys.push_back(MVT::i32);
1742 ResTys.push_back(MVT::Other);
1744 SDValue Pred = getAL(CurDAG, dl);
1745 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1747 SmallVector<SDValue, 7> Ops;
1749 // Double registers and VLD1/VLD2 quad registers are directly supported.
1750 if (is64BitVector || NumVecs <= 2) {
1751 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1752 QOpcodes0[OpcodeIndex]);
1753 Ops.push_back(MemAddr);
1754 Ops.push_back(Align);
1756 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1757 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1758 // case entirely when the rest are updated to that form, too.
1759 if ((NumVecs <= 2) && !isa<ConstantSDNode>(Inc.getNode()))
1760 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1761 // FIXME: We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1762 // check for that explicitly too. Horribly hacky, but temporary.
1763 if ((NumVecs > 2 && !isVLDfixed(Opc)) ||
1764 !isa<ConstantSDNode>(Inc.getNode()))
1765 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1767 Ops.push_back(Pred);
1768 Ops.push_back(Reg0);
1769 Ops.push_back(Chain);
1770 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1773 // Otherwise, quad registers are loaded with two separate instructions,
1774 // where one loads the even registers and the other loads the odd registers.
1775 EVT AddrTy = MemAddr.getValueType();
1777 // Load the even subregs. This is always an updating load, so that it
1778 // provides the address to the second load for the odd subregs.
1780 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1781 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1782 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1783 ResTy, AddrTy, MVT::Other, OpsA);
1784 Chain = SDValue(VLdA, 2);
1786 // Load the odd subregs.
1787 Ops.push_back(SDValue(VLdA, 1));
1788 Ops.push_back(Align);
1790 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1791 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1792 "only constant post-increment update allowed for VLD3/4");
1794 Ops.push_back(Reg0);
1796 Ops.push_back(SDValue(VLdA, 0));
1797 Ops.push_back(Pred);
1798 Ops.push_back(Reg0);
1799 Ops.push_back(Chain);
1800 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops);
1803 // Transfer memoperands.
1804 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1805 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1806 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1811 // Extract out the subregisters.
1812 SDValue SuperReg = SDValue(VLd, 0);
1813 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1814 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1815 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1816 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1817 ReplaceUses(SDValue(N, Vec),
1818 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1819 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1821 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1825 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1826 const uint16_t *DOpcodes,
1827 const uint16_t *QOpcodes0,
1828 const uint16_t *QOpcodes1) {
1829 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1832 SDValue MemAddr, Align;
1833 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1834 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1835 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1838 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1839 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1841 SDValue Chain = N->getOperand(0);
1842 EVT VT = N->getOperand(Vec0Idx).getValueType();
1843 bool is64BitVector = VT.is64BitVector();
1844 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
1846 unsigned OpcodeIndex;
1847 switch (VT.getSimpleVT().SimpleTy) {
1848 default: llvm_unreachable("unhandled vst type");
1849 // Double-register operations:
1850 case MVT::v8i8: OpcodeIndex = 0; break;
1851 case MVT::v4i16: OpcodeIndex = 1; break;
1853 case MVT::v2i32: OpcodeIndex = 2; break;
1854 case MVT::v1i64: OpcodeIndex = 3; break;
1855 // Quad-register operations:
1856 case MVT::v16i8: OpcodeIndex = 0; break;
1857 case MVT::v8i16: OpcodeIndex = 1; break;
1859 case MVT::v4i32: OpcodeIndex = 2; break;
1861 case MVT::v2i64: OpcodeIndex = 3;
1862 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1866 std::vector<EVT> ResTys;
1868 ResTys.push_back(MVT::i32);
1869 ResTys.push_back(MVT::Other);
1871 SDValue Pred = getAL(CurDAG, dl);
1872 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1873 SmallVector<SDValue, 7> Ops;
1875 // Double registers and VST1/VST2 quad registers are directly supported.
1876 if (is64BitVector || NumVecs <= 2) {
1879 SrcReg = N->getOperand(Vec0Idx);
1880 } else if (is64BitVector) {
1881 // Form a REG_SEQUENCE to force register allocation.
1882 SDValue V0 = N->getOperand(Vec0Idx + 0);
1883 SDValue V1 = N->getOperand(Vec0Idx + 1);
1885 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
1887 SDValue V2 = N->getOperand(Vec0Idx + 2);
1888 // If it's a vst3, form a quad D-register and leave the last part as
1890 SDValue V3 = (NumVecs == 3)
1891 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1892 : N->getOperand(Vec0Idx + 3);
1893 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
1896 // Form a QQ register.
1897 SDValue Q0 = N->getOperand(Vec0Idx);
1898 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1899 SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0);
1902 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1903 QOpcodes0[OpcodeIndex]);
1904 Ops.push_back(MemAddr);
1905 Ops.push_back(Align);
1907 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1908 // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
1909 // case entirely when the rest are updated to that form, too.
1910 if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1911 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1912 // FIXME: We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
1913 // check for that explicitly too. Horribly hacky, but temporary.
1914 if (!isa<ConstantSDNode>(Inc.getNode()))
1916 else if (NumVecs > 2 && !isVSTfixed(Opc))
1917 Ops.push_back(Reg0);
1919 Ops.push_back(SrcReg);
1920 Ops.push_back(Pred);
1921 Ops.push_back(Reg0);
1922 Ops.push_back(Chain);
1923 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1925 // Transfer memoperands.
1926 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1931 // Otherwise, quad registers are stored with two separate instructions,
1932 // where one stores the even registers and the other stores the odd registers.
1934 // Form the QQQQ REG_SEQUENCE.
1935 SDValue V0 = N->getOperand(Vec0Idx + 0);
1936 SDValue V1 = N->getOperand(Vec0Idx + 1);
1937 SDValue V2 = N->getOperand(Vec0Idx + 2);
1938 SDValue V3 = (NumVecs == 3)
1939 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1940 : N->getOperand(Vec0Idx + 3);
1941 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
1943 // Store the even D registers. This is always an updating store, so that it
1944 // provides the address to the second store for the odd subregs.
1945 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1946 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1947 MemAddr.getValueType(),
1949 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
1950 Chain = SDValue(VStA, 1);
1952 // Store the odd D registers.
1953 Ops.push_back(SDValue(VStA, 0));
1954 Ops.push_back(Align);
1956 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1957 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1958 "only constant post-increment update allowed for VST3/4");
1960 Ops.push_back(Reg0);
1962 Ops.push_back(RegSeq);
1963 Ops.push_back(Pred);
1964 Ops.push_back(Reg0);
1965 Ops.push_back(Chain);
1966 SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1968 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
1972 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1973 bool isUpdating, unsigned NumVecs,
1974 const uint16_t *DOpcodes,
1975 const uint16_t *QOpcodes) {
1976 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1979 SDValue MemAddr, Align;
1980 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1981 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1982 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1985 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1986 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1988 SDValue Chain = N->getOperand(0);
1990 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1991 EVT VT = N->getOperand(Vec0Idx).getValueType();
1992 bool is64BitVector = VT.is64BitVector();
1994 unsigned Alignment = 0;
1996 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1997 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1998 if (Alignment > NumBytes)
1999 Alignment = NumBytes;
2000 if (Alignment < 8 && Alignment < NumBytes)
2002 // Alignment must be a power of two; make sure of that.
2003 Alignment = (Alignment & -Alignment);
2007 Align = CurDAG->getTargetConstant(Alignment, dl, MVT::i32);
2009 unsigned OpcodeIndex;
2010 switch (VT.getSimpleVT().SimpleTy) {
2011 default: llvm_unreachable("unhandled vld/vst lane type");
2012 // Double-register operations:
2013 case MVT::v8i8: OpcodeIndex = 0; break;
2014 case MVT::v4i16: OpcodeIndex = 1; break;
2016 case MVT::v2i32: OpcodeIndex = 2; break;
2017 // Quad-register operations:
2018 case MVT::v8i16: OpcodeIndex = 0; break;
2020 case MVT::v4i32: OpcodeIndex = 1; break;
2023 std::vector<EVT> ResTys;
2025 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2028 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
2029 MVT::i64, ResTyElts));
2032 ResTys.push_back(MVT::i32);
2033 ResTys.push_back(MVT::Other);
2035 SDValue Pred = getAL(CurDAG, dl);
2036 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2038 SmallVector<SDValue, 8> Ops;
2039 Ops.push_back(MemAddr);
2040 Ops.push_back(Align);
2042 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2043 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2047 SDValue V0 = N->getOperand(Vec0Idx + 0);
2048 SDValue V1 = N->getOperand(Vec0Idx + 1);
2051 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2053 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2055 SDValue V2 = N->getOperand(Vec0Idx + 2);
2056 SDValue V3 = (NumVecs == 3)
2057 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2058 : N->getOperand(Vec0Idx + 3);
2060 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2062 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2064 Ops.push_back(SuperReg);
2065 Ops.push_back(getI32Imm(Lane, dl));
2066 Ops.push_back(Pred);
2067 Ops.push_back(Reg0);
2068 Ops.push_back(Chain);
2070 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
2071 QOpcodes[OpcodeIndex]);
2072 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2073 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
2077 // Extract the subregisters.
2078 SuperReg = SDValue(VLdLn, 0);
2079 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
2080 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
2081 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2082 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2083 ReplaceUses(SDValue(N, Vec),
2084 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2085 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2087 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2091 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
2093 const uint16_t *Opcodes) {
2094 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2097 SDValue MemAddr, Align;
2098 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
2101 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2102 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2104 SDValue Chain = N->getOperand(0);
2105 EVT VT = N->getValueType(0);
2107 unsigned Alignment = 0;
2109 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2110 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2111 if (Alignment > NumBytes)
2112 Alignment = NumBytes;
2113 if (Alignment < 8 && Alignment < NumBytes)
2115 // Alignment must be a power of two; make sure of that.
2116 Alignment = (Alignment & -Alignment);
2120 Align = CurDAG->getTargetConstant(Alignment, dl, MVT::i32);
2122 unsigned OpcodeIndex;
2123 switch (VT.getSimpleVT().SimpleTy) {
2124 default: llvm_unreachable("unhandled vld-dup type");
2125 case MVT::v8i8: OpcodeIndex = 0; break;
2126 case MVT::v4i16: OpcodeIndex = 1; break;
2128 case MVT::v2i32: OpcodeIndex = 2; break;
2131 SDValue Pred = getAL(CurDAG, dl);
2132 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2134 unsigned Opc = Opcodes[OpcodeIndex];
2135 SmallVector<SDValue, 6> Ops;
2136 Ops.push_back(MemAddr);
2137 Ops.push_back(Align);
2139 // fixed-stride update instructions don't have an explicit writeback
2140 // operand. It's implicit in the opcode itself.
2141 SDValue Inc = N->getOperand(2);
2142 if (!isa<ConstantSDNode>(Inc.getNode()))
2144 // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
2145 else if (NumVecs > 2)
2146 Ops.push_back(Reg0);
2148 Ops.push_back(Pred);
2149 Ops.push_back(Reg0);
2150 Ops.push_back(Chain);
2152 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2153 std::vector<EVT> ResTys;
2154 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2156 ResTys.push_back(MVT::i32);
2157 ResTys.push_back(MVT::Other);
2158 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2159 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2160 SuperReg = SDValue(VLdDup, 0);
2162 // Extract the subregisters.
2163 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2164 unsigned SubIdx = ARM::dsub_0;
2165 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2166 ReplaceUses(SDValue(N, Vec),
2167 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2168 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2170 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2174 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2176 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2178 EVT VT = N->getValueType(0);
2179 unsigned FirstTblReg = IsExt ? 2 : 1;
2181 // Form a REG_SEQUENCE to force register allocation.
2183 SDValue V0 = N->getOperand(FirstTblReg + 0);
2184 SDValue V1 = N->getOperand(FirstTblReg + 1);
2186 RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
2188 SDValue V2 = N->getOperand(FirstTblReg + 2);
2189 // If it's a vtbl3, form a quad D-register and leave the last part as
2191 SDValue V3 = (NumVecs == 3)
2192 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2193 : N->getOperand(FirstTblReg + 3);
2194 RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2197 SmallVector<SDValue, 6> Ops;
2199 Ops.push_back(N->getOperand(1));
2200 Ops.push_back(RegSeq);
2201 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2202 Ops.push_back(getAL(CurDAG, dl)); // predicate
2203 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2204 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2207 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2209 if (!Subtarget->hasV6T2Ops())
2212 unsigned Opc = isSigned
2213 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2214 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2217 // For unsigned extracts, check for a shift right and mask
2218 unsigned And_imm = 0;
2219 if (N->getOpcode() == ISD::AND) {
2220 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2222 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2223 if (And_imm & (And_imm + 1))
2226 unsigned Srl_imm = 0;
2227 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2229 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2231 // Note: The width operand is encoded as width-1.
2232 unsigned Width = countTrailingOnes(And_imm) - 1;
2233 unsigned LSB = Srl_imm;
2235 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2237 if ((LSB + Width + 1) == N->getValueType(0).getSizeInBits()) {
2238 // It's cheaper to use a right shift to extract the top bits.
2239 if (Subtarget->isThumb()) {
2240 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
2241 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2242 CurDAG->getTargetConstant(LSB, dl, MVT::i32),
2243 getAL(CurDAG, dl), Reg0, Reg0 };
2244 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2247 // ARM models shift instructions as MOVsi with shifter operand.
2248 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
2250 CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, LSB), dl,
2252 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
2253 getAL(CurDAG, dl), Reg0, Reg0 };
2254 return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops);
2257 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2258 CurDAG->getTargetConstant(LSB, dl, MVT::i32),
2259 CurDAG->getTargetConstant(Width, dl, MVT::i32),
2260 getAL(CurDAG, dl), Reg0 };
2261 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2267 // Otherwise, we're looking for a shift of a shift
2268 unsigned Shl_imm = 0;
2269 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2270 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2271 unsigned Srl_imm = 0;
2272 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2273 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2274 // Note: The width operand is encoded as width-1.
2275 unsigned Width = 32 - Srl_imm - 1;
2276 int LSB = Srl_imm - Shl_imm;
2279 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2280 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2281 CurDAG->getTargetConstant(LSB, dl, MVT::i32),
2282 CurDAG->getTargetConstant(Width, dl, MVT::i32),
2283 getAL(CurDAG, dl), Reg0 };
2284 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2288 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2289 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
2291 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, LSB) &&
2292 !isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRA, LSB))
2295 if (LSB + Width > 32)
2298 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2299 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2300 CurDAG->getTargetConstant(LSB, dl, MVT::i32),
2301 CurDAG->getTargetConstant(Width - 1, dl, MVT::i32),
2302 getAL(CurDAG, dl), Reg0 };
2303 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2309 /// Target-specific DAG combining for ISD::XOR.
2310 /// Target-independent combining lowers SELECT_CC nodes of the form
2311 /// select_cc setg[ge] X, 0, X, -X
2312 /// select_cc setgt X, -1, X, -X
2313 /// select_cc setl[te] X, 0, -X, X
2314 /// select_cc setlt X, 1, -X, X
2315 /// which represent Integer ABS into:
2316 /// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2317 /// ARM instruction selection detects the latter and matches it to
2318 /// ARM::ABS or ARM::t2ABS machine node.
2319 SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2320 SDValue XORSrc0 = N->getOperand(0);
2321 SDValue XORSrc1 = N->getOperand(1);
2322 EVT VT = N->getValueType(0);
2324 if (Subtarget->isThumb1Only())
2327 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2330 SDValue ADDSrc0 = XORSrc0.getOperand(0);
2331 SDValue ADDSrc1 = XORSrc0.getOperand(1);
2332 SDValue SRASrc0 = XORSrc1.getOperand(0);
2333 SDValue SRASrc1 = XORSrc1.getOperand(1);
2334 ConstantSDNode *SRAConstant = dyn_cast<ConstantSDNode>(SRASrc1);
2335 EVT XType = SRASrc0.getValueType();
2336 unsigned Size = XType.getSizeInBits() - 1;
2338 if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
2339 XType.isInteger() && SRAConstant != nullptr &&
2340 Size == SRAConstant->getZExtValue()) {
2341 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
2342 return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2348 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2349 // The only time a CONCAT_VECTORS operation can have legal types is when
2350 // two 64-bit vectors are concatenated to a 128-bit vector.
2351 EVT VT = N->getValueType(0);
2352 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2353 llvm_unreachable("unexpected CONCAT_VECTORS");
2354 return createDRegPairNode(VT, N->getOperand(0), N->getOperand(1));
2357 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2360 if (N->isMachineOpcode()) {
2362 return nullptr; // Already selected.
2365 switch (N->getOpcode()) {
2367 case ISD::WRITE_REGISTER: {
2368 SDNode *ResNode = SelectWriteRegister(N);
2373 case ISD::READ_REGISTER: {
2374 SDNode *ResNode = SelectReadRegister(N);
2379 case ISD::INLINEASM: {
2380 SDNode *ResNode = SelectInlineAsm(N);
2386 // Select special operations if XOR node forms integer ABS pattern
2387 SDNode *ResNode = SelectABSOp(N);
2390 // Other cases are autogenerated.
2393 case ISD::Constant: {
2394 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2396 if (Subtarget->useMovt(*MF))
2397 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2398 // be done with MOV + MOVT, at worst.
2401 if (Subtarget->isThumb()) {
2402 UseCP = (Val > 255 && // MOV
2403 ~Val > 255 && // MOV + MVN
2404 !ARM_AM::isThumbImmShiftedVal(Val) && // MOV + LSL
2405 !(Subtarget->hasV6T2Ops() && Val <= 0xffff)); // MOVW
2407 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2408 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2409 !ARM_AM::isSOImmTwoPartVal(Val) && // two instrs.
2410 !(Subtarget->hasV6T2Ops() && Val <= 0xffff)); // MOVW
2414 SDValue CPIdx = CurDAG->getTargetConstantPool(
2415 ConstantInt::get(Type::getInt32Ty(*CurDAG->getContext()), Val),
2416 TLI->getPointerTy(CurDAG->getDataLayout()));
2419 if (Subtarget->isThumb()) {
2420 SDValue Pred = getAL(CurDAG, dl);
2421 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2422 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2423 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2428 CurDAG->getTargetConstant(0, dl, MVT::i32),
2430 CurDAG->getRegister(0, MVT::i32),
2431 CurDAG->getEntryNode()
2433 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2436 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2440 // Other cases are autogenerated.
2443 case ISD::FrameIndex: {
2444 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2445 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2446 SDValue TFI = CurDAG->getTargetFrameIndex(
2447 FI, TLI->getPointerTy(CurDAG->getDataLayout()));
2448 if (Subtarget->isThumb1Only()) {
2449 // Set the alignment of the frame object to 4, to avoid having to generate
2450 // more than one ADD
2451 MachineFrameInfo *MFI = MF->getFrameInfo();
2452 if (MFI->getObjectAlignment(FI) < 4)
2453 MFI->setObjectAlignment(FI, 4);
2454 return CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI,
2455 CurDAG->getTargetConstant(0, dl, MVT::i32));
2457 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2458 ARM::t2ADDri : ARM::ADDri);
2459 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, dl, MVT::i32),
2460 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
2461 CurDAG->getRegister(0, MVT::i32) };
2462 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2466 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2469 case ISD::SIGN_EXTEND_INREG:
2471 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2475 if (Subtarget->isThumb1Only())
2477 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2478 unsigned RHSV = C->getZExtValue();
2480 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2481 unsigned ShImm = Log2_32(RHSV-1);
2484 SDValue V = N->getOperand(0);
2485 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2486 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, dl, MVT::i32);
2487 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2488 if (Subtarget->isThumb()) {
2489 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
2490 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
2492 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
2494 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
2497 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2498 unsigned ShImm = Log2_32(RHSV+1);
2501 SDValue V = N->getOperand(0);
2502 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2503 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, dl, MVT::i32);
2504 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2505 if (Subtarget->isThumb()) {
2506 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
2507 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
2509 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
2511 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
2517 // Check for unsigned bitfield extract
2518 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2521 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2522 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2523 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2524 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2525 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2526 EVT VT = N->getValueType(0);
2529 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2531 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2534 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2535 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2538 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2539 SDValue N2 = N0.getOperand(1);
2540 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2543 unsigned N1CVal = N1C->getZExtValue();
2544 unsigned N2CVal = N2C->getZExtValue();
2545 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2546 (N1CVal & 0xffffU) == 0xffffU &&
2547 (N2CVal & 0xffffU) == 0x0U) {
2548 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2550 SDValue Ops[] = { N0.getOperand(0), Imm16,
2551 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) };
2552 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2557 case ARMISD::VMOVRRD:
2558 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2559 N->getOperand(0), getAL(CurDAG, dl),
2560 CurDAG->getRegister(0, MVT::i32));
2561 case ISD::UMUL_LOHI: {
2562 if (Subtarget->isThumb1Only())
2564 if (Subtarget->isThumb()) {
2565 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2566 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) };
2567 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops);
2569 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2570 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
2571 CurDAG->getRegister(0, MVT::i32) };
2572 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2573 ARM::UMULL : ARM::UMULLv5,
2574 dl, MVT::i32, MVT::i32, Ops);
2577 case ISD::SMUL_LOHI: {
2578 if (Subtarget->isThumb1Only())
2580 if (Subtarget->isThumb()) {
2581 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2582 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32) };
2583 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops);
2585 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2586 getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),
2587 CurDAG->getRegister(0, MVT::i32) };
2588 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2589 ARM::SMULL : ARM::SMULLv5,
2590 dl, MVT::i32, MVT::i32, Ops);
2593 case ARMISD::UMLAL:{
2594 if (Subtarget->isThumb()) {
2595 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2596 N->getOperand(3), getAL(CurDAG, dl),
2597 CurDAG->getRegister(0, MVT::i32)};
2598 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops);
2600 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2601 N->getOperand(3), getAL(CurDAG, dl),
2602 CurDAG->getRegister(0, MVT::i32),
2603 CurDAG->getRegister(0, MVT::i32) };
2604 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2605 ARM::UMLAL : ARM::UMLALv5,
2606 dl, MVT::i32, MVT::i32, Ops);
2609 case ARMISD::SMLAL:{
2610 if (Subtarget->isThumb()) {
2611 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2612 N->getOperand(3), getAL(CurDAG, dl),
2613 CurDAG->getRegister(0, MVT::i32)};
2614 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops);
2616 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2617 N->getOperand(3), getAL(CurDAG, dl),
2618 CurDAG->getRegister(0, MVT::i32),
2619 CurDAG->getRegister(0, MVT::i32) };
2620 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2621 ARM::SMLAL : ARM::SMLALv5,
2622 dl, MVT::i32, MVT::i32, Ops);
2626 SDNode *ResNode = nullptr;
2627 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2628 ResNode = SelectT2IndexedLoad(N);
2630 ResNode = SelectARMIndexedLoad(N);
2633 // Other cases are autogenerated.
2636 case ARMISD::BRCOND: {
2637 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2638 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2639 // Pattern complexity = 6 cost = 1 size = 0
2641 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2642 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2643 // Pattern complexity = 6 cost = 1 size = 0
2645 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2646 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2647 // Pattern complexity = 6 cost = 1 size = 0
2649 unsigned Opc = Subtarget->isThumb() ?
2650 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2651 SDValue Chain = N->getOperand(0);
2652 SDValue N1 = N->getOperand(1);
2653 SDValue N2 = N->getOperand(2);
2654 SDValue N3 = N->getOperand(3);
2655 SDValue InFlag = N->getOperand(4);
2656 assert(N1.getOpcode() == ISD::BasicBlock);
2657 assert(N2.getOpcode() == ISD::Constant);
2658 assert(N3.getOpcode() == ISD::Register);
2660 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2661 cast<ConstantSDNode>(N2)->getZExtValue()), dl,
2663 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2664 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2666 Chain = SDValue(ResNode, 0);
2667 if (N->getNumValues() == 2) {
2668 InFlag = SDValue(ResNode, 1);
2669 ReplaceUses(SDValue(N, 1), InFlag);
2671 ReplaceUses(SDValue(N, 0),
2672 SDValue(Chain.getNode(), Chain.getResNo()));
2675 case ARMISD::VZIP: {
2677 EVT VT = N->getValueType(0);
2678 switch (VT.getSimpleVT().SimpleTy) {
2679 default: return nullptr;
2680 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2681 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2683 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2684 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2685 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2686 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2688 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2690 SDValue Pred = getAL(CurDAG, dl);
2691 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2692 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2693 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2695 case ARMISD::VUZP: {
2697 EVT VT = N->getValueType(0);
2698 switch (VT.getSimpleVT().SimpleTy) {
2699 default: return nullptr;
2700 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2701 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2703 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2704 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2705 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2706 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2708 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2710 SDValue Pred = getAL(CurDAG, dl);
2711 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2712 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2713 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2715 case ARMISD::VTRN: {
2717 EVT VT = N->getValueType(0);
2718 switch (VT.getSimpleVT().SimpleTy) {
2719 default: return nullptr;
2720 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2721 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2723 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2724 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2725 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2727 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2729 SDValue Pred = getAL(CurDAG, dl);
2730 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2731 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2732 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2734 case ARMISD::BUILD_VECTOR: {
2735 EVT VecVT = N->getValueType(0);
2736 EVT EltVT = VecVT.getVectorElementType();
2737 unsigned NumElts = VecVT.getVectorNumElements();
2738 if (EltVT == MVT::f64) {
2739 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2740 return createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2742 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2744 return createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2745 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2746 return createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
2747 N->getOperand(2), N->getOperand(3));
2750 case ARMISD::VLD2DUP: {
2751 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
2753 return SelectVLDDup(N, false, 2, Opcodes);
2756 case ARMISD::VLD3DUP: {
2757 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
2758 ARM::VLD3DUPd16Pseudo,
2759 ARM::VLD3DUPd32Pseudo };
2760 return SelectVLDDup(N, false, 3, Opcodes);
2763 case ARMISD::VLD4DUP: {
2764 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
2765 ARM::VLD4DUPd16Pseudo,
2766 ARM::VLD4DUPd32Pseudo };
2767 return SelectVLDDup(N, false, 4, Opcodes);
2770 case ARMISD::VLD2DUP_UPD: {
2771 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
2772 ARM::VLD2DUPd16wb_fixed,
2773 ARM::VLD2DUPd32wb_fixed };
2774 return SelectVLDDup(N, true, 2, Opcodes);
2777 case ARMISD::VLD3DUP_UPD: {
2778 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
2779 ARM::VLD3DUPd16Pseudo_UPD,
2780 ARM::VLD3DUPd32Pseudo_UPD };
2781 return SelectVLDDup(N, true, 3, Opcodes);
2784 case ARMISD::VLD4DUP_UPD: {
2785 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
2786 ARM::VLD4DUPd16Pseudo_UPD,
2787 ARM::VLD4DUPd32Pseudo_UPD };
2788 return SelectVLDDup(N, true, 4, Opcodes);
2791 case ARMISD::VLD1_UPD: {
2792 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
2793 ARM::VLD1d16wb_fixed,
2794 ARM::VLD1d32wb_fixed,
2795 ARM::VLD1d64wb_fixed };
2796 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
2797 ARM::VLD1q16wb_fixed,
2798 ARM::VLD1q32wb_fixed,
2799 ARM::VLD1q64wb_fixed };
2800 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, nullptr);
2803 case ARMISD::VLD2_UPD: {
2804 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
2805 ARM::VLD2d16wb_fixed,
2806 ARM::VLD2d32wb_fixed,
2807 ARM::VLD1q64wb_fixed};
2808 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
2809 ARM::VLD2q16PseudoWB_fixed,
2810 ARM::VLD2q32PseudoWB_fixed };
2811 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, nullptr);
2814 case ARMISD::VLD3_UPD: {
2815 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
2816 ARM::VLD3d16Pseudo_UPD,
2817 ARM::VLD3d32Pseudo_UPD,
2818 ARM::VLD1d64TPseudoWB_fixed};
2819 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2820 ARM::VLD3q16Pseudo_UPD,
2821 ARM::VLD3q32Pseudo_UPD };
2822 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2823 ARM::VLD3q16oddPseudo_UPD,
2824 ARM::VLD3q32oddPseudo_UPD };
2825 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2828 case ARMISD::VLD4_UPD: {
2829 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
2830 ARM::VLD4d16Pseudo_UPD,
2831 ARM::VLD4d32Pseudo_UPD,
2832 ARM::VLD1d64QPseudoWB_fixed};
2833 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2834 ARM::VLD4q16Pseudo_UPD,
2835 ARM::VLD4q32Pseudo_UPD };
2836 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2837 ARM::VLD4q16oddPseudo_UPD,
2838 ARM::VLD4q32oddPseudo_UPD };
2839 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2842 case ARMISD::VLD2LN_UPD: {
2843 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
2844 ARM::VLD2LNd16Pseudo_UPD,
2845 ARM::VLD2LNd32Pseudo_UPD };
2846 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2847 ARM::VLD2LNq32Pseudo_UPD };
2848 return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2851 case ARMISD::VLD3LN_UPD: {
2852 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
2853 ARM::VLD3LNd16Pseudo_UPD,
2854 ARM::VLD3LNd32Pseudo_UPD };
2855 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2856 ARM::VLD3LNq32Pseudo_UPD };
2857 return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2860 case ARMISD::VLD4LN_UPD: {
2861 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
2862 ARM::VLD4LNd16Pseudo_UPD,
2863 ARM::VLD4LNd32Pseudo_UPD };
2864 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2865 ARM::VLD4LNq32Pseudo_UPD };
2866 return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2869 case ARMISD::VST1_UPD: {
2870 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
2871 ARM::VST1d16wb_fixed,
2872 ARM::VST1d32wb_fixed,
2873 ARM::VST1d64wb_fixed };
2874 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
2875 ARM::VST1q16wb_fixed,
2876 ARM::VST1q32wb_fixed,
2877 ARM::VST1q64wb_fixed };
2878 return SelectVST(N, true, 1, DOpcodes, QOpcodes, nullptr);
2881 case ARMISD::VST2_UPD: {
2882 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
2883 ARM::VST2d16wb_fixed,
2884 ARM::VST2d32wb_fixed,
2885 ARM::VST1q64wb_fixed};
2886 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
2887 ARM::VST2q16PseudoWB_fixed,
2888 ARM::VST2q32PseudoWB_fixed };
2889 return SelectVST(N, true, 2, DOpcodes, QOpcodes, nullptr);
2892 case ARMISD::VST3_UPD: {
2893 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
2894 ARM::VST3d16Pseudo_UPD,
2895 ARM::VST3d32Pseudo_UPD,
2896 ARM::VST1d64TPseudoWB_fixed};
2897 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2898 ARM::VST3q16Pseudo_UPD,
2899 ARM::VST3q32Pseudo_UPD };
2900 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2901 ARM::VST3q16oddPseudo_UPD,
2902 ARM::VST3q32oddPseudo_UPD };
2903 return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2906 case ARMISD::VST4_UPD: {
2907 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
2908 ARM::VST4d16Pseudo_UPD,
2909 ARM::VST4d32Pseudo_UPD,
2910 ARM::VST1d64QPseudoWB_fixed};
2911 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2912 ARM::VST4q16Pseudo_UPD,
2913 ARM::VST4q32Pseudo_UPD };
2914 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2915 ARM::VST4q16oddPseudo_UPD,
2916 ARM::VST4q32oddPseudo_UPD };
2917 return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2920 case ARMISD::VST2LN_UPD: {
2921 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
2922 ARM::VST2LNd16Pseudo_UPD,
2923 ARM::VST2LNd32Pseudo_UPD };
2924 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2925 ARM::VST2LNq32Pseudo_UPD };
2926 return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2929 case ARMISD::VST3LN_UPD: {
2930 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
2931 ARM::VST3LNd16Pseudo_UPD,
2932 ARM::VST3LNd32Pseudo_UPD };
2933 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2934 ARM::VST3LNq32Pseudo_UPD };
2935 return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2938 case ARMISD::VST4LN_UPD: {
2939 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
2940 ARM::VST4LNd16Pseudo_UPD,
2941 ARM::VST4LNd32Pseudo_UPD };
2942 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2943 ARM::VST4LNq32Pseudo_UPD };
2944 return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2947 case ISD::INTRINSIC_VOID:
2948 case ISD::INTRINSIC_W_CHAIN: {
2949 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2954 case Intrinsic::arm_ldaexd:
2955 case Intrinsic::arm_ldrexd: {
2957 SDValue Chain = N->getOperand(0);
2958 SDValue MemAddr = N->getOperand(2);
2959 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
2961 bool IsAcquire = IntNo == Intrinsic::arm_ldaexd;
2962 unsigned NewOpc = isThumb ? (IsAcquire ? ARM::t2LDAEXD : ARM::t2LDREXD)
2963 : (IsAcquire ? ARM::LDAEXD : ARM::LDREXD);
2965 // arm_ldrexd returns a i64 value in {i32, i32}
2966 std::vector<EVT> ResTys;
2968 ResTys.push_back(MVT::i32);
2969 ResTys.push_back(MVT::i32);
2971 ResTys.push_back(MVT::Untyped);
2972 ResTys.push_back(MVT::Other);
2974 // Place arguments in the right order.
2975 SmallVector<SDValue, 7> Ops;
2976 Ops.push_back(MemAddr);
2977 Ops.push_back(getAL(CurDAG, dl));
2978 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2979 Ops.push_back(Chain);
2980 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
2981 // Transfer memoperands.
2982 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2983 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2984 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
2987 SDValue OutChain = isThumb ? SDValue(Ld, 2) : SDValue(Ld, 1);
2988 if (!SDValue(N, 0).use_empty()) {
2991 Result = SDValue(Ld, 0);
2994 CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32);
2995 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2996 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
2997 Result = SDValue(ResNode,0);
2999 ReplaceUses(SDValue(N, 0), Result);
3001 if (!SDValue(N, 1).use_empty()) {
3004 Result = SDValue(Ld, 1);
3007 CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32);
3008 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3009 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3010 Result = SDValue(ResNode,0);
3012 ReplaceUses(SDValue(N, 1), Result);
3014 ReplaceUses(SDValue(N, 2), OutChain);
3017 case Intrinsic::arm_stlexd:
3018 case Intrinsic::arm_strexd: {
3020 SDValue Chain = N->getOperand(0);
3021 SDValue Val0 = N->getOperand(2);
3022 SDValue Val1 = N->getOperand(3);
3023 SDValue MemAddr = N->getOperand(4);
3025 // Store exclusive double return a i32 value which is the return status
3026 // of the issued store.
3027 const EVT ResTys[] = {MVT::i32, MVT::Other};
3029 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3030 // Place arguments in the right order.
3031 SmallVector<SDValue, 7> Ops;
3033 Ops.push_back(Val0);
3034 Ops.push_back(Val1);
3036 // arm_strexd uses GPRPair.
3037 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
3038 Ops.push_back(MemAddr);
3039 Ops.push_back(getAL(CurDAG, dl));
3040 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3041 Ops.push_back(Chain);
3043 bool IsRelease = IntNo == Intrinsic::arm_stlexd;
3044 unsigned NewOpc = isThumb ? (IsRelease ? ARM::t2STLEXD : ARM::t2STREXD)
3045 : (IsRelease ? ARM::STLEXD : ARM::STREXD);
3047 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3048 // Transfer memoperands.
3049 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3050 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3051 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3056 case Intrinsic::arm_neon_vld1: {
3057 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3058 ARM::VLD1d32, ARM::VLD1d64 };
3059 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3060 ARM::VLD1q32, ARM::VLD1q64};
3061 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, nullptr);
3064 case Intrinsic::arm_neon_vld2: {
3065 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3066 ARM::VLD2d32, ARM::VLD1q64 };
3067 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3068 ARM::VLD2q32Pseudo };
3069 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
3072 case Intrinsic::arm_neon_vld3: {
3073 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
3076 ARM::VLD1d64TPseudo };
3077 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3078 ARM::VLD3q16Pseudo_UPD,
3079 ARM::VLD3q32Pseudo_UPD };
3080 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3081 ARM::VLD3q16oddPseudo,
3082 ARM::VLD3q32oddPseudo };
3083 return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3086 case Intrinsic::arm_neon_vld4: {
3087 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
3090 ARM::VLD1d64QPseudo };
3091 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3092 ARM::VLD4q16Pseudo_UPD,
3093 ARM::VLD4q32Pseudo_UPD };
3094 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3095 ARM::VLD4q16oddPseudo,
3096 ARM::VLD4q32oddPseudo };
3097 return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3100 case Intrinsic::arm_neon_vld2lane: {
3101 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
3102 ARM::VLD2LNd16Pseudo,
3103 ARM::VLD2LNd32Pseudo };
3104 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
3105 ARM::VLD2LNq32Pseudo };
3106 return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3109 case Intrinsic::arm_neon_vld3lane: {
3110 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
3111 ARM::VLD3LNd16Pseudo,
3112 ARM::VLD3LNd32Pseudo };
3113 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
3114 ARM::VLD3LNq32Pseudo };
3115 return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3118 case Intrinsic::arm_neon_vld4lane: {
3119 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
3120 ARM::VLD4LNd16Pseudo,
3121 ARM::VLD4LNd32Pseudo };
3122 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
3123 ARM::VLD4LNq32Pseudo };
3124 return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3127 case Intrinsic::arm_neon_vst1: {
3128 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3129 ARM::VST1d32, ARM::VST1d64 };
3130 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3131 ARM::VST1q32, ARM::VST1q64 };
3132 return SelectVST(N, false, 1, DOpcodes, QOpcodes, nullptr);
3135 case Intrinsic::arm_neon_vst2: {
3136 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3137 ARM::VST2d32, ARM::VST1q64 };
3138 static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3139 ARM::VST2q32Pseudo };
3140 return SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
3143 case Intrinsic::arm_neon_vst3: {
3144 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
3147 ARM::VST1d64TPseudo };
3148 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3149 ARM::VST3q16Pseudo_UPD,
3150 ARM::VST3q32Pseudo_UPD };
3151 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
3152 ARM::VST3q16oddPseudo,
3153 ARM::VST3q32oddPseudo };
3154 return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3157 case Intrinsic::arm_neon_vst4: {
3158 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
3161 ARM::VST1d64QPseudo };
3162 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3163 ARM::VST4q16Pseudo_UPD,
3164 ARM::VST4q32Pseudo_UPD };
3165 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
3166 ARM::VST4q16oddPseudo,
3167 ARM::VST4q32oddPseudo };
3168 return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3171 case Intrinsic::arm_neon_vst2lane: {
3172 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
3173 ARM::VST2LNd16Pseudo,
3174 ARM::VST2LNd32Pseudo };
3175 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
3176 ARM::VST2LNq32Pseudo };
3177 return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3180 case Intrinsic::arm_neon_vst3lane: {
3181 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
3182 ARM::VST3LNd16Pseudo,
3183 ARM::VST3LNd32Pseudo };
3184 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
3185 ARM::VST3LNq32Pseudo };
3186 return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3189 case Intrinsic::arm_neon_vst4lane: {
3190 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
3191 ARM::VST4LNd16Pseudo,
3192 ARM::VST4LNd32Pseudo };
3193 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
3194 ARM::VST4LNq32Pseudo };
3195 return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3201 case ISD::INTRINSIC_WO_CHAIN: {
3202 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3207 case Intrinsic::arm_neon_vtbl2:
3208 return SelectVTBL(N, false, 2, ARM::VTBL2);
3209 case Intrinsic::arm_neon_vtbl3:
3210 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3211 case Intrinsic::arm_neon_vtbl4:
3212 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3214 case Intrinsic::arm_neon_vtbx2:
3215 return SelectVTBL(N, true, 2, ARM::VTBX2);
3216 case Intrinsic::arm_neon_vtbx3:
3217 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3218 case Intrinsic::arm_neon_vtbx4:
3219 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3224 case ARMISD::VTBL1: {
3226 EVT VT = N->getValueType(0);
3227 SmallVector<SDValue, 6> Ops;
3229 Ops.push_back(N->getOperand(0));
3230 Ops.push_back(N->getOperand(1));
3231 Ops.push_back(getAL(CurDAG, dl)); // Predicate
3232 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3233 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops);
3235 case ARMISD::VTBL2: {
3237 EVT VT = N->getValueType(0);
3239 // Form a REG_SEQUENCE to force register allocation.
3240 SDValue V0 = N->getOperand(0);
3241 SDValue V1 = N->getOperand(1);
3242 SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
3244 SmallVector<SDValue, 6> Ops;
3245 Ops.push_back(RegSeq);
3246 Ops.push_back(N->getOperand(2));
3247 Ops.push_back(getAL(CurDAG, dl)); // Predicate
3248 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3249 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops);
3252 case ISD::CONCAT_VECTORS:
3253 return SelectConcatVector(N);
3256 return SelectCode(N);
3259 // Inspect a register string of the form
3260 // cp<coprocessor>:<opc1>:c<CRn>:c<CRm>:<opc2> (32bit) or
3261 // cp<coprocessor>:<opc1>:c<CRm> (64bit) inspect the fields of the string
3262 // and obtain the integer operands from them, adding these operands to the
3264 static void getIntOperandsFromRegisterString(StringRef RegString,
3265 SelectionDAG *CurDAG, SDLoc DL,
3266 std::vector<SDValue>& Ops) {
3267 SmallVector<StringRef, 5> Fields;
3268 RegString.split(Fields, ':');
3270 if (Fields.size() > 1) {
3271 bool AllIntFields = true;
3273 for (StringRef Field : Fields) {
3274 // Need to trim out leading 'cp' characters and get the integer field.
3276 AllIntFields &= !Field.trim("CPcp").getAsInteger(10, IntField);
3277 Ops.push_back(CurDAG->getTargetConstant(IntField, DL, MVT::i32));
3280 assert(AllIntFields &&
3281 "Unexpected non-integer value in special register string.");
3285 // Maps a Banked Register string to its mask value. The mask value returned is
3286 // for use in the MRSbanked / MSRbanked instruction nodes as the Banked Register
3287 // mask operand, which expresses which register is to be used, e.g. r8, and in
3288 // which mode it is to be used, e.g. usr. Returns -1 to signify that the string
3290 static inline int getBankedRegisterMask(StringRef RegString) {
3291 return StringSwitch<int>(RegString.lower())
3292 .Case("r8_usr", 0x00)
3293 .Case("r9_usr", 0x01)
3294 .Case("r10_usr", 0x02)
3295 .Case("r11_usr", 0x03)
3296 .Case("r12_usr", 0x04)
3297 .Case("sp_usr", 0x05)
3298 .Case("lr_usr", 0x06)
3299 .Case("r8_fiq", 0x08)
3300 .Case("r9_fiq", 0x09)
3301 .Case("r10_fiq", 0x0a)
3302 .Case("r11_fiq", 0x0b)
3303 .Case("r12_fiq", 0x0c)
3304 .Case("sp_fiq", 0x0d)
3305 .Case("lr_fiq", 0x0e)
3306 .Case("lr_irq", 0x10)
3307 .Case("sp_irq", 0x11)
3308 .Case("lr_svc", 0x12)
3309 .Case("sp_svc", 0x13)
3310 .Case("lr_abt", 0x14)
3311 .Case("sp_abt", 0x15)
3312 .Case("lr_und", 0x16)
3313 .Case("sp_und", 0x17)
3314 .Case("lr_mon", 0x1c)
3315 .Case("sp_mon", 0x1d)
3316 .Case("elr_hyp", 0x1e)
3317 .Case("sp_hyp", 0x1f)
3318 .Case("spsr_fiq", 0x2e)
3319 .Case("spsr_irq", 0x30)
3320 .Case("spsr_svc", 0x32)
3321 .Case("spsr_abt", 0x34)
3322 .Case("spsr_und", 0x36)
3323 .Case("spsr_mon", 0x3c)
3324 .Case("spsr_hyp", 0x3e)
3328 // Maps a MClass special register string to its value for use in the
3329 // t2MRS_M / t2MSR_M instruction nodes as the SYSm value operand.
3330 // Returns -1 to signify that the string was invalid.
3331 static inline int getMClassRegisterSYSmValueMask(StringRef RegString) {
3332 return StringSwitch<int>(RegString.lower())
3342 .Case("primask", 0x10)
3343 .Case("basepri", 0x11)
3344 .Case("basepri_max", 0x12)
3345 .Case("faultmask", 0x13)
3346 .Case("control", 0x14)
3350 // The flags here are common to those allowed for apsr in the A class cores and
3351 // those allowed for the special registers in the M class cores. Returns a
3352 // value representing which flags were present, -1 if invalid.
3353 static inline int getMClassFlagsMask(StringRef Flags, bool hasThumb2DSP) {
3355 return 0x2 | (int)hasThumb2DSP;
3357 return StringSwitch<int>(Flags)
3360 .Case("nzcvqg", 0x3)
3364 static int getMClassRegisterMask(StringRef Reg, StringRef Flags, bool IsRead,
3365 const ARMSubtarget *Subtarget) {
3366 // Ensure that the register (without flags) was a valid M Class special
3368 int SYSmvalue = getMClassRegisterSYSmValueMask(Reg);
3369 if (SYSmvalue == -1)
3372 // basepri, basepri_max and faultmask are only valid for V7m.
3373 if (!Subtarget->hasV7Ops() && SYSmvalue >= 0x11 && SYSmvalue <= 0x13)
3376 // If it was a read then we won't be expecting flags and so at this point
3377 // we can return the mask.
3379 assert (Flags.empty() && "Unexpected flags for reading M class register.");
3383 // We know we are now handling a write so need to get the mask for the flags.
3384 int Mask = getMClassFlagsMask(Flags, Subtarget->hasThumb2DSP());
3386 // Only apsr, iapsr, eapsr, xpsr can have flags. The other register values
3387 // shouldn't have flags present.
3388 if ((SYSmvalue < 0x4 && Mask == -1) || (SYSmvalue > 0x4 && !Flags.empty()))
3391 // The _g and _nzcvqg versions are only valid if the DSP extension is
3393 if (!Subtarget->hasThumb2DSP() && (Mask & 0x1))
3396 // The register was valid so need to put the mask in the correct place
3397 // (the flags need to be in bits 11-10) and combine with the SYSmvalue to
3398 // construct the operand for the instruction node.
3399 if (SYSmvalue < 0x4)
3400 return SYSmvalue | Mask << 10;
3405 static int getARClassRegisterMask(StringRef Reg, StringRef Flags) {
3406 // The mask operand contains the special register (R Bit) in bit 4, whether
3407 // the register is spsr (R bit is 1) or one of cpsr/apsr (R bit is 0), and
3408 // bits 3-0 contains the fields to be accessed in the special register, set by
3409 // the flags provided with the register.
3411 if (Reg == "apsr") {
3412 // The flags permitted for apsr are the same flags that are allowed in
3413 // M class registers. We get the flag value and then shift the flags into
3414 // the correct place to combine with the mask.
3415 Mask = getMClassFlagsMask(Flags, true);
3421 if (Reg != "cpsr" && Reg != "spsr") {
3425 // This is the same as if the flags were "fc"
3426 if (Flags.empty() || Flags == "all")
3429 // Inspect the supplied flags string and set the bits in the mask for
3430 // the relevant and valid flags allowed for cpsr and spsr.
3431 for (char Flag : Flags) {
3450 // This avoids allowing strings where the same flag bit appears twice.
3451 if (!FlagVal || (Mask & FlagVal))
3456 // If the register is spsr then we need to set the R bit.
3463 // Lower the read_register intrinsic to ARM specific DAG nodes
3464 // using the supplied metadata string to select the instruction node to use
3465 // and the registers/masks to construct as operands for the node.
3466 SDNode *ARMDAGToDAGISel::SelectReadRegister(SDNode *N){
3467 const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
3468 const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
3469 bool IsThumb2 = Subtarget->isThumb2();
3472 std::vector<SDValue> Ops;
3473 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops);
3476 // If the special register string was constructed of fields (as defined
3477 // in the ACLE) then need to lower to MRC node (32 bit) or
3478 // MRRC node(64 bit), we can make the distinction based on the number of
3479 // operands we have.
3481 SmallVector<EVT, 3> ResTypes;
3482 if (Ops.size() == 5){
3483 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC;
3484 ResTypes.append({ MVT::i32, MVT::Other });
3486 assert(Ops.size() == 3 &&
3487 "Invalid number of fields in special register string.");
3488 Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC;
3489 ResTypes.append({ MVT::i32, MVT::i32, MVT::Other });
3492 Ops.push_back(getAL(CurDAG, DL));
3493 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3494 Ops.push_back(N->getOperand(0));
3495 return CurDAG->getMachineNode(Opcode, DL, ResTypes, Ops);
3498 std::string SpecialReg = RegString->getString().lower();
3500 int BankedReg = getBankedRegisterMask(SpecialReg);
3501 if (BankedReg != -1) {
3502 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32),
3503 getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
3505 return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked,
3506 DL, MVT::i32, MVT::Other, Ops);
3509 // The VFP registers are read by creating SelectionDAG nodes with opcodes
3510 // corresponding to the register that is being read from. So we switch on the
3511 // string to find which opcode we need to use.
3512 unsigned Opcode = StringSwitch<unsigned>(SpecialReg)
3513 .Case("fpscr", ARM::VMRS)
3514 .Case("fpexc", ARM::VMRS_FPEXC)
3515 .Case("fpsid", ARM::VMRS_FPSID)
3516 .Case("mvfr0", ARM::VMRS_MVFR0)
3517 .Case("mvfr1", ARM::VMRS_MVFR1)
3518 .Case("mvfr2", ARM::VMRS_MVFR2)
3519 .Case("fpinst", ARM::VMRS_FPINST)
3520 .Case("fpinst2", ARM::VMRS_FPINST2)
3523 // If an opcode was found then we can lower the read to a VFP instruction.
3525 if (!Subtarget->hasVFP2())
3527 if (Opcode == ARM::VMRS_MVFR2 && !Subtarget->hasFPARMv8())
3530 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
3532 return CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::Other, Ops);
3535 // If the target is M Class then need to validate that the register string
3536 // is an acceptable value, so check that a mask can be constructed from the
3538 if (Subtarget->isMClass()) {
3539 int SYSmValue = getMClassRegisterMask(SpecialReg, "", true, Subtarget);
3540 if (SYSmValue == -1)
3543 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
3544 getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
3546 return CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops);
3549 // Here we know the target is not M Class so we need to check if it is one
3550 // of the remaining possible values which are apsr, cpsr or spsr.
3551 if (SpecialReg == "apsr" || SpecialReg == "cpsr") {
3552 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
3554 return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS, DL,
3555 MVT::i32, MVT::Other, Ops);
3558 if (SpecialReg == "spsr") {
3559 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
3561 return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys,
3562 DL, MVT::i32, MVT::Other, Ops);
3568 // Lower the write_register intrinsic to ARM specific DAG nodes
3569 // using the supplied metadata string to select the instruction node to use
3570 // and the registers/masks to use in the nodes
3571 SDNode *ARMDAGToDAGISel::SelectWriteRegister(SDNode *N){
3572 const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(N->getOperand(1));
3573 const MDString *RegString = dyn_cast<MDString>(MD->getMD()->getOperand(0));
3574 bool IsThumb2 = Subtarget->isThumb2();
3577 std::vector<SDValue> Ops;
3578 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops);
3581 // If the special register string was constructed of fields (as defined
3582 // in the ACLE) then need to lower to MCR node (32 bit) or
3583 // MCRR node(64 bit), we can make the distinction based on the number of
3584 // operands we have.
3586 if (Ops.size() == 5) {
3587 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR;
3588 Ops.insert(Ops.begin()+2, N->getOperand(2));
3590 assert(Ops.size() == 3 &&
3591 "Invalid number of fields in special register string.");
3592 Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR;
3593 SDValue WriteValue[] = { N->getOperand(2), N->getOperand(3) };
3594 Ops.insert(Ops.begin()+2, WriteValue, WriteValue+2);
3597 Ops.push_back(getAL(CurDAG, DL));
3598 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3599 Ops.push_back(N->getOperand(0));
3601 return CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
3604 std::string SpecialReg = RegString->getString().lower();
3605 int BankedReg = getBankedRegisterMask(SpecialReg);
3606 if (BankedReg != -1) {
3607 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32), N->getOperand(2),
3608 getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
3610 return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked,
3611 DL, MVT::Other, Ops);
3614 // The VFP registers are written to by creating SelectionDAG nodes with
3615 // opcodes corresponding to the register that is being written. So we switch
3616 // on the string to find which opcode we need to use.
3617 unsigned Opcode = StringSwitch<unsigned>(SpecialReg)
3618 .Case("fpscr", ARM::VMSR)
3619 .Case("fpexc", ARM::VMSR_FPEXC)
3620 .Case("fpsid", ARM::VMSR_FPSID)
3621 .Case("fpinst", ARM::VMSR_FPINST)
3622 .Case("fpinst2", ARM::VMSR_FPINST2)
3626 if (!Subtarget->hasVFP2())
3628 Ops = { N->getOperand(2), getAL(CurDAG, DL),
3629 CurDAG->getRegister(0, MVT::i32), N->getOperand(0) };
3630 return CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
3633 SmallVector<StringRef, 5> Fields;
3634 StringRef(SpecialReg).split(Fields, '_', 1, false);
3635 std::string Reg = Fields[0].str();
3636 StringRef Flags = Fields.size() == 2 ? Fields[1] : "";
3638 // If the target was M Class then need to validate the special register value
3639 // and retrieve the mask for use in the instruction node.
3640 if (Subtarget->isMClass()) {
3641 // basepri_max gets split so need to correct Reg and Flags.
3642 if (SpecialReg == "basepri_max") {
3646 int SYSmValue = getMClassRegisterMask(Reg, Flags, false, Subtarget);
3647 if (SYSmValue == -1)
3650 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32),
3651 N->getOperand(2), getAL(CurDAG, DL),
3652 CurDAG->getRegister(0, MVT::i32), N->getOperand(0) };
3653 return CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops);
3656 // We then check to see if a valid mask can be constructed for one of the
3657 // register string values permitted for the A and R class cores. These values
3658 // are apsr, spsr and cpsr; these are also valid on older cores.
3659 int Mask = getARClassRegisterMask(Reg, Flags);
3661 Ops = { CurDAG->getTargetConstant(Mask, DL, MVT::i32), N->getOperand(2),
3662 getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32),
3664 return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSR_AR : ARM::MSR,
3665 DL, MVT::Other, Ops);
3671 SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
3672 std::vector<SDValue> AsmNodeOperands;
3673 unsigned Flag, Kind;
3674 bool Changed = false;
3675 unsigned NumOps = N->getNumOperands();
3677 // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
3678 // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
3679 // (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
3680 // respectively. Since there is no constraint to explicitly specify a
3681 // reg pair, we use GPRPair reg class for "%r" for 64-bit data. For Thumb,
3682 // the 64-bit data may be referred by H, Q, R modifiers, so we still pack
3683 // them into a GPRPair.
3686 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1)
3687 : SDValue(nullptr,0);
3689 SmallVector<bool, 8> OpChanged;
3690 // Glue node will be appended late.
3691 for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
3692 SDValue op = N->getOperand(i);
3693 AsmNodeOperands.push_back(op);
3695 if (i < InlineAsm::Op_FirstOperand)
3698 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
3699 Flag = C->getZExtValue();
3700 Kind = InlineAsm::getKind(Flag);
3705 // Immediate operands to inline asm in the SelectionDAG are modeled with
3706 // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
3707 // the second is a constant with the value of the immediate. If we get here
3708 // and we have a Kind_Imm, skip the next operand, and continue.
3709 if (Kind == InlineAsm::Kind_Imm) {
3710 SDValue op = N->getOperand(++i);
3711 AsmNodeOperands.push_back(op);
3715 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
3717 OpChanged.push_back(false);
3719 unsigned DefIdx = 0;
3720 bool IsTiedToChangedOp = false;
3721 // If it's a use that is tied with a previous def, it has no
3722 // reg class constraint.
3723 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
3724 IsTiedToChangedOp = OpChanged[DefIdx];
3726 if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
3727 && Kind != InlineAsm::Kind_RegDefEarlyClobber)
3731 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
3732 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
3736 assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
3737 SDValue V0 = N->getOperand(i+1);
3738 SDValue V1 = N->getOperand(i+2);
3739 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
3740 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
3742 MachineRegisterInfo &MRI = MF->getRegInfo();
3744 if (Kind == InlineAsm::Kind_RegDef ||
3745 Kind == InlineAsm::Kind_RegDefEarlyClobber) {
3746 // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
3747 // the original GPRs.
3749 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3750 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3751 SDValue Chain = SDValue(N,0);
3753 SDNode *GU = N->getGluedUser();
3754 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
3757 // Extract values from a GPRPair reg and copy to the original GPR reg.
3758 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
3760 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
3762 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
3763 RegCopy.getValue(1));
3764 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
3766 // Update the original glue user.
3767 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
3768 Ops.push_back(T1.getValue(1));
3769 CurDAG->UpdateNodeOperands(GU, Ops);
3772 // For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
3773 // GPRPair and then pass the GPRPair to the inline asm.
3774 SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
3776 // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
3777 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
3779 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
3781 SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
3783 // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
3784 // i32 VRs of inline asm with it.
3785 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3786 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3787 Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
3789 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
3790 Glue = Chain.getValue(1);
3795 if(PairedReg.getNode()) {
3796 OpChanged[OpChanged.size() -1 ] = true;
3797 Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
3798 if (IsTiedToChangedOp)
3799 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
3801 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
3802 // Replace the current flag.
3803 AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
3804 Flag, dl, MVT::i32);
3805 // Add the new register node and skip the original two GPRs.
3806 AsmNodeOperands.push_back(PairedReg);
3807 // Skip the next two GPRs.
3813 AsmNodeOperands.push_back(Glue);
3817 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
3818 CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
3820 return New.getNode();
3824 bool ARMDAGToDAGISel::
3825 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
3826 std::vector<SDValue> &OutOps) {
3827 switch(ConstraintID) {
3829 llvm_unreachable("Unexpected asm memory constraint");
3830 case InlineAsm::Constraint_i:
3831 // FIXME: It seems strange that 'i' is needed here since it's supposed to
3832 // be an immediate and not a memory constraint.
3834 case InlineAsm::Constraint_m:
3835 case InlineAsm::Constraint_Q:
3836 case InlineAsm::Constraint_Um:
3837 case InlineAsm::Constraint_Un:
3838 case InlineAsm::Constraint_Uq:
3839 case InlineAsm::Constraint_Us:
3840 case InlineAsm::Constraint_Ut:
3841 case InlineAsm::Constraint_Uv:
3842 case InlineAsm::Constraint_Uy:
3843 // Require the address to be in a register. That is safe for all ARM
3844 // variants and it is hard to do anything much smarter without knowing
3845 // how the operand is used.
3846 OutOps.push_back(Op);
3852 /// createARMISelDag - This pass converts a legalized DAG into a
3853 /// ARM-specific DAG, ready for instruction scheduling.
3855 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3856 CodeGenOpt::Level OptLevel) {
3857 return new ARMDAGToDAGISel(TM, OptLevel);