1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMAddressingModes.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
40 DisableShifterOp("disable-shifter-op", cl::Hidden,
41 cl::desc("Disable isel of shifter-op"),
44 //===--------------------------------------------------------------------===//
45 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
46 /// instructions for SelectionDAG operations.
51 AM2_BASE, // Simple AM2 (+-imm12)
52 AM2_SHOP // Shifter-op AM2
55 class ARMDAGToDAGISel : public SelectionDAGISel {
56 ARMBaseTargetMachine &TM;
58 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
59 /// make the right decision when generating code for different targets.
60 const ARMSubtarget *Subtarget;
63 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
64 CodeGenOpt::Level OptLevel)
65 : SelectionDAGISel(tm, OptLevel), TM(tm),
66 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
69 virtual const char *getPassName() const {
70 return "ARM Instruction Selection";
73 /// getI32Imm - Return a target constant of type i32 with the specified
75 inline SDValue getI32Imm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, MVT::i32);
79 SDNode *Select(SDNode *N);
81 bool isShifterOpProfitable(const SDValue &Shift,
82 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
83 bool SelectShifterOperandReg(SDValue N, SDValue &A,
84 SDValue &B, SDValue &C);
85 bool SelectShiftShifterOperandReg(SDValue N, SDValue &A,
86 SDValue &B, SDValue &C);
87 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
88 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
90 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
91 SDValue &Offset, SDValue &Opc);
92 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
94 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
97 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
99 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
102 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
104 SelectAddrMode2Worker(N, Base, Offset, Opc);
105 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
106 // This always matches one way or another.
110 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
111 SDValue &Offset, SDValue &Opc);
112 bool SelectAddrMode3(SDValue N, SDValue &Base,
113 SDValue &Offset, SDValue &Opc);
114 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
115 SDValue &Offset, SDValue &Opc);
116 bool SelectAddrMode4(SDValue N, SDValue &Addr, SDValue &Mode);
117 bool SelectAddrMode5(SDValue N, SDValue &Base,
119 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
121 bool SelectAddrModePC(SDValue N, SDValue &Offset,
124 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
125 bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
126 SDValue &Base, SDValue &OffImm,
128 bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
129 SDValue &OffImm, SDValue &Offset);
130 bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
131 SDValue &OffImm, SDValue &Offset);
132 bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
133 SDValue &OffImm, SDValue &Offset);
134 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
136 bool SelectT2ShifterOperandReg(SDValue N,
137 SDValue &BaseReg, SDValue &Opc);
138 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
139 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
141 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
143 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
144 SDValue &OffReg, SDValue &ShImm);
146 inline bool Pred_so_imm(SDNode *inN) const {
147 ConstantSDNode *N = cast<ConstantSDNode>(inN);
148 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
151 inline bool Pred_t2_so_imm(SDNode *inN) const {
152 ConstantSDNode *N = cast<ConstantSDNode>(inN);
153 return ARM_AM::getT2SOImmVal(N->getZExtValue()) != -1;
156 // Include the pieces autogenerated from the target description.
157 #include "ARMGenDAGISel.inc"
160 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
162 SDNode *SelectARMIndexedLoad(SDNode *N);
163 SDNode *SelectT2IndexedLoad(SDNode *N);
165 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
166 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
167 /// loads of D registers and even subregs and odd subregs of Q registers.
168 /// For NumVecs <= 2, QOpcodes1 is not used.
169 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
170 unsigned *QOpcodes0, unsigned *QOpcodes1);
172 /// SelectVST - Select NEON store intrinsics. NumVecs should
173 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
174 /// stores of D registers and even subregs and odd subregs of Q registers.
175 /// For NumVecs <= 2, QOpcodes1 is not used.
176 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
177 unsigned *QOpcodes0, unsigned *QOpcodes1);
179 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
180 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
181 /// load/store of D registers and Q registers.
182 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
183 unsigned *DOpcodes, unsigned *QOpcodes);
185 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
186 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
187 /// generated to force the table registers to be consecutive.
188 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
190 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
191 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
193 /// SelectCMOVOp - Select CMOV instructions for ARM.
194 SDNode *SelectCMOVOp(SDNode *N);
195 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
196 ARMCC::CondCodes CCVal, SDValue CCR,
198 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
199 ARMCC::CondCodes CCVal, SDValue CCR,
201 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
202 ARMCC::CondCodes CCVal, SDValue CCR,
204 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
205 ARMCC::CondCodes CCVal, SDValue CCR,
208 SDNode *SelectConcatVector(SDNode *N);
210 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
211 /// inline asm expressions.
212 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
214 std::vector<SDValue> &OutOps);
216 // Form pairs of consecutive S, D, or Q registers.
217 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
218 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
219 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
221 // Form sequences of 4 consecutive S, D, or Q registers.
222 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
223 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
224 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
226 // Get the alignment operand for a NEON VLD or VST instruction.
227 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
231 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
232 /// operand. If so Imm will receive the 32-bit value.
233 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
234 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
235 Imm = cast<ConstantSDNode>(N)->getZExtValue();
241 // isInt32Immediate - This method tests to see if a constant operand.
242 // If so Imm will receive the 32 bit value.
243 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
244 return isInt32Immediate(N.getNode(), Imm);
247 // isOpcWithIntImmediate - This method tests to see if the node is a specific
248 // opcode and that it has a immediate integer right operand.
249 // If so Imm will receive the 32 bit value.
250 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
251 return N->getOpcode() == Opc &&
252 isInt32Immediate(N->getOperand(1).getNode(), Imm);
256 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
257 ARM_AM::ShiftOpc ShOpcVal,
259 if (!Subtarget->isCortexA9())
261 if (Shift.hasOneUse())
264 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
267 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
271 if (DisableShifterOp)
274 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
276 // Don't match base register only case. That is matched to a separate
277 // lower complexity pattern with explicit register operand.
278 if (ShOpcVal == ARM_AM::no_shift) return false;
280 BaseReg = N.getOperand(0);
281 unsigned ShImmVal = 0;
282 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
283 ShReg = CurDAG->getRegister(0, MVT::i32);
284 ShImmVal = RHS->getZExtValue() & 31;
286 ShReg = N.getOperand(1);
287 if (!isShifterOpProfitable(N, ShOpcVal, ShImmVal))
290 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
295 bool ARMDAGToDAGISel::SelectShiftShifterOperandReg(SDValue N,
299 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
301 // Don't match base register only case. That is matched to a separate
302 // lower complexity pattern with explicit register operand.
303 if (ShOpcVal == ARM_AM::no_shift) return false;
305 BaseReg = N.getOperand(0);
306 unsigned ShImmVal = 0;
307 // Do not check isShifterOpProfitable. This must return true.
308 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
309 ShReg = CurDAG->getRegister(0, MVT::i32);
310 ShImmVal = RHS->getZExtValue() & 31;
312 ShReg = N.getOperand(1);
314 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
319 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
322 // Match simple R + imm12 operands.
325 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
326 if (N.getOpcode() == ISD::FrameIndex) {
327 // Match frame index...
328 int FI = cast<FrameIndexSDNode>(N)->getIndex();
329 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
330 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
332 } else if (N.getOpcode() == ARMISD::Wrapper &&
333 !(Subtarget->useMovt() &&
334 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
335 Base = N.getOperand(0);
338 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
342 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
343 int RHSC = (int)RHS->getZExtValue();
344 if (N.getOpcode() == ISD::SUB)
347 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
348 Base = N.getOperand(0);
349 if (Base.getOpcode() == ISD::FrameIndex) {
350 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
351 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
353 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
360 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
366 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
368 if (N.getOpcode() == ISD::MUL &&
369 (!Subtarget->isCortexA9() || N.hasOneUse())) {
370 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
371 // X * [3,5,9] -> X + X * [2,4,8] etc.
372 int RHSC = (int)RHS->getZExtValue();
375 ARM_AM::AddrOpc AddSub = ARM_AM::add;
377 AddSub = ARM_AM::sub;
380 if (isPowerOf2_32(RHSC)) {
381 unsigned ShAmt = Log2_32(RHSC);
382 Base = Offset = N.getOperand(0);
383 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
392 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB)
395 // Leave simple R +/- imm12 operands for LDRi12
396 if (N.getOpcode() == ISD::ADD) {
397 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
398 int RHSC = (int)RHS->getZExtValue();
399 if ((RHSC >= 0 && RHSC < 0x1000) ||
400 (RHSC < 0 && RHSC > -0x1000)) // 12 bits.
405 if (Subtarget->isCortexA9() && !N.hasOneUse())
406 // Compute R +/- (R << N) and reuse it.
409 // Otherwise this is R +/- [possibly shifted] R.
410 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
411 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
414 Base = N.getOperand(0);
415 Offset = N.getOperand(1);
417 if (ShOpcVal != ARM_AM::no_shift) {
418 // Check to see if the RHS of the shift is a constant, if not, we can't fold
420 if (ConstantSDNode *Sh =
421 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
422 ShAmt = Sh->getZExtValue();
423 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
424 Offset = N.getOperand(1).getOperand(0);
427 ShOpcVal = ARM_AM::no_shift;
430 ShOpcVal = ARM_AM::no_shift;
434 // Try matching (R shl C) + (R).
435 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
436 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
437 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
438 if (ShOpcVal != ARM_AM::no_shift) {
439 // Check to see if the RHS of the shift is a constant, if not, we can't
441 if (ConstantSDNode *Sh =
442 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
443 ShAmt = Sh->getZExtValue();
444 if (!Subtarget->isCortexA9() ||
446 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
447 Offset = N.getOperand(0).getOperand(0);
448 Base = N.getOperand(1);
451 ShOpcVal = ARM_AM::no_shift;
454 ShOpcVal = ARM_AM::no_shift;
459 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
469 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
473 if (N.getOpcode() == ISD::MUL &&
474 (!Subtarget->isCortexA9() || N.hasOneUse())) {
475 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
476 // X * [3,5,9] -> X + X * [2,4,8] etc.
477 int RHSC = (int)RHS->getZExtValue();
480 ARM_AM::AddrOpc AddSub = ARM_AM::add;
482 AddSub = ARM_AM::sub;
485 if (isPowerOf2_32(RHSC)) {
486 unsigned ShAmt = Log2_32(RHSC);
487 Base = Offset = N.getOperand(0);
488 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
497 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
499 if (N.getOpcode() == ISD::FrameIndex) {
500 int FI = cast<FrameIndexSDNode>(N)->getIndex();
501 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
502 } else if (N.getOpcode() == ARMISD::Wrapper &&
503 !(Subtarget->useMovt() &&
504 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
505 Base = N.getOperand(0);
507 Offset = CurDAG->getRegister(0, MVT::i32);
508 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
514 // Match simple R +/- imm12 operands.
515 if (N.getOpcode() == ISD::ADD) {
516 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
517 int RHSC = (int)RHS->getZExtValue();
518 if ((RHSC >= 0 && RHSC < 0x1000) ||
519 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
520 Base = N.getOperand(0);
521 if (Base.getOpcode() == ISD::FrameIndex) {
522 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
523 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
525 Offset = CurDAG->getRegister(0, MVT::i32);
527 ARM_AM::AddrOpc AddSub = ARM_AM::add;
529 AddSub = ARM_AM::sub;
532 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
540 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
541 // Compute R +/- (R << N) and reuse it.
543 Offset = CurDAG->getRegister(0, MVT::i32);
544 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
550 // Otherwise this is R +/- [possibly shifted] R.
551 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
552 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
555 Base = N.getOperand(0);
556 Offset = N.getOperand(1);
558 if (ShOpcVal != ARM_AM::no_shift) {
559 // Check to see if the RHS of the shift is a constant, if not, we can't fold
561 if (ConstantSDNode *Sh =
562 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
563 ShAmt = Sh->getZExtValue();
564 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
565 Offset = N.getOperand(1).getOperand(0);
568 ShOpcVal = ARM_AM::no_shift;
571 ShOpcVal = ARM_AM::no_shift;
575 // Try matching (R shl C) + (R).
576 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
577 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
578 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
579 if (ShOpcVal != ARM_AM::no_shift) {
580 // Check to see if the RHS of the shift is a constant, if not, we can't
582 if (ConstantSDNode *Sh =
583 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
584 ShAmt = Sh->getZExtValue();
585 if (!Subtarget->isCortexA9() ||
587 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
588 Offset = N.getOperand(0).getOperand(0);
589 Base = N.getOperand(1);
592 ShOpcVal = ARM_AM::no_shift;
595 ShOpcVal = ARM_AM::no_shift;
600 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
605 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
606 SDValue &Offset, SDValue &Opc) {
607 unsigned Opcode = Op->getOpcode();
608 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
609 ? cast<LoadSDNode>(Op)->getAddressingMode()
610 : cast<StoreSDNode>(Op)->getAddressingMode();
611 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
612 ? ARM_AM::add : ARM_AM::sub;
613 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
614 int Val = (int)C->getZExtValue();
615 if (Val >= 0 && Val < 0x1000) { // 12 bits.
616 Offset = CurDAG->getRegister(0, MVT::i32);
617 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
625 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
627 if (ShOpcVal != ARM_AM::no_shift) {
628 // Check to see if the RHS of the shift is a constant, if not, we can't fold
630 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
631 ShAmt = Sh->getZExtValue();
632 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
633 Offset = N.getOperand(0);
636 ShOpcVal = ARM_AM::no_shift;
639 ShOpcVal = ARM_AM::no_shift;
643 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
649 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
650 SDValue &Base, SDValue &Offset,
652 if (N.getOpcode() == ISD::SUB) {
653 // X - C is canonicalize to X + -C, no need to handle it here.
654 Base = N.getOperand(0);
655 Offset = N.getOperand(1);
656 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
660 if (N.getOpcode() != ISD::ADD) {
662 if (N.getOpcode() == ISD::FrameIndex) {
663 int FI = cast<FrameIndexSDNode>(N)->getIndex();
664 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
666 Offset = CurDAG->getRegister(0, MVT::i32);
667 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
671 // If the RHS is +/- imm8, fold into addr mode.
672 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
673 int RHSC = (int)RHS->getZExtValue();
674 if ((RHSC >= 0 && RHSC < 256) ||
675 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
676 Base = N.getOperand(0);
677 if (Base.getOpcode() == ISD::FrameIndex) {
678 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
679 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
681 Offset = CurDAG->getRegister(0, MVT::i32);
683 ARM_AM::AddrOpc AddSub = ARM_AM::add;
685 AddSub = ARM_AM::sub;
688 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
693 Base = N.getOperand(0);
694 Offset = N.getOperand(1);
695 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
699 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
700 SDValue &Offset, SDValue &Opc) {
701 unsigned Opcode = Op->getOpcode();
702 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
703 ? cast<LoadSDNode>(Op)->getAddressingMode()
704 : cast<StoreSDNode>(Op)->getAddressingMode();
705 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
706 ? ARM_AM::add : ARM_AM::sub;
707 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
708 int Val = (int)C->getZExtValue();
709 if (Val >= 0 && Val < 256) {
710 Offset = CurDAG->getRegister(0, MVT::i32);
711 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
717 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
721 bool ARMDAGToDAGISel::SelectAddrMode4(SDValue N, SDValue &Addr, SDValue &Mode) {
723 Mode = CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32);
727 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
728 SDValue &Base, SDValue &Offset) {
729 if (N.getOpcode() != ISD::ADD) {
731 if (N.getOpcode() == ISD::FrameIndex) {
732 int FI = cast<FrameIndexSDNode>(N)->getIndex();
733 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
734 } else if (N.getOpcode() == ARMISD::Wrapper &&
735 !(Subtarget->useMovt() &&
736 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
737 Base = N.getOperand(0);
739 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
744 // If the RHS is +/- imm8, fold into addr mode.
745 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
746 int RHSC = (int)RHS->getZExtValue();
747 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
749 if ((RHSC >= 0 && RHSC < 256) ||
750 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
751 Base = N.getOperand(0);
752 if (Base.getOpcode() == ISD::FrameIndex) {
753 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
754 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
757 ARM_AM::AddrOpc AddSub = ARM_AM::add;
759 AddSub = ARM_AM::sub;
762 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
770 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
775 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
779 unsigned Alignment = 0;
780 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
781 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
782 // The maximum alignment is equal to the memory size being referenced.
783 unsigned LSNAlign = LSN->getAlignment();
784 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
785 if (LSNAlign > MemSize && MemSize > 1)
788 // All other uses of addrmode6 are for intrinsics. For now just record
789 // the raw alignment value; it will be refined later based on the legal
790 // alignment operands for the intrinsic.
791 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
794 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
798 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
799 SDValue &Offset, SDValue &Label) {
800 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
801 Offset = N.getOperand(0);
802 SDValue N1 = N.getOperand(1);
803 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
810 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
811 SDValue &Base, SDValue &Offset){
812 // FIXME dl should come from the parent load or store, not the address
813 if (N.getOpcode() != ISD::ADD) {
814 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
815 if (!NC || !NC->isNullValue())
822 Base = N.getOperand(0);
823 Offset = N.getOperand(1);
828 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
829 unsigned Scale, SDValue &Base,
830 SDValue &OffImm, SDValue &Offset) {
832 SDValue TmpBase, TmpOffImm;
833 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
834 return false; // We want to select tLDRspi / tSTRspi instead.
835 if (N.getOpcode() == ARMISD::Wrapper &&
836 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
837 return false; // We want to select tLDRpci instead.
840 if (N.getOpcode() != ISD::ADD) {
841 if (N.getOpcode() == ARMISD::Wrapper &&
842 !(Subtarget->useMovt() &&
843 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
844 Base = N.getOperand(0);
848 Offset = CurDAG->getRegister(0, MVT::i32);
849 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
853 // Thumb does not have [sp, r] address mode.
854 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
855 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
856 if ((LHSR && LHSR->getReg() == ARM::SP) ||
857 (RHSR && RHSR->getReg() == ARM::SP)) {
859 Offset = CurDAG->getRegister(0, MVT::i32);
860 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
864 // If the RHS is + imm5 * scale, fold into addr mode.
865 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
866 int RHSC = (int)RHS->getZExtValue();
867 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
869 if (RHSC >= 0 && RHSC < 32) {
870 Base = N.getOperand(0);
871 Offset = CurDAG->getRegister(0, MVT::i32);
872 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
878 Base = N.getOperand(0);
879 Offset = N.getOperand(1);
880 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
884 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
885 SDValue &Base, SDValue &OffImm,
887 return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
890 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
891 SDValue &Base, SDValue &OffImm,
893 return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
896 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
897 SDValue &Base, SDValue &OffImm,
899 return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
902 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
903 SDValue &Base, SDValue &OffImm) {
904 if (N.getOpcode() == ISD::FrameIndex) {
905 int FI = cast<FrameIndexSDNode>(N)->getIndex();
906 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
907 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
911 if (N.getOpcode() != ISD::ADD)
914 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
915 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
916 (LHSR && LHSR->getReg() == ARM::SP)) {
917 // If the RHS is + imm8 * scale, fold into addr mode.
918 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
919 int RHSC = (int)RHS->getZExtValue();
920 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
922 if (RHSC >= 0 && RHSC < 256) {
923 Base = N.getOperand(0);
924 if (Base.getOpcode() == ISD::FrameIndex) {
925 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
926 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
928 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
938 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
940 if (DisableShifterOp)
943 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
945 // Don't match base register only case. That is matched to a separate
946 // lower complexity pattern with explicit register operand.
947 if (ShOpcVal == ARM_AM::no_shift) return false;
949 BaseReg = N.getOperand(0);
950 unsigned ShImmVal = 0;
951 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
952 ShImmVal = RHS->getZExtValue() & 31;
953 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
960 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
961 SDValue &Base, SDValue &OffImm) {
962 // Match simple R + imm12 operands.
965 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
966 if (N.getOpcode() == ISD::FrameIndex) {
967 // Match frame index...
968 int FI = cast<FrameIndexSDNode>(N)->getIndex();
969 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
970 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
972 } else if (N.getOpcode() == ARMISD::Wrapper &&
973 !(Subtarget->useMovt() &&
974 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
975 Base = N.getOperand(0);
976 if (Base.getOpcode() == ISD::TargetConstantPool)
977 return false; // We want to select t2LDRpci instead.
980 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
984 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
985 if (SelectT2AddrModeImm8(N, Base, OffImm))
986 // Let t2LDRi8 handle (R - imm8).
989 int RHSC = (int)RHS->getZExtValue();
990 if (N.getOpcode() == ISD::SUB)
993 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
994 Base = N.getOperand(0);
995 if (Base.getOpcode() == ISD::FrameIndex) {
996 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
997 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
999 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1006 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1010 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1011 SDValue &Base, SDValue &OffImm) {
1012 // Match simple R - imm8 operands.
1013 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
1014 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1015 int RHSC = (int)RHS->getSExtValue();
1016 if (N.getOpcode() == ISD::SUB)
1019 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1020 Base = N.getOperand(0);
1021 if (Base.getOpcode() == ISD::FrameIndex) {
1022 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1023 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1025 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1034 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1036 unsigned Opcode = Op->getOpcode();
1037 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1038 ? cast<LoadSDNode>(Op)->getAddressingMode()
1039 : cast<StoreSDNode>(Op)->getAddressingMode();
1040 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
1041 int RHSC = (int)RHS->getZExtValue();
1042 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
1043 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1044 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1045 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1053 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1055 SDValue &OffReg, SDValue &ShImm) {
1056 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1057 if (N.getOpcode() != ISD::ADD)
1060 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1061 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1062 int RHSC = (int)RHS->getZExtValue();
1063 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1065 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1069 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1070 // Compute R + (R << [1,2,3]) and reuse it.
1075 // Look for (R + R) or (R + (R << [1,2,3])).
1077 Base = N.getOperand(0);
1078 OffReg = N.getOperand(1);
1080 // Swap if it is ((R << c) + R).
1081 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
1082 if (ShOpcVal != ARM_AM::lsl) {
1083 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
1084 if (ShOpcVal == ARM_AM::lsl)
1085 std::swap(Base, OffReg);
1088 if (ShOpcVal == ARM_AM::lsl) {
1089 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1091 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1092 ShAmt = Sh->getZExtValue();
1093 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1094 OffReg = OffReg.getOperand(0);
1097 ShOpcVal = ARM_AM::no_shift;
1100 ShOpcVal = ARM_AM::no_shift;
1104 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1109 //===--------------------------------------------------------------------===//
1111 /// getAL - Returns a ARMCC::AL immediate node.
1112 static inline SDValue getAL(SelectionDAG *CurDAG) {
1113 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1116 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1117 LoadSDNode *LD = cast<LoadSDNode>(N);
1118 ISD::MemIndexedMode AM = LD->getAddressingMode();
1119 if (AM == ISD::UNINDEXED)
1122 EVT LoadedVT = LD->getMemoryVT();
1123 SDValue Offset, AMOpc;
1124 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1125 unsigned Opcode = 0;
1127 if (LoadedVT == MVT::i32 &&
1128 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1129 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
1131 } else if (LoadedVT == MVT::i16 &&
1132 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1134 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1135 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1136 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1137 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1138 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1139 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1141 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1144 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1146 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
1152 SDValue Chain = LD->getChain();
1153 SDValue Base = LD->getBasePtr();
1154 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1155 CurDAG->getRegister(0, MVT::i32), Chain };
1156 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1157 MVT::Other, Ops, 6);
1163 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1164 LoadSDNode *LD = cast<LoadSDNode>(N);
1165 ISD::MemIndexedMode AM = LD->getAddressingMode();
1166 if (AM == ISD::UNINDEXED)
1169 EVT LoadedVT = LD->getMemoryVT();
1170 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1172 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1173 unsigned Opcode = 0;
1175 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1176 switch (LoadedVT.getSimpleVT().SimpleTy) {
1178 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1182 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1184 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1189 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1191 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1200 SDValue Chain = LD->getChain();
1201 SDValue Base = LD->getBasePtr();
1202 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1203 CurDAG->getRegister(0, MVT::i32), Chain };
1204 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1205 MVT::Other, Ops, 5);
1211 /// PairSRegs - Form a D register from a pair of S registers.
1213 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1214 DebugLoc dl = V0.getNode()->getDebugLoc();
1215 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1216 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1217 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1218 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1221 /// PairDRegs - Form a quad register from a pair of D registers.
1223 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1224 DebugLoc dl = V0.getNode()->getDebugLoc();
1225 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1226 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1227 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1228 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1231 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1233 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1234 DebugLoc dl = V0.getNode()->getDebugLoc();
1235 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1236 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1237 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1238 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1241 /// QuadSRegs - Form 4 consecutive S registers.
1243 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1244 SDValue V2, SDValue V3) {
1245 DebugLoc dl = V0.getNode()->getDebugLoc();
1246 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1247 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1248 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1249 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1250 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1251 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1254 /// QuadDRegs - Form 4 consecutive D registers.
1256 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1257 SDValue V2, SDValue V3) {
1258 DebugLoc dl = V0.getNode()->getDebugLoc();
1259 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1260 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1261 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1262 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1263 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1264 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1267 /// QuadQRegs - Form 4 consecutive Q registers.
1269 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1270 SDValue V2, SDValue V3) {
1271 DebugLoc dl = V0.getNode()->getDebugLoc();
1272 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1273 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1274 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1275 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1276 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1277 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1280 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1281 /// of a NEON VLD or VST instruction. The supported values depend on the
1282 /// number of registers being loaded.
1283 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1284 bool is64BitVector) {
1285 unsigned NumRegs = NumVecs;
1286 if (!is64BitVector && NumVecs < 3)
1289 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1290 if (Alignment >= 32 && NumRegs == 4)
1292 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1294 else if (Alignment >= 8)
1299 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1302 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
1303 unsigned *DOpcodes, unsigned *QOpcodes0,
1304 unsigned *QOpcodes1) {
1305 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1306 DebugLoc dl = N->getDebugLoc();
1308 SDValue MemAddr, Align;
1309 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1312 SDValue Chain = N->getOperand(0);
1313 EVT VT = N->getValueType(0);
1314 bool is64BitVector = VT.is64BitVector();
1315 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1317 unsigned OpcodeIndex;
1318 switch (VT.getSimpleVT().SimpleTy) {
1319 default: llvm_unreachable("unhandled vld type");
1320 // Double-register operations:
1321 case MVT::v8i8: OpcodeIndex = 0; break;
1322 case MVT::v4i16: OpcodeIndex = 1; break;
1324 case MVT::v2i32: OpcodeIndex = 2; break;
1325 case MVT::v1i64: OpcodeIndex = 3; break;
1326 // Quad-register operations:
1327 case MVT::v16i8: OpcodeIndex = 0; break;
1328 case MVT::v8i16: OpcodeIndex = 1; break;
1330 case MVT::v4i32: OpcodeIndex = 2; break;
1331 case MVT::v2i64: OpcodeIndex = 3;
1332 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1340 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1343 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1346 SDValue Pred = getAL(CurDAG);
1347 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1349 if (is64BitVector) {
1350 unsigned Opc = DOpcodes[OpcodeIndex];
1351 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1352 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1356 SuperReg = SDValue(VLd, 0);
1357 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1358 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1359 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
1361 ReplaceUses(SDValue(N, Vec), D);
1363 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1368 // Quad registers are directly supported for VLD1 and VLD2,
1369 // loading pairs of D regs.
1370 unsigned Opc = QOpcodes0[OpcodeIndex];
1371 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1372 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1376 SuperReg = SDValue(VLd, 0);
1377 Chain = SDValue(VLd, 1);
1380 // Otherwise, quad registers are loaded with two separate instructions,
1381 // where one loads the even registers and the other loads the odd registers.
1382 EVT AddrTy = MemAddr.getValueType();
1384 // Load the even subregs.
1385 unsigned Opc = QOpcodes0[OpcodeIndex];
1387 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1388 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1390 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsA, 7);
1391 Chain = SDValue(VLdA, 2);
1393 // Load the odd subregs.
1394 Opc = QOpcodes1[OpcodeIndex];
1395 const SDValue OpsB[] = { SDValue(VLdA, 1), Align, Reg0, SDValue(VLdA, 0),
1396 Pred, Reg0, Chain };
1398 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsB, 7);
1399 SuperReg = SDValue(VLdB, 0);
1400 Chain = SDValue(VLdB, 2);
1403 // Extract out the Q registers.
1404 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1405 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1406 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
1408 ReplaceUses(SDValue(N, Vec), Q);
1410 ReplaceUses(SDValue(N, NumVecs), Chain);
1414 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1415 unsigned *DOpcodes, unsigned *QOpcodes0,
1416 unsigned *QOpcodes1) {
1417 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1418 DebugLoc dl = N->getDebugLoc();
1420 SDValue MemAddr, Align;
1421 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1424 SDValue Chain = N->getOperand(0);
1425 EVT VT = N->getOperand(3).getValueType();
1426 bool is64BitVector = VT.is64BitVector();
1427 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1429 unsigned OpcodeIndex;
1430 switch (VT.getSimpleVT().SimpleTy) {
1431 default: llvm_unreachable("unhandled vst type");
1432 // Double-register operations:
1433 case MVT::v8i8: OpcodeIndex = 0; break;
1434 case MVT::v4i16: OpcodeIndex = 1; break;
1436 case MVT::v2i32: OpcodeIndex = 2; break;
1437 case MVT::v1i64: OpcodeIndex = 3; break;
1438 // Quad-register operations:
1439 case MVT::v16i8: OpcodeIndex = 0; break;
1440 case MVT::v8i16: OpcodeIndex = 1; break;
1442 case MVT::v4i32: OpcodeIndex = 2; break;
1443 case MVT::v2i64: OpcodeIndex = 3;
1444 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1448 SDValue Pred = getAL(CurDAG);
1449 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1451 SmallVector<SDValue, 7> Ops;
1452 Ops.push_back(MemAddr);
1453 Ops.push_back(Align);
1455 if (is64BitVector) {
1457 Ops.push_back(N->getOperand(3));
1460 SDValue V0 = N->getOperand(0+3);
1461 SDValue V1 = N->getOperand(1+3);
1463 // Form a REG_SEQUENCE to force register allocation.
1465 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1467 SDValue V2 = N->getOperand(2+3);
1468 // If it's a vld3, form a quad D-register and leave the last part as
1470 SDValue V3 = (NumVecs == 3)
1471 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1472 : N->getOperand(3+3);
1473 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1475 Ops.push_back(RegSeq);
1477 Ops.push_back(Pred);
1478 Ops.push_back(Reg0); // predicate register
1479 Ops.push_back(Chain);
1480 unsigned Opc = DOpcodes[OpcodeIndex];
1481 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1485 // Quad registers are directly supported for VST1 and VST2.
1486 unsigned Opc = QOpcodes0[OpcodeIndex];
1488 Ops.push_back(N->getOperand(3));
1490 // Form a QQ register.
1491 SDValue Q0 = N->getOperand(3);
1492 SDValue Q1 = N->getOperand(4);
1493 Ops.push_back(SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0));
1495 Ops.push_back(Pred);
1496 Ops.push_back(Reg0); // predicate register
1497 Ops.push_back(Chain);
1498 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1501 // Otherwise, quad registers are stored with two separate instructions,
1502 // where one stores the even registers and the other stores the odd registers.
1504 // Form the QQQQ REG_SEQUENCE.
1505 SDValue V0 = N->getOperand(0+3);
1506 SDValue V1 = N->getOperand(1+3);
1507 SDValue V2 = N->getOperand(2+3);
1508 SDValue V3 = (NumVecs == 3)
1509 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1510 : N->getOperand(3+3);
1511 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1513 // Store the even D registers.
1514 Ops.push_back(Reg0); // post-access address offset
1515 Ops.push_back(RegSeq);
1516 Ops.push_back(Pred);
1517 Ops.push_back(Reg0); // predicate register
1518 Ops.push_back(Chain);
1519 unsigned Opc = QOpcodes0[OpcodeIndex];
1520 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1521 MVT::Other, Ops.data(), 7);
1522 Chain = SDValue(VStA, 1);
1524 // Store the odd D registers.
1525 Ops[0] = SDValue(VStA, 0); // MemAddr
1527 Opc = QOpcodes1[OpcodeIndex];
1528 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1529 MVT::Other, Ops.data(), 7);
1530 Chain = SDValue(VStB, 1);
1531 ReplaceUses(SDValue(N, 0), Chain);
1535 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1536 unsigned NumVecs, unsigned *DOpcodes,
1537 unsigned *QOpcodes) {
1538 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1539 DebugLoc dl = N->getDebugLoc();
1541 SDValue MemAddr, Align;
1542 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1545 SDValue Chain = N->getOperand(0);
1547 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1548 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1549 bool is64BitVector = VT.is64BitVector();
1551 unsigned Alignment = 0;
1553 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1554 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1555 if (Alignment > NumBytes)
1556 Alignment = NumBytes;
1557 // Alignment must be a power of two; make sure of that.
1558 Alignment = (Alignment & -Alignment);
1562 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1564 unsigned OpcodeIndex;
1565 switch (VT.getSimpleVT().SimpleTy) {
1566 default: llvm_unreachable("unhandled vld/vst lane type");
1567 // Double-register operations:
1568 case MVT::v8i8: OpcodeIndex = 0; break;
1569 case MVT::v4i16: OpcodeIndex = 1; break;
1571 case MVT::v2i32: OpcodeIndex = 2; break;
1572 // Quad-register operations:
1573 case MVT::v8i16: OpcodeIndex = 0; break;
1575 case MVT::v4i32: OpcodeIndex = 1; break;
1578 SDValue Pred = getAL(CurDAG);
1579 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1581 SmallVector<SDValue, 7> Ops;
1582 Ops.push_back(MemAddr);
1583 Ops.push_back(Align);
1585 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1586 QOpcodes[OpcodeIndex]);
1589 SDValue V0 = N->getOperand(0+3);
1590 SDValue V1 = N->getOperand(1+3);
1593 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1595 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1597 SDValue V2 = N->getOperand(2+3);
1598 SDValue V3 = (NumVecs == 3)
1599 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1600 : N->getOperand(3+3);
1602 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1604 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1606 Ops.push_back(SuperReg);
1607 Ops.push_back(getI32Imm(Lane));
1608 Ops.push_back(Pred);
1609 Ops.push_back(Reg0);
1610 Ops.push_back(Chain);
1613 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 7);
1616 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1619 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1621 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other,
1623 SuperReg = SDValue(VLdLn, 0);
1624 Chain = SDValue(VLdLn, 1);
1626 // Extract the subregisters.
1627 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1628 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1629 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1630 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1631 ReplaceUses(SDValue(N, Vec),
1632 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1633 ReplaceUses(SDValue(N, NumVecs), Chain);
1637 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1639 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1640 DebugLoc dl = N->getDebugLoc();
1641 EVT VT = N->getValueType(0);
1642 unsigned FirstTblReg = IsExt ? 2 : 1;
1644 // Form a REG_SEQUENCE to force register allocation.
1646 SDValue V0 = N->getOperand(FirstTblReg + 0);
1647 SDValue V1 = N->getOperand(FirstTblReg + 1);
1649 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1651 SDValue V2 = N->getOperand(FirstTblReg + 2);
1652 // If it's a vtbl3, form a quad D-register and leave the last part as
1654 SDValue V3 = (NumVecs == 3)
1655 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1656 : N->getOperand(FirstTblReg + 3);
1657 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1660 SmallVector<SDValue, 6> Ops;
1662 Ops.push_back(N->getOperand(1));
1663 Ops.push_back(RegSeq);
1664 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1665 Ops.push_back(getAL(CurDAG)); // predicate
1666 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1667 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1670 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1672 if (!Subtarget->hasV6T2Ops())
1675 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1676 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1679 // For unsigned extracts, check for a shift right and mask
1680 unsigned And_imm = 0;
1681 if (N->getOpcode() == ISD::AND) {
1682 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1684 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1685 if (And_imm & (And_imm + 1))
1688 unsigned Srl_imm = 0;
1689 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1691 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1693 unsigned Width = CountTrailingOnes_32(And_imm);
1694 unsigned LSB = Srl_imm;
1695 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1696 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1697 CurDAG->getTargetConstant(LSB, MVT::i32),
1698 CurDAG->getTargetConstant(Width, MVT::i32),
1699 getAL(CurDAG), Reg0 };
1700 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1706 // Otherwise, we're looking for a shift of a shift
1707 unsigned Shl_imm = 0;
1708 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1709 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1710 unsigned Srl_imm = 0;
1711 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1712 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1713 unsigned Width = 32 - Srl_imm;
1714 int LSB = Srl_imm - Shl_imm;
1717 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1718 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1719 CurDAG->getTargetConstant(LSB, MVT::i32),
1720 CurDAG->getTargetConstant(Width, MVT::i32),
1721 getAL(CurDAG), Reg0 };
1722 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1728 SDNode *ARMDAGToDAGISel::
1729 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1730 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1733 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
1734 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1735 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1738 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1739 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1740 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1741 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1743 llvm_unreachable("Unknown so_reg opcode!");
1747 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1748 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1749 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1750 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1755 SDNode *ARMDAGToDAGISel::
1756 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1757 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1761 if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1762 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1763 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1764 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1769 SDNode *ARMDAGToDAGISel::
1770 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1771 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1772 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1776 unsigned TrueImm = T->getZExtValue();
1777 bool isSoImm = Pred_t2_so_imm(TrueVal.getNode());
1778 if (isSoImm || TrueImm <= 0xffff) {
1779 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1780 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1781 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1782 return CurDAG->SelectNodeTo(N, (isSoImm ? ARM::t2MOVCCi : ARM::t2MOVCCi16),
1788 SDNode *ARMDAGToDAGISel::
1789 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1790 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1791 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1795 unsigned TrueImm = T->getZExtValue();
1796 bool isSoImm = Pred_so_imm(TrueVal.getNode());
1797 if (isSoImm || (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff)) {
1798 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
1799 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1800 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1801 return CurDAG->SelectNodeTo(N, (isSoImm ? ARM::MOVCCi : ARM::MOVCCi16),
1807 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1808 EVT VT = N->getValueType(0);
1809 SDValue FalseVal = N->getOperand(0);
1810 SDValue TrueVal = N->getOperand(1);
1811 SDValue CC = N->getOperand(2);
1812 SDValue CCR = N->getOperand(3);
1813 SDValue InFlag = N->getOperand(4);
1814 assert(CC.getOpcode() == ISD::Constant);
1815 assert(CCR.getOpcode() == ISD::Register);
1816 ARMCC::CondCodes CCVal =
1817 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1819 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1820 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1821 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1822 // Pattern complexity = 18 cost = 1 size = 0
1826 if (Subtarget->isThumb()) {
1827 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1828 CCVal, CCR, InFlag);
1830 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1831 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1835 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1836 CCVal, CCR, InFlag);
1838 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1839 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1844 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1845 // (imm:i32)<<P:Pred_so_imm>>:$true,
1847 // Emits: (MOVCCi:i32 GPR:i32:$false,
1848 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1849 // Pattern complexity = 10 cost = 1 size = 0
1850 if (Subtarget->isThumb()) {
1851 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
1852 CCVal, CCR, InFlag);
1854 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
1855 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1859 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
1860 CCVal, CCR, InFlag);
1862 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
1863 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1869 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1870 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1871 // Pattern complexity = 6 cost = 1 size = 0
1873 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1874 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1875 // Pattern complexity = 6 cost = 11 size = 0
1877 // Also FCPYScc and FCPYDcc.
1878 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1879 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1881 switch (VT.getSimpleVT().SimpleTy) {
1882 default: assert(false && "Illegal conditional move type!");
1885 Opc = Subtarget->isThumb()
1886 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1896 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1899 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
1900 // The only time a CONCAT_VECTORS operation can have legal types is when
1901 // two 64-bit vectors are concatenated to a 128-bit vector.
1902 EVT VT = N->getValueType(0);
1903 if (!VT.is128BitVector() || N->getNumOperands() != 2)
1904 llvm_unreachable("unexpected CONCAT_VECTORS");
1905 DebugLoc dl = N->getDebugLoc();
1906 SDValue V0 = N->getOperand(0);
1907 SDValue V1 = N->getOperand(1);
1908 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1909 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1910 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1911 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1914 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
1915 DebugLoc dl = N->getDebugLoc();
1917 if (N->isMachineOpcode())
1918 return NULL; // Already selected.
1920 switch (N->getOpcode()) {
1922 case ISD::Constant: {
1923 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1925 if (Subtarget->hasThumb2())
1926 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1927 // be done with MOV + MOVT, at worst.
1930 if (Subtarget->isThumb()) {
1931 UseCP = (Val > 255 && // MOV
1932 ~Val > 255 && // MOV + MVN
1933 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1935 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1936 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1937 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1942 CurDAG->getTargetConstantPool(ConstantInt::get(
1943 Type::getInt32Ty(*CurDAG->getContext()), Val),
1944 TLI.getPointerTy());
1947 if (Subtarget->isThumb1Only()) {
1948 SDValue Pred = getAL(CurDAG);
1949 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1950 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1951 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1956 CurDAG->getTargetConstant(0, MVT::i32),
1958 CurDAG->getRegister(0, MVT::i32),
1959 CurDAG->getEntryNode()
1961 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1964 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
1968 // Other cases are autogenerated.
1971 case ISD::FrameIndex: {
1972 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1973 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1974 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1975 if (Subtarget->isThumb1Only()) {
1976 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1977 CurDAG->getTargetConstant(0, MVT::i32));
1979 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1980 ARM::t2ADDri : ARM::ADDri);
1981 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1982 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1983 CurDAG->getRegister(0, MVT::i32) };
1984 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1988 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
1992 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
1996 if (Subtarget->isThumb1Only())
1998 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1999 unsigned RHSV = C->getZExtValue();
2001 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2002 unsigned ShImm = Log2_32(RHSV-1);
2005 SDValue V = N->getOperand(0);
2006 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2007 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2008 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2009 if (Subtarget->isThumb()) {
2010 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2011 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2013 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2014 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
2017 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2018 unsigned ShImm = Log2_32(RHSV+1);
2021 SDValue V = N->getOperand(0);
2022 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2023 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2024 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2025 if (Subtarget->isThumb()) {
2026 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2027 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2029 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2030 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
2036 // Check for unsigned bitfield extract
2037 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2040 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2041 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2042 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2043 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2044 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2045 EVT VT = N->getValueType(0);
2048 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2050 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2053 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2054 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2057 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2058 SDValue N2 = N0.getOperand(1);
2059 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2062 unsigned N1CVal = N1C->getZExtValue();
2063 unsigned N2CVal = N2C->getZExtValue();
2064 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2065 (N1CVal & 0xffffU) == 0xffffU &&
2066 (N2CVal & 0xffffU) == 0x0U) {
2067 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2069 SDValue Ops[] = { N0.getOperand(0), Imm16,
2070 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2071 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2076 case ARMISD::VMOVRRD:
2077 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2078 N->getOperand(0), getAL(CurDAG),
2079 CurDAG->getRegister(0, MVT::i32));
2080 case ISD::UMUL_LOHI: {
2081 if (Subtarget->isThumb1Only())
2083 if (Subtarget->isThumb()) {
2084 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2085 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2086 CurDAG->getRegister(0, MVT::i32) };
2087 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2089 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2090 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2091 CurDAG->getRegister(0, MVT::i32) };
2092 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2095 case ISD::SMUL_LOHI: {
2096 if (Subtarget->isThumb1Only())
2098 if (Subtarget->isThumb()) {
2099 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2100 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2101 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2103 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2104 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2105 CurDAG->getRegister(0, MVT::i32) };
2106 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2110 SDNode *ResNode = 0;
2111 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2112 ResNode = SelectT2IndexedLoad(N);
2114 ResNode = SelectARMIndexedLoad(N);
2117 // Other cases are autogenerated.
2120 case ARMISD::BRCOND: {
2121 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2122 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2123 // Pattern complexity = 6 cost = 1 size = 0
2125 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2126 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2127 // Pattern complexity = 6 cost = 1 size = 0
2129 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2130 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2131 // Pattern complexity = 6 cost = 1 size = 0
2133 unsigned Opc = Subtarget->isThumb() ?
2134 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2135 SDValue Chain = N->getOperand(0);
2136 SDValue N1 = N->getOperand(1);
2137 SDValue N2 = N->getOperand(2);
2138 SDValue N3 = N->getOperand(3);
2139 SDValue InFlag = N->getOperand(4);
2140 assert(N1.getOpcode() == ISD::BasicBlock);
2141 assert(N2.getOpcode() == ISD::Constant);
2142 assert(N3.getOpcode() == ISD::Register);
2144 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2145 cast<ConstantSDNode>(N2)->getZExtValue()),
2147 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2148 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2150 Chain = SDValue(ResNode, 0);
2151 if (N->getNumValues() == 2) {
2152 InFlag = SDValue(ResNode, 1);
2153 ReplaceUses(SDValue(N, 1), InFlag);
2155 ReplaceUses(SDValue(N, 0),
2156 SDValue(Chain.getNode(), Chain.getResNo()));
2160 return SelectCMOVOp(N);
2161 case ARMISD::CNEG: {
2162 EVT VT = N->getValueType(0);
2163 SDValue N0 = N->getOperand(0);
2164 SDValue N1 = N->getOperand(1);
2165 SDValue N2 = N->getOperand(2);
2166 SDValue N3 = N->getOperand(3);
2167 SDValue InFlag = N->getOperand(4);
2168 assert(N2.getOpcode() == ISD::Constant);
2169 assert(N3.getOpcode() == ISD::Register);
2171 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2172 cast<ConstantSDNode>(N2)->getZExtValue()),
2174 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
2176 switch (VT.getSimpleVT().SimpleTy) {
2177 default: assert(false && "Illegal conditional move type!");
2186 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2189 case ARMISD::VZIP: {
2191 EVT VT = N->getValueType(0);
2192 switch (VT.getSimpleVT().SimpleTy) {
2193 default: return NULL;
2194 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2195 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2197 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2198 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2199 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2201 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2203 SDValue Pred = getAL(CurDAG);
2204 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2205 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2206 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2208 case ARMISD::VUZP: {
2210 EVT VT = N->getValueType(0);
2211 switch (VT.getSimpleVT().SimpleTy) {
2212 default: return NULL;
2213 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2214 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2216 case MVT::v2i32: Opc = ARM::VUZPd32; break;
2217 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2218 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2220 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2222 SDValue Pred = getAL(CurDAG);
2223 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2224 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2225 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2227 case ARMISD::VTRN: {
2229 EVT VT = N->getValueType(0);
2230 switch (VT.getSimpleVT().SimpleTy) {
2231 default: return NULL;
2232 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2233 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2235 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2236 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2237 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2239 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2241 SDValue Pred = getAL(CurDAG);
2242 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2243 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2244 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2246 case ARMISD::BUILD_VECTOR: {
2247 EVT VecVT = N->getValueType(0);
2248 EVT EltVT = VecVT.getVectorElementType();
2249 unsigned NumElts = VecVT.getVectorNumElements();
2250 if (EltVT.getSimpleVT() == MVT::f64) {
2251 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2252 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2254 assert(EltVT.getSimpleVT() == MVT::f32 &&
2255 "unexpected type for BUILD_VECTOR");
2257 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2258 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2259 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2260 N->getOperand(2), N->getOperand(3));
2263 case ISD::INTRINSIC_VOID:
2264 case ISD::INTRINSIC_W_CHAIN: {
2265 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2270 case Intrinsic::arm_neon_vld1: {
2271 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2272 ARM::VLD1d32, ARM::VLD1d64 };
2273 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2274 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2275 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0);
2278 case Intrinsic::arm_neon_vld2: {
2279 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2280 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2281 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2282 ARM::VLD2q32Pseudo };
2283 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
2286 case Intrinsic::arm_neon_vld3: {
2287 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2288 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2289 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2290 ARM::VLD3q16Pseudo_UPD,
2291 ARM::VLD3q32Pseudo_UPD };
2292 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2293 ARM::VLD3q16oddPseudo_UPD,
2294 ARM::VLD3q32oddPseudo_UPD };
2295 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2298 case Intrinsic::arm_neon_vld4: {
2299 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2300 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2301 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2302 ARM::VLD4q16Pseudo_UPD,
2303 ARM::VLD4q32Pseudo_UPD };
2304 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2305 ARM::VLD4q16oddPseudo_UPD,
2306 ARM::VLD4q32oddPseudo_UPD };
2307 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2310 case Intrinsic::arm_neon_vld2lane: {
2311 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2312 ARM::VLD2LNd32Pseudo };
2313 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2314 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes);
2317 case Intrinsic::arm_neon_vld3lane: {
2318 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2319 ARM::VLD3LNd32Pseudo };
2320 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2321 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes);
2324 case Intrinsic::arm_neon_vld4lane: {
2325 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2326 ARM::VLD4LNd32Pseudo };
2327 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2328 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes);
2331 case Intrinsic::arm_neon_vst1: {
2332 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2333 ARM::VST1d32, ARM::VST1d64 };
2334 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2335 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2336 return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
2339 case Intrinsic::arm_neon_vst2: {
2340 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
2341 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
2342 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
2343 ARM::VST2q32Pseudo };
2344 return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
2347 case Intrinsic::arm_neon_vst3: {
2348 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
2349 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
2350 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2351 ARM::VST3q16Pseudo_UPD,
2352 ARM::VST3q32Pseudo_UPD };
2353 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2354 ARM::VST3q16oddPseudo_UPD,
2355 ARM::VST3q32oddPseudo_UPD };
2356 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2359 case Intrinsic::arm_neon_vst4: {
2360 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
2361 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
2362 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2363 ARM::VST4q16Pseudo_UPD,
2364 ARM::VST4q32Pseudo_UPD };
2365 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2366 ARM::VST4q16oddPseudo_UPD,
2367 ARM::VST4q32oddPseudo_UPD };
2368 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2371 case Intrinsic::arm_neon_vst2lane: {
2372 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
2373 ARM::VST2LNd32Pseudo };
2374 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
2375 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes);
2378 case Intrinsic::arm_neon_vst3lane: {
2379 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
2380 ARM::VST3LNd32Pseudo };
2381 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
2382 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes);
2385 case Intrinsic::arm_neon_vst4lane: {
2386 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
2387 ARM::VST4LNd32Pseudo };
2388 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
2389 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes);
2395 case ISD::INTRINSIC_WO_CHAIN: {
2396 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2401 case Intrinsic::arm_neon_vtbl2:
2402 return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
2403 case Intrinsic::arm_neon_vtbl3:
2404 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
2405 case Intrinsic::arm_neon_vtbl4:
2406 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
2408 case Intrinsic::arm_neon_vtbx2:
2409 return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
2410 case Intrinsic::arm_neon_vtbx3:
2411 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
2412 case Intrinsic::arm_neon_vtbx4:
2413 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
2418 case ISD::CONCAT_VECTORS:
2419 return SelectConcatVector(N);
2422 return SelectCode(N);
2425 bool ARMDAGToDAGISel::
2426 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2427 std::vector<SDValue> &OutOps) {
2428 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2429 // Require the address to be in a register. That is safe for all ARM
2430 // variants and it is hard to do anything much smarter without knowing
2431 // how the operand is used.
2432 OutOps.push_back(Op);
2436 /// createARMISelDag - This pass converts a legalized DAG into a
2437 /// ARM-specific DAG, ready for instruction scheduling.
2439 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2440 CodeGenOpt::Level OptLevel) {
2441 return new ARMDAGToDAGISel(TM, OptLevel);