1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
39 static const unsigned arm_dsubreg_0 = 5;
40 static const unsigned arm_dsubreg_1 = 6;
42 //===--------------------------------------------------------------------===//
43 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
44 /// instructions for SelectionDAG operations.
47 class ARMDAGToDAGISel : public SelectionDAGISel {
48 ARMBaseTargetMachine &TM;
50 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
51 /// make the right decision when generating code for different targets.
52 const ARMSubtarget *Subtarget;
55 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm)
56 : SelectionDAGISel(tm), TM(tm),
57 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
60 virtual const char *getPassName() const {
61 return "ARM Instruction Selection";
64 /// getI32Imm - Return a target constant with the specified value, of type i32.
65 inline SDValue getI32Imm(unsigned Imm) {
66 return CurDAG->getTargetConstant(Imm, MVT::i32);
69 SDNode *Select(SDValue Op);
70 virtual void InstructionSelect();
71 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
72 SDValue &B, SDValue &C);
73 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
74 SDValue &Offset, SDValue &Opc);
75 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
76 SDValue &Offset, SDValue &Opc);
77 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
78 SDValue &Offset, SDValue &Opc);
79 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
80 SDValue &Offset, SDValue &Opc);
81 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
83 bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
86 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
89 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
91 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
92 SDValue &Base, SDValue &OffImm,
94 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
95 SDValue &OffImm, SDValue &Offset);
96 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
97 SDValue &OffImm, SDValue &Offset);
98 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
99 SDValue &OffImm, SDValue &Offset);
100 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
103 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
104 SDValue &BaseReg, SDValue &Opc);
105 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
107 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
109 bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
111 bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
113 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
114 SDValue &OffReg, SDValue &ShImm);
116 // Include the pieces autogenerated from the target description.
117 #include "ARMGenDAGISel.inc"
120 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
122 SDNode *SelectARMIndexedLoad(SDValue Op);
123 SDNode *SelectT2IndexedLoad(SDValue Op);
126 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
127 /// inline asm expressions.
128 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
130 std::vector<SDValue> &OutOps);
134 void ARMDAGToDAGISel::InstructionSelect() {
138 CurDAG->RemoveDeadNodes();
141 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
146 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
148 // Don't match base register only case. That is matched to a separate
149 // lower complexity pattern with explicit register operand.
150 if (ShOpcVal == ARM_AM::no_shift) return false;
152 BaseReg = N.getOperand(0);
153 unsigned ShImmVal = 0;
154 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
155 ShReg = CurDAG->getRegister(0, MVT::i32);
156 ShImmVal = RHS->getZExtValue() & 31;
158 ShReg = N.getOperand(1);
160 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
165 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
166 SDValue &Base, SDValue &Offset,
168 if (N.getOpcode() == ISD::MUL) {
169 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
170 // X * [3,5,9] -> X + X * [2,4,8] etc.
171 int RHSC = (int)RHS->getZExtValue();
174 ARM_AM::AddrOpc AddSub = ARM_AM::add;
176 AddSub = ARM_AM::sub;
179 if (isPowerOf2_32(RHSC)) {
180 unsigned ShAmt = Log2_32(RHSC);
181 Base = Offset = N.getOperand(0);
182 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
191 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
193 if (N.getOpcode() == ISD::FrameIndex) {
194 int FI = cast<FrameIndexSDNode>(N)->getIndex();
195 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
196 } else if (N.getOpcode() == ARMISD::Wrapper) {
197 Base = N.getOperand(0);
199 Offset = CurDAG->getRegister(0, MVT::i32);
200 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
206 // Match simple R +/- imm12 operands.
207 if (N.getOpcode() == ISD::ADD)
208 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
209 int RHSC = (int)RHS->getZExtValue();
210 if ((RHSC >= 0 && RHSC < 0x1000) ||
211 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
212 Base = N.getOperand(0);
213 if (Base.getOpcode() == ISD::FrameIndex) {
214 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
215 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
217 Offset = CurDAG->getRegister(0, MVT::i32);
219 ARM_AM::AddrOpc AddSub = ARM_AM::add;
221 AddSub = ARM_AM::sub;
224 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
231 // Otherwise this is R +/- [possibly shifted] R
232 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
233 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
236 Base = N.getOperand(0);
237 Offset = N.getOperand(1);
239 if (ShOpcVal != ARM_AM::no_shift) {
240 // Check to see if the RHS of the shift is a constant, if not, we can't fold
242 if (ConstantSDNode *Sh =
243 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
244 ShAmt = Sh->getZExtValue();
245 Offset = N.getOperand(1).getOperand(0);
247 ShOpcVal = ARM_AM::no_shift;
251 // Try matching (R shl C) + (R).
252 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
253 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
254 if (ShOpcVal != ARM_AM::no_shift) {
255 // Check to see if the RHS of the shift is a constant, if not, we can't
257 if (ConstantSDNode *Sh =
258 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
259 ShAmt = Sh->getZExtValue();
260 Offset = N.getOperand(0).getOperand(0);
261 Base = N.getOperand(1);
263 ShOpcVal = ARM_AM::no_shift;
268 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
273 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
274 SDValue &Offset, SDValue &Opc) {
275 unsigned Opcode = Op.getOpcode();
276 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
277 ? cast<LoadSDNode>(Op)->getAddressingMode()
278 : cast<StoreSDNode>(Op)->getAddressingMode();
279 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
280 ? ARM_AM::add : ARM_AM::sub;
281 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
282 int Val = (int)C->getZExtValue();
283 if (Val >= 0 && Val < 0x1000) { // 12 bits.
284 Offset = CurDAG->getRegister(0, MVT::i32);
285 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
293 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
295 if (ShOpcVal != ARM_AM::no_shift) {
296 // Check to see if the RHS of the shift is a constant, if not, we can't fold
298 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
299 ShAmt = Sh->getZExtValue();
300 Offset = N.getOperand(0);
302 ShOpcVal = ARM_AM::no_shift;
306 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
312 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
313 SDValue &Base, SDValue &Offset,
315 if (N.getOpcode() == ISD::SUB) {
316 // X - C is canonicalize to X + -C, no need to handle it here.
317 Base = N.getOperand(0);
318 Offset = N.getOperand(1);
319 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
323 if (N.getOpcode() != ISD::ADD) {
325 if (N.getOpcode() == ISD::FrameIndex) {
326 int FI = cast<FrameIndexSDNode>(N)->getIndex();
327 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
329 Offset = CurDAG->getRegister(0, MVT::i32);
330 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
334 // If the RHS is +/- imm8, fold into addr mode.
335 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
336 int RHSC = (int)RHS->getZExtValue();
337 if ((RHSC >= 0 && RHSC < 256) ||
338 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
339 Base = N.getOperand(0);
340 if (Base.getOpcode() == ISD::FrameIndex) {
341 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
342 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
344 Offset = CurDAG->getRegister(0, MVT::i32);
346 ARM_AM::AddrOpc AddSub = ARM_AM::add;
348 AddSub = ARM_AM::sub;
351 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
356 Base = N.getOperand(0);
357 Offset = N.getOperand(1);
358 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
362 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
363 SDValue &Offset, SDValue &Opc) {
364 unsigned Opcode = Op.getOpcode();
365 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
366 ? cast<LoadSDNode>(Op)->getAddressingMode()
367 : cast<StoreSDNode>(Op)->getAddressingMode();
368 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
369 ? ARM_AM::add : ARM_AM::sub;
370 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
371 int Val = (int)C->getZExtValue();
372 if (Val >= 0 && Val < 256) {
373 Offset = CurDAG->getRegister(0, MVT::i32);
374 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
380 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
385 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
386 SDValue &Base, SDValue &Offset) {
387 if (N.getOpcode() != ISD::ADD) {
389 if (N.getOpcode() == ISD::FrameIndex) {
390 int FI = cast<FrameIndexSDNode>(N)->getIndex();
391 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
392 } else if (N.getOpcode() == ARMISD::Wrapper) {
393 Base = N.getOperand(0);
395 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
400 // If the RHS is +/- imm8, fold into addr mode.
401 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
402 int RHSC = (int)RHS->getZExtValue();
403 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
405 if ((RHSC >= 0 && RHSC < 256) ||
406 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
407 Base = N.getOperand(0);
408 if (Base.getOpcode() == ISD::FrameIndex) {
409 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
410 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
413 ARM_AM::AddrOpc AddSub = ARM_AM::add;
415 AddSub = ARM_AM::sub;
418 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
426 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
431 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
432 SDValue &Addr, SDValue &Update,
435 // The optional writeback is handled in ARMLoadStoreOpt.
436 Update = CurDAG->getRegister(0, MVT::i32);
437 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
441 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
442 SDValue &Offset, SDValue &Label) {
443 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
444 Offset = N.getOperand(0);
445 SDValue N1 = N.getOperand(1);
446 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
453 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
454 SDValue &Base, SDValue &Offset){
455 // FIXME dl should come from the parent load or store, not the address
456 DebugLoc dl = Op.getDebugLoc();
457 if (N.getOpcode() != ISD::ADD) {
458 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
459 if (!NC || NC->getZExtValue() != 0)
466 Base = N.getOperand(0);
467 Offset = N.getOperand(1);
472 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
473 unsigned Scale, SDValue &Base,
474 SDValue &OffImm, SDValue &Offset) {
476 SDValue TmpBase, TmpOffImm;
477 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
478 return false; // We want to select tLDRspi / tSTRspi instead.
479 if (N.getOpcode() == ARMISD::Wrapper &&
480 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
481 return false; // We want to select tLDRpci instead.
484 if (N.getOpcode() != ISD::ADD) {
485 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
486 Offset = CurDAG->getRegister(0, MVT::i32);
487 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
491 // Thumb does not have [sp, r] address mode.
492 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
493 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
494 if ((LHSR && LHSR->getReg() == ARM::SP) ||
495 (RHSR && RHSR->getReg() == ARM::SP)) {
497 Offset = CurDAG->getRegister(0, MVT::i32);
498 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
502 // If the RHS is + imm5 * scale, fold into addr mode.
503 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
504 int RHSC = (int)RHS->getZExtValue();
505 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
507 if (RHSC >= 0 && RHSC < 32) {
508 Base = N.getOperand(0);
509 Offset = CurDAG->getRegister(0, MVT::i32);
510 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
516 Base = N.getOperand(0);
517 Offset = N.getOperand(1);
518 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
522 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
523 SDValue &Base, SDValue &OffImm,
525 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
528 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
529 SDValue &Base, SDValue &OffImm,
531 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
534 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
535 SDValue &Base, SDValue &OffImm,
537 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
540 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
541 SDValue &Base, SDValue &OffImm) {
542 if (N.getOpcode() == ISD::FrameIndex) {
543 int FI = cast<FrameIndexSDNode>(N)->getIndex();
544 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
545 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
549 if (N.getOpcode() != ISD::ADD)
552 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
553 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
554 (LHSR && LHSR->getReg() == ARM::SP)) {
555 // If the RHS is + imm8 * scale, fold into addr mode.
556 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
557 int RHSC = (int)RHS->getZExtValue();
558 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
560 if (RHSC >= 0 && RHSC < 256) {
561 Base = N.getOperand(0);
562 if (Base.getOpcode() == ISD::FrameIndex) {
563 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
564 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
566 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
576 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
579 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
581 // Don't match base register only case. That is matched to a separate
582 // lower complexity pattern with explicit register operand.
583 if (ShOpcVal == ARM_AM::no_shift) return false;
585 BaseReg = N.getOperand(0);
586 unsigned ShImmVal = 0;
587 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
588 ShImmVal = RHS->getZExtValue() & 31;
589 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
596 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
597 SDValue &Base, SDValue &OffImm) {
598 // Match simple R + imm12 operands.
599 if (N.getOpcode() != ISD::ADD)
602 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
603 int RHSC = (int)RHS->getZExtValue();
604 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits.
605 Base = N.getOperand(0);
606 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
614 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
615 SDValue &Base, SDValue &OffImm) {
616 if (N.getOpcode() == ISD::ADD) {
617 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
618 int RHSC = (int)RHS->getZExtValue();
619 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
620 Base = N.getOperand(0);
621 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
625 } else if (N.getOpcode() == ISD::SUB) {
626 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
627 int RHSC = (int)RHS->getZExtValue();
628 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
629 Base = N.getOperand(0);
630 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
639 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
641 unsigned Opcode = Op.getOpcode();
642 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
643 ? cast<LoadSDNode>(Op)->getAddressingMode()
644 : cast<StoreSDNode>(Op)->getAddressingMode();
645 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
646 int RHSC = (int)RHS->getZExtValue();
647 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
648 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
649 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
650 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
658 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
659 SDValue &Base, SDValue &OffImm) {
660 if (N.getOpcode() == ISD::ADD) {
661 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
662 int RHSC = (int)RHS->getZExtValue();
663 if (((RHSC & 0x3) == 0) &&
664 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
665 Base = N.getOperand(0);
666 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
670 } else if (N.getOpcode() == ISD::SUB) {
671 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
672 int RHSC = (int)RHS->getZExtValue();
673 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
674 Base = N.getOperand(0);
675 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
684 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
686 SDValue &OffReg, SDValue &ShImm) {
688 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
690 if (N.getOpcode() == ISD::FrameIndex) {
691 int FI = cast<FrameIndexSDNode>(N)->getIndex();
692 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
693 } else if (N.getOpcode() == ARMISD::Wrapper) {
694 Base = N.getOperand(0);
695 if (Base.getOpcode() == ISD::TargetConstantPool)
696 return false; // We want to select t2LDRpci instead.
698 OffReg = CurDAG->getRegister(0, MVT::i32);
699 ShImm = CurDAG->getTargetConstant(0, MVT::i32);
703 // Look for (R + R) or (R + (R << [1,2,3])).
705 Base = N.getOperand(0);
706 OffReg = N.getOperand(1);
708 // Swap if it is ((R << c) + R).
709 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
710 if (ShOpcVal != ARM_AM::lsl) {
711 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
712 if (ShOpcVal == ARM_AM::lsl)
713 std::swap(Base, OffReg);
716 if (ShOpcVal == ARM_AM::lsl) {
717 // Check to see if the RHS of the shift is a constant, if not, we can't fold
719 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
720 ShAmt = Sh->getZExtValue();
723 ShOpcVal = ARM_AM::no_shift;
725 OffReg = OffReg.getOperand(0);
727 ShOpcVal = ARM_AM::no_shift;
729 } else if (SelectT2AddrModeImm12(Op, N, Base, ShImm) ||
730 SelectT2AddrModeImm8 (Op, N, Base, ShImm))
731 // Don't match if it's possible to match to one of the r +/- imm cases.
734 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
739 //===--------------------------------------------------------------------===//
741 /// getAL - Returns a ARMCC::AL immediate node.
742 static inline SDValue getAL(SelectionDAG *CurDAG) {
743 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
746 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
747 LoadSDNode *LD = cast<LoadSDNode>(Op);
748 ISD::MemIndexedMode AM = LD->getAddressingMode();
749 if (AM == ISD::UNINDEXED)
752 MVT LoadedVT = LD->getMemoryVT();
753 SDValue Offset, AMOpc;
754 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
757 if (LoadedVT == MVT::i32 &&
758 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
759 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
761 } else if (LoadedVT == MVT::i16 &&
762 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
764 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
765 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
766 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
767 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
768 if (LD->getExtensionType() == ISD::SEXTLOAD) {
769 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
771 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
774 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
776 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
782 SDValue Chain = LD->getChain();
783 SDValue Base = LD->getBasePtr();
784 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
785 CurDAG->getRegister(0, MVT::i32), Chain };
786 return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
793 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
794 LoadSDNode *LD = cast<LoadSDNode>(Op);
795 ISD::MemIndexedMode AM = LD->getAddressingMode();
796 if (AM == ISD::UNINDEXED)
799 MVT LoadedVT = LD->getMemoryVT();
800 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
802 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
805 if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
806 switch (LoadedVT.getSimpleVT()) {
808 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
812 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
814 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
819 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
821 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
830 SDValue Chain = LD->getChain();
831 SDValue Base = LD->getBasePtr();
832 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
833 CurDAG->getRegister(0, MVT::i32), Chain };
834 return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
842 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
843 SDNode *N = Op.getNode();
844 DebugLoc dl = N->getDebugLoc();
846 if (N->isMachineOpcode())
847 return NULL; // Already selected.
849 switch (N->getOpcode()) {
851 case ISD::Constant: {
852 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
854 if (Subtarget->isThumb()) {
855 if (Subtarget->hasThumb2())
856 // Thumb2 has the MOVT instruction, so all immediates can
857 // be done with MOV + MOVT, at worst.
860 UseCP = (Val > 255 && // MOV
861 ~Val > 255 && // MOV + MVN
862 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
864 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
865 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
866 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
869 CurDAG->getTargetConstantPool(
870 CurDAG->getContext()->getConstantInt(Type::Int32Ty, Val),
874 if (Subtarget->isThumb1Only()) {
875 SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
876 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
877 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
878 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
883 CurDAG->getRegister(0, MVT::i32),
884 CurDAG->getTargetConstant(0, MVT::i32),
886 CurDAG->getRegister(0, MVT::i32),
887 CurDAG->getEntryNode()
889 ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
892 ReplaceUses(Op, SDValue(ResNode, 0));
896 // Other cases are autogenerated.
899 case ISD::FrameIndex: {
900 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
901 int FI = cast<FrameIndexSDNode>(N)->getIndex();
902 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
903 if (Subtarget->isThumb1Only()) {
904 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
905 CurDAG->getTargetConstant(0, MVT::i32));
907 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
908 ARM::t2ADDri : ARM::ADDri);
909 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
910 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
911 CurDAG->getRegister(0, MVT::i32) };
912 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
916 if (!Subtarget->isThumb1Only())
918 // Select add sp, c to tADDhirr.
919 SDValue N0 = Op.getOperand(0);
920 SDValue N1 = Op.getOperand(1);
921 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
922 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
923 if (LHSR && LHSR->getReg() == ARM::SP) {
925 std::swap(LHSR, RHSR);
927 if (RHSR && RHSR->getReg() == ARM::SP) {
928 SDValue Val = SDValue(CurDAG->getTargetNode(ARM::tMOVlor2hir, dl,
929 Op.getValueType(), N0, N0),0);
930 return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), Val, N1);
935 if (Subtarget->isThumb1Only())
937 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
938 unsigned RHSV = C->getZExtValue();
940 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
941 SDValue V = Op.getOperand(0);
942 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
943 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
944 CurDAG->getTargetConstant(ShImm, MVT::i32),
945 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
946 CurDAG->getRegister(0, MVT::i32) };
947 return CurDAG->SelectNodeTo(N, (Subtarget->isThumb() &&
948 Subtarget->hasThumb2()) ?
949 ARM::t2ADDrs : ARM::ADDrs, MVT::i32, Ops, 7);
951 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
952 SDValue V = Op.getOperand(0);
953 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
954 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
955 CurDAG->getTargetConstant(ShImm, MVT::i32),
956 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
957 CurDAG->getRegister(0, MVT::i32) };
958 return CurDAG->SelectNodeTo(N, (Subtarget->isThumb() &&
959 Subtarget->hasThumb2()) ?
960 ARM::t2RSBrs : ARM::RSBrs, MVT::i32, Ops, 7);
965 return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
966 Op.getOperand(0), getAL(CurDAG),
967 CurDAG->getRegister(0, MVT::i32));
968 case ISD::UMUL_LOHI: {
969 if (Subtarget->isThumb1Only())
971 if (Subtarget->isThumb()) {
972 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
973 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
974 CurDAG->getRegister(0, MVT::i32) };
975 return CurDAG->getTargetNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
977 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
978 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
979 CurDAG->getRegister(0, MVT::i32) };
980 return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
983 case ISD::SMUL_LOHI: {
984 if (Subtarget->isThumb1Only())
986 if (Subtarget->isThumb()) {
987 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
988 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
989 return CurDAG->getTargetNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
991 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
992 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
993 CurDAG->getRegister(0, MVT::i32) };
994 return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
999 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1000 ResNode = SelectT2IndexedLoad(Op);
1002 ResNode = SelectARMIndexedLoad(Op);
1005 // Other cases are autogenerated.
1008 case ARMISD::BRCOND: {
1009 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1010 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1011 // Pattern complexity = 6 cost = 1 size = 0
1013 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1014 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1015 // Pattern complexity = 6 cost = 1 size = 0
1017 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1018 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1019 // Pattern complexity = 6 cost = 1 size = 0
1021 unsigned Opc = Subtarget->isThumb() ?
1022 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1023 SDValue Chain = Op.getOperand(0);
1024 SDValue N1 = Op.getOperand(1);
1025 SDValue N2 = Op.getOperand(2);
1026 SDValue N3 = Op.getOperand(3);
1027 SDValue InFlag = Op.getOperand(4);
1028 assert(N1.getOpcode() == ISD::BasicBlock);
1029 assert(N2.getOpcode() == ISD::Constant);
1030 assert(N3.getOpcode() == ISD::Register);
1032 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1033 cast<ConstantSDNode>(N2)->getZExtValue()),
1035 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1036 SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
1038 Chain = SDValue(ResNode, 0);
1039 if (Op.getNode()->getNumValues() == 2) {
1040 InFlag = SDValue(ResNode, 1);
1041 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1043 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
1046 case ARMISD::CMOV: {
1047 MVT VT = Op.getValueType();
1048 SDValue N0 = Op.getOperand(0);
1049 SDValue N1 = Op.getOperand(1);
1050 SDValue N2 = Op.getOperand(2);
1051 SDValue N3 = Op.getOperand(3);
1052 SDValue InFlag = Op.getOperand(4);
1053 assert(N2.getOpcode() == ISD::Constant);
1054 assert(N3.getOpcode() == ISD::Register);
1056 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1057 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1058 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1059 // Pattern complexity = 18 cost = 1 size = 0
1063 if (Subtarget->isThumb()) {
1064 if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
1065 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1066 cast<ConstantSDNode>(N2)->getZExtValue()),
1068 SDValue Ops[] = { N0, CPTmp0, CPTmp1, Tmp2, N3, InFlag };
1069 return CurDAG->SelectNodeTo(Op.getNode(),
1070 ARM::t2MOVCCs, MVT::i32,Ops, 6);
1073 if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
1074 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1075 cast<ConstantSDNode>(N2)->getZExtValue()),
1077 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
1078 return CurDAG->SelectNodeTo(Op.getNode(),
1079 ARM::MOVCCs, MVT::i32, Ops, 7);
1083 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1084 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1086 // Emits: (MOVCCi:i32 GPR:i32:$false,
1087 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1088 // Pattern complexity = 10 cost = 1 size = 0
1089 if (N3.getOpcode() == ISD::Constant) {
1090 if (Subtarget->isThumb()) {
1091 if (Predicate_t2_so_imm(N3.getNode())) {
1092 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1093 cast<ConstantSDNode>(N1)->getZExtValue()),
1095 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1096 cast<ConstantSDNode>(N2)->getZExtValue()),
1098 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1099 return CurDAG->SelectNodeTo(Op.getNode(),
1100 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1103 if (Predicate_so_imm(N3.getNode())) {
1104 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1105 cast<ConstantSDNode>(N1)->getZExtValue()),
1107 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1108 cast<ConstantSDNode>(N2)->getZExtValue()),
1110 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1111 return CurDAG->SelectNodeTo(Op.getNode(),
1112 ARM::MOVCCi, MVT::i32, Ops, 5);
1118 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1119 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1120 // Pattern complexity = 6 cost = 1 size = 0
1122 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1123 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1124 // Pattern complexity = 6 cost = 11 size = 0
1126 // Also FCPYScc and FCPYDcc.
1127 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1128 cast<ConstantSDNode>(N2)->getZExtValue()),
1130 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1132 switch (VT.getSimpleVT()) {
1133 default: assert(false && "Illegal conditional move type!");
1136 Opc = Subtarget->isThumb()
1137 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr)
1147 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1149 case ARMISD::CNEG: {
1150 MVT VT = Op.getValueType();
1151 SDValue N0 = Op.getOperand(0);
1152 SDValue N1 = Op.getOperand(1);
1153 SDValue N2 = Op.getOperand(2);
1154 SDValue N3 = Op.getOperand(3);
1155 SDValue InFlag = Op.getOperand(4);
1156 assert(N2.getOpcode() == ISD::Constant);
1157 assert(N3.getOpcode() == ISD::Register);
1159 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1160 cast<ConstantSDNode>(N2)->getZExtValue()),
1162 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1164 switch (VT.getSimpleVT()) {
1165 default: assert(false && "Illegal conditional move type!");
1174 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1177 case ISD::DECLARE: {
1178 SDValue Chain = Op.getOperand(0);
1179 SDValue N1 = Op.getOperand(1);
1180 SDValue N2 = Op.getOperand(2);
1181 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
1182 // FIXME: handle VLAs.
1184 ReplaceUses(Op.getValue(0), Chain);
1187 if (N2.getOpcode() == ARMISD::PIC_ADD && isa<LoadSDNode>(N2.getOperand(0)))
1188 N2 = N2.getOperand(0);
1189 LoadSDNode *Ld = dyn_cast<LoadSDNode>(N2);
1191 ReplaceUses(Op.getValue(0), Chain);
1194 SDValue BasePtr = Ld->getBasePtr();
1195 assert(BasePtr.getOpcode() == ARMISD::Wrapper &&
1196 isa<ConstantPoolSDNode>(BasePtr.getOperand(0)) &&
1197 "llvm.dbg.variable should be a constantpool node");
1198 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(BasePtr.getOperand(0));
1199 GlobalValue *GV = 0;
1200 if (CP->isMachineConstantPoolEntry()) {
1201 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal();
1204 GV = dyn_cast<GlobalValue>(CP->getConstVal());
1206 ReplaceUses(Op.getValue(0), Chain);
1210 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
1211 TLI.getPointerTy());
1212 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
1213 SDValue Ops[] = { Tmp1, Tmp2, Chain };
1214 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
1215 MVT::Other, Ops, 3);
1218 case ISD::CONCAT_VECTORS: {
1219 MVT VT = Op.getValueType();
1220 assert(VT.is128BitVector() && Op.getNumOperands() == 2 &&
1221 "unexpected CONCAT_VECTORS");
1222 SDValue N0 = Op.getOperand(0);
1223 SDValue N1 = Op.getOperand(1);
1225 CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT);
1226 if (N0.getOpcode() != ISD::UNDEF)
1227 Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
1228 SDValue(Result, 0), N0,
1229 CurDAG->getTargetConstant(arm_dsubreg_0,
1231 if (N1.getOpcode() != ISD::UNDEF)
1232 Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
1233 SDValue(Result, 0), N1,
1234 CurDAG->getTargetConstant(arm_dsubreg_1,
1239 case ISD::VECTOR_SHUFFLE: {
1240 MVT VT = Op.getValueType();
1242 // Match 128-bit splat to VDUPLANEQ. (This could be done with a Pat in
1243 // ARMInstrNEON.td but it is awkward because the shuffle mask needs to be
1244 // transformed first into a lane number and then to both a subregister
1245 // index and an adjusted lane number.) If the source operand is a
1246 // SCALAR_TO_VECTOR, leave it so it will be matched later as a VDUP.
1247 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1248 if (VT.is128BitVector() && SVOp->isSplat() &&
1249 Op.getOperand(0).getOpcode() != ISD::SCALAR_TO_VECTOR &&
1250 Op.getOperand(1).getOpcode() == ISD::UNDEF) {
1251 unsigned LaneVal = SVOp->getSplatIndex();
1255 switch (VT.getVectorElementType().getSimpleVT()) {
1256 default: assert(false && "unhandled VDUP splat type");
1257 case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break;
1258 case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
1259 case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
1260 case MVT::f32: Opc = ARM::VDUPLNfq; HalfVT = MVT::v2f32; break;
1263 // The source operand needs to be changed to a subreg of the original
1264 // 128-bit operand, and the lane number needs to be adjusted accordingly.
1265 unsigned NumElts = VT.getVectorNumElements() / 2;
1266 unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1);
1267 SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32);
1268 SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32);
1269 SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
1270 dl, HalfVT, N->getOperand(0), SR);
1271 return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane);
1278 return SelectCode(Op);
1281 bool ARMDAGToDAGISel::
1282 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1283 std::vector<SDValue> &OutOps) {
1284 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1286 SDValue Base, Offset, Opc;
1287 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
1290 OutOps.push_back(Base);
1291 OutOps.push_back(Offset);
1292 OutOps.push_back(Opc);
1296 /// createARMISelDag - This pass converts a legalized DAG into a
1297 /// ARM-specific DAG, ready for instruction scheduling.
1299 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM) {
1300 return new ARMDAGToDAGISel(TM);