1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMTargetMachine.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
34 //===--------------------------------------------------------------------===//
35 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
36 /// instructions for SelectionDAG operations.
39 class ARMDAGToDAGISel : public SelectionDAGISel {
42 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
43 /// make the right decision when generating code for different targets.
44 const ARMSubtarget *Subtarget;
47 explicit ARMDAGToDAGISel(ARMTargetMachine &tm)
48 : SelectionDAGISel(*tm.getTargetLowering()), TM(tm),
49 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
52 virtual const char *getPassName() const {
53 return "ARM Instruction Selection";
56 SDNode *Select(SDValue Op);
57 virtual void InstructionSelect();
58 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
59 SDValue &Offset, SDValue &Opc);
60 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
61 SDValue &Offset, SDValue &Opc);
62 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
63 SDValue &Offset, SDValue &Opc);
64 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
65 SDValue &Offset, SDValue &Opc);
66 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
69 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
72 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
74 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
75 SDValue &Base, SDValue &OffImm,
77 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
78 SDValue &OffImm, SDValue &Offset);
79 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
80 SDValue &OffImm, SDValue &Offset);
81 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
82 SDValue &OffImm, SDValue &Offset);
83 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
86 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
87 SDValue &B, SDValue &C);
89 // Include the pieces autogenerated from the target description.
90 #include "ARMGenDAGISel.inc"
94 void ARMDAGToDAGISel::InstructionSelect() {
98 CurDAG->RemoveDeadNodes();
101 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
102 SDValue &Base, SDValue &Offset,
104 if (N.getOpcode() == ISD::MUL) {
105 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
106 // X * [3,5,9] -> X + X * [2,4,8] etc.
107 int RHSC = (int)RHS->getZExtValue();
110 ARM_AM::AddrOpc AddSub = ARM_AM::add;
112 AddSub = ARM_AM::sub;
115 if (isPowerOf2_32(RHSC)) {
116 unsigned ShAmt = Log2_32(RHSC);
117 Base = Offset = N.getOperand(0);
118 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
127 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
129 if (N.getOpcode() == ISD::FrameIndex) {
130 int FI = cast<FrameIndexSDNode>(N)->getIndex();
131 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
132 } else if (N.getOpcode() == ARMISD::Wrapper) {
133 Base = N.getOperand(0);
135 Offset = CurDAG->getRegister(0, MVT::i32);
136 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
142 // Match simple R +/- imm12 operands.
143 if (N.getOpcode() == ISD::ADD)
144 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
145 int RHSC = (int)RHS->getZExtValue();
146 if ((RHSC >= 0 && RHSC < 0x1000) ||
147 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
148 Base = N.getOperand(0);
149 if (Base.getOpcode() == ISD::FrameIndex) {
150 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
151 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
153 Offset = CurDAG->getRegister(0, MVT::i32);
155 ARM_AM::AddrOpc AddSub = ARM_AM::add;
157 AddSub = ARM_AM::sub;
160 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
167 // Otherwise this is R +/- [possibly shifted] R
168 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
169 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
172 Base = N.getOperand(0);
173 Offset = N.getOperand(1);
175 if (ShOpcVal != ARM_AM::no_shift) {
176 // Check to see if the RHS of the shift is a constant, if not, we can't fold
178 if (ConstantSDNode *Sh =
179 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
180 ShAmt = Sh->getZExtValue();
181 Offset = N.getOperand(1).getOperand(0);
183 ShOpcVal = ARM_AM::no_shift;
187 // Try matching (R shl C) + (R).
188 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
189 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
190 if (ShOpcVal != ARM_AM::no_shift) {
191 // Check to see if the RHS of the shift is a constant, if not, we can't
193 if (ConstantSDNode *Sh =
194 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
195 ShAmt = Sh->getZExtValue();
196 Offset = N.getOperand(0).getOperand(0);
197 Base = N.getOperand(1);
199 ShOpcVal = ARM_AM::no_shift;
204 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
209 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
210 SDValue &Offset, SDValue &Opc) {
211 unsigned Opcode = Op.getOpcode();
212 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
213 ? cast<LoadSDNode>(Op)->getAddressingMode()
214 : cast<StoreSDNode>(Op)->getAddressingMode();
215 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
216 ? ARM_AM::add : ARM_AM::sub;
217 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
218 int Val = (int)C->getZExtValue();
219 if (Val >= 0 && Val < 0x1000) { // 12 bits.
220 Offset = CurDAG->getRegister(0, MVT::i32);
221 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
229 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
231 if (ShOpcVal != ARM_AM::no_shift) {
232 // Check to see if the RHS of the shift is a constant, if not, we can't fold
234 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
235 ShAmt = Sh->getZExtValue();
236 Offset = N.getOperand(0);
238 ShOpcVal = ARM_AM::no_shift;
242 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
248 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
249 SDValue &Base, SDValue &Offset,
251 if (N.getOpcode() == ISD::SUB) {
252 // X - C is canonicalize to X + -C, no need to handle it here.
253 Base = N.getOperand(0);
254 Offset = N.getOperand(1);
255 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
259 if (N.getOpcode() != ISD::ADD) {
261 if (N.getOpcode() == ISD::FrameIndex) {
262 int FI = cast<FrameIndexSDNode>(N)->getIndex();
263 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
265 Offset = CurDAG->getRegister(0, MVT::i32);
266 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
270 // If the RHS is +/- imm8, fold into addr mode.
271 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
272 int RHSC = (int)RHS->getZExtValue();
273 if ((RHSC >= 0 && RHSC < 256) ||
274 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
275 Base = N.getOperand(0);
276 if (Base.getOpcode() == ISD::FrameIndex) {
277 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
278 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
280 Offset = CurDAG->getRegister(0, MVT::i32);
282 ARM_AM::AddrOpc AddSub = ARM_AM::add;
284 AddSub = ARM_AM::sub;
287 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
292 Base = N.getOperand(0);
293 Offset = N.getOperand(1);
294 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
298 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
299 SDValue &Offset, SDValue &Opc) {
300 unsigned Opcode = Op.getOpcode();
301 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
302 ? cast<LoadSDNode>(Op)->getAddressingMode()
303 : cast<StoreSDNode>(Op)->getAddressingMode();
304 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
305 ? ARM_AM::add : ARM_AM::sub;
306 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
307 int Val = (int)C->getZExtValue();
308 if (Val >= 0 && Val < 256) {
309 Offset = CurDAG->getRegister(0, MVT::i32);
310 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
316 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
321 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
322 SDValue &Base, SDValue &Offset) {
323 if (N.getOpcode() != ISD::ADD) {
325 if (N.getOpcode() == ISD::FrameIndex) {
326 int FI = cast<FrameIndexSDNode>(N)->getIndex();
327 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
328 } else if (N.getOpcode() == ARMISD::Wrapper) {
329 Base = N.getOperand(0);
331 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
336 // If the RHS is +/- imm8, fold into addr mode.
337 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
338 int RHSC = (int)RHS->getZExtValue();
339 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
341 if ((RHSC >= 0 && RHSC < 256) ||
342 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
343 Base = N.getOperand(0);
344 if (Base.getOpcode() == ISD::FrameIndex) {
345 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
346 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
349 ARM_AM::AddrOpc AddSub = ARM_AM::add;
351 AddSub = ARM_AM::sub;
354 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
362 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
367 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
368 SDValue &Offset, SDValue &Label) {
369 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
370 Offset = N.getOperand(0);
371 SDValue N1 = N.getOperand(1);
372 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
379 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
380 SDValue &Base, SDValue &Offset){
381 if (N.getOpcode() != ISD::ADD) {
383 // We must materialize a zero in a reg! Returning an constant here won't
384 // work since its node is -1 so it won't get added to the selection queue.
385 // Explicitly issue a tMOVri8 node!
386 Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
387 CurDAG->getTargetConstant(0, MVT::i32)), 0);
391 Base = N.getOperand(0);
392 Offset = N.getOperand(1);
397 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
398 unsigned Scale, SDValue &Base,
399 SDValue &OffImm, SDValue &Offset) {
401 SDValue TmpBase, TmpOffImm;
402 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
403 return false; // We want to select tLDRspi / tSTRspi instead.
404 if (N.getOpcode() == ARMISD::Wrapper &&
405 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
406 return false; // We want to select tLDRpci instead.
409 if (N.getOpcode() != ISD::ADD) {
410 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
411 Offset = CurDAG->getRegister(0, MVT::i32);
412 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
416 // Thumb does not have [sp, r] address mode.
417 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
418 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
419 if ((LHSR && LHSR->getReg() == ARM::SP) ||
420 (RHSR && RHSR->getReg() == ARM::SP)) {
422 Offset = CurDAG->getRegister(0, MVT::i32);
423 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
427 // If the RHS is + imm5 * scale, fold into addr mode.
428 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
429 int RHSC = (int)RHS->getZExtValue();
430 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
432 if (RHSC >= 0 && RHSC < 32) {
433 Base = N.getOperand(0);
434 Offset = CurDAG->getRegister(0, MVT::i32);
435 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
441 Base = N.getOperand(0);
442 Offset = N.getOperand(1);
443 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
447 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
448 SDValue &Base, SDValue &OffImm,
450 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
453 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
454 SDValue &Base, SDValue &OffImm,
456 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
459 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
460 SDValue &Base, SDValue &OffImm,
462 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
465 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
466 SDValue &Base, SDValue &OffImm) {
467 if (N.getOpcode() == ISD::FrameIndex) {
468 int FI = cast<FrameIndexSDNode>(N)->getIndex();
469 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
470 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
474 if (N.getOpcode() != ISD::ADD)
477 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
478 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
479 (LHSR && LHSR->getReg() == ARM::SP)) {
480 // If the RHS is + imm8 * scale, fold into addr mode.
481 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
482 int RHSC = (int)RHS->getZExtValue();
483 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
485 if (RHSC >= 0 && RHSC < 256) {
486 Base = N.getOperand(0);
487 if (Base.getOpcode() == ISD::FrameIndex) {
488 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
489 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
491 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
501 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
506 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
508 // Don't match base register only case. That is matched to a separate
509 // lower complexity pattern with explicit register operand.
510 if (ShOpcVal == ARM_AM::no_shift) return false;
512 BaseReg = N.getOperand(0);
513 unsigned ShImmVal = 0;
514 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
515 ShReg = CurDAG->getRegister(0, MVT::i32);
516 ShImmVal = RHS->getZExtValue() & 31;
518 ShReg = N.getOperand(1);
520 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
525 /// getAL - Returns a ARMCC::AL immediate node.
526 static inline SDValue getAL(SelectionDAG *CurDAG) {
527 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
531 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
532 SDNode *N = Op.getNode();
534 if (N->isMachineOpcode())
535 return NULL; // Already selected.
537 switch (N->getOpcode()) {
539 case ISD::Constant: {
540 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
542 if (Subtarget->isThumb())
543 UseCP = (Val > 255 && // MOV
544 ~Val > 255 && // MOV + MVN
545 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
547 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
548 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
549 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
552 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
556 if (Subtarget->isThumb())
557 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other,
558 CPIdx, CurDAG->getEntryNode());
562 CurDAG->getRegister(0, MVT::i32),
563 CurDAG->getTargetConstant(0, MVT::i32),
565 CurDAG->getRegister(0, MVT::i32),
566 CurDAG->getEntryNode()
568 ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6);
570 ReplaceUses(Op, SDValue(ResNode, 0));
574 // Other cases are autogenerated.
577 case ISD::FrameIndex: {
578 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
579 int FI = cast<FrameIndexSDNode>(N)->getIndex();
580 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
581 if (Subtarget->isThumb())
582 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
583 CurDAG->getTargetConstant(0, MVT::i32));
585 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
586 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
587 CurDAG->getRegister(0, MVT::i32) };
588 return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
592 // Select add sp, c to tADDhirr.
593 SDValue N0 = Op.getOperand(0);
594 SDValue N1 = Op.getOperand(1);
595 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
596 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
597 if (LHSR && LHSR->getReg() == ARM::SP) {
599 std::swap(LHSR, RHSR);
601 if (RHSR && RHSR->getReg() == ARM::SP) {
602 return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), N0, N1);
607 if (Subtarget->isThumb())
609 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
610 unsigned RHSV = C->getZExtValue();
612 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
613 SDValue V = Op.getOperand(0);
614 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
615 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
616 CurDAG->getTargetConstant(ShImm, MVT::i32),
617 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
618 CurDAG->getRegister(0, MVT::i32) };
619 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
621 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
622 SDValue V = Op.getOperand(0);
623 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
624 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
625 CurDAG->getTargetConstant(ShImm, MVT::i32),
626 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
627 CurDAG->getRegister(0, MVT::i32) };
628 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
633 return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32,
634 Op.getOperand(0), getAL(CurDAG),
635 CurDAG->getRegister(0, MVT::i32));
636 case ISD::UMUL_LOHI: {
637 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
638 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
639 CurDAG->getRegister(0, MVT::i32) };
640 return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5);
642 case ISD::SMUL_LOHI: {
643 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
644 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
645 CurDAG->getRegister(0, MVT::i32) };
646 return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5);
649 LoadSDNode *LD = cast<LoadSDNode>(Op);
650 ISD::MemIndexedMode AM = LD->getAddressingMode();
651 MVT LoadedVT = LD->getMemoryVT();
652 if (AM != ISD::UNINDEXED) {
653 SDValue Offset, AMOpc;
654 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
657 if (LoadedVT == MVT::i32 &&
658 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
659 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
661 } else if (LoadedVT == MVT::i16 &&
662 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
664 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
665 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
666 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
667 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
668 if (LD->getExtensionType() == ISD::SEXTLOAD) {
669 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
671 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
674 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
676 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
682 SDValue Chain = LD->getChain();
683 SDValue Base = LD->getBasePtr();
684 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
685 CurDAG->getRegister(0, MVT::i32), Chain };
686 return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
690 // Other cases are autogenerated.
693 case ARMISD::BRCOND: {
694 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
695 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
696 // Pattern complexity = 6 cost = 1 size = 0
698 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
699 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
700 // Pattern complexity = 6 cost = 1 size = 0
702 unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc;
703 SDValue Chain = Op.getOperand(0);
704 SDValue N1 = Op.getOperand(1);
705 SDValue N2 = Op.getOperand(2);
706 SDValue N3 = Op.getOperand(3);
707 SDValue InFlag = Op.getOperand(4);
708 assert(N1.getOpcode() == ISD::BasicBlock);
709 assert(N2.getOpcode() == ISD::Constant);
710 assert(N3.getOpcode() == ISD::Register);
712 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
713 cast<ConstantSDNode>(N2)->getZExtValue()),
715 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
716 SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
717 Chain = SDValue(ResNode, 0);
718 if (Op.getNode()->getNumValues() == 2) {
719 InFlag = SDValue(ResNode, 1);
720 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
722 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
726 bool isThumb = Subtarget->isThumb();
727 MVT VT = Op.getValueType();
728 SDValue N0 = Op.getOperand(0);
729 SDValue N1 = Op.getOperand(1);
730 SDValue N2 = Op.getOperand(2);
731 SDValue N3 = Op.getOperand(3);
732 SDValue InFlag = Op.getOperand(4);
733 assert(N2.getOpcode() == ISD::Constant);
734 assert(N3.getOpcode() == ISD::Register);
736 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
737 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
738 // Pattern complexity = 18 cost = 1 size = 0
742 if (!isThumb && VT == MVT::i32 &&
743 SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
744 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
745 cast<ConstantSDNode>(N2)->getZExtValue()),
747 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
748 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
751 // Pattern: (ARMcmov:i32 GPR:i32:$false,
752 // (imm:i32)<<P:Predicate_so_imm>><<X:so_imm_XFORM>>:$true,
754 // Emits: (MOVCCi:i32 GPR:i32:$false,
755 // (so_imm_XFORM:i32 (imm:i32):$true), (imm:i32):$cc)
756 // Pattern complexity = 10 cost = 1 size = 0
757 if (VT == MVT::i32 &&
758 N3.getOpcode() == ISD::Constant &&
759 Predicate_so_imm(N3.getNode())) {
760 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
761 cast<ConstantSDNode>(N1)->getZExtValue()),
763 Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
764 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
765 cast<ConstantSDNode>(N2)->getZExtValue()),
767 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
768 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5);
771 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
772 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
773 // Pattern complexity = 6 cost = 1 size = 0
775 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
776 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
777 // Pattern complexity = 6 cost = 11 size = 0
779 // Also FCPYScc and FCPYDcc.
780 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
781 cast<ConstantSDNode>(N2)->getZExtValue()),
783 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
785 switch (VT.getSimpleVT()) {
786 default: assert(false && "Illegal conditional move type!");
789 Opc = isThumb ? ARM::tMOVCCr : ARM::MOVCCr;
798 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
801 MVT VT = Op.getValueType();
802 SDValue N0 = Op.getOperand(0);
803 SDValue N1 = Op.getOperand(1);
804 SDValue N2 = Op.getOperand(2);
805 SDValue N3 = Op.getOperand(3);
806 SDValue InFlag = Op.getOperand(4);
807 assert(N2.getOpcode() == ISD::Constant);
808 assert(N3.getOpcode() == ISD::Register);
810 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
811 cast<ConstantSDNode>(N2)->getZExtValue()),
813 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
815 switch (VT.getSimpleVT()) {
816 default: assert(false && "Illegal conditional move type!");
825 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
828 return SelectCode(Op);
831 /// createARMISelDag - This pass converts a legalized DAG into a
832 /// ARM-specific DAG, ready for instruction scheduling.
834 FunctionPass *llvm::createARMISelDag(ARMTargetMachine &TM) {
835 return new ARMDAGToDAGISel(TM);