1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMAddressingModes.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
40 DisableShifterOp("disable-shifter-op", cl::Hidden,
41 cl::desc("Disable isel of shifter-op"),
44 //===--------------------------------------------------------------------===//
45 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
46 /// instructions for SelectionDAG operations.
51 AM2_BASE, // Simple AM2 (+-imm12)
52 AM2_SHOP // Shifter-op AM2
55 class ARMDAGToDAGISel : public SelectionDAGISel {
56 ARMBaseTargetMachine &TM;
58 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
59 /// make the right decision when generating code for different targets.
60 const ARMSubtarget *Subtarget;
63 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
64 CodeGenOpt::Level OptLevel)
65 : SelectionDAGISel(tm, OptLevel), TM(tm),
66 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
69 virtual const char *getPassName() const {
70 return "ARM Instruction Selection";
73 /// getI32Imm - Return a target constant of type i32 with the specified
75 inline SDValue getI32Imm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, MVT::i32);
79 SDNode *Select(SDNode *N);
81 bool SelectShifterOperandReg(SDValue N, SDValue &A,
82 SDValue &B, SDValue &C);
83 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
84 SDValue &Offset, SDValue &Opc);
85 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
87 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
90 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
92 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
95 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
97 SelectAddrMode2Worker(N, Base, Offset, Opc);
98 // This always matches one way or another.
102 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
103 SDValue &Offset, SDValue &Opc);
104 bool SelectAddrMode3(SDValue N, SDValue &Base,
105 SDValue &Offset, SDValue &Opc);
106 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
107 SDValue &Offset, SDValue &Opc);
108 bool SelectAddrMode4(SDValue N, SDValue &Addr, SDValue &Mode);
109 bool SelectAddrMode5(SDValue N, SDValue &Base,
111 bool SelectAddrMode6(SDValue N, SDValue &Addr, SDValue &Align);
113 bool SelectAddrModePC(SDValue N, SDValue &Offset,
116 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
117 bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
118 SDValue &Base, SDValue &OffImm,
120 bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
121 SDValue &OffImm, SDValue &Offset);
122 bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
123 SDValue &OffImm, SDValue &Offset);
124 bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
125 SDValue &OffImm, SDValue &Offset);
126 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
128 bool SelectT2ShifterOperandReg(SDValue N,
129 SDValue &BaseReg, SDValue &Opc);
130 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
131 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
133 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
135 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
136 SDValue &OffReg, SDValue &ShImm);
138 inline bool Pred_so_imm(SDNode *inN) const {
139 ConstantSDNode *N = cast<ConstantSDNode>(inN);
140 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
143 inline bool Pred_t2_so_imm(SDNode *inN) const {
144 ConstantSDNode *N = cast<ConstantSDNode>(inN);
145 return ARM_AM::getT2SOImmVal(N->getZExtValue()) != -1;
148 // Include the pieces autogenerated from the target description.
149 #include "ARMGenDAGISel.inc"
152 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
154 SDNode *SelectARMIndexedLoad(SDNode *N);
155 SDNode *SelectT2IndexedLoad(SDNode *N);
157 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
158 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
159 /// loads of D registers and even subregs and odd subregs of Q registers.
160 /// For NumVecs <= 2, QOpcodes1 is not used.
161 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
162 unsigned *QOpcodes0, unsigned *QOpcodes1);
164 /// SelectVST - Select NEON store intrinsics. NumVecs should
165 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
166 /// stores of D registers and even subregs and odd subregs of Q registers.
167 /// For NumVecs <= 2, QOpcodes1 is not used.
168 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
169 unsigned *QOpcodes0, unsigned *QOpcodes1);
171 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
172 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
173 /// load/store of D registers and Q registers.
174 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
175 unsigned *DOpcodes, unsigned *QOpcodes);
177 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
178 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
179 /// generated to force the table registers to be consecutive.
180 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
182 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
183 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
185 /// SelectCMOVOp - Select CMOV instructions for ARM.
186 SDNode *SelectCMOVOp(SDNode *N);
187 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
188 ARMCC::CondCodes CCVal, SDValue CCR,
190 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
191 ARMCC::CondCodes CCVal, SDValue CCR,
193 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
194 ARMCC::CondCodes CCVal, SDValue CCR,
196 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
197 ARMCC::CondCodes CCVal, SDValue CCR,
200 SDNode *SelectConcatVector(SDNode *N);
202 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
203 /// inline asm expressions.
204 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
206 std::vector<SDValue> &OutOps);
208 // Form pairs of consecutive S, D, or Q registers.
209 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
210 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
211 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
213 // Form sequences of 4 consecutive S, D, or Q registers.
214 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
215 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
216 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
220 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
221 /// operand. If so Imm will receive the 32-bit value.
222 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
223 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
224 Imm = cast<ConstantSDNode>(N)->getZExtValue();
230 // isInt32Immediate - This method tests to see if a constant operand.
231 // If so Imm will receive the 32 bit value.
232 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
233 return isInt32Immediate(N.getNode(), Imm);
236 // isOpcWithIntImmediate - This method tests to see if the node is a specific
237 // opcode and that it has a immediate integer right operand.
238 // If so Imm will receive the 32 bit value.
239 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
240 return N->getOpcode() == Opc &&
241 isInt32Immediate(N->getOperand(1).getNode(), Imm);
245 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
249 if (DisableShifterOp)
252 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
254 // Don't match base register only case. That is matched to a separate
255 // lower complexity pattern with explicit register operand.
256 if (ShOpcVal == ARM_AM::no_shift) return false;
258 BaseReg = N.getOperand(0);
259 unsigned ShImmVal = 0;
260 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
261 ShReg = CurDAG->getRegister(0, MVT::i32);
262 ShImmVal = RHS->getZExtValue() & 31;
264 ShReg = N.getOperand(1);
266 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
271 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
275 if (N.getOpcode() == ISD::MUL) {
276 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
277 // X * [3,5,9] -> X + X * [2,4,8] etc.
278 int RHSC = (int)RHS->getZExtValue();
281 ARM_AM::AddrOpc AddSub = ARM_AM::add;
283 AddSub = ARM_AM::sub;
286 if (isPowerOf2_32(RHSC)) {
287 unsigned ShAmt = Log2_32(RHSC);
288 Base = Offset = N.getOperand(0);
289 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
298 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
300 if (N.getOpcode() == ISD::FrameIndex) {
301 int FI = cast<FrameIndexSDNode>(N)->getIndex();
302 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
303 } else if (N.getOpcode() == ARMISD::Wrapper &&
304 !(Subtarget->useMovt() &&
305 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
306 Base = N.getOperand(0);
308 Offset = CurDAG->getRegister(0, MVT::i32);
309 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
315 // Match simple R +/- imm12 operands.
316 if (N.getOpcode() == ISD::ADD) {
317 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
318 int RHSC = (int)RHS->getZExtValue();
319 if ((RHSC >= 0 && RHSC < 0x1000) ||
320 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
321 Base = N.getOperand(0);
322 if (Base.getOpcode() == ISD::FrameIndex) {
323 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
324 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
326 Offset = CurDAG->getRegister(0, MVT::i32);
328 ARM_AM::AddrOpc AddSub = ARM_AM::add;
330 AddSub = ARM_AM::sub;
333 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
341 // Otherwise this is R +/- [possibly shifted] R.
342 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
343 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
346 Base = N.getOperand(0);
347 Offset = N.getOperand(1);
349 if (ShOpcVal != ARM_AM::no_shift) {
350 // Check to see if the RHS of the shift is a constant, if not, we can't fold
352 if (ConstantSDNode *Sh =
353 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
354 ShAmt = Sh->getZExtValue();
355 Offset = N.getOperand(1).getOperand(0);
357 ShOpcVal = ARM_AM::no_shift;
361 // Try matching (R shl C) + (R).
362 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
363 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
364 if (ShOpcVal != ARM_AM::no_shift) {
365 // Check to see if the RHS of the shift is a constant, if not, we can't
367 if (ConstantSDNode *Sh =
368 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
369 ShAmt = Sh->getZExtValue();
370 Offset = N.getOperand(0).getOperand(0);
371 Base = N.getOperand(1);
373 ShOpcVal = ARM_AM::no_shift;
378 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
383 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
384 SDValue &Offset, SDValue &Opc) {
385 unsigned Opcode = Op->getOpcode();
386 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
387 ? cast<LoadSDNode>(Op)->getAddressingMode()
388 : cast<StoreSDNode>(Op)->getAddressingMode();
389 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
390 ? ARM_AM::add : ARM_AM::sub;
391 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
392 int Val = (int)C->getZExtValue();
393 if (Val >= 0 && Val < 0x1000) { // 12 bits.
394 Offset = CurDAG->getRegister(0, MVT::i32);
395 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
403 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
405 if (ShOpcVal != ARM_AM::no_shift) {
406 // Check to see if the RHS of the shift is a constant, if not, we can't fold
408 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
409 ShAmt = Sh->getZExtValue();
410 Offset = N.getOperand(0);
412 ShOpcVal = ARM_AM::no_shift;
416 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
422 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
423 SDValue &Base, SDValue &Offset,
425 if (N.getOpcode() == ISD::SUB) {
426 // X - C is canonicalize to X + -C, no need to handle it here.
427 Base = N.getOperand(0);
428 Offset = N.getOperand(1);
429 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
433 if (N.getOpcode() != ISD::ADD) {
435 if (N.getOpcode() == ISD::FrameIndex) {
436 int FI = cast<FrameIndexSDNode>(N)->getIndex();
437 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
439 Offset = CurDAG->getRegister(0, MVT::i32);
440 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
444 // If the RHS is +/- imm8, fold into addr mode.
445 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
446 int RHSC = (int)RHS->getZExtValue();
447 if ((RHSC >= 0 && RHSC < 256) ||
448 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
449 Base = N.getOperand(0);
450 if (Base.getOpcode() == ISD::FrameIndex) {
451 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
452 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
454 Offset = CurDAG->getRegister(0, MVT::i32);
456 ARM_AM::AddrOpc AddSub = ARM_AM::add;
458 AddSub = ARM_AM::sub;
461 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
466 Base = N.getOperand(0);
467 Offset = N.getOperand(1);
468 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
472 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
473 SDValue &Offset, SDValue &Opc) {
474 unsigned Opcode = Op->getOpcode();
475 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
476 ? cast<LoadSDNode>(Op)->getAddressingMode()
477 : cast<StoreSDNode>(Op)->getAddressingMode();
478 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
479 ? ARM_AM::add : ARM_AM::sub;
480 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
481 int Val = (int)C->getZExtValue();
482 if (Val >= 0 && Val < 256) {
483 Offset = CurDAG->getRegister(0, MVT::i32);
484 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
490 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
494 bool ARMDAGToDAGISel::SelectAddrMode4(SDValue N, SDValue &Addr, SDValue &Mode) {
496 Mode = CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32);
500 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
501 SDValue &Base, SDValue &Offset) {
502 if (N.getOpcode() != ISD::ADD) {
504 if (N.getOpcode() == ISD::FrameIndex) {
505 int FI = cast<FrameIndexSDNode>(N)->getIndex();
506 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
507 } else if (N.getOpcode() == ARMISD::Wrapper &&
508 !(Subtarget->useMovt() &&
509 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
510 Base = N.getOperand(0);
512 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
517 // If the RHS is +/- imm8, fold into addr mode.
518 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
519 int RHSC = (int)RHS->getZExtValue();
520 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
522 if ((RHSC >= 0 && RHSC < 256) ||
523 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
524 Base = N.getOperand(0);
525 if (Base.getOpcode() == ISD::FrameIndex) {
526 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
527 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
530 ARM_AM::AddrOpc AddSub = ARM_AM::add;
532 AddSub = ARM_AM::sub;
535 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
543 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
548 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue N, SDValue &Addr, SDValue &Align){
550 // Default to no alignment.
551 Align = CurDAG->getTargetConstant(0, MVT::i32);
555 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
556 SDValue &Offset, SDValue &Label) {
557 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
558 Offset = N.getOperand(0);
559 SDValue N1 = N.getOperand(1);
560 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
567 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
568 SDValue &Base, SDValue &Offset){
569 // FIXME dl should come from the parent load or store, not the address
570 if (N.getOpcode() != ISD::ADD) {
571 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
572 if (!NC || !NC->isNullValue())
579 Base = N.getOperand(0);
580 Offset = N.getOperand(1);
585 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
586 unsigned Scale, SDValue &Base,
587 SDValue &OffImm, SDValue &Offset) {
589 SDValue TmpBase, TmpOffImm;
590 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
591 return false; // We want to select tLDRspi / tSTRspi instead.
592 if (N.getOpcode() == ARMISD::Wrapper &&
593 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
594 return false; // We want to select tLDRpci instead.
597 if (N.getOpcode() != ISD::ADD) {
598 if (N.getOpcode() == ARMISD::Wrapper &&
599 !(Subtarget->useMovt() &&
600 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
601 Base = N.getOperand(0);
605 Offset = CurDAG->getRegister(0, MVT::i32);
606 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
610 // Thumb does not have [sp, r] address mode.
611 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
612 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
613 if ((LHSR && LHSR->getReg() == ARM::SP) ||
614 (RHSR && RHSR->getReg() == ARM::SP)) {
616 Offset = CurDAG->getRegister(0, MVT::i32);
617 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
621 // If the RHS is + imm5 * scale, fold into addr mode.
622 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
623 int RHSC = (int)RHS->getZExtValue();
624 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
626 if (RHSC >= 0 && RHSC < 32) {
627 Base = N.getOperand(0);
628 Offset = CurDAG->getRegister(0, MVT::i32);
629 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
635 Base = N.getOperand(0);
636 Offset = N.getOperand(1);
637 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
641 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
642 SDValue &Base, SDValue &OffImm,
644 return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
647 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
648 SDValue &Base, SDValue &OffImm,
650 return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
653 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
654 SDValue &Base, SDValue &OffImm,
656 return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
659 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
660 SDValue &Base, SDValue &OffImm) {
661 if (N.getOpcode() == ISD::FrameIndex) {
662 int FI = cast<FrameIndexSDNode>(N)->getIndex();
663 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
664 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
668 if (N.getOpcode() != ISD::ADD)
671 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
672 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
673 (LHSR && LHSR->getReg() == ARM::SP)) {
674 // If the RHS is + imm8 * scale, fold into addr mode.
675 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
676 int RHSC = (int)RHS->getZExtValue();
677 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
679 if (RHSC >= 0 && RHSC < 256) {
680 Base = N.getOperand(0);
681 if (Base.getOpcode() == ISD::FrameIndex) {
682 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
683 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
685 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
695 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
697 if (DisableShifterOp)
700 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
702 // Don't match base register only case. That is matched to a separate
703 // lower complexity pattern with explicit register operand.
704 if (ShOpcVal == ARM_AM::no_shift) return false;
706 BaseReg = N.getOperand(0);
707 unsigned ShImmVal = 0;
708 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
709 ShImmVal = RHS->getZExtValue() & 31;
710 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
717 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
718 SDValue &Base, SDValue &OffImm) {
719 // Match simple R + imm12 operands.
722 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
723 if (N.getOpcode() == ISD::FrameIndex) {
724 // Match frame index...
725 int FI = cast<FrameIndexSDNode>(N)->getIndex();
726 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
727 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
729 } else if (N.getOpcode() == ARMISD::Wrapper &&
730 !(Subtarget->useMovt() &&
731 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
732 Base = N.getOperand(0);
733 if (Base.getOpcode() == ISD::TargetConstantPool)
734 return false; // We want to select t2LDRpci instead.
737 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
741 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
742 if (SelectT2AddrModeImm8(N, Base, OffImm))
743 // Let t2LDRi8 handle (R - imm8).
746 int RHSC = (int)RHS->getZExtValue();
747 if (N.getOpcode() == ISD::SUB)
750 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
751 Base = N.getOperand(0);
752 if (Base.getOpcode() == ISD::FrameIndex) {
753 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
754 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
756 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
763 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
767 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
768 SDValue &Base, SDValue &OffImm) {
769 // Match simple R - imm8 operands.
770 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
771 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
772 int RHSC = (int)RHS->getSExtValue();
773 if (N.getOpcode() == ISD::SUB)
776 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
777 Base = N.getOperand(0);
778 if (Base.getOpcode() == ISD::FrameIndex) {
779 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
780 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
782 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
791 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
793 unsigned Opcode = Op->getOpcode();
794 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
795 ? cast<LoadSDNode>(Op)->getAddressingMode()
796 : cast<StoreSDNode>(Op)->getAddressingMode();
797 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
798 int RHSC = (int)RHS->getZExtValue();
799 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
800 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
801 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
802 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
810 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
812 SDValue &OffReg, SDValue &ShImm) {
813 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
814 if (N.getOpcode() != ISD::ADD)
817 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
818 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
819 int RHSC = (int)RHS->getZExtValue();
820 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
822 else if (RHSC < 0 && RHSC >= -255) // 8 bits
826 // Look for (R + R) or (R + (R << [1,2,3])).
828 Base = N.getOperand(0);
829 OffReg = N.getOperand(1);
831 // Swap if it is ((R << c) + R).
832 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
833 if (ShOpcVal != ARM_AM::lsl) {
834 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
835 if (ShOpcVal == ARM_AM::lsl)
836 std::swap(Base, OffReg);
839 if (ShOpcVal == ARM_AM::lsl) {
840 // Check to see if the RHS of the shift is a constant, if not, we can't fold
842 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
843 ShAmt = Sh->getZExtValue();
846 ShOpcVal = ARM_AM::no_shift;
848 OffReg = OffReg.getOperand(0);
850 ShOpcVal = ARM_AM::no_shift;
854 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
859 //===--------------------------------------------------------------------===//
861 /// getAL - Returns a ARMCC::AL immediate node.
862 static inline SDValue getAL(SelectionDAG *CurDAG) {
863 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
866 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
867 LoadSDNode *LD = cast<LoadSDNode>(N);
868 ISD::MemIndexedMode AM = LD->getAddressingMode();
869 if (AM == ISD::UNINDEXED)
872 EVT LoadedVT = LD->getMemoryVT();
873 SDValue Offset, AMOpc;
874 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
877 if (LoadedVT == MVT::i32 &&
878 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
879 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
881 } else if (LoadedVT == MVT::i16 &&
882 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
884 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
885 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
886 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
887 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
888 if (LD->getExtensionType() == ISD::SEXTLOAD) {
889 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
891 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
894 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
896 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
902 SDValue Chain = LD->getChain();
903 SDValue Base = LD->getBasePtr();
904 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
905 CurDAG->getRegister(0, MVT::i32), Chain };
906 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
913 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
914 LoadSDNode *LD = cast<LoadSDNode>(N);
915 ISD::MemIndexedMode AM = LD->getAddressingMode();
916 if (AM == ISD::UNINDEXED)
919 EVT LoadedVT = LD->getMemoryVT();
920 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
922 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
925 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
926 switch (LoadedVT.getSimpleVT().SimpleTy) {
928 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
932 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
934 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
939 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
941 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
950 SDValue Chain = LD->getChain();
951 SDValue Base = LD->getBasePtr();
952 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
953 CurDAG->getRegister(0, MVT::i32), Chain };
954 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
961 /// PairSRegs - Form a D register from a pair of S registers.
963 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
964 DebugLoc dl = V0.getNode()->getDebugLoc();
965 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
966 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
967 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
968 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
971 /// PairDRegs - Form a quad register from a pair of D registers.
973 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
974 DebugLoc dl = V0.getNode()->getDebugLoc();
975 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
976 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
977 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
978 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
981 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
983 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
984 DebugLoc dl = V0.getNode()->getDebugLoc();
985 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
986 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
987 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
988 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
991 /// QuadSRegs - Form 4 consecutive S registers.
993 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
994 SDValue V2, SDValue V3) {
995 DebugLoc dl = V0.getNode()->getDebugLoc();
996 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
997 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
998 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
999 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1000 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1001 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1004 /// QuadDRegs - Form 4 consecutive D registers.
1006 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1007 SDValue V2, SDValue V3) {
1008 DebugLoc dl = V0.getNode()->getDebugLoc();
1009 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1010 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1011 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1012 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1013 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1014 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1017 /// QuadQRegs - Form 4 consecutive Q registers.
1019 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1020 SDValue V2, SDValue V3) {
1021 DebugLoc dl = V0.getNode()->getDebugLoc();
1022 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1023 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1024 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1025 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1026 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1027 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1030 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1031 /// of a NEON VLD or VST instruction. The supported values depend on the
1032 /// number of registers being loaded.
1033 static unsigned GetVLDSTAlign(SDNode *N, unsigned NumVecs, bool is64BitVector) {
1034 unsigned NumRegs = NumVecs;
1035 if (!is64BitVector && NumVecs < 3)
1038 unsigned Alignment = cast<MemIntrinsicSDNode>(N)->getAlignment();
1039 if (Alignment >= 32 && NumRegs == 4)
1041 if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1048 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
1049 unsigned *DOpcodes, unsigned *QOpcodes0,
1050 unsigned *QOpcodes1) {
1051 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1052 DebugLoc dl = N->getDebugLoc();
1054 SDValue MemAddr, Align;
1055 if (!SelectAddrMode6(N->getOperand(2), MemAddr, Align))
1058 SDValue Chain = N->getOperand(0);
1059 EVT VT = N->getValueType(0);
1060 bool is64BitVector = VT.is64BitVector();
1062 unsigned Alignment = GetVLDSTAlign(N, NumVecs, is64BitVector);
1063 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1065 unsigned OpcodeIndex;
1066 switch (VT.getSimpleVT().SimpleTy) {
1067 default: llvm_unreachable("unhandled vld type");
1068 // Double-register operations:
1069 case MVT::v8i8: OpcodeIndex = 0; break;
1070 case MVT::v4i16: OpcodeIndex = 1; break;
1072 case MVT::v2i32: OpcodeIndex = 2; break;
1073 case MVT::v1i64: OpcodeIndex = 3; break;
1074 // Quad-register operations:
1075 case MVT::v16i8: OpcodeIndex = 0; break;
1076 case MVT::v8i16: OpcodeIndex = 1; break;
1078 case MVT::v4i32: OpcodeIndex = 2; break;
1079 case MVT::v2i64: OpcodeIndex = 3;
1080 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1088 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1091 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1094 SDValue Pred = getAL(CurDAG);
1095 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1097 if (is64BitVector) {
1098 unsigned Opc = DOpcodes[OpcodeIndex];
1099 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1100 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1104 SuperReg = SDValue(VLd, 0);
1105 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1106 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1107 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
1109 ReplaceUses(SDValue(N, Vec), D);
1111 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1116 // Quad registers are directly supported for VLD1 and VLD2,
1117 // loading pairs of D regs.
1118 unsigned Opc = QOpcodes0[OpcodeIndex];
1119 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1120 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1124 SuperReg = SDValue(VLd, 0);
1125 Chain = SDValue(VLd, 1);
1128 // Otherwise, quad registers are loaded with two separate instructions,
1129 // where one loads the even registers and the other loads the odd registers.
1130 EVT AddrTy = MemAddr.getValueType();
1132 // Load the even subregs.
1133 unsigned Opc = QOpcodes0[OpcodeIndex];
1135 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1136 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1138 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsA, 7);
1139 Chain = SDValue(VLdA, 2);
1141 // Load the odd subregs.
1142 Opc = QOpcodes1[OpcodeIndex];
1143 const SDValue OpsB[] = { SDValue(VLdA, 1), Align, Reg0, SDValue(VLdA, 0),
1144 Pred, Reg0, Chain };
1146 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsB, 7);
1147 SuperReg = SDValue(VLdB, 0);
1148 Chain = SDValue(VLdB, 2);
1151 // Extract out the Q registers.
1152 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1153 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1154 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
1156 ReplaceUses(SDValue(N, Vec), Q);
1158 ReplaceUses(SDValue(N, NumVecs), Chain);
1162 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1163 unsigned *DOpcodes, unsigned *QOpcodes0,
1164 unsigned *QOpcodes1) {
1165 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1166 DebugLoc dl = N->getDebugLoc();
1168 SDValue MemAddr, Align;
1169 if (!SelectAddrMode6(N->getOperand(2), MemAddr, Align))
1172 SDValue Chain = N->getOperand(0);
1173 EVT VT = N->getOperand(3).getValueType();
1174 bool is64BitVector = VT.is64BitVector();
1176 unsigned Alignment = GetVLDSTAlign(N, NumVecs, is64BitVector);
1177 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1179 unsigned OpcodeIndex;
1180 switch (VT.getSimpleVT().SimpleTy) {
1181 default: llvm_unreachable("unhandled vst type");
1182 // Double-register operations:
1183 case MVT::v8i8: OpcodeIndex = 0; break;
1184 case MVT::v4i16: OpcodeIndex = 1; break;
1186 case MVT::v2i32: OpcodeIndex = 2; break;
1187 case MVT::v1i64: OpcodeIndex = 3; break;
1188 // Quad-register operations:
1189 case MVT::v16i8: OpcodeIndex = 0; break;
1190 case MVT::v8i16: OpcodeIndex = 1; break;
1192 case MVT::v4i32: OpcodeIndex = 2; break;
1193 case MVT::v2i64: OpcodeIndex = 3;
1194 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1198 SDValue Pred = getAL(CurDAG);
1199 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1201 SmallVector<SDValue, 7> Ops;
1202 Ops.push_back(MemAddr);
1203 Ops.push_back(Align);
1205 if (is64BitVector) {
1207 Ops.push_back(N->getOperand(3));
1210 SDValue V0 = N->getOperand(0+3);
1211 SDValue V1 = N->getOperand(1+3);
1213 // Form a REG_SEQUENCE to force register allocation.
1215 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1217 SDValue V2 = N->getOperand(2+3);
1218 // If it's a vld3, form a quad D-register and leave the last part as
1220 SDValue V3 = (NumVecs == 3)
1221 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1222 : N->getOperand(3+3);
1223 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1225 Ops.push_back(RegSeq);
1227 Ops.push_back(Pred);
1228 Ops.push_back(Reg0); // predicate register
1229 Ops.push_back(Chain);
1230 unsigned Opc = DOpcodes[OpcodeIndex];
1231 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1235 // Quad registers are directly supported for VST1 and VST2.
1236 unsigned Opc = QOpcodes0[OpcodeIndex];
1238 Ops.push_back(N->getOperand(3));
1240 // Form a QQ register.
1241 SDValue Q0 = N->getOperand(3);
1242 SDValue Q1 = N->getOperand(4);
1243 Ops.push_back(SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0));
1245 Ops.push_back(Pred);
1246 Ops.push_back(Reg0); // predicate register
1247 Ops.push_back(Chain);
1248 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1251 // Otherwise, quad registers are stored with two separate instructions,
1252 // where one stores the even registers and the other stores the odd registers.
1254 // Form the QQQQ REG_SEQUENCE.
1255 SDValue V0 = N->getOperand(0+3);
1256 SDValue V1 = N->getOperand(1+3);
1257 SDValue V2 = N->getOperand(2+3);
1258 SDValue V3 = (NumVecs == 3)
1259 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1260 : N->getOperand(3+3);
1261 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1263 // Store the even D registers.
1264 Ops.push_back(Reg0); // post-access address offset
1265 Ops.push_back(RegSeq);
1266 Ops.push_back(Pred);
1267 Ops.push_back(Reg0); // predicate register
1268 Ops.push_back(Chain);
1269 unsigned Opc = QOpcodes0[OpcodeIndex];
1270 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1271 MVT::Other, Ops.data(), 7);
1272 Chain = SDValue(VStA, 1);
1274 // Store the odd D registers.
1275 Ops[0] = SDValue(VStA, 0); // MemAddr
1277 Opc = QOpcodes1[OpcodeIndex];
1278 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1279 MVT::Other, Ops.data(), 7);
1280 Chain = SDValue(VStB, 1);
1281 ReplaceUses(SDValue(N, 0), Chain);
1285 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1286 unsigned NumVecs, unsigned *DOpcodes,
1287 unsigned *QOpcodes) {
1288 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1289 DebugLoc dl = N->getDebugLoc();
1291 SDValue MemAddr, Align;
1292 if (!SelectAddrMode6(N->getOperand(2), MemAddr, Align))
1295 SDValue Chain = N->getOperand(0);
1297 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1298 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1299 bool is64BitVector = VT.is64BitVector();
1302 unsigned Alignment = cast<MemIntrinsicSDNode>(N)->getAlignment();
1303 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1304 if (Alignment > NumBytes)
1305 Alignment = NumBytes;
1306 // Alignment must be a power of two; make sure of that.
1307 Alignment = (Alignment & -Alignment);
1309 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1312 unsigned OpcodeIndex;
1313 switch (VT.getSimpleVT().SimpleTy) {
1314 default: llvm_unreachable("unhandled vld/vst lane type");
1315 // Double-register operations:
1316 case MVT::v8i8: OpcodeIndex = 0; break;
1317 case MVT::v4i16: OpcodeIndex = 1; break;
1319 case MVT::v2i32: OpcodeIndex = 2; break;
1320 // Quad-register operations:
1321 case MVT::v8i16: OpcodeIndex = 0; break;
1323 case MVT::v4i32: OpcodeIndex = 1; break;
1326 SDValue Pred = getAL(CurDAG);
1327 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1329 SmallVector<SDValue, 7> Ops;
1330 Ops.push_back(MemAddr);
1331 Ops.push_back(Align);
1333 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1334 QOpcodes[OpcodeIndex]);
1337 SDValue V0 = N->getOperand(0+3);
1338 SDValue V1 = N->getOperand(1+3);
1341 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1343 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1345 SDValue V2 = N->getOperand(2+3);
1346 SDValue V3 = (NumVecs == 3)
1347 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1348 : N->getOperand(3+3);
1350 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1352 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1354 Ops.push_back(SuperReg);
1355 Ops.push_back(getI32Imm(Lane));
1356 Ops.push_back(Pred);
1357 Ops.push_back(Reg0);
1358 Ops.push_back(Chain);
1361 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 7);
1364 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1367 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1369 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other,
1371 SuperReg = SDValue(VLdLn, 0);
1372 Chain = SDValue(VLdLn, 1);
1374 // Extract the subregisters.
1375 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1376 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1377 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1378 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1379 ReplaceUses(SDValue(N, Vec),
1380 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1381 ReplaceUses(SDValue(N, NumVecs), Chain);
1385 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1387 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1388 DebugLoc dl = N->getDebugLoc();
1389 EVT VT = N->getValueType(0);
1390 unsigned FirstTblReg = IsExt ? 2 : 1;
1392 // Form a REG_SEQUENCE to force register allocation.
1394 SDValue V0 = N->getOperand(FirstTblReg + 0);
1395 SDValue V1 = N->getOperand(FirstTblReg + 1);
1397 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1399 SDValue V2 = N->getOperand(FirstTblReg + 2);
1400 // If it's a vtbl3, form a quad D-register and leave the last part as
1402 SDValue V3 = (NumVecs == 3)
1403 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1404 : N->getOperand(FirstTblReg + 3);
1405 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1408 SmallVector<SDValue, 6> Ops;
1410 Ops.push_back(N->getOperand(1));
1411 Ops.push_back(RegSeq);
1412 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1413 Ops.push_back(getAL(CurDAG)); // predicate
1414 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1415 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1418 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1420 if (!Subtarget->hasV6T2Ops())
1423 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1424 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1427 // For unsigned extracts, check for a shift right and mask
1428 unsigned And_imm = 0;
1429 if (N->getOpcode() == ISD::AND) {
1430 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1432 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1433 if (And_imm & (And_imm + 1))
1436 unsigned Srl_imm = 0;
1437 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1439 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1441 unsigned Width = CountTrailingOnes_32(And_imm);
1442 unsigned LSB = Srl_imm;
1443 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1444 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1445 CurDAG->getTargetConstant(LSB, MVT::i32),
1446 CurDAG->getTargetConstant(Width, MVT::i32),
1447 getAL(CurDAG), Reg0 };
1448 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1454 // Otherwise, we're looking for a shift of a shift
1455 unsigned Shl_imm = 0;
1456 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1457 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1458 unsigned Srl_imm = 0;
1459 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1460 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1461 unsigned Width = 32 - Srl_imm;
1462 int LSB = Srl_imm - Shl_imm;
1465 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1466 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1467 CurDAG->getTargetConstant(LSB, MVT::i32),
1468 CurDAG->getTargetConstant(Width, MVT::i32),
1469 getAL(CurDAG), Reg0 };
1470 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1476 SDNode *ARMDAGToDAGISel::
1477 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1478 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1481 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
1482 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1483 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1486 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1487 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1488 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1489 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1491 llvm_unreachable("Unknown so_reg opcode!");
1495 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1496 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1497 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1498 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1503 SDNode *ARMDAGToDAGISel::
1504 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1505 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1509 if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1510 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1511 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1512 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1517 SDNode *ARMDAGToDAGISel::
1518 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1519 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1520 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1524 unsigned TrueImm = T->getZExtValue();
1525 bool isSoImm = Pred_t2_so_imm(TrueVal.getNode());
1526 if (isSoImm || TrueImm <= 0xffff) {
1527 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1528 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1529 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1530 return CurDAG->SelectNodeTo(N, (isSoImm ? ARM::t2MOVCCi : ARM::t2MOVCCi16),
1536 SDNode *ARMDAGToDAGISel::
1537 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1538 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1539 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1543 unsigned TrueImm = T->getZExtValue();
1544 bool isSoImm = Pred_so_imm(TrueVal.getNode());
1545 if (isSoImm || (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff)) {
1546 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
1547 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1548 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1549 return CurDAG->SelectNodeTo(N, (isSoImm ? ARM::MOVCCi : ARM::MOVCCi16),
1555 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1556 EVT VT = N->getValueType(0);
1557 SDValue FalseVal = N->getOperand(0);
1558 SDValue TrueVal = N->getOperand(1);
1559 SDValue CC = N->getOperand(2);
1560 SDValue CCR = N->getOperand(3);
1561 SDValue InFlag = N->getOperand(4);
1562 assert(CC.getOpcode() == ISD::Constant);
1563 assert(CCR.getOpcode() == ISD::Register);
1564 ARMCC::CondCodes CCVal =
1565 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1567 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1568 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1569 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1570 // Pattern complexity = 18 cost = 1 size = 0
1574 if (Subtarget->isThumb()) {
1575 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1576 CCVal, CCR, InFlag);
1578 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1579 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1583 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1584 CCVal, CCR, InFlag);
1586 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1587 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1592 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1593 // (imm:i32)<<P:Pred_so_imm>>:$true,
1595 // Emits: (MOVCCi:i32 GPR:i32:$false,
1596 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1597 // Pattern complexity = 10 cost = 1 size = 0
1598 if (Subtarget->isThumb()) {
1599 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
1600 CCVal, CCR, InFlag);
1602 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
1603 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1607 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
1608 CCVal, CCR, InFlag);
1610 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
1611 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1617 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1618 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1619 // Pattern complexity = 6 cost = 1 size = 0
1621 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1622 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1623 // Pattern complexity = 6 cost = 11 size = 0
1625 // Also FCPYScc and FCPYDcc.
1626 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1627 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1629 switch (VT.getSimpleVT().SimpleTy) {
1630 default: assert(false && "Illegal conditional move type!");
1633 Opc = Subtarget->isThumb()
1634 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1644 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1647 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
1648 // The only time a CONCAT_VECTORS operation can have legal types is when
1649 // two 64-bit vectors are concatenated to a 128-bit vector.
1650 EVT VT = N->getValueType(0);
1651 if (!VT.is128BitVector() || N->getNumOperands() != 2)
1652 llvm_unreachable("unexpected CONCAT_VECTORS");
1653 DebugLoc dl = N->getDebugLoc();
1654 SDValue V0 = N->getOperand(0);
1655 SDValue V1 = N->getOperand(1);
1656 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1657 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1658 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1659 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1662 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
1663 DebugLoc dl = N->getDebugLoc();
1665 if (N->isMachineOpcode())
1666 return NULL; // Already selected.
1668 switch (N->getOpcode()) {
1670 case ISD::Constant: {
1671 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1673 if (Subtarget->hasThumb2())
1674 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1675 // be done with MOV + MOVT, at worst.
1678 if (Subtarget->isThumb()) {
1679 UseCP = (Val > 255 && // MOV
1680 ~Val > 255 && // MOV + MVN
1681 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1683 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1684 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1685 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1690 CurDAG->getTargetConstantPool(ConstantInt::get(
1691 Type::getInt32Ty(*CurDAG->getContext()), Val),
1692 TLI.getPointerTy());
1695 if (Subtarget->isThumb1Only()) {
1696 SDValue Pred = getAL(CurDAG);
1697 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1698 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1699 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1704 CurDAG->getRegister(0, MVT::i32),
1705 CurDAG->getTargetConstant(0, MVT::i32),
1707 CurDAG->getRegister(0, MVT::i32),
1708 CurDAG->getEntryNode()
1710 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1713 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
1717 // Other cases are autogenerated.
1720 case ISD::FrameIndex: {
1721 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1722 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1723 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1724 if (Subtarget->isThumb1Only()) {
1725 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1726 CurDAG->getTargetConstant(0, MVT::i32));
1728 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1729 ARM::t2ADDri : ARM::ADDri);
1730 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1731 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1732 CurDAG->getRegister(0, MVT::i32) };
1733 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1737 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
1741 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
1745 if (Subtarget->isThumb1Only())
1747 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1748 unsigned RHSV = C->getZExtValue();
1750 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1751 unsigned ShImm = Log2_32(RHSV-1);
1754 SDValue V = N->getOperand(0);
1755 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1756 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1757 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1758 if (Subtarget->isThumb()) {
1759 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1760 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1762 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1763 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1766 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1767 unsigned ShImm = Log2_32(RHSV+1);
1770 SDValue V = N->getOperand(0);
1771 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1772 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1773 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1774 if (Subtarget->isThumb()) {
1775 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1776 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
1778 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1779 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1785 // Check for unsigned bitfield extract
1786 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
1789 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
1790 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
1791 // are entirely contributed by c2 and lower 16-bits are entirely contributed
1792 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
1793 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
1794 EVT VT = N->getValueType(0);
1797 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
1799 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
1802 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1803 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1806 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
1807 SDValue N2 = N0.getOperand(1);
1808 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1811 unsigned N1CVal = N1C->getZExtValue();
1812 unsigned N2CVal = N2C->getZExtValue();
1813 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
1814 (N1CVal & 0xffffU) == 0xffffU &&
1815 (N2CVal & 0xffffU) == 0x0U) {
1816 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
1818 SDValue Ops[] = { N0.getOperand(0), Imm16,
1819 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1820 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
1825 case ARMISD::VMOVRRD:
1826 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
1827 N->getOperand(0), getAL(CurDAG),
1828 CurDAG->getRegister(0, MVT::i32));
1829 case ISD::UMUL_LOHI: {
1830 if (Subtarget->isThumb1Only())
1832 if (Subtarget->isThumb()) {
1833 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1834 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1835 CurDAG->getRegister(0, MVT::i32) };
1836 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
1838 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1839 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1840 CurDAG->getRegister(0, MVT::i32) };
1841 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1844 case ISD::SMUL_LOHI: {
1845 if (Subtarget->isThumb1Only())
1847 if (Subtarget->isThumb()) {
1848 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1849 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1850 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
1852 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1853 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1854 CurDAG->getRegister(0, MVT::i32) };
1855 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1859 SDNode *ResNode = 0;
1860 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1861 ResNode = SelectT2IndexedLoad(N);
1863 ResNode = SelectARMIndexedLoad(N);
1866 // Other cases are autogenerated.
1869 case ARMISD::BRCOND: {
1870 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1871 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1872 // Pattern complexity = 6 cost = 1 size = 0
1874 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1875 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1876 // Pattern complexity = 6 cost = 1 size = 0
1878 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1879 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1880 // Pattern complexity = 6 cost = 1 size = 0
1882 unsigned Opc = Subtarget->isThumb() ?
1883 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1884 SDValue Chain = N->getOperand(0);
1885 SDValue N1 = N->getOperand(1);
1886 SDValue N2 = N->getOperand(2);
1887 SDValue N3 = N->getOperand(3);
1888 SDValue InFlag = N->getOperand(4);
1889 assert(N1.getOpcode() == ISD::BasicBlock);
1890 assert(N2.getOpcode() == ISD::Constant);
1891 assert(N3.getOpcode() == ISD::Register);
1893 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1894 cast<ConstantSDNode>(N2)->getZExtValue()),
1896 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1897 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1899 Chain = SDValue(ResNode, 0);
1900 if (N->getNumValues() == 2) {
1901 InFlag = SDValue(ResNode, 1);
1902 ReplaceUses(SDValue(N, 1), InFlag);
1904 ReplaceUses(SDValue(N, 0),
1905 SDValue(Chain.getNode(), Chain.getResNo()));
1909 return SelectCMOVOp(N);
1910 case ARMISD::CNEG: {
1911 EVT VT = N->getValueType(0);
1912 SDValue N0 = N->getOperand(0);
1913 SDValue N1 = N->getOperand(1);
1914 SDValue N2 = N->getOperand(2);
1915 SDValue N3 = N->getOperand(3);
1916 SDValue InFlag = N->getOperand(4);
1917 assert(N2.getOpcode() == ISD::Constant);
1918 assert(N3.getOpcode() == ISD::Register);
1920 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1921 cast<ConstantSDNode>(N2)->getZExtValue()),
1923 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1925 switch (VT.getSimpleVT().SimpleTy) {
1926 default: assert(false && "Illegal conditional move type!");
1935 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1938 case ARMISD::VZIP: {
1940 EVT VT = N->getValueType(0);
1941 switch (VT.getSimpleVT().SimpleTy) {
1942 default: return NULL;
1943 case MVT::v8i8: Opc = ARM::VZIPd8; break;
1944 case MVT::v4i16: Opc = ARM::VZIPd16; break;
1946 case MVT::v2i32: Opc = ARM::VZIPd32; break;
1947 case MVT::v16i8: Opc = ARM::VZIPq8; break;
1948 case MVT::v8i16: Opc = ARM::VZIPq16; break;
1950 case MVT::v4i32: Opc = ARM::VZIPq32; break;
1952 SDValue Pred = getAL(CurDAG);
1953 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1954 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1955 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1957 case ARMISD::VUZP: {
1959 EVT VT = N->getValueType(0);
1960 switch (VT.getSimpleVT().SimpleTy) {
1961 default: return NULL;
1962 case MVT::v8i8: Opc = ARM::VUZPd8; break;
1963 case MVT::v4i16: Opc = ARM::VUZPd16; break;
1965 case MVT::v2i32: Opc = ARM::VUZPd32; break;
1966 case MVT::v16i8: Opc = ARM::VUZPq8; break;
1967 case MVT::v8i16: Opc = ARM::VUZPq16; break;
1969 case MVT::v4i32: Opc = ARM::VUZPq32; break;
1971 SDValue Pred = getAL(CurDAG);
1972 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1973 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1974 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1976 case ARMISD::VTRN: {
1978 EVT VT = N->getValueType(0);
1979 switch (VT.getSimpleVT().SimpleTy) {
1980 default: return NULL;
1981 case MVT::v8i8: Opc = ARM::VTRNd8; break;
1982 case MVT::v4i16: Opc = ARM::VTRNd16; break;
1984 case MVT::v2i32: Opc = ARM::VTRNd32; break;
1985 case MVT::v16i8: Opc = ARM::VTRNq8; break;
1986 case MVT::v8i16: Opc = ARM::VTRNq16; break;
1988 case MVT::v4i32: Opc = ARM::VTRNq32; break;
1990 SDValue Pred = getAL(CurDAG);
1991 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1992 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1993 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1995 case ARMISD::BUILD_VECTOR: {
1996 EVT VecVT = N->getValueType(0);
1997 EVT EltVT = VecVT.getVectorElementType();
1998 unsigned NumElts = VecVT.getVectorNumElements();
1999 if (EltVT.getSimpleVT() == MVT::f64) {
2000 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2001 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2003 assert(EltVT.getSimpleVT() == MVT::f32 &&
2004 "unexpected type for BUILD_VECTOR");
2006 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2007 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2008 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2009 N->getOperand(2), N->getOperand(3));
2012 case ISD::INTRINSIC_VOID:
2013 case ISD::INTRINSIC_W_CHAIN: {
2014 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2019 case Intrinsic::arm_neon_vld1: {
2020 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2021 ARM::VLD1d32, ARM::VLD1d64 };
2022 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2023 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2024 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0);
2027 case Intrinsic::arm_neon_vld2: {
2028 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2029 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2030 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2031 ARM::VLD2q32Pseudo };
2032 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
2035 case Intrinsic::arm_neon_vld3: {
2036 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2037 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2038 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2039 ARM::VLD3q16Pseudo_UPD,
2040 ARM::VLD3q32Pseudo_UPD };
2041 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2042 ARM::VLD3q16oddPseudo_UPD,
2043 ARM::VLD3q32oddPseudo_UPD };
2044 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2047 case Intrinsic::arm_neon_vld4: {
2048 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2049 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2050 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2051 ARM::VLD4q16Pseudo_UPD,
2052 ARM::VLD4q32Pseudo_UPD };
2053 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2054 ARM::VLD4q16oddPseudo_UPD,
2055 ARM::VLD4q32oddPseudo_UPD };
2056 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2059 case Intrinsic::arm_neon_vld2lane: {
2060 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2061 ARM::VLD2LNd32Pseudo };
2062 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2063 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes);
2066 case Intrinsic::arm_neon_vld3lane: {
2067 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2068 ARM::VLD3LNd32Pseudo };
2069 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2070 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes);
2073 case Intrinsic::arm_neon_vld4lane: {
2074 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2075 ARM::VLD4LNd32Pseudo };
2076 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2077 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes);
2080 case Intrinsic::arm_neon_vst1: {
2081 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2082 ARM::VST1d32, ARM::VST1d64 };
2083 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2084 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2085 return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
2088 case Intrinsic::arm_neon_vst2: {
2089 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
2090 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
2091 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
2092 ARM::VST2q32Pseudo };
2093 return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
2096 case Intrinsic::arm_neon_vst3: {
2097 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
2098 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
2099 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2100 ARM::VST3q16Pseudo_UPD,
2101 ARM::VST3q32Pseudo_UPD };
2102 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2103 ARM::VST3q16oddPseudo_UPD,
2104 ARM::VST3q32oddPseudo_UPD };
2105 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2108 case Intrinsic::arm_neon_vst4: {
2109 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
2110 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
2111 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2112 ARM::VST4q16Pseudo_UPD,
2113 ARM::VST4q32Pseudo_UPD };
2114 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2115 ARM::VST4q16oddPseudo_UPD,
2116 ARM::VST4q32oddPseudo_UPD };
2117 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2120 case Intrinsic::arm_neon_vst2lane: {
2121 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
2122 ARM::VST2LNd32Pseudo };
2123 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
2124 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes);
2127 case Intrinsic::arm_neon_vst3lane: {
2128 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
2129 ARM::VST3LNd32Pseudo };
2130 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
2131 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes);
2134 case Intrinsic::arm_neon_vst4lane: {
2135 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
2136 ARM::VST4LNd32Pseudo };
2137 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
2138 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes);
2144 case ISD::INTRINSIC_WO_CHAIN: {
2145 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2150 case Intrinsic::arm_neon_vtbl2:
2151 return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
2152 case Intrinsic::arm_neon_vtbl3:
2153 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
2154 case Intrinsic::arm_neon_vtbl4:
2155 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
2157 case Intrinsic::arm_neon_vtbx2:
2158 return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
2159 case Intrinsic::arm_neon_vtbx3:
2160 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
2161 case Intrinsic::arm_neon_vtbx4:
2162 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
2167 case ISD::CONCAT_VECTORS:
2168 return SelectConcatVector(N);
2171 return SelectCode(N);
2174 bool ARMDAGToDAGISel::
2175 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2176 std::vector<SDValue> &OutOps) {
2177 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2178 // Require the address to be in a register. That is safe for all ARM
2179 // variants and it is hard to do anything much smarter without knowing
2180 // how the operand is used.
2181 OutOps.push_back(Op);
2185 /// createARMISelDag - This pass converts a legalized DAG into a
2186 /// ARM-specific DAG, ready for instruction scheduling.
2188 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2189 CodeGenOpt::Level OptLevel) {
2190 return new ARMDAGToDAGISel(TM, OptLevel);